1 /***************************************************************************
2 * Copyright (C) 2009-2011 by Mathias Kuester *
3 * mkdorg@users.sourceforge.net *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
27 #include "target_type.h"
30 #include "dsp563xx_once.h"
32 //#define DSP563XX_JTAG_INS_LEN 4
34 #define ASM_REG_W_R0 0x60F400
35 #define ASM_REG_W_R1 0x61F400
36 #define ASM_REG_W_R2 0x62F400
37 #define ASM_REG_W_R3 0x63F400
38 #define ASM_REG_W_R4 0x64F400
39 #define ASM_REG_W_R5 0x65F400
40 #define ASM_REG_W_R6 0x66F400
41 #define ASM_REG_W_R7 0x67F400
43 #define ASM_REG_W_N0 0x70F400
44 #define ASM_REG_W_N1 0x71F400
45 #define ASM_REG_W_N2 0x72F400
46 #define ASM_REG_W_N3 0x73F400
47 #define ASM_REG_W_N4 0x74F400
48 #define ASM_REG_W_N5 0x75F400
49 #define ASM_REG_W_N6 0x76F400
50 #define ASM_REG_W_N7 0x77F400
52 #define ASM_REG_W_M0 0x05F420
53 #define ASM_REG_W_M1 0x05F421
54 #define ASM_REG_W_M2 0x05F422
55 #define ASM_REG_W_M3 0x05F423
56 #define ASM_REG_W_M4 0x05F424
57 #define ASM_REG_W_M5 0x05F425
58 #define ASM_REG_W_M6 0x05F426
59 #define ASM_REG_W_M7 0x05F427
61 #define ASM_REG_W_X0 0x44F400
62 #define ASM_REG_W_X1 0x45F400
64 #define ASM_REG_W_Y0 0x46F400
65 #define ASM_REG_W_Y1 0x47F400
67 #define ASM_REG_W_A0 0x50F400
68 #define ASM_REG_W_A1 0x54F400
69 #define ASM_REG_W_A2 0x52F400
71 #define ASM_REG_W_B0 0x51F400
72 #define ASM_REG_W_B1 0x55F400
73 #define ASM_REG_W_B2 0x53F400
75 #define ASM_REG_W_VBA 0x05F430
76 #define ASM_REG_W_OMR 0x05F43A
77 #define ASM_REG_W_EP 0x05F42A
78 #define ASM_REG_W_SC 0x05F431
79 #define ASM_REG_W_SZ 0x05F438
80 #define ASM_REG_W_SR 0x05F439
81 #define ASM_REG_W_SP 0x05F43B
82 #define ASM_REG_W_SSH 0x05F43C
83 #define ASM_REG_W_SSL 0x05F43D
84 #define ASM_REG_W_LA 0x05F43E
85 #define ASM_REG_W_LC 0x05F43F
86 #define ASM_REG_W_PC 0x000000
87 #define ASM_REG_W_IPRC 0xFFFFFF
88 #define ASM_REG_W_IPRP 0xFFFFFE
90 #define ASM_REG_W_BCR 0xFFFFFB
91 #define ASM_REG_W_DCR 0xFFFFFA
92 #define ASM_REG_W_AAR0 0xFFFFF9
93 #define ASM_REG_W_AAR1 0xFFFFF8
94 #define ASM_REG_W_AAR2 0xFFFFF7
95 #define ASM_REG_W_AAR3 0xFFFFF6
97 static struct once_reg once_regs
[] = {
98 {0, 0x00, 24, "OSCR", 0},
99 {1, 0x01, 24, "OMBC", 0},
100 {2, 0x02, 24, "OBCR", 0},
101 {3, 0x05, 24, "OMLR0", 0},
102 {4, 0x06, 24, "OMLR1", 0},
103 {5, 0x09, 24, "OGDBR", 0},
104 {6, 0x0a, 24, "OPDBR", 0},
105 {7, 0x0b, 24, "OPILR", 0},
106 {8, 0x0c, 24, "PDB", 0},
107 {9, 0x0d, 24, "OTC", 0},
108 {10, 0x0f, 24, "OPABFR", 0},
109 {11, 0x10, 24, "OPABDR", 0},
110 {12, 0x11, 24, "OPABEX", 0},
111 {13, 0x12, 25, "OPABF0", 0},
112 {14, 0x12, 25, "OPABF1", 0},
113 {15, 0x12, 25, "OPABF2", 0},
114 {16, 0x12, 25, "OPABF3", 0},
115 {17, 0x12, 25, "OPABF4", 0},
116 {18, 0x12, 25, "OPABF5", 0},
117 {19, 0x12, 25, "OPABF6", 0},
118 {20, 0x12, 25, "OPABF7", 0},
119 {21, 0x12, 25, "OPABF8", 0},
120 {22, 0x12, 25, "OPABF9", 0},
121 {23, 0x12, 25, "OPABF10", 0},
122 {24, 0x12, 25, "OPABF11", 0},
123 // {25,0x1f,24,"NRSEL",0},
131 /* effective addressing mode encoding */
137 /* address registers */
138 { 0, "r0", 24, 0x10, ASM_REG_W_R0
},
139 { 1, "r1", 24, 0x11, ASM_REG_W_R1
},
140 { 2, "r2", 24, 0x12, ASM_REG_W_R2
},
141 { 3, "r3", 24, 0x13, ASM_REG_W_R3
},
142 { 4, "r4", 24, 0x14, ASM_REG_W_R4
},
143 { 5, "r5", 24, 0x15, ASM_REG_W_R5
},
144 { 6, "r6", 24, 0x16, ASM_REG_W_R6
},
145 { 7, "r7", 24, 0x17, ASM_REG_W_R7
},
146 /* offset registers */
147 { 8, "n0", 24, 0x18, ASM_REG_W_N0
},
148 { 9, "n1", 24, 0x19, ASM_REG_W_N1
},
149 {10, "n2", 24, 0x1a, ASM_REG_W_N2
},
150 {11, "n3", 24, 0x1b, ASM_REG_W_N3
},
151 {12, "n4", 24, 0x1c, ASM_REG_W_N4
},
152 {13, "n5", 24, 0x1d, ASM_REG_W_N5
},
153 {14, "n6", 24, 0x1e, ASM_REG_W_N6
},
154 {15, "n7", 24, 0x1f, ASM_REG_W_N7
},
155 /* modifier registers */
156 {16, "m0", 24, 0x20, ASM_REG_W_M0
},
157 {17, "m1", 24, 0x21, ASM_REG_W_M1
},
158 {18, "m2", 24, 0x22, ASM_REG_W_M2
},
159 {19, "m3", 24, 0x23, ASM_REG_W_M3
},
160 {20, "m4", 24, 0x24, ASM_REG_W_M4
},
161 {21, "m5", 24, 0x25, ASM_REG_W_M5
},
162 {22, "m6", 24, 0x26, ASM_REG_W_M6
},
163 {23, "m7", 24, 0x27, ASM_REG_W_M7
},
164 /* data alu input register */
165 {24, "x0", 24, 0x04, ASM_REG_W_X0
},
166 {25, "x1", 24, 0x05, ASM_REG_W_X1
},
167 {26, "y0", 24, 0x06, ASM_REG_W_Y0
},
168 {27, "y1", 24, 0x07, ASM_REG_W_Y1
},
169 /* data alu accumulator register */
170 {28, "a0", 24, 0x08, ASM_REG_W_A0
},
171 {29, "a1", 24, 0x0c, ASM_REG_W_A1
},
172 {30, "a2", 8, 0x0a, ASM_REG_W_A2
},
173 {31, "b0", 24, 0x09, ASM_REG_W_B0
},
174 {32, "b1", 24, 0x0d, ASM_REG_W_B1
},
175 {33, "b2", 8, 0x0b, ASM_REG_W_B2
},
177 {34, "ssh",24, 0x3c, ASM_REG_W_SSH
},
178 {35, "ssl",24, 0x3d, ASM_REG_W_SSL
},
179 {36, "sp", 24, 0x3b, ASM_REG_W_SP
},
180 {37, "ep", 24, 0x2a, ASM_REG_W_EP
},
181 {38, "sz", 24, 0x38, ASM_REG_W_SZ
},
182 {39, "sc", 24, 0x31, ASM_REG_W_SC
},
184 {40, "pc", 24, 0x00, ASM_REG_W_PC
},
185 {41, "sr", 24, 0x39, ASM_REG_W_SR
},
186 {42, "omr",24, 0x3a, ASM_REG_W_OMR
},
187 {43, "la", 24, 0x3e, ASM_REG_W_LA
},
188 {44, "lc", 24, 0x3f, ASM_REG_W_LC
},
190 {45, "vba", 24, 0x30, ASM_REG_W_VBA
},
191 {46, "iprc",24, 0x00, ASM_REG_W_IPRC
},
192 {47, "iprp",24, 0x00, ASM_REG_W_IPRP
},
194 {48, "bcr", 24, 0x00, ASM_REG_W_BCR
},
195 {49, "dcr", 24, 0x00, ASM_REG_W_DCR
},
196 {50, "aar0",24, 0x00, ASM_REG_W_AAR0
},
197 {51, "aar1",24, 0x00, ASM_REG_W_AAR1
},
198 {52, "aar2",24, 0x00, ASM_REG_W_AAR2
},
199 {53, "aar3",24, 0x00, ASM_REG_W_AAR3
},
207 #define REG_NUM_M0 16
208 #define REG_NUM_M1 17
209 #define REG_NUM_SSH 34
210 #define REG_NUM_SSL 35
211 #define REG_NUM_SP 36
212 #define REG_NUM_EP 37
213 #define REG_NUM_SC 39
214 #define REG_NUM_PC 40
215 #define REG_NUM_SR 41
216 #define REG_NUM_IPRC 46
217 #define REG_NUM_IPRP 47
218 #define REG_NUM_BCR 48
219 #define REG_NUM_DCR 49
220 #define REG_NUM_AAR0 50
221 #define REG_NUM_AAR1 51
222 #define REG_NUM_AAR2 52
223 #define REG_NUM_AAR3 53
232 #define INSTR_JUMP 0x0AF080
233 /* Effective Addressing Mode Encoding */
235 /* instrcution encoder */
237 * s - peripheral space X/Y (X=0,Y=1)
239 * d - source/destination register
240 * p - IO short address
242 #define INSTR_MOVEP_REG_HIO(s,w,d,p) (0x084000 | ((s & 1)<<16) | ((w&1)<<15) | ((d & 0x3f)<<8) | (p & 0x3f))
244 static int dsp563xx_get_gdb_reg_list(struct target
*target
, struct reg
**reg_list
[], int *reg_list_size
)
247 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
249 if (target
->state
!= TARGET_HALTED
)
251 return ERROR_TARGET_NOT_HALTED
;
254 *reg_list_size
= DSP563XX_NUMCOREREGS
;
255 *reg_list
= malloc(sizeof(struct reg
*) * (*reg_list_size
));
258 return ERROR_INVALID_ARGUMENTS
;
260 for (i
= 0; i
< DSP563XX_NUMCOREREGS
; i
++)
262 (*reg_list
)[i
] = &dsp563xx
->core_cache
->reg_list
[i
];
269 static int dsp563xx_read_core_reg(struct target
*target
, int num
)
272 struct dsp563xx_core_reg
*dsp563xx_core_reg
;
273 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
275 if ((num
< 0) || (num
>= DSP563XX_NUMCOREREGS
))
276 return ERROR_INVALID_ARGUMENTS
;
278 dsp563xx_core_reg
= dsp563xx
->core_cache
->reg_list
[num
].arch_info
;
279 reg_value
= dsp563xx
->core_regs
[num
];
280 buf_set_u32(dsp563xx
->core_cache
->reg_list
[num
].value
, 0, 32, reg_value
);
281 dsp563xx
->core_cache
->reg_list
[num
].valid
= 1;
282 dsp563xx
->core_cache
->reg_list
[num
].dirty
= 0;
287 static int dsp563xx_write_core_reg(struct target
*target
, int num
)
290 struct dsp563xx_core_reg
*dsp563xx_core_reg
;
291 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
293 if ((num
< 0) || (num
>= DSP563XX_NUMCOREREGS
))
294 return ERROR_INVALID_ARGUMENTS
;
296 reg_value
= buf_get_u32(dsp563xx
->core_cache
->reg_list
[num
].value
, 0, 32);
297 dsp563xx_core_reg
= dsp563xx
->core_cache
->reg_list
[num
].arch_info
;
298 dsp563xx
->core_regs
[num
] = reg_value
;
299 dsp563xx
->core_cache
->reg_list
[num
].valid
= 1;
300 dsp563xx
->core_cache
->reg_list
[num
].dirty
= 0;
305 static int dsp563xx_target_create(struct target
*target
, Jim_Interp
* interp
)
307 struct dsp563xx_common
*dsp563xx
= calloc(1, sizeof(struct dsp563xx_common
));
310 return ERROR_INVALID_ARGUMENTS
;
312 dsp563xx
->jtag_info
.tap
= target
->tap
;
313 target
->arch_info
= dsp563xx
;
314 dsp563xx
->read_core_reg
= dsp563xx_read_core_reg
;
315 dsp563xx
->write_core_reg
= dsp563xx_write_core_reg
;
320 static int dsp563xx_get_core_reg(struct reg
*reg
)
322 struct dsp563xx_core_reg
*dsp563xx_reg
= reg
->arch_info
;
323 struct target
*target
= dsp563xx_reg
->target
;
324 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
326 LOG_DEBUG("%s", __FUNCTION__
);
328 if (target
->state
!= TARGET_HALTED
)
330 return ERROR_TARGET_NOT_HALTED
;
333 return dsp563xx
->read_core_reg(target
, dsp563xx_reg
->num
);
336 static int dsp563xx_set_core_reg(struct reg
*reg
, uint8_t * buf
)
338 LOG_DEBUG("%s", __FUNCTION__
);
340 struct dsp563xx_core_reg
*dsp563xx_reg
= reg
->arch_info
;
341 struct target
*target
= dsp563xx_reg
->target
;
342 uint32_t value
= buf_get_u32(buf
, 0, 32);
344 if (target
->state
!= TARGET_HALTED
)
346 return ERROR_TARGET_NOT_HALTED
;
349 buf_set_u32(reg
->value
, 0, reg
->size
, value
);
356 static int dsp563xx_read_register(struct target
*target
, int num
, int force
);
357 static int dsp563xx_write_register(struct target
*target
, int num
, int force
);
359 static int dsp563xx_reg_read_high_io(struct target
*target
, uint32_t instr_mask
, uint32_t * data
)
363 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
365 /* we use r0 to store temporary data */
366 if (!dsp563xx
->core_cache
->reg_list
[REG_NUM_R0
].valid
)
367 dsp563xx
->read_core_reg(target
, REG_NUM_R0
);
369 /* move source memory to r0 */
370 instr
= INSTR_MOVEP_REG_HIO(MEM_X
, 0, EAME_R0
, instr_mask
);
371 if ((err
= dsp563xx_once_execute_sw_ir_nq(target
->tap
, instr
)) != ERROR_OK
)
373 /* move r0 to debug register */
374 instr
= INSTR_MOVEP_REG_HIO(MEM_X
, 1, EAME_R0
, 0xfffffc);
375 if ((err
= dsp563xx_once_execute_sw_ir(target
->tap
, instr
)) != ERROR_OK
)
377 /* read debug register */
378 if ((err
= dsp563xx_once_reg_read(target
->tap
, DSP563XX_ONCE_OGDBR
, data
)) != ERROR_OK
)
380 /* r0 is no longer valid on target */
381 dsp563xx
->core_cache
->reg_list
[REG_NUM_R0
].dirty
= 1;
386 static int dsp563xx_reg_write_high_io(struct target
*target
, uint32_t instr_mask
, uint32_t data
)
390 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
392 /* we use r0 to store temporary data */
393 if (!dsp563xx
->core_cache
->reg_list
[REG_NUM_R0
].valid
)
394 dsp563xx
->read_core_reg(target
, REG_NUM_R0
);
396 /* move data to r0 */
397 if ((err
= dsp563xx_once_execute_dw_ir_nq(target
->tap
, 0x60F400, data
)) != ERROR_OK
)
399 /* move r0 to destination memory */
400 instr
= INSTR_MOVEP_REG_HIO(MEM_X
, 1, EAME_R0
, instr_mask
);
401 if ((err
= dsp563xx_once_execute_sw_ir(target
->tap
, instr
)) != ERROR_OK
)
404 /* r0 is no longer valid on target */
405 dsp563xx
->core_cache
->reg_list
[REG_NUM_R0
].dirty
= 1;
410 static int dsp563xx_reg_read(struct target
*target
, uint32_t eame
, uint32_t * data
)
415 instr
= INSTR_MOVEP_REG_HIO(MEM_X
, 1, eame
, 0xfffffc);
416 if ((err
= dsp563xx_once_execute_sw_ir_nq(target
->tap
, instr
)) != ERROR_OK
)
419 if ((err
= dsp563xx_once_execute_sw_ir(target
->tap
, 0x000000)) != ERROR_OK
)
421 /* read debug register */
422 return dsp563xx_once_reg_read(target
->tap
, DSP563XX_ONCE_OGDBR
, data
);
425 static int dsp563xx_reg_write(struct target
*target
, uint32_t instr_mask
, uint32_t data
)
429 if ((err
= dsp563xx_once_execute_dw_ir_nq(target
->tap
, instr_mask
, data
)) != ERROR_OK
)
432 return dsp563xx_once_execute_sw_ir(target
->tap
, 0x000000);
435 static int dsp563xx_reg_pc_read(struct target
*target
)
438 uint32_t opabdr
, opabex
;
439 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
441 /* pc was changed, nothing todo */
442 if (dsp563xx
->core_cache
->reg_list
[REG_NUM_PC
].dirty
)
445 if ((err
= dsp563xx_once_reg_read(target
->tap
, DSP563XX_ONCE_OPABDR
, &opabdr
)) != ERROR_OK
)
447 if ((err
= dsp563xx_once_reg_read(target
->tap
, DSP563XX_ONCE_OPABEX
, &opabex
)) != ERROR_OK
)
450 /* conditional branch check */
451 if (opabdr
== opabex
)
453 /* TODO: check the trace buffer and if a
454 * conditional branch is detected then decode
455 * the branch command and add the relative
456 * address to the current pc
458 LOG_DEBUG("%s conditional branch not supported yet", __FUNCTION__
);
462 dsp563xx
->core_regs
[REG_NUM_PC
] = opabex
;
463 dsp563xx
->read_core_reg(target
, REG_NUM_PC
);
469 static int dsp563xx_reg_ssh_read(struct target
*target
)
473 struct dsp563xx_core_reg
*arch_info
;
474 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
476 arch_info
= dsp563xx
->core_cache
->reg_list
[REG_NUM_SSH
].arch_info
;
478 /* get a valid stack pointer */
479 if ((err
= dsp563xx_read_register(target
, REG_NUM_SP
, 0)) != ERROR_OK
)
481 sp
= dsp563xx
->core_regs
[REG_NUM_SP
];
482 if ((err
= dsp563xx_write_register(target
, REG_NUM_SP
, 0)) != ERROR_OK
)
485 /* get a valid stack count */
486 if ((err
= dsp563xx_read_register(target
, REG_NUM_SC
, 0)) != ERROR_OK
)
488 sc
= dsp563xx
->core_regs
[REG_NUM_SC
];
489 if ((err
= dsp563xx_write_register(target
, REG_NUM_SC
, 0)) != ERROR_OK
)
492 /* get a valid extended pointer */
493 if ((err
= dsp563xx_read_register(target
, REG_NUM_EP
, 0)) != ERROR_OK
)
495 ep
= dsp563xx
->core_regs
[REG_NUM_EP
];
496 if ((err
= dsp563xx_write_register(target
, REG_NUM_EP
, 0)) != ERROR_OK
)
505 if ((err
= dsp563xx_reg_read(target
, arch_info
->eame
, &sp
)) != ERROR_OK
)
508 if ((err
= dsp563xx_write_register(target
, REG_NUM_SC
, 1)) != ERROR_OK
)
510 if ((err
= dsp563xx_write_register(target
, REG_NUM_SP
, 1)) != ERROR_OK
)
512 if ((err
= dsp563xx_write_register(target
, REG_NUM_EP
, 1)) != ERROR_OK
)
516 dsp563xx
->core_regs
[REG_NUM_SSH
] = sp
;
517 dsp563xx
->read_core_reg(target
, REG_NUM_SSH
);
522 static int dsp563xx_reg_ssh_write(struct target
*target
)
526 struct dsp563xx_core_reg
*arch_info
;
527 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
529 arch_info
= dsp563xx
->core_cache
->reg_list
[REG_NUM_SSH
].arch_info
;
531 /* get a valid stack pointer */
532 if ((err
= dsp563xx_read_register(target
, REG_NUM_SP
, 0)) != ERROR_OK
)
534 sp
= dsp563xx
->core_regs
[REG_NUM_SP
];
539 /* write new stackpointer */
540 dsp563xx
->core_regs
[REG_NUM_SP
] = sp
;
541 if ((err
= dsp563xx
->read_core_reg(target
, REG_NUM_SP
)) != ERROR_OK
)
543 if ((err
= dsp563xx_write_register(target
, REG_NUM_SP
, 1)) != ERROR_OK
)
546 if ((err
= dsp563xx_reg_write(target
, arch_info
->instr_mask
, dsp563xx
->core_regs
[REG_NUM_SSH
])) != ERROR_OK
)
549 if ((err
= dsp563xx_read_register(target
, REG_NUM_SP
, 1)) != ERROR_OK
)
551 if ((err
= dsp563xx_read_register(target
, REG_NUM_SSH
, 1)) != ERROR_OK
)
558 static int dsp563xx_reg_ssl_read(struct target
*target
)
562 struct dsp563xx_core_reg
*arch_info
;
563 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
565 arch_info
= dsp563xx
->core_cache
->reg_list
[REG_NUM_SSL
].arch_info
;
567 /* get a valid stack pointer */
568 if ((err
= dsp563xx_read_register(target
, REG_NUM_SP
, 0)) != ERROR_OK
)
570 sp
= dsp563xx
->core_regs
[REG_NUM_SP
];
578 if ((err
= dsp563xx_reg_read(target
, arch_info
->eame
, &sp
)) != ERROR_OK
)
582 dsp563xx
->core_regs
[REG_NUM_SSL
] = sp
;
583 dsp563xx
->read_core_reg(target
, REG_NUM_SSL
);
588 static int dsp563xx_read_register(struct target
*target
, int num
, int force
)
592 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
593 struct dsp563xx_core_reg
*arch_info
;
596 dsp563xx
->core_cache
->reg_list
[num
].valid
= 0;
598 if (!dsp563xx
->core_cache
->reg_list
[num
].valid
)
600 arch_info
= dsp563xx
->core_cache
->reg_list
[num
].arch_info
;
602 switch (arch_info
->num
)
605 err
= dsp563xx_reg_ssh_read(target
);
608 err
= dsp563xx_reg_ssl_read(target
);
611 err
= dsp563xx_reg_pc_read(target
);
621 err
= dsp563xx_reg_read_high_io(target
, arch_info
->instr_mask
, &data
);
624 dsp563xx
->core_regs
[num
] = data
;
625 dsp563xx
->read_core_reg(target
, num
);
629 err
= dsp563xx_reg_read(target
, arch_info
->eame
, &data
);
632 dsp563xx
->core_regs
[num
] = data
;
633 dsp563xx
->read_core_reg(target
, num
);
643 static int dsp563xx_write_register(struct target
*target
, int num
, int force
)
646 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
647 struct dsp563xx_core_reg
*arch_info
;
650 dsp563xx
->core_cache
->reg_list
[num
].dirty
= 1;
652 if (dsp563xx
->core_cache
->reg_list
[num
].dirty
)
654 arch_info
= dsp563xx
->core_cache
->reg_list
[num
].arch_info
;
656 dsp563xx
->write_core_reg(target
, num
);
658 switch (arch_info
->num
)
661 err
= dsp563xx_reg_ssh_write(target
);
664 /* pc is updated on resume, no need to write it here */
674 err
= dsp563xx_reg_write_high_io(target
, arch_info
->instr_mask
, dsp563xx
->core_regs
[num
]);
677 err
= dsp563xx_reg_write(target
, arch_info
->instr_mask
, dsp563xx
->core_regs
[num
]);
679 if ((err
== ERROR_OK
) && (arch_info
->num
== REG_NUM_SP
))
681 dsp563xx
->core_cache
->reg_list
[REG_NUM_SSH
].valid
= 0;
682 dsp563xx
->core_cache
->reg_list
[REG_NUM_SSL
].valid
= 0;
692 static int dsp563xx_save_context(struct target
*target
)
694 int i
, err
= ERROR_OK
;
696 for (i
= 0; i
< DSP563XX_NUMCOREREGS
; i
++)
698 if ((err
= dsp563xx_read_register(target
, i
, 0)) != ERROR_OK
)
705 static int dsp563xx_restore_context(struct target
*target
)
707 int i
, err
= ERROR_OK
;
709 for (i
= 0; i
< DSP563XX_NUMCOREREGS
; i
++)
711 if ((err
= dsp563xx_write_register(target
, i
, 0)) != ERROR_OK
)
718 static const struct reg_arch_type dsp563xx_reg_type
= {
719 .get
= dsp563xx_get_core_reg
,
720 .set
= dsp563xx_set_core_reg
,
723 static int dsp563xx_init_target(struct command_context
*cmd_ctx
, struct target
*target
)
725 /* get pointers to arch-specific information */
726 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
728 struct reg_cache
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
729 struct reg_cache
*cache
= malloc(sizeof(struct reg_cache
));
730 struct reg
*reg_list
= malloc(sizeof(struct reg
) * DSP563XX_NUMCOREREGS
);
731 struct dsp563xx_core_reg
*arch_info
= malloc(sizeof(struct dsp563xx_core_reg
) * DSP563XX_NUMCOREREGS
);
734 LOG_DEBUG("%s", __FUNCTION__
);
736 /* Build the process context cache */
737 cache
->name
= "dsp563xx registers";
739 cache
->reg_list
= reg_list
;
740 cache
->num_regs
= DSP563XX_NUMCOREREGS
;
742 dsp563xx
->core_cache
= cache
;
744 for (i
= 0; i
< DSP563XX_NUMCOREREGS
; i
++)
746 arch_info
[i
].num
= dsp563xx_regs
[i
].id
;
747 arch_info
[i
].name
= dsp563xx_regs
[i
].name
;
748 arch_info
[i
].size
= dsp563xx_regs
[i
].bits
;
749 arch_info
[i
].eame
= dsp563xx_regs
[i
].eame
;
750 arch_info
[i
].instr_mask
= dsp563xx_regs
[i
].instr_mask
;
751 arch_info
[i
].target
= target
;
752 arch_info
[i
].dsp563xx_common
= dsp563xx
;
753 reg_list
[i
].name
= dsp563xx_regs
[i
].name
;
754 reg_list
[i
].size
= dsp563xx_regs
[i
].bits
;
755 reg_list
[i
].value
= calloc(1, 4);
756 reg_list
[i
].dirty
= 0;
757 reg_list
[i
].valid
= 0;
758 reg_list
[i
].type
= &dsp563xx_reg_type
;
759 reg_list
[i
].arch_info
= &arch_info
[i
];
765 static int dsp563xx_arch_state(struct target
*target
)
767 LOG_DEBUG("%s", __FUNCTION__
);
771 #define DSP563XX_SR_SA (1<<17)
772 #define DSP563XX_SR_SC (1<<13)
774 static int dsp563xx_debug_once_init(struct target
*target
)
776 return dsp563xx_once_read_register(target
->tap
, once_regs
, DSP563XX_NUMONCEREGS
);
779 static int dsp563xx_debug_init(struct target
*target
)
783 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
784 struct dsp563xx_core_reg
*arch_info
;
786 if ((err
= dsp563xx_debug_once_init(target
)) != ERROR_OK
)
789 arch_info
= dsp563xx
->core_cache
->reg_list
[REG_NUM_SR
].arch_info
;
791 /* check 24bit mode */
792 if ((err
= dsp563xx_read_register(target
, REG_NUM_SR
, 0)) != ERROR_OK
)
795 sr
= dsp563xx
->core_regs
[REG_NUM_SR
];
797 if (sr
& (DSP563XX_SR_SA
| DSP563XX_SR_SC
))
799 sr
&= ~(DSP563XX_SR_SA
| DSP563XX_SR_SC
);
801 if ((err
= dsp563xx_once_execute_dw_ir(target
->tap
, arch_info
->instr_mask
, sr
)) != ERROR_OK
)
803 dsp563xx
->core_cache
->reg_list
[REG_NUM_SR
].dirty
= 1;
806 if ((err
= dsp563xx_read_register(target
, REG_NUM_N0
, 0)) != ERROR_OK
)
808 if ((err
= dsp563xx_read_register(target
, REG_NUM_N1
, 0)) != ERROR_OK
)
810 if ((err
= dsp563xx_read_register(target
, REG_NUM_M0
, 0)) != ERROR_OK
)
812 if ((err
= dsp563xx_read_register(target
, REG_NUM_M1
, 0)) != ERROR_OK
)
815 if (dsp563xx
->core_regs
[REG_NUM_N0
] != 0x000000)
817 arch_info
= dsp563xx
->core_cache
->reg_list
[REG_NUM_N0
].arch_info
;
818 if ((err
= dsp563xx_reg_write(target
, arch_info
->instr_mask
, 0x000000)) != ERROR_OK
)
821 dsp563xx
->core_cache
->reg_list
[REG_NUM_N0
].dirty
= 1;
823 if (dsp563xx
->core_regs
[REG_NUM_N1
] != 0x000000)
825 arch_info
= dsp563xx
->core_cache
->reg_list
[REG_NUM_N1
].arch_info
;
826 if ((err
= dsp563xx_reg_write(target
, arch_info
->instr_mask
, 0x000000)) != ERROR_OK
)
829 dsp563xx
->core_cache
->reg_list
[REG_NUM_N1
].dirty
= 1;
831 if (dsp563xx
->core_regs
[REG_NUM_M0
] != 0xffffff)
833 arch_info
= dsp563xx
->core_cache
->reg_list
[REG_NUM_M0
].arch_info
;
834 if ((err
= dsp563xx_reg_write(target
, arch_info
->instr_mask
, 0xffffff)) != ERROR_OK
)
837 dsp563xx
->core_cache
->reg_list
[REG_NUM_M0
].dirty
= 1;
839 if (dsp563xx
->core_regs
[REG_NUM_M1
] != 0xffffff)
841 arch_info
= dsp563xx
->core_cache
->reg_list
[REG_NUM_M1
].arch_info
;
842 if ((err
= dsp563xx_reg_write(target
, arch_info
->instr_mask
, 0xffffff)) != ERROR_OK
)
845 dsp563xx
->core_cache
->reg_list
[REG_NUM_M1
].dirty
= 1;
847 if ((err
= dsp563xx_save_context(target
)) != ERROR_OK
)
853 static int dsp563xx_jtag_debug_request(struct target
*target
)
855 return dsp563xx_once_request_debug(target
->tap
, target
->state
== TARGET_RESET
);
858 static int dsp563xx_poll(struct target
*target
)
861 uint32_t once_status
;
864 state
= dsp563xx_once_target_status(target
->tap
);
866 if (state
== TARGET_UNKNOWN
)
868 target
->state
= state
;
869 LOG_ERROR("jtag status contains invalid mode value - communication failure");
870 return ERROR_TARGET_FAILURE
;
873 if ((err
= dsp563xx_once_reg_read(target
->tap
, DSP563XX_ONCE_OSCR
, &once_status
)) != ERROR_OK
)
876 if ((once_status
& DSP563XX_ONCE_OSCR_DEBUG_M
) == DSP563XX_ONCE_OSCR_DEBUG_M
)
878 if (target
->state
!= TARGET_HALTED
)
880 target
->state
= TARGET_HALTED
;
881 if ((err
= dsp563xx_debug_init(target
)) != ERROR_OK
)
884 LOG_DEBUG("target->state: %s", target_state_name(target
));
891 static int dsp563xx_halt(struct target
*target
)
894 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
896 if (target
->state
== TARGET_HALTED
)
898 LOG_DEBUG("target was already halted");
902 if (target
->state
== TARGET_UNKNOWN
)
904 LOG_WARNING("target was in unknown state when halt was requested");
907 if ((err
= dsp563xx_jtag_debug_request(target
)) != ERROR_OK
)
910 /* store pipeline register */
911 if ((err
= dsp563xx_once_reg_read(target
->tap
, DSP563XX_ONCE_OPILR
, &dsp563xx
->pipeline_context
.once_opilr
)) != ERROR_OK
)
913 if ((err
= dsp563xx_once_reg_read(target
->tap
, DSP563XX_ONCE_OPDBR
, &dsp563xx
->pipeline_context
.once_opdbr
)) != ERROR_OK
)
916 LOG_DEBUG("%s", __FUNCTION__
);
921 static int dsp563xx_resume(struct target
*target
, int current
, uint32_t address
, int handle_breakpoints
, int debug_execution
)
924 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
926 LOG_DEBUG("%s", __FUNCTION__
);
928 if ((err
= dsp563xx_restore_context(target
)) != ERROR_OK
)
930 register_cache_invalidate(dsp563xx
->core_cache
);
934 /* restore pipeline registers and go */
935 if ((err
= dsp563xx_once_reg_write(target
->tap
, DSP563XX_ONCE_OPILR
, dsp563xx
->pipeline_context
.once_opilr
)) != ERROR_OK
)
938 dsp563xx_once_reg_write(target
->tap
, DSP563XX_ONCE_OPDBR
| DSP563XX_ONCE_OCR_EX
| DSP563XX_ONCE_OCR_GO
,
939 dsp563xx
->pipeline_context
.once_opdbr
)) != ERROR_OK
)
944 /* set to go register and jump */
945 if ((err
= dsp563xx_once_reg_write(target
->tap
, DSP563XX_ONCE_OPDBR
, INSTR_JUMP
)) != ERROR_OK
)
947 if ((err
= dsp563xx_once_reg_write(target
->tap
, DSP563XX_ONCE_PDBGOTO
| DSP563XX_ONCE_OCR_EX
| DSP563XX_ONCE_OCR_GO
, address
)) != ERROR_OK
)
951 target
->state
= TARGET_RUNNING
;
956 static int dsp563xx_step_ex(struct target
*target
, int current
, uint32_t address
, int handle_breakpoints
, int steps
)
959 uint32_t once_status
;
961 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
963 if (target
->state
!= TARGET_HALTED
)
965 LOG_DEBUG("target was not halted");
969 LOG_DEBUG("%s %08X %08X", __FUNCTION__
, current
, (unsigned) address
);
971 if ((err
= dsp563xx_jtag_debug_request(target
)) != ERROR_OK
)
973 if ((err
= dsp563xx_restore_context(target
)) != ERROR_OK
)
976 /* reset trace mode */
977 if ((err
= dsp563xx_once_reg_write(target
->tap
, DSP563XX_ONCE_OSCR
, 0x000000)) != ERROR_OK
)
979 /* enable trace mode */
980 if ((err
= dsp563xx_once_reg_write(target
->tap
, DSP563XX_ONCE_OSCR
, DSP563XX_ONCE_OSCR_TME
)) != ERROR_OK
)
985 /* on JUMP we need one extra cycle */
989 /* load step counter with N-1 */
990 if ((err
= dsp563xx_once_reg_write(target
->tap
, DSP563XX_ONCE_OTC
, cnt
)) != ERROR_OK
)
995 /* restore pipeline registers and go */
996 if ((err
= dsp563xx_once_reg_write(target
->tap
, DSP563XX_ONCE_OPILR
, dsp563xx
->pipeline_context
.once_opilr
)) != ERROR_OK
)
999 dsp563xx_once_reg_write(target
->tap
, DSP563XX_ONCE_OPDBR
| DSP563XX_ONCE_OCR_EX
| DSP563XX_ONCE_OCR_GO
,
1000 dsp563xx
->pipeline_context
.once_opdbr
)) != ERROR_OK
)
1005 /* set to go register and jump */
1006 if ((err
= dsp563xx_once_reg_write(target
->tap
, DSP563XX_ONCE_OPDBR
, INSTR_JUMP
)) != ERROR_OK
)
1008 if ((err
= dsp563xx_once_reg_write(target
->tap
, DSP563XX_ONCE_PDBGOTO
| DSP563XX_ONCE_OCR_EX
| DSP563XX_ONCE_OCR_GO
, address
)) != ERROR_OK
)
1014 if ((err
= dsp563xx_once_reg_read(target
->tap
, DSP563XX_ONCE_OSCR
, &once_status
)) != ERROR_OK
)
1017 if (once_status
& DSP563XX_ONCE_OSCR_TO
)
1019 /* store pipeline register */
1020 if ((err
= dsp563xx_once_reg_read(target
->tap
, DSP563XX_ONCE_OPILR
, &dsp563xx
->pipeline_context
.once_opilr
)) != ERROR_OK
)
1022 if ((err
= dsp563xx_once_reg_read(target
->tap
, DSP563XX_ONCE_OPDBR
, &dsp563xx
->pipeline_context
.once_opdbr
)) != ERROR_OK
)
1025 if ((err
= dsp563xx_once_reg_read(target
->tap
, DSP563XX_ONCE_OPABFR
, &dr_in
)) != ERROR_OK
)
1027 LOG_DEBUG("fetch: %08X", (unsigned) dr_in
);
1028 if ((err
= dsp563xx_once_reg_read(target
->tap
, DSP563XX_ONCE_OPABDR
, &dr_in
)) != ERROR_OK
)
1030 LOG_DEBUG("decode: %08X", (unsigned) dr_in
);
1031 if ((err
= dsp563xx_once_reg_read(target
->tap
, DSP563XX_ONCE_OPABEX
, &dr_in
)) != ERROR_OK
)
1033 LOG_DEBUG("execute: %08X", (unsigned) dr_in
);
1035 /* reset trace mode */
1036 if ((err
= dsp563xx_once_reg_write(target
->tap
, DSP563XX_ONCE_OSCR
, 0x000000)) != ERROR_OK
)
1039 register_cache_invalidate(dsp563xx
->core_cache
);
1040 if ((err
= dsp563xx_debug_init(target
)) != ERROR_OK
)
1050 static int dsp563xx_step(struct target
*target
, int current
, uint32_t address
, int handle_breakpoints
)
1052 return dsp563xx_step_ex(target
, current
, address
, handle_breakpoints
, 0);
1055 static int dsp563xx_assert_reset(struct target
*target
)
1058 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
1059 enum reset_types jtag_reset_config
= jtag_get_reset_config();
1061 if (jtag_reset_config
& RESET_HAS_SRST
)
1063 /* default to asserting srst */
1064 if (jtag_reset_config
& RESET_SRST_PULLS_TRST
)
1066 jtag_add_reset(1, 1);
1070 jtag_add_reset(0, 1);
1074 target
->state
= TARGET_RESET
;
1075 jtag_add_sleep(5000);
1077 /* registers are now invalid */
1078 register_cache_invalidate(dsp563xx
->core_cache
);
1080 if (target
->reset_halt
)
1082 if ((retval
= target_halt(target
)) != ERROR_OK
)
1086 LOG_DEBUG("%s", __FUNCTION__
);
1090 static int dsp563xx_deassert_reset(struct target
*target
)
1094 /* deassert reset lines */
1095 jtag_add_reset(0, 0);
1097 if ((err
= dsp563xx_poll(target
)) != ERROR_OK
)
1100 if (target
->reset_halt
)
1102 if (target
->state
== TARGET_HALTED
)
1104 /* after a reset the cpu jmp to the
1105 * reset vector and need 2 cycles to fill
1106 * the cache (fetch,decode,excecute)
1108 if ((err
= dsp563xx_step_ex(target
, 1, 0, 1, 1)) != ERROR_OK
)
1113 // target->state = TARGET_RUNNING;
1115 LOG_DEBUG("%s", __FUNCTION__
);
1119 static int dsp563xx_soft_reset_halt(struct target
*target
)
1121 LOG_DEBUG("%s", __FUNCTION__
);
1125 static int dsp563xx_read_memory(struct target
*target
, int mem_type
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t * buffer
)
1128 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
1130 uint32_t data
, move_cmd
;
1133 LOG_DEBUG("address: 0x%8.8" PRIx32
", size: 0x%8.8" PRIx32
", count: 0x%8.8" PRIx32
, address
, size
, count
);
1135 if (target
->state
!= TARGET_HALTED
)
1137 LOG_WARNING("target not halted");
1138 return ERROR_TARGET_NOT_HALTED
;
1144 move_cmd
= 0x61d800;
1147 move_cmd
= 0x69d800;
1150 move_cmd
= 0x07d891;
1153 return ERROR_INVALID_ARGUMENTS
;
1156 /* we use r0 to store temporary data */
1157 if (!dsp563xx
->core_cache
->reg_list
[REG_NUM_R0
].valid
)
1158 dsp563xx
->read_core_reg(target
, REG_NUM_R0
);
1159 /* we use r1 to store temporary data */
1160 if (!dsp563xx
->core_cache
->reg_list
[REG_NUM_R1
].valid
)
1161 dsp563xx
->read_core_reg(target
, REG_NUM_R1
);
1163 /* r0 is no longer valid on target */
1164 dsp563xx
->core_cache
->reg_list
[REG_NUM_R0
].dirty
= 1;
1165 /* r1 is no longer valid on target */
1166 dsp563xx
->core_cache
->reg_list
[REG_NUM_R1
].dirty
= 1;
1171 if ((err
= dsp563xx_once_execute_dw_ir(target
->tap
, 0x60F400, address
)) != ERROR_OK
)
1174 for (i
= 0; i
< x
; i
++)
1177 if ((err
= dsp563xx_once_execute_sw_ir_nq(target
->tap
, move_cmd
)) != ERROR_OK
)
1179 if ((err
= dsp563xx_once_execute_sw_ir(target
->tap
, 0x08D13C)) != ERROR_OK
)
1181 if ((err
= dsp563xx_once_reg_read(target
->tap
, DSP563XX_ONCE_OGDBR
, &data
)) != ERROR_OK
)
1183 target_buffer_set_u32(target
, b
, data
);
1186 LOG_DEBUG("R: %08X", data
);
1192 static int dsp563xx_read_memory_p(struct target
*target
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t * buffer
)
1194 return dsp563xx_read_memory(target
, MEM_P
, address
, size
, count
, buffer
);
1197 static int dsp563xx_write_memory(struct target
*target
, int mem_type
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t * buffer
)
1200 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
1202 uint32_t data
, move_cmd
;
1205 LOG_DEBUG("address: 0x%8.8" PRIx32
", size: 0x%8.8" PRIx32
", count: 0x%8.8" PRIx32
"", address
, size
, count
);
1207 if (target
->state
!= TARGET_HALTED
)
1209 LOG_WARNING("target not halted");
1210 return ERROR_TARGET_NOT_HALTED
;
1216 move_cmd
= 0x615800;
1219 move_cmd
= 0x695800;
1222 move_cmd
= 0x075891;
1225 return ERROR_INVALID_ARGUMENTS
;
1228 /* we use r0 to store temporary data */
1229 if (!dsp563xx
->core_cache
->reg_list
[REG_NUM_R0
].valid
)
1230 dsp563xx
->read_core_reg(target
, REG_NUM_R0
);
1231 /* we use r1 to store temporary data */
1232 if (!dsp563xx
->core_cache
->reg_list
[REG_NUM_R1
].valid
)
1233 dsp563xx
->read_core_reg(target
, REG_NUM_R1
);
1235 /* r0 is no longer valid on target */
1236 dsp563xx
->core_cache
->reg_list
[REG_NUM_R0
].dirty
= 1;
1237 /* r1 is no longer valid on target */
1238 dsp563xx
->core_cache
->reg_list
[REG_NUM_R1
].dirty
= 1;
1243 if ((err
= dsp563xx_once_execute_dw_ir(target
->tap
, 0x60F400, address
)) != ERROR_OK
)
1246 for (i
= 0; i
< x
; i
++)
1248 data
= target_buffer_get_u32(target
, b
);
1251 LOG_DEBUG("W: %08X", data
);
1253 if ((err
= dsp563xx_once_execute_dw_ir_nq(target
->tap
, 0x61F400, data
)) != ERROR_OK
)
1255 if ((err
= dsp563xx_once_execute_sw_ir(target
->tap
, move_cmd
)) != ERROR_OK
)
1264 static int dsp563xx_write_memory_p(struct target
*target
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t * buffer
)
1266 return dsp563xx_write_memory(target
, MEM_P
, address
, size
, count
, buffer
);
1269 static void handle_md_output(struct command_context
*cmd_ctx
, struct target
*target
, uint32_t address
, unsigned size
, unsigned count
, const uint8_t * buffer
)
1271 const unsigned line_bytecnt
= 32;
1272 unsigned line_modulo
= line_bytecnt
/ size
;
1274 char output
[line_bytecnt
* 4 + 1];
1275 unsigned output_len
= 0;
1277 const char *value_fmt
;
1281 value_fmt
= "%8.8x ";
1284 value_fmt
= "%4.4x ";
1287 value_fmt
= "%2.2x ";
1290 /* "can't happen", caller checked */
1291 LOG_ERROR("invalid memory read size: %u", size
);
1295 for (unsigned i
= 0; i
< count
; i
++)
1297 if (i
% line_modulo
== 0)
1299 output_len
+= snprintf(output
+ output_len
, sizeof(output
) - output_len
, "0x%8.8x: ", (unsigned) (address
+ (i
* size
)));
1303 const uint8_t *value_ptr
= buffer
+ i
* size
;
1307 value
= target_buffer_get_u32(target
, value_ptr
);
1310 value
= target_buffer_get_u16(target
, value_ptr
);
1315 output_len
+= snprintf(output
+ output_len
, sizeof(output
) - output_len
, value_fmt
, value
);
1317 if ((i
% line_modulo
== line_modulo
- 1) || (i
== count
- 1))
1319 command_print(cmd_ctx
, "%s", output
);
1325 COMMAND_HANDLER(dsp563xx_mem_command
)
1327 struct target
*target
= get_current_target(CMD_CTX
);
1330 uint32_t address
= 0;
1331 uint32_t count
= 1, i
;
1332 uint32_t pattern
= 0;
1334 uint8_t *buffer
, *b
;
1336 switch (CMD_NAME
[1])
1345 return ERROR_COMMAND_SYNTAX_ERROR
;
1348 switch (CMD_NAME
[3])
1360 return ERROR_COMMAND_SYNTAX_ERROR
;
1365 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], address
);
1372 return ERROR_COMMAND_SYNTAX_ERROR
;
1376 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], pattern
);
1380 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[2], count
);
1388 return ERROR_COMMAND_SYNTAX_ERROR
;
1392 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], count
);
1396 buffer
= calloc(count
, sizeof(uint32_t));
1400 if ((err
= dsp563xx_read_memory(target
, mem_type
, address
, sizeof(uint32_t), count
, buffer
)) == ERROR_OK
)
1401 handle_md_output(CMD_CTX
, target
, address
, sizeof(uint32_t), count
, buffer
);
1407 for (i
= 0; i
< count
; i
++)
1409 target_buffer_set_u32(target
, b
, pattern
);
1413 err
= dsp563xx_write_memory(target
, mem_type
, address
, sizeof(uint32_t), count
, buffer
);
1421 static const struct command_registration dsp563xx_command_handlers
[] = {
1424 .handler
= dsp563xx_mem_command
,
1425 .mode
= COMMAND_EXEC
,
1426 .help
= "write x memory words",
1427 .usage
= "mwwx address value [count]",
1431 .handler
= dsp563xx_mem_command
,
1432 .mode
= COMMAND_EXEC
,
1433 .help
= "write y memory words",
1434 .usage
= "mwwy address value [count]",
1438 .handler
= dsp563xx_mem_command
,
1439 .mode
= COMMAND_EXEC
,
1440 .help
= "write p memory words",
1441 .usage
= "mwwp address value [count]",
1445 .handler
= dsp563xx_mem_command
,
1446 .mode
= COMMAND_EXEC
,
1447 .help
= "display x memory words",
1448 .usage
= "mdwx address [count]",
1452 .handler
= dsp563xx_mem_command
,
1453 .mode
= COMMAND_EXEC
,
1454 .help
= "display y memory words",
1455 .usage
= "mdwy address [count]",
1459 .handler
= dsp563xx_mem_command
,
1460 .mode
= COMMAND_EXEC
,
1461 .help
= "display p memory words",
1462 .usage
= "mdwp address [count]",
1464 COMMAND_REGISTRATION_DONE
1467 /** Holds methods for DSP563XX targets. */
1468 struct target_type dsp563xx_target
= {
1471 .poll
= dsp563xx_poll
,
1472 .arch_state
= dsp563xx_arch_state
,
1474 .target_request_data
= NULL
,
1476 .get_gdb_reg_list
= dsp563xx_get_gdb_reg_list
,
1478 .halt
= dsp563xx_halt
,
1479 .resume
= dsp563xx_resume
,
1480 .step
= dsp563xx_step
,
1482 .assert_reset
= dsp563xx_assert_reset
,
1483 .deassert_reset
= dsp563xx_deassert_reset
,
1484 .soft_reset_halt
= dsp563xx_soft_reset_halt
,
1486 .read_memory
= dsp563xx_read_memory_p
,
1487 .write_memory
= dsp563xx_write_memory_p
,
1489 .commands
= dsp563xx_command_handlers
,
1490 .target_create
= dsp563xx_target_create
,
1491 .init_target
= dsp563xx_init_target
,
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