1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include <helper/log.h>
12 #include <helper/time_support.h>
13 #include "target/target.h"
14 #include "target/algorithm.h"
15 #include "target/target_type.h"
16 #include <target/smp.h>
17 #include "jtag/jtag.h"
18 #include "target/register.h"
19 #include "target/breakpoints.h"
22 #include "rtos/rtos.h"
23 #include "debug_defines.h"
24 #include <helper/bits.h>
26 #define get_field(reg, mask) (((reg) & (mask)) / ((mask) & ~((mask) << 1)))
27 #define set_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))
29 /* Constants for legacy SiFive hardware breakpoints. */
30 #define CSR_BPCONTROL_X (1<<0)
31 #define CSR_BPCONTROL_W (1<<1)
32 #define CSR_BPCONTROL_R (1<<2)
33 #define CSR_BPCONTROL_U (1<<3)
34 #define CSR_BPCONTROL_S (1<<4)
35 #define CSR_BPCONTROL_H (1<<5)
36 #define CSR_BPCONTROL_M (1<<6)
37 #define CSR_BPCONTROL_BPMATCH (0xf<<7)
38 #define CSR_BPCONTROL_BPACTION (0xff<<11)
40 #define DEBUG_ROM_START 0x800
41 #define DEBUG_ROM_RESUME (DEBUG_ROM_START + 4)
42 #define DEBUG_ROM_EXCEPTION (DEBUG_ROM_START + 8)
43 #define DEBUG_RAM_START 0x400
45 #define SETHALTNOT 0x10c
47 /*** JTAG registers. ***/
49 #define DTMCONTROL 0x10
50 #define DTMCONTROL_DBUS_RESET (1<<16)
51 #define DTMCONTROL_IDLE (7<<10)
52 #define DTMCONTROL_ADDRBITS (0xf<<4)
53 #define DTMCONTROL_VERSION (0xf)
56 #define DBUS_OP_START 0
57 #define DBUS_OP_SIZE 2
64 DBUS_STATUS_SUCCESS
= 0,
65 DBUS_STATUS_FAILED
= 2,
68 #define DBUS_DATA_START 2
69 #define DBUS_DATA_SIZE 34
70 #define DBUS_ADDRESS_START 36
78 /*** Debug Bus registers. ***/
80 #define DMCONTROL 0x10
81 #define DMCONTROL_INTERRUPT (((uint64_t)1)<<33)
82 #define DMCONTROL_HALTNOT (((uint64_t)1)<<32)
83 #define DMCONTROL_BUSERROR (7<<19)
84 #define DMCONTROL_SERIAL (3<<16)
85 #define DMCONTROL_AUTOINCREMENT (1<<15)
86 #define DMCONTROL_ACCESS (7<<12)
87 #define DMCONTROL_HARTID (0x3ff<<2)
88 #define DMCONTROL_NDRESET (1<<1)
89 #define DMCONTROL_FULLRESET 1
92 #define DMINFO_ABUSSIZE (0x7fU<<25)
93 #define DMINFO_SERIALCOUNT (0xf<<21)
94 #define DMINFO_ACCESS128 (1<<20)
95 #define DMINFO_ACCESS64 (1<<19)
96 #define DMINFO_ACCESS32 (1<<18)
97 #define DMINFO_ACCESS16 (1<<17)
98 #define DMINFO_ACCESS8 (1<<16)
99 #define DMINFO_DRAMSIZE (0x3f<<10)
100 #define DMINFO_AUTHENTICATED (1<<5)
101 #define DMINFO_AUTHBUSY (1<<4)
102 #define DMINFO_AUTHTYPE (3<<2)
103 #define DMINFO_VERSION 3
105 /*** Info about the core being debugged. ***/
107 #define DBUS_ADDRESS_UNKNOWN 0xffff
110 #define DRAM_CACHE_SIZE 16
112 static uint8_t ir_dtmcontrol
[4] = {DTMCONTROL
};
113 struct scan_field select_dtmcontrol
= {
115 .out_value
= ir_dtmcontrol
117 static uint8_t ir_dbus
[4] = {DBUS
};
118 struct scan_field select_dbus
= {
122 static uint8_t ir_idcode
[4] = {0x1};
123 struct scan_field select_idcode
= {
125 .out_value
= ir_idcode
128 static bscan_tunnel_type_t bscan_tunnel_type
;
129 int bscan_tunnel_ir_width
; /* if zero, then tunneling is not present/active */
131 static const uint8_t bscan_zero
[4] = {0};
132 static const uint8_t bscan_one
[4] = {1};
134 static uint8_t ir_user4
[4];
135 static struct scan_field select_user4
= {
137 .out_value
= ir_user4
141 static uint8_t bscan_tunneled_ir_width
[4] = {5}; /* overridden by assignment in riscv_init_target */
142 static struct scan_field _bscan_tunnel_data_register_select_dmi
[] = {
145 .out_value
= bscan_zero
,
149 .num_bits
= 5, /* initialized in riscv_init_target to ir width of DM */
150 .out_value
= ir_dbus
,
155 .out_value
= bscan_tunneled_ir_width
,
160 .out_value
= bscan_zero
,
165 static struct scan_field _bscan_tunnel_nested_tap_select_dmi
[] = {
168 .out_value
= bscan_zero
,
173 .out_value
= bscan_tunneled_ir_width
,
177 .num_bits
= 0, /* initialized in riscv_init_target to ir width of DM */
178 .out_value
= ir_dbus
,
183 .out_value
= bscan_zero
,
187 static struct scan_field
*bscan_tunnel_nested_tap_select_dmi
= _bscan_tunnel_nested_tap_select_dmi
;
188 static uint32_t bscan_tunnel_nested_tap_select_dmi_num_fields
= ARRAY_SIZE(_bscan_tunnel_nested_tap_select_dmi
);
190 static struct scan_field
*bscan_tunnel_data_register_select_dmi
= _bscan_tunnel_data_register_select_dmi
;
191 static uint32_t bscan_tunnel_data_register_select_dmi_num_fields
= ARRAY_SIZE(_bscan_tunnel_data_register_select_dmi
);
198 bool read
, write
, execute
;
202 /* Wall-clock timeout for a command/access. Settable via RISC-V Target commands.*/
203 int riscv_command_timeout_sec
= DEFAULT_COMMAND_TIMEOUT_SEC
;
205 /* Wall-clock timeout after reset. Settable via RISC-V Target commands.*/
206 int riscv_reset_timeout_sec
= DEFAULT_RESET_TIMEOUT_SEC
;
208 static bool riscv_enable_virt2phys
= true;
209 bool riscv_ebreakm
= true;
210 bool riscv_ebreaks
= true;
211 bool riscv_ebreaku
= true;
213 bool riscv_enable_virtual
;
220 static const virt2phys_info_t sv32
= {
225 .vpn_shift
= {12, 22},
226 .vpn_mask
= {0x3ff, 0x3ff},
227 .pte_ppn_shift
= {10, 20},
228 .pte_ppn_mask
= {0x3ff, 0xfff},
229 .pa_ppn_shift
= {12, 22},
230 .pa_ppn_mask
= {0x3ff, 0xfff},
233 static const virt2phys_info_t sv39
= {
238 .vpn_shift
= {12, 21, 30},
239 .vpn_mask
= {0x1ff, 0x1ff, 0x1ff},
240 .pte_ppn_shift
= {10, 19, 28},
241 .pte_ppn_mask
= {0x1ff, 0x1ff, 0x3ffffff},
242 .pa_ppn_shift
= {12, 21, 30},
243 .pa_ppn_mask
= {0x1ff, 0x1ff, 0x3ffffff},
246 static const virt2phys_info_t sv48
= {
251 .vpn_shift
= {12, 21, 30, 39},
252 .vpn_mask
= {0x1ff, 0x1ff, 0x1ff, 0x1ff},
253 .pte_ppn_shift
= {10, 19, 28, 37},
254 .pte_ppn_mask
= {0x1ff, 0x1ff, 0x1ff, 0x1ffff},
255 .pa_ppn_shift
= {12, 21, 30, 39},
256 .pa_ppn_mask
= {0x1ff, 0x1ff, 0x1ff, 0x1ffff},
259 static enum riscv_halt_reason
riscv_halt_reason(struct target
*target
, int hartid
);
260 static void riscv_info_init(struct target
*target
, struct riscv_info
*r
);
261 static void riscv_invalidate_register_cache(struct target
*target
);
262 static int riscv_step_rtos_hart(struct target
*target
);
264 static void riscv_sample_buf_maybe_add_timestamp(struct target
*target
, bool before
)
267 uint32_t now
= timeval_ms() & 0xffffffff;
268 if (r
->sample_buf
.used
+ 5 < r
->sample_buf
.size
) {
270 r
->sample_buf
.buf
[r
->sample_buf
.used
++] = RISCV_SAMPLE_BUF_TIMESTAMP_BEFORE
;
272 r
->sample_buf
.buf
[r
->sample_buf
.used
++] = RISCV_SAMPLE_BUF_TIMESTAMP_AFTER
;
273 r
->sample_buf
.buf
[r
->sample_buf
.used
++] = now
& 0xff;
274 r
->sample_buf
.buf
[r
->sample_buf
.used
++] = (now
>> 8) & 0xff;
275 r
->sample_buf
.buf
[r
->sample_buf
.used
++] = (now
>> 16) & 0xff;
276 r
->sample_buf
.buf
[r
->sample_buf
.used
++] = (now
>> 24) & 0xff;
280 static int riscv_resume_go_all_harts(struct target
*target
);
282 void select_dmi_via_bscan(struct target
*target
)
284 jtag_add_ir_scan(target
->tap
, &select_user4
, TAP_IDLE
);
285 if (bscan_tunnel_type
== BSCAN_TUNNEL_DATA_REGISTER
)
286 jtag_add_dr_scan(target
->tap
, bscan_tunnel_data_register_select_dmi_num_fields
,
287 bscan_tunnel_data_register_select_dmi
, TAP_IDLE
);
288 else /* BSCAN_TUNNEL_NESTED_TAP */
289 jtag_add_dr_scan(target
->tap
, bscan_tunnel_nested_tap_select_dmi_num_fields
,
290 bscan_tunnel_nested_tap_select_dmi
, TAP_IDLE
);
293 uint32_t dtmcontrol_scan_via_bscan(struct target
*target
, uint32_t out
)
295 /* On BSCAN TAP: Select IR=USER4, issue tunneled IR scan via BSCAN TAP's DR */
296 uint8_t tunneled_ir_width
[4] = {bscan_tunnel_ir_width
};
297 uint8_t tunneled_dr_width
[4] = {32};
298 uint8_t out_value
[5] = {0};
299 uint8_t in_value
[5] = {0};
301 buf_set_u32(out_value
, 0, 32, out
);
302 struct scan_field tunneled_ir
[4] = {};
303 struct scan_field tunneled_dr
[4] = {};
305 if (bscan_tunnel_type
== BSCAN_TUNNEL_DATA_REGISTER
) {
306 tunneled_ir
[0].num_bits
= 3;
307 tunneled_ir
[0].out_value
= bscan_zero
;
308 tunneled_ir
[0].in_value
= NULL
;
309 tunneled_ir
[1].num_bits
= bscan_tunnel_ir_width
;
310 tunneled_ir
[1].out_value
= ir_dtmcontrol
;
311 tunneled_ir
[1].in_value
= NULL
;
312 tunneled_ir
[2].num_bits
= 7;
313 tunneled_ir
[2].out_value
= tunneled_ir_width
;
314 tunneled_ir
[2].in_value
= NULL
;
315 tunneled_ir
[3].num_bits
= 1;
316 tunneled_ir
[3].out_value
= bscan_zero
;
317 tunneled_ir
[3].in_value
= NULL
;
319 tunneled_dr
[0].num_bits
= 3;
320 tunneled_dr
[0].out_value
= bscan_zero
;
321 tunneled_dr
[0].in_value
= NULL
;
322 tunneled_dr
[1].num_bits
= 32 + 1;
323 tunneled_dr
[1].out_value
= out_value
;
324 tunneled_dr
[1].in_value
= in_value
;
325 tunneled_dr
[2].num_bits
= 7;
326 tunneled_dr
[2].out_value
= tunneled_dr_width
;
327 tunneled_dr
[2].in_value
= NULL
;
328 tunneled_dr
[3].num_bits
= 1;
329 tunneled_dr
[3].out_value
= bscan_one
;
330 tunneled_dr
[3].in_value
= NULL
;
332 /* BSCAN_TUNNEL_NESTED_TAP */
333 tunneled_ir
[3].num_bits
= 3;
334 tunneled_ir
[3].out_value
= bscan_zero
;
335 tunneled_ir
[3].in_value
= NULL
;
336 tunneled_ir
[2].num_bits
= bscan_tunnel_ir_width
;
337 tunneled_ir
[2].out_value
= ir_dtmcontrol
;
338 tunneled_ir
[1].in_value
= NULL
;
339 tunneled_ir
[1].num_bits
= 7;
340 tunneled_ir
[1].out_value
= tunneled_ir_width
;
341 tunneled_ir
[2].in_value
= NULL
;
342 tunneled_ir
[0].num_bits
= 1;
343 tunneled_ir
[0].out_value
= bscan_zero
;
344 tunneled_ir
[0].in_value
= NULL
;
346 tunneled_dr
[3].num_bits
= 3;
347 tunneled_dr
[3].out_value
= bscan_zero
;
348 tunneled_dr
[3].in_value
= NULL
;
349 tunneled_dr
[2].num_bits
= 32 + 1;
350 tunneled_dr
[2].out_value
= out_value
;
351 tunneled_dr
[2].in_value
= in_value
;
352 tunneled_dr
[1].num_bits
= 7;
353 tunneled_dr
[1].out_value
= tunneled_dr_width
;
354 tunneled_dr
[1].in_value
= NULL
;
355 tunneled_dr
[0].num_bits
= 1;
356 tunneled_dr
[0].out_value
= bscan_one
;
357 tunneled_dr
[0].in_value
= NULL
;
359 jtag_add_ir_scan(target
->tap
, &select_user4
, TAP_IDLE
);
360 jtag_add_dr_scan(target
->tap
, ARRAY_SIZE(tunneled_ir
), tunneled_ir
, TAP_IDLE
);
361 jtag_add_dr_scan(target
->tap
, ARRAY_SIZE(tunneled_dr
), tunneled_dr
, TAP_IDLE
);
362 select_dmi_via_bscan(target
);
364 int retval
= jtag_execute_queue();
365 if (retval
!= ERROR_OK
) {
366 LOG_ERROR("failed jtag scan: %d", retval
);
369 /* Note the starting offset is bit 1, not bit 0. In BSCAN tunnel, there is a one-bit TCK skew between
371 uint32_t in
= buf_get_u32(in_value
, 1, 32);
372 LOG_DEBUG("DTMCS: 0x%x -> 0x%x", out
, in
);
377 static uint32_t dtmcontrol_scan(struct target
*target
, uint32_t out
)
379 struct scan_field field
;
381 uint8_t out_value
[4] = { 0 };
383 if (bscan_tunnel_ir_width
!= 0)
384 return dtmcontrol_scan_via_bscan(target
, out
);
387 buf_set_u32(out_value
, 0, 32, out
);
389 jtag_add_ir_scan(target
->tap
, &select_dtmcontrol
, TAP_IDLE
);
392 field
.out_value
= out_value
;
393 field
.in_value
= in_value
;
394 jtag_add_dr_scan(target
->tap
, 1, &field
, TAP_IDLE
);
396 /* Always return to dbus. */
397 jtag_add_ir_scan(target
->tap
, &select_dbus
, TAP_IDLE
);
399 int retval
= jtag_execute_queue();
400 if (retval
!= ERROR_OK
) {
401 LOG_ERROR("failed jtag scan: %d", retval
);
405 uint32_t in
= buf_get_u32(field
.in_value
, 0, 32);
406 LOG_DEBUG("DTMCONTROL: 0x%x -> 0x%x", out
, in
);
411 static struct target_type
*get_target_type(struct target
*target
)
413 if (!target
->arch_info
) {
414 LOG_ERROR("Target has not been initialized");
419 switch (info
->dtm_version
) {
421 return &riscv011_target
;
423 return &riscv013_target
;
425 LOG_ERROR("Unsupported DTM version: %d", info
->dtm_version
);
430 static int riscv_create_target(struct target
*target
, Jim_Interp
*interp
)
432 LOG_DEBUG("riscv_create_target()");
433 target
->arch_info
= calloc(1, sizeof(struct riscv_info
));
434 if (!target
->arch_info
) {
435 LOG_ERROR("Failed to allocate RISC-V target structure.");
438 riscv_info_init(target
, target
->arch_info
);
442 static int riscv_init_target(struct command_context
*cmd_ctx
,
443 struct target
*target
)
445 LOG_DEBUG("riscv_init_target()");
447 info
->cmd_ctx
= cmd_ctx
;
449 select_dtmcontrol
.num_bits
= target
->tap
->ir_length
;
450 select_dbus
.num_bits
= target
->tap
->ir_length
;
451 select_idcode
.num_bits
= target
->tap
->ir_length
;
453 if (bscan_tunnel_ir_width
!= 0) {
454 assert(target
->tap
->ir_length
>= 6);
455 uint32_t ir_user4_raw
= 0x23 << (target
->tap
->ir_length
- 6);
456 h_u32_to_le(ir_user4
, ir_user4_raw
);
457 select_user4
.num_bits
= target
->tap
->ir_length
;
458 bscan_tunneled_ir_width
[0] = bscan_tunnel_ir_width
;
459 if (bscan_tunnel_type
== BSCAN_TUNNEL_DATA_REGISTER
)
460 bscan_tunnel_data_register_select_dmi
[1].num_bits
= bscan_tunnel_ir_width
;
461 else /* BSCAN_TUNNEL_NESTED_TAP */
462 bscan_tunnel_nested_tap_select_dmi
[2].num_bits
= bscan_tunnel_ir_width
;
465 riscv_semihosting_init(target
);
467 target
->debug_reason
= DBG_REASON_DBGRQ
;
472 static void riscv_free_registers(struct target
*target
)
474 /* Free the shared structure use for most registers. */
475 if (target
->reg_cache
) {
476 if (target
->reg_cache
->reg_list
) {
477 free(target
->reg_cache
->reg_list
[0].arch_info
);
478 /* Free the ones we allocated separately. */
479 for (unsigned i
= GDB_REGNO_COUNT
; i
< target
->reg_cache
->num_regs
; i
++)
480 free(target
->reg_cache
->reg_list
[i
].arch_info
);
481 for (unsigned int i
= 0; i
< target
->reg_cache
->num_regs
; i
++)
482 free(target
->reg_cache
->reg_list
[i
].value
);
483 free(target
->reg_cache
->reg_list
);
485 free(target
->reg_cache
);
489 static void riscv_deinit_target(struct target
*target
)
491 LOG_DEBUG("riscv_deinit_target()");
493 struct riscv_info
*info
= target
->arch_info
;
494 struct target_type
*tt
= get_target_type(target
);
496 if (tt
&& info
&& info
->version_specific
)
497 tt
->deinit_target(target
);
499 riscv_free_registers(target
);
504 range_list_t
*entry
, *tmp
;
505 list_for_each_entry_safe(entry
, tmp
, &info
->expose_csr
, list
) {
510 list_for_each_entry_safe(entry
, tmp
, &info
->expose_custom
, list
) {
515 free(info
->reg_names
);
516 free(target
->arch_info
);
518 target
->arch_info
= NULL
;
521 static void trigger_from_breakpoint(struct trigger
*trigger
,
522 const struct breakpoint
*breakpoint
)
524 trigger
->address
= breakpoint
->address
;
525 trigger
->length
= breakpoint
->length
;
526 trigger
->mask
= ~0LL;
527 trigger
->read
= false;
528 trigger
->write
= false;
529 trigger
->execute
= true;
530 /* unique_id is unique across both breakpoints and watchpoints. */
531 trigger
->unique_id
= breakpoint
->unique_id
;
534 static int maybe_add_trigger_t1(struct target
*target
,
535 struct trigger
*trigger
, uint64_t tdata1
)
539 const uint32_t bpcontrol_x
= 1<<0;
540 const uint32_t bpcontrol_w
= 1<<1;
541 const uint32_t bpcontrol_r
= 1<<2;
542 const uint32_t bpcontrol_u
= 1<<3;
543 const uint32_t bpcontrol_s
= 1<<4;
544 const uint32_t bpcontrol_h
= 1<<5;
545 const uint32_t bpcontrol_m
= 1<<6;
546 const uint32_t bpcontrol_bpmatch
= 0xf << 7;
547 const uint32_t bpcontrol_bpaction
= 0xff << 11;
549 if (tdata1
& (bpcontrol_r
| bpcontrol_w
| bpcontrol_x
)) {
550 /* Trigger is already in use, presumably by user code. */
551 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
554 tdata1
= set_field(tdata1
, bpcontrol_r
, trigger
->read
);
555 tdata1
= set_field(tdata1
, bpcontrol_w
, trigger
->write
);
556 tdata1
= set_field(tdata1
, bpcontrol_x
, trigger
->execute
);
557 tdata1
= set_field(tdata1
, bpcontrol_u
,
558 !!(r
->misa
& BIT('U' - 'A')));
559 tdata1
= set_field(tdata1
, bpcontrol_s
,
560 !!(r
->misa
& BIT('S' - 'A')));
561 tdata1
= set_field(tdata1
, bpcontrol_h
,
562 !!(r
->misa
& BIT('H' - 'A')));
563 tdata1
|= bpcontrol_m
;
564 tdata1
= set_field(tdata1
, bpcontrol_bpmatch
, 0); /* exact match */
565 tdata1
= set_field(tdata1
, bpcontrol_bpaction
, 0); /* cause bp exception */
567 riscv_set_register(target
, GDB_REGNO_TDATA1
, tdata1
);
569 riscv_reg_t tdata1_rb
;
570 if (riscv_get_register(target
, &tdata1_rb
, GDB_REGNO_TDATA1
) != ERROR_OK
)
572 LOG_DEBUG("tdata1=0x%" PRIx64
, tdata1_rb
);
574 if (tdata1
!= tdata1_rb
) {
575 LOG_DEBUG("Trigger doesn't support what we need; After writing 0x%"
576 PRIx64
" to tdata1 it contains 0x%" PRIx64
,
578 riscv_set_register(target
, GDB_REGNO_TDATA1
, 0);
579 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
582 riscv_set_register(target
, GDB_REGNO_TDATA2
, trigger
->address
);
587 static int maybe_add_trigger_t2(struct target
*target
,
588 struct trigger
*trigger
, uint64_t tdata1
)
592 /* tselect is already set */
593 if (tdata1
& (MCONTROL_EXECUTE
| MCONTROL_STORE
| MCONTROL_LOAD
)) {
594 /* Trigger is already in use, presumably by user code. */
595 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
598 /* address/data match trigger */
599 tdata1
|= MCONTROL_DMODE(riscv_xlen(target
));
600 tdata1
= set_field(tdata1
, MCONTROL_ACTION
,
601 MCONTROL_ACTION_DEBUG_MODE
);
602 tdata1
= set_field(tdata1
, MCONTROL_MATCH
, MCONTROL_MATCH_EQUAL
);
603 tdata1
|= MCONTROL_M
;
604 if (r
->misa
& (1 << ('S' - 'A')))
605 tdata1
|= MCONTROL_S
;
606 if (r
->misa
& (1 << ('U' - 'A')))
607 tdata1
|= MCONTROL_U
;
609 if (trigger
->execute
)
610 tdata1
|= MCONTROL_EXECUTE
;
612 tdata1
|= MCONTROL_LOAD
;
614 tdata1
|= MCONTROL_STORE
;
616 riscv_set_register(target
, GDB_REGNO_TDATA1
, tdata1
);
619 int result
= riscv_get_register(target
, &tdata1_rb
, GDB_REGNO_TDATA1
);
620 if (result
!= ERROR_OK
)
622 LOG_DEBUG("tdata1=0x%" PRIx64
, tdata1_rb
);
624 if (tdata1
!= tdata1_rb
) {
625 LOG_DEBUG("Trigger doesn't support what we need; After writing 0x%"
626 PRIx64
" to tdata1 it contains 0x%" PRIx64
,
628 riscv_set_register(target
, GDB_REGNO_TDATA1
, 0);
629 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
632 riscv_set_register(target
, GDB_REGNO_TDATA2
, trigger
->address
);
637 static int maybe_add_trigger_t6(struct target
*target
,
638 struct trigger
*trigger
, uint64_t tdata1
)
642 /* tselect is already set */
643 if (tdata1
& (CSR_MCONTROL6_EXECUTE
| CSR_MCONTROL6_STORE
| CSR_MCONTROL6_LOAD
)) {
644 /* Trigger is already in use, presumably by user code. */
645 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
648 /* address/data match trigger */
649 tdata1
|= MCONTROL_DMODE(riscv_xlen(target
));
650 tdata1
= set_field(tdata1
, CSR_MCONTROL6_ACTION
,
651 MCONTROL_ACTION_DEBUG_MODE
);
652 tdata1
= set_field(tdata1
, CSR_MCONTROL6_MATCH
, MCONTROL_MATCH_EQUAL
);
653 tdata1
|= CSR_MCONTROL6_M
;
654 if (r
->misa
& (1 << ('H' - 'A')))
655 tdata1
|= CSR_MCONTROL6_VS
| CSR_MCONTROL6_VU
;
656 if (r
->misa
& (1 << ('S' - 'A')))
657 tdata1
|= CSR_MCONTROL6_S
;
658 if (r
->misa
& (1 << ('U' - 'A')))
659 tdata1
|= CSR_MCONTROL6_U
;
661 if (trigger
->execute
)
662 tdata1
|= CSR_MCONTROL6_EXECUTE
;
664 tdata1
|= CSR_MCONTROL6_LOAD
;
666 tdata1
|= CSR_MCONTROL6_STORE
;
668 riscv_set_register(target
, GDB_REGNO_TDATA1
, tdata1
);
671 int result
= riscv_get_register(target
, &tdata1_rb
, GDB_REGNO_TDATA1
);
672 if (result
!= ERROR_OK
)
674 LOG_DEBUG("tdata1=0x%" PRIx64
, tdata1_rb
);
676 if (tdata1
!= tdata1_rb
) {
677 LOG_DEBUG("Trigger doesn't support what we need; After writing 0x%"
678 PRIx64
" to tdata1 it contains 0x%" PRIx64
,
680 riscv_set_register(target
, GDB_REGNO_TDATA1
, 0);
681 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
684 riscv_set_register(target
, GDB_REGNO_TDATA2
, trigger
->address
);
689 static int add_trigger(struct target
*target
, struct trigger
*trigger
)
693 if (riscv_enumerate_triggers(target
) != ERROR_OK
)
697 if (riscv_get_register(target
, &tselect
, GDB_REGNO_TSELECT
) != ERROR_OK
)
701 for (i
= 0; i
< r
->trigger_count
; i
++) {
702 if (r
->trigger_unique_id
[i
] != -1)
705 riscv_set_register(target
, GDB_REGNO_TSELECT
, i
);
708 int result
= riscv_get_register(target
, &tdata1
, GDB_REGNO_TDATA1
);
709 if (result
!= ERROR_OK
)
711 int type
= get_field(tdata1
, MCONTROL_TYPE(riscv_xlen(target
)));
715 result
= maybe_add_trigger_t1(target
, trigger
, tdata1
);
718 result
= maybe_add_trigger_t2(target
, trigger
, tdata1
);
721 result
= maybe_add_trigger_t6(target
, trigger
, tdata1
);
724 LOG_DEBUG("trigger %d has unknown type %d", i
, type
);
728 if (result
!= ERROR_OK
)
731 LOG_DEBUG("[%d] Using trigger %d (type %d) for bp %d", target
->coreid
,
732 i
, type
, trigger
->unique_id
);
733 r
->trigger_unique_id
[i
] = trigger
->unique_id
;
737 riscv_set_register(target
, GDB_REGNO_TSELECT
, tselect
);
739 if (i
>= r
->trigger_count
) {
740 LOG_ERROR("Couldn't find an available hardware trigger.");
741 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
748 * Write one memory item of given "size". Use memory access of given "access_size".
749 * Utilize read-modify-write, if needed.
751 static int write_by_given_size(struct target
*target
, target_addr_t address
,
752 uint32_t size
, uint8_t *buffer
, uint32_t access_size
)
754 assert(size
== 1 || size
== 2 || size
== 4 || size
== 8);
755 assert(access_size
== 1 || access_size
== 2 || access_size
== 4 || access_size
== 8);
757 if (access_size
<= size
&& address
% access_size
== 0)
758 /* Can do the memory access directly without a helper buffer. */
759 return target_write_memory(target
, address
, access_size
, size
/ access_size
, buffer
);
761 unsigned int offset_head
= address
% access_size
;
762 unsigned int n_blocks
= ((size
+ offset_head
) <= access_size
) ? 1 : 2;
763 uint8_t helper_buf
[n_blocks
* access_size
];
765 /* Read from memory */
766 if (target_read_memory(target
, address
- offset_head
, access_size
, n_blocks
, helper_buf
) != ERROR_OK
)
769 /* Modify and write back */
770 memcpy(helper_buf
+ offset_head
, buffer
, size
);
771 return target_write_memory(target
, address
- offset_head
, access_size
, n_blocks
, helper_buf
);
775 * Read one memory item of given "size". Use memory access of given "access_size".
776 * Read larger section of memory and pick out the required portion, if needed.
778 static int read_by_given_size(struct target
*target
, target_addr_t address
,
779 uint32_t size
, uint8_t *buffer
, uint32_t access_size
)
781 assert(size
== 1 || size
== 2 || size
== 4 || size
== 8);
782 assert(access_size
== 1 || access_size
== 2 || access_size
== 4 || access_size
== 8);
784 if (access_size
<= size
&& address
% access_size
== 0)
785 /* Can do the memory access directly without a helper buffer. */
786 return target_read_memory(target
, address
, access_size
, size
/ access_size
, buffer
);
788 unsigned int offset_head
= address
% access_size
;
789 unsigned int n_blocks
= ((size
+ offset_head
) <= access_size
) ? 1 : 2;
790 uint8_t helper_buf
[n_blocks
* access_size
];
792 /* Read from memory */
793 if (target_read_memory(target
, address
- offset_head
, access_size
, n_blocks
, helper_buf
) != ERROR_OK
)
796 /* Pick the requested portion from the buffer */
797 memcpy(buffer
, helper_buf
+ offset_head
, size
);
802 * Write one memory item using any memory access size that will work.
803 * Utilize read-modify-write, if needed.
805 int riscv_write_by_any_size(struct target
*target
, target_addr_t address
, uint32_t size
, uint8_t *buffer
)
807 assert(size
== 1 || size
== 2 || size
== 4 || size
== 8);
809 /* Find access size that correspond to data size and the alignment. */
810 unsigned int preferred_size
= size
;
811 while (address
% preferred_size
!= 0)
814 /* First try the preferred (most natural) access size. */
815 if (write_by_given_size(target
, address
, size
, buffer
, preferred_size
) == ERROR_OK
)
818 /* On failure, try other access sizes.
819 Minimize the number of accesses by trying first the largest size. */
820 for (unsigned int access_size
= 8; access_size
> 0; access_size
/= 2) {
821 if (access_size
== preferred_size
)
822 /* Already tried this size. */
825 if (write_by_given_size(target
, address
, size
, buffer
, access_size
) == ERROR_OK
)
829 /* No access attempt succeeded. */
834 * Read one memory item using any memory access size that will work.
835 * Read larger section of memory and pick out the required portion, if needed.
837 int riscv_read_by_any_size(struct target
*target
, target_addr_t address
, uint32_t size
, uint8_t *buffer
)
839 assert(size
== 1 || size
== 2 || size
== 4 || size
== 8);
841 /* Find access size that correspond to data size and the alignment. */
842 unsigned int preferred_size
= size
;
843 while (address
% preferred_size
!= 0)
846 /* First try the preferred (most natural) access size. */
847 if (read_by_given_size(target
, address
, size
, buffer
, preferred_size
) == ERROR_OK
)
850 /* On failure, try other access sizes.
851 Minimize the number of accesses by trying first the largest size. */
852 for (unsigned int access_size
= 8; access_size
> 0; access_size
/= 2) {
853 if (access_size
== preferred_size
)
854 /* Already tried this size. */
857 if (read_by_given_size(target
, address
, size
, buffer
, access_size
) == ERROR_OK
)
861 /* No access attempt succeeded. */
865 static int riscv_add_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
867 LOG_DEBUG("[%d] @0x%" TARGET_PRIxADDR
, target
->coreid
, breakpoint
->address
);
869 if (breakpoint
->type
== BKPT_SOFT
) {
870 /** @todo check RVC for size/alignment */
871 if (!(breakpoint
->length
== 4 || breakpoint
->length
== 2)) {
872 LOG_ERROR("Invalid breakpoint length %d", breakpoint
->length
);
876 if (0 != (breakpoint
->address
% 2)) {
877 LOG_ERROR("Invalid breakpoint alignment for address 0x%" TARGET_PRIxADDR
, breakpoint
->address
);
881 /* Read the original instruction. */
882 if (riscv_read_by_any_size(
883 target
, breakpoint
->address
, breakpoint
->length
, breakpoint
->orig_instr
) != ERROR_OK
) {
884 LOG_ERROR("Failed to read original instruction at 0x%" TARGET_PRIxADDR
,
885 breakpoint
->address
);
889 uint8_t buff
[4] = { 0 };
890 buf_set_u32(buff
, 0, breakpoint
->length
* CHAR_BIT
, breakpoint
->length
== 4 ? ebreak() : ebreak_c());
891 /* Write the ebreak instruction. */
892 if (riscv_write_by_any_size(target
, breakpoint
->address
, breakpoint
->length
, buff
) != ERROR_OK
) {
893 LOG_ERROR("Failed to write %d-byte breakpoint instruction at 0x%"
894 TARGET_PRIxADDR
, breakpoint
->length
, breakpoint
->address
);
898 } else if (breakpoint
->type
== BKPT_HARD
) {
899 struct trigger trigger
;
900 trigger_from_breakpoint(&trigger
, breakpoint
);
901 int const result
= add_trigger(target
, &trigger
);
902 if (result
!= ERROR_OK
)
905 LOG_INFO("OpenOCD only supports hardware and software breakpoints.");
906 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
909 breakpoint
->is_set
= true;
913 static int remove_trigger(struct target
*target
, struct trigger
*trigger
)
917 if (riscv_enumerate_triggers(target
) != ERROR_OK
)
921 for (i
= 0; i
< r
->trigger_count
; i
++) {
922 if (r
->trigger_unique_id
[i
] == trigger
->unique_id
)
925 if (i
>= r
->trigger_count
) {
926 LOG_ERROR("Couldn't find the hardware resources used by hardware "
930 LOG_DEBUG("[%d] Stop using resource %d for bp %d", target
->coreid
, i
,
934 int result
= riscv_get_register(target
, &tselect
, GDB_REGNO_TSELECT
);
935 if (result
!= ERROR_OK
)
937 riscv_set_register(target
, GDB_REGNO_TSELECT
, i
);
938 riscv_set_register(target
, GDB_REGNO_TDATA1
, 0);
939 riscv_set_register(target
, GDB_REGNO_TSELECT
, tselect
);
940 r
->trigger_unique_id
[i
] = -1;
945 static int riscv_remove_breakpoint(struct target
*target
,
946 struct breakpoint
*breakpoint
)
948 if (breakpoint
->type
== BKPT_SOFT
) {
949 /* Write the original instruction. */
950 if (riscv_write_by_any_size(
951 target
, breakpoint
->address
, breakpoint
->length
, breakpoint
->orig_instr
) != ERROR_OK
) {
952 LOG_ERROR("Failed to restore instruction for %d-byte breakpoint at "
953 "0x%" TARGET_PRIxADDR
, breakpoint
->length
, breakpoint
->address
);
957 } else if (breakpoint
->type
== BKPT_HARD
) {
958 struct trigger trigger
;
959 trigger_from_breakpoint(&trigger
, breakpoint
);
960 int result
= remove_trigger(target
, &trigger
);
961 if (result
!= ERROR_OK
)
965 LOG_INFO("OpenOCD only supports hardware and software breakpoints.");
966 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
969 breakpoint
->is_set
= false;
974 static void trigger_from_watchpoint(struct trigger
*trigger
,
975 const struct watchpoint
*watchpoint
)
977 trigger
->address
= watchpoint
->address
;
978 trigger
->length
= watchpoint
->length
;
979 trigger
->mask
= watchpoint
->mask
;
980 trigger
->value
= watchpoint
->value
;
981 trigger
->read
= (watchpoint
->rw
== WPT_READ
|| watchpoint
->rw
== WPT_ACCESS
);
982 trigger
->write
= (watchpoint
->rw
== WPT_WRITE
|| watchpoint
->rw
== WPT_ACCESS
);
983 trigger
->execute
= false;
984 /* unique_id is unique across both breakpoints and watchpoints. */
985 trigger
->unique_id
= watchpoint
->unique_id
;
988 int riscv_add_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
990 struct trigger trigger
;
991 trigger_from_watchpoint(&trigger
, watchpoint
);
993 int result
= add_trigger(target
, &trigger
);
994 if (result
!= ERROR_OK
)
996 watchpoint
->is_set
= true;
1001 int riscv_remove_watchpoint(struct target
*target
,
1002 struct watchpoint
*watchpoint
)
1004 LOG_DEBUG("[%d] @0x%" TARGET_PRIxADDR
, target
->coreid
, watchpoint
->address
);
1006 struct trigger trigger
;
1007 trigger_from_watchpoint(&trigger
, watchpoint
);
1009 int result
= remove_trigger(target
, &trigger
);
1010 if (result
!= ERROR_OK
)
1012 watchpoint
->is_set
= false;
1017 /* Sets *hit_watchpoint to the first watchpoint identified as causing the
1020 * The GDB server uses this information to tell GDB what data address has
1021 * been hit, which enables GDB to print the hit variable along with its old
1023 static int riscv_hit_watchpoint(struct target
*target
, struct watchpoint
**hit_watchpoint
)
1025 struct watchpoint
*wp
= target
->watchpoints
;
1027 LOG_DEBUG("Current hartid = %d", riscv_current_hartid(target
));
1029 /*TODO instead of disassembling the instruction that we think caused the
1030 * trigger, check the hit bit of each watchpoint first. The hit bit is
1031 * simpler and more reliable to check but as it is optional and relatively
1032 * new, not all hardware will implement it */
1034 riscv_get_register(target
, &dpc
, GDB_REGNO_DPC
);
1035 const uint8_t length
= 4;
1036 LOG_DEBUG("dpc is 0x%" PRIx64
, dpc
);
1038 /* fetch the instruction at dpc */
1039 uint8_t buffer
[length
];
1040 if (target_read_buffer(target
, dpc
, length
, buffer
) != ERROR_OK
) {
1041 LOG_ERROR("Failed to read instruction at dpc 0x%" PRIx64
, dpc
);
1045 uint32_t instruction
= 0;
1047 for (int i
= 0; i
< length
; i
++) {
1048 LOG_DEBUG("Next byte is %x", buffer
[i
]);
1049 instruction
+= (buffer
[i
] << 8 * i
);
1051 LOG_DEBUG("Full instruction is %x", instruction
);
1053 /* find out which memory address is accessed by the instruction at dpc */
1054 /* opcode is first 7 bits of the instruction */
1055 uint8_t opcode
= instruction
& 0x7F;
1058 riscv_reg_t mem_addr
;
1060 if (opcode
== MATCH_LB
|| opcode
== MATCH_SB
) {
1061 rs1
= (instruction
& 0xf8000) >> 15;
1062 riscv_get_register(target
, &mem_addr
, rs1
);
1064 if (opcode
== MATCH_SB
) {
1065 LOG_DEBUG("%x is store instruction", instruction
);
1066 imm
= ((instruction
& 0xf80) >> 7) | ((instruction
& 0xfe000000) >> 20);
1068 LOG_DEBUG("%x is load instruction", instruction
);
1069 imm
= (instruction
& 0xfff00000) >> 20;
1071 /* sign extend 12-bit imm to 16-bits */
1072 if (imm
& (1 << 11))
1075 LOG_DEBUG("memory address=0x%" PRIx64
, mem_addr
);
1077 LOG_DEBUG("%x is not a RV32I load or store", instruction
);
1082 /*TODO support length/mask */
1083 if (wp
->address
== mem_addr
) {
1084 *hit_watchpoint
= wp
;
1085 LOG_DEBUG("Hit address=%" TARGET_PRIxADDR
, wp
->address
);
1091 /* No match found - either we hit a watchpoint caused by an instruction that
1092 * this function does not yet disassemble, or we hit a breakpoint.
1094 * OpenOCD will behave as if this function had never been implemented i.e.
1095 * report the halt to GDB with no address information. */
1100 static int oldriscv_step(struct target
*target
, int current
, uint32_t address
,
1101 int handle_breakpoints
)
1103 struct target_type
*tt
= get_target_type(target
);
1104 return tt
->step(target
, current
, address
, handle_breakpoints
);
1107 static int old_or_new_riscv_step(struct target
*target
, int current
,
1108 target_addr_t address
, int handle_breakpoints
)
1111 LOG_DEBUG("handle_breakpoints=%d", handle_breakpoints
);
1113 return oldriscv_step(target
, current
, address
, handle_breakpoints
);
1115 return riscv_openocd_step(target
, current
, address
, handle_breakpoints
);
1119 static int riscv_examine(struct target
*target
)
1121 LOG_DEBUG("riscv_examine()");
1122 if (target_was_examined(target
)) {
1123 LOG_DEBUG("Target was already examined.");
1127 /* Don't need to select dbus, since the first thing we do is read dtmcontrol. */
1130 uint32_t dtmcontrol
= dtmcontrol_scan(target
, 0);
1131 LOG_DEBUG("dtmcontrol=0x%x", dtmcontrol
);
1132 info
->dtm_version
= get_field(dtmcontrol
, DTMCONTROL_VERSION
);
1133 LOG_DEBUG(" version=0x%x", info
->dtm_version
);
1135 struct target_type
*tt
= get_target_type(target
);
1139 int result
= tt
->init_target(info
->cmd_ctx
, target
);
1140 if (result
!= ERROR_OK
)
1143 return tt
->examine(target
);
1146 static int oldriscv_poll(struct target
*target
)
1148 struct target_type
*tt
= get_target_type(target
);
1149 return tt
->poll(target
);
1152 static int old_or_new_riscv_poll(struct target
*target
)
1156 return oldriscv_poll(target
);
1158 return riscv_openocd_poll(target
);
1161 int riscv_select_current_hart(struct target
*target
)
1163 return riscv_set_current_hartid(target
, target
->coreid
);
1166 static int halt_prep(struct target
*target
)
1170 LOG_DEBUG("[%s] prep hart, debug_reason=%d", target_name(target
),
1171 target
->debug_reason
);
1172 if (riscv_select_current_hart(target
) != ERROR_OK
)
1174 if (riscv_is_halted(target
)) {
1175 LOG_DEBUG("[%s] Hart is already halted (reason=%d).",
1176 target_name(target
), target
->debug_reason
);
1178 if (r
->halt_prep(target
) != ERROR_OK
)
1186 static int riscv_halt_go_all_harts(struct target
*target
)
1190 if (riscv_select_current_hart(target
) != ERROR_OK
)
1192 if (riscv_is_halted(target
)) {
1193 LOG_DEBUG("[%s] Hart is already halted.", target_name(target
));
1195 if (r
->halt_go(target
) != ERROR_OK
)
1199 riscv_invalidate_register_cache(target
);
1204 static int halt_go(struct target
*target
)
1208 if (!r
->is_halted
) {
1209 struct target_type
*tt
= get_target_type(target
);
1210 result
= tt
->halt(target
);
1212 result
= riscv_halt_go_all_harts(target
);
1214 target
->state
= TARGET_HALTED
;
1215 if (target
->debug_reason
== DBG_REASON_NOTHALTED
)
1216 target
->debug_reason
= DBG_REASON_DBGRQ
;
1221 static int halt_finish(struct target
*target
)
1223 return target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
1226 int riscv_halt(struct target
*target
)
1230 if (!r
->is_halted
) {
1231 struct target_type
*tt
= get_target_type(target
);
1232 return tt
->halt(target
);
1235 LOG_DEBUG("[%d] halting all harts", target
->coreid
);
1237 int result
= ERROR_OK
;
1239 struct target_list
*tlist
;
1240 foreach_smp_target(tlist
, target
->smp_targets
) {
1241 struct target
*t
= tlist
->target
;
1242 if (halt_prep(t
) != ERROR_OK
)
1243 result
= ERROR_FAIL
;
1246 foreach_smp_target(tlist
, target
->smp_targets
) {
1247 struct target
*t
= tlist
->target
;
1248 struct riscv_info
*i
= riscv_info(t
);
1250 if (halt_go(t
) != ERROR_OK
)
1251 result
= ERROR_FAIL
;
1255 foreach_smp_target(tlist
, target
->smp_targets
) {
1256 struct target
*t
= tlist
->target
;
1257 if (halt_finish(t
) != ERROR_OK
)
1262 if (halt_prep(target
) != ERROR_OK
)
1263 result
= ERROR_FAIL
;
1264 if (halt_go(target
) != ERROR_OK
)
1265 result
= ERROR_FAIL
;
1266 if (halt_finish(target
) != ERROR_OK
)
1273 static int riscv_assert_reset(struct target
*target
)
1275 LOG_DEBUG("[%d]", target
->coreid
);
1276 struct target_type
*tt
= get_target_type(target
);
1277 riscv_invalidate_register_cache(target
);
1278 return tt
->assert_reset(target
);
1281 static int riscv_deassert_reset(struct target
*target
)
1283 LOG_DEBUG("[%d]", target
->coreid
);
1284 struct target_type
*tt
= get_target_type(target
);
1285 return tt
->deassert_reset(target
);
1288 static int riscv_resume_prep_all_harts(struct target
*target
)
1292 LOG_DEBUG("[%s] prep hart", target_name(target
));
1293 if (riscv_select_current_hart(target
) != ERROR_OK
)
1295 if (riscv_is_halted(target
)) {
1296 if (r
->resume_prep(target
) != ERROR_OK
)
1299 LOG_DEBUG("[%s] hart requested resume, but was already resumed",
1300 target_name(target
));
1303 LOG_DEBUG("[%s] mark as prepped", target_name(target
));
1309 /* state must be riscv_reg_t state[RISCV_MAX_HWBPS] = {0}; */
1310 static int disable_triggers(struct target
*target
, riscv_reg_t
*state
)
1314 LOG_DEBUG("deal with triggers");
1316 if (riscv_enumerate_triggers(target
) != ERROR_OK
)
1319 if (r
->manual_hwbp_set
) {
1320 /* Look at every trigger that may have been set. */
1321 riscv_reg_t tselect
;
1322 if (riscv_get_register(target
, &tselect
, GDB_REGNO_TSELECT
) != ERROR_OK
)
1324 for (unsigned int t
= 0; t
< r
->trigger_count
; t
++) {
1325 if (riscv_set_register(target
, GDB_REGNO_TSELECT
, t
) != ERROR_OK
)
1328 if (riscv_get_register(target
, &tdata1
, GDB_REGNO_TDATA1
) != ERROR_OK
)
1330 if (tdata1
& MCONTROL_DMODE(riscv_xlen(target
))) {
1332 if (riscv_set_register(target
, GDB_REGNO_TDATA1
, 0) != ERROR_OK
)
1336 if (riscv_set_register(target
, GDB_REGNO_TSELECT
, tselect
) != ERROR_OK
)
1340 /* Just go through the triggers we manage. */
1341 struct watchpoint
*watchpoint
= target
->watchpoints
;
1343 while (watchpoint
) {
1344 LOG_DEBUG("watchpoint %d: set=%d", i
, watchpoint
->is_set
);
1345 state
[i
] = watchpoint
->is_set
;
1346 if (watchpoint
->is_set
) {
1347 if (riscv_remove_watchpoint(target
, watchpoint
) != ERROR_OK
)
1350 watchpoint
= watchpoint
->next
;
1358 static int enable_triggers(struct target
*target
, riscv_reg_t
*state
)
1362 if (r
->manual_hwbp_set
) {
1363 /* Look at every trigger that may have been set. */
1364 riscv_reg_t tselect
;
1365 if (riscv_get_register(target
, &tselect
, GDB_REGNO_TSELECT
) != ERROR_OK
)
1367 for (unsigned int t
= 0; t
< r
->trigger_count
; t
++) {
1368 if (state
[t
] != 0) {
1369 if (riscv_set_register(target
, GDB_REGNO_TSELECT
, t
) != ERROR_OK
)
1371 if (riscv_set_register(target
, GDB_REGNO_TDATA1
, state
[t
]) != ERROR_OK
)
1375 if (riscv_set_register(target
, GDB_REGNO_TSELECT
, tselect
) != ERROR_OK
)
1379 struct watchpoint
*watchpoint
= target
->watchpoints
;
1381 while (watchpoint
) {
1382 LOG_DEBUG("watchpoint %d: cleared=%" PRId64
, i
, state
[i
]);
1384 if (riscv_add_watchpoint(target
, watchpoint
) != ERROR_OK
)
1387 watchpoint
= watchpoint
->next
;
1396 * Get everything ready to resume.
1398 static int resume_prep(struct target
*target
, int current
,
1399 target_addr_t address
, int handle_breakpoints
, int debug_execution
)
1402 LOG_DEBUG("[%d]", target
->coreid
);
1405 riscv_set_register(target
, GDB_REGNO_PC
, address
);
1407 if (target
->debug_reason
== DBG_REASON_WATCHPOINT
) {
1408 /* To be able to run off a trigger, disable all the triggers, step, and
1409 * then resume as usual. */
1410 riscv_reg_t trigger_state
[RISCV_MAX_HWBPS
] = {0};
1412 if (disable_triggers(target
, trigger_state
) != ERROR_OK
)
1415 if (old_or_new_riscv_step(target
, true, 0, false) != ERROR_OK
)
1418 if (enable_triggers(target
, trigger_state
) != ERROR_OK
)
1423 if (riscv_resume_prep_all_harts(target
) != ERROR_OK
)
1427 LOG_DEBUG("[%d] mark as prepped", target
->coreid
);
1434 * Resume all the harts that have been prepped, as close to instantaneous as
1437 static int resume_go(struct target
*target
, int current
,
1438 target_addr_t address
, int handle_breakpoints
, int debug_execution
)
1442 if (!r
->is_halted
) {
1443 struct target_type
*tt
= get_target_type(target
);
1444 result
= tt
->resume(target
, current
, address
, handle_breakpoints
,
1447 result
= riscv_resume_go_all_harts(target
);
1453 static int resume_finish(struct target
*target
)
1455 register_cache_invalidate(target
->reg_cache
);
1457 target
->state
= TARGET_RUNNING
;
1458 target
->debug_reason
= DBG_REASON_NOTHALTED
;
1459 return target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
1463 * @par single_hart When true, only resume a single hart even if SMP is
1464 * configured. This is used to run algorithms on just one hart.
1466 static int riscv_resume(
1467 struct target
*target
,
1469 target_addr_t address
,
1470 int handle_breakpoints
,
1471 int debug_execution
,
1474 LOG_DEBUG("handle_breakpoints=%d", handle_breakpoints
);
1475 int result
= ERROR_OK
;
1476 if (target
->smp
&& !single_hart
) {
1477 struct target_list
*tlist
;
1478 foreach_smp_target_direction(resume_order
== RO_NORMAL
,
1479 tlist
, target
->smp_targets
) {
1480 struct target
*t
= tlist
->target
;
1481 if (resume_prep(t
, current
, address
, handle_breakpoints
,
1482 debug_execution
) != ERROR_OK
)
1483 result
= ERROR_FAIL
;
1486 foreach_smp_target_direction(resume_order
== RO_NORMAL
,
1487 tlist
, target
->smp_targets
) {
1488 struct target
*t
= tlist
->target
;
1489 struct riscv_info
*i
= riscv_info(t
);
1491 if (resume_go(t
, current
, address
, handle_breakpoints
,
1492 debug_execution
) != ERROR_OK
)
1493 result
= ERROR_FAIL
;
1497 foreach_smp_target_direction(resume_order
== RO_NORMAL
,
1498 tlist
, target
->smp_targets
) {
1499 struct target
*t
= tlist
->target
;
1500 if (resume_finish(t
) != ERROR_OK
)
1505 if (resume_prep(target
, current
, address
, handle_breakpoints
,
1506 debug_execution
) != ERROR_OK
)
1507 result
= ERROR_FAIL
;
1508 if (resume_go(target
, current
, address
, handle_breakpoints
,
1509 debug_execution
) != ERROR_OK
)
1510 result
= ERROR_FAIL
;
1511 if (resume_finish(target
) != ERROR_OK
)
1518 static int riscv_target_resume(struct target
*target
, int current
, target_addr_t address
,
1519 int handle_breakpoints
, int debug_execution
)
1521 return riscv_resume(target
, current
, address
, handle_breakpoints
,
1522 debug_execution
, false);
1525 static int riscv_mmu(struct target
*target
, int *enabled
)
1527 if (!riscv_enable_virt2phys
) {
1532 /* Don't use MMU in explicit or effective M (machine) mode */
1534 if (riscv_get_register(target
, &priv
, GDB_REGNO_PRIV
) != ERROR_OK
) {
1535 LOG_ERROR("Failed to read priv register.");
1539 riscv_reg_t mstatus
;
1540 if (riscv_get_register(target
, &mstatus
, GDB_REGNO_MSTATUS
) != ERROR_OK
) {
1541 LOG_ERROR("Failed to read mstatus register.");
1545 if ((get_field(mstatus
, MSTATUS_MPRV
) ? get_field(mstatus
, MSTATUS_MPP
) : priv
) == PRV_M
) {
1546 LOG_DEBUG("SATP/MMU ignored in Machine mode (mstatus=0x%" PRIx64
").", mstatus
);
1552 if (riscv_get_register(target
, &satp
, GDB_REGNO_SATP
) != ERROR_OK
) {
1553 LOG_DEBUG("Couldn't read SATP.");
1554 /* If we can't read SATP, then there must not be an MMU. */
1559 if (get_field(satp
, RISCV_SATP_MODE(riscv_xlen(target
))) == SATP_MODE_OFF
) {
1560 LOG_DEBUG("MMU is disabled.");
1563 LOG_DEBUG("MMU is enabled.");
1570 static int riscv_address_translate(struct target
*target
,
1571 target_addr_t
virtual, target_addr_t
*physical
)
1574 riscv_reg_t satp_value
;
1577 target_addr_t table_address
;
1578 const virt2phys_info_t
*info
;
1582 int result
= riscv_get_register(target
, &satp_value
, GDB_REGNO_SATP
);
1583 if (result
!= ERROR_OK
)
1586 unsigned xlen
= riscv_xlen(target
);
1587 mode
= get_field(satp_value
, RISCV_SATP_MODE(xlen
));
1589 case SATP_MODE_SV32
:
1592 case SATP_MODE_SV39
:
1595 case SATP_MODE_SV48
:
1599 LOG_ERROR("No translation or protection." \
1600 " (satp: 0x%" PRIx64
")", satp_value
);
1603 LOG_ERROR("The translation mode is not supported." \
1604 " (satp: 0x%" PRIx64
")", satp_value
);
1607 LOG_DEBUG("virtual=0x%" TARGET_PRIxADDR
"; mode=%s", virtual, info
->name
);
1609 /* verify bits xlen-1:va_bits-1 are all equal */
1610 assert(xlen
>= info
->va_bits
);
1611 target_addr_t mask
= ((target_addr_t
)1 << (xlen
- (info
->va_bits
- 1))) - 1;
1612 target_addr_t masked_msbs
= (virtual >> (info
->va_bits
- 1)) & mask
;
1613 if (masked_msbs
!= 0 && masked_msbs
!= mask
) {
1614 LOG_ERROR("Virtual address 0x%" TARGET_PRIxADDR
" is not sign-extended "
1615 "for %s mode.", virtual, info
->name
);
1619 ppn_value
= get_field(satp_value
, RISCV_SATP_PPN(xlen
));
1620 table_address
= ppn_value
<< RISCV_PGSHIFT
;
1621 i
= info
->level
- 1;
1623 uint64_t vpn
= virtual >> info
->vpn_shift
[i
];
1624 vpn
&= info
->vpn_mask
[i
];
1625 target_addr_t pte_address
= table_address
+
1626 (vpn
<< info
->pte_shift
);
1628 assert(info
->pte_shift
<= 3);
1629 int retval
= r
->read_memory(target
, pte_address
,
1630 4, (1 << info
->pte_shift
) / 4, buffer
, 4);
1631 if (retval
!= ERROR_OK
)
1634 if (info
->pte_shift
== 2)
1635 pte
= buf_get_u32(buffer
, 0, 32);
1637 pte
= buf_get_u64(buffer
, 0, 64);
1639 LOG_DEBUG("i=%d; PTE @0x%" TARGET_PRIxADDR
" = 0x%" PRIx64
, i
,
1642 if (!(pte
& PTE_V
) || (!(pte
& PTE_R
) && (pte
& PTE_W
)))
1645 if ((pte
& PTE_R
) || (pte
& PTE_X
)) /* Found leaf PTE. */
1651 ppn_value
= pte
>> PTE_PPN_SHIFT
;
1652 table_address
= ppn_value
<< RISCV_PGSHIFT
;
1656 LOG_ERROR("Couldn't find the PTE.");
1660 /* Make sure to clear out the high bits that may be set. */
1661 *physical
= virtual & (((target_addr_t
)1 << info
->va_bits
) - 1);
1663 while (i
< info
->level
) {
1664 ppn_value
= pte
>> info
->pte_ppn_shift
[i
];
1665 ppn_value
&= info
->pte_ppn_mask
[i
];
1666 *physical
&= ~(((target_addr_t
)info
->pa_ppn_mask
[i
]) <<
1667 info
->pa_ppn_shift
[i
]);
1668 *physical
|= (ppn_value
<< info
->pa_ppn_shift
[i
]);
1671 LOG_DEBUG("0x%" TARGET_PRIxADDR
" -> 0x%" TARGET_PRIxADDR
, virtual,
1677 static int riscv_virt2phys(struct target
*target
, target_addr_t
virtual, target_addr_t
*physical
)
1680 if (riscv_mmu(target
, &enabled
) == ERROR_OK
) {
1684 if (riscv_address_translate(target
, virtual, physical
) == ERROR_OK
)
1691 static int riscv_read_phys_memory(struct target
*target
, target_addr_t phys_address
,
1692 uint32_t size
, uint32_t count
, uint8_t *buffer
)
1695 if (riscv_select_current_hart(target
) != ERROR_OK
)
1697 return r
->read_memory(target
, phys_address
, size
, count
, buffer
, size
);
1700 static int riscv_read_memory(struct target
*target
, target_addr_t address
,
1701 uint32_t size
, uint32_t count
, uint8_t *buffer
)
1704 LOG_WARNING("0-length read from 0x%" TARGET_PRIxADDR
, address
);
1708 if (riscv_select_current_hart(target
) != ERROR_OK
)
1711 target_addr_t physical_addr
;
1712 if (target
->type
->virt2phys(target
, address
, &physical_addr
) == ERROR_OK
)
1713 address
= physical_addr
;
1716 return r
->read_memory(target
, address
, size
, count
, buffer
, size
);
1719 static int riscv_write_phys_memory(struct target
*target
, target_addr_t phys_address
,
1720 uint32_t size
, uint32_t count
, const uint8_t *buffer
)
1722 if (riscv_select_current_hart(target
) != ERROR_OK
)
1724 struct target_type
*tt
= get_target_type(target
);
1725 return tt
->write_memory(target
, phys_address
, size
, count
, buffer
);
1728 static int riscv_write_memory(struct target
*target
, target_addr_t address
,
1729 uint32_t size
, uint32_t count
, const uint8_t *buffer
)
1732 LOG_WARNING("0-length write to 0x%" TARGET_PRIxADDR
, address
);
1736 if (riscv_select_current_hart(target
) != ERROR_OK
)
1739 target_addr_t physical_addr
;
1740 if (target
->type
->virt2phys(target
, address
, &physical_addr
) == ERROR_OK
)
1741 address
= physical_addr
;
1743 struct target_type
*tt
= get_target_type(target
);
1744 return tt
->write_memory(target
, address
, size
, count
, buffer
);
1747 static const char *riscv_get_gdb_arch(struct target
*target
)
1749 switch (riscv_xlen(target
)) {
1751 return "riscv:rv32";
1753 return "riscv:rv64";
1755 LOG_ERROR("Unsupported xlen: %d", riscv_xlen(target
));
1759 static int riscv_get_gdb_reg_list_internal(struct target
*target
,
1760 struct reg
**reg_list
[], int *reg_list_size
,
1761 enum target_register_class reg_class
, bool read
)
1764 LOG_DEBUG("[%s] {%d} reg_class=%d, read=%d",
1765 target_name(target
), r
->current_hartid
, reg_class
, read
);
1767 if (!target
->reg_cache
) {
1768 LOG_ERROR("Target not initialized. Return ERROR_FAIL.");
1772 if (riscv_select_current_hart(target
) != ERROR_OK
)
1775 switch (reg_class
) {
1776 case REG_CLASS_GENERAL
:
1777 *reg_list_size
= 33;
1780 *reg_list_size
= target
->reg_cache
->num_regs
;
1783 LOG_ERROR("Unsupported reg_class: %d", reg_class
);
1787 *reg_list
= calloc(*reg_list_size
, sizeof(struct reg
*));
1791 for (int i
= 0; i
< *reg_list_size
; i
++) {
1792 assert(!target
->reg_cache
->reg_list
[i
].valid
||
1793 target
->reg_cache
->reg_list
[i
].size
> 0);
1794 (*reg_list
)[i
] = &target
->reg_cache
->reg_list
[i
];
1796 target
->reg_cache
->reg_list
[i
].exist
&&
1797 !target
->reg_cache
->reg_list
[i
].valid
) {
1798 if (target
->reg_cache
->reg_list
[i
].type
->get(
1799 &target
->reg_cache
->reg_list
[i
]) != ERROR_OK
)
1807 static int riscv_get_gdb_reg_list_noread(struct target
*target
,
1808 struct reg
**reg_list
[], int *reg_list_size
,
1809 enum target_register_class reg_class
)
1811 return riscv_get_gdb_reg_list_internal(target
, reg_list
, reg_list_size
,
1815 static int riscv_get_gdb_reg_list(struct target
*target
,
1816 struct reg
**reg_list
[], int *reg_list_size
,
1817 enum target_register_class reg_class
)
1819 return riscv_get_gdb_reg_list_internal(target
, reg_list
, reg_list_size
,
1823 static int riscv_arch_state(struct target
*target
)
1825 struct target_type
*tt
= get_target_type(target
);
1826 return tt
->arch_state(target
);
1829 /* Algorithm must end with a software breakpoint instruction. */
1830 static int riscv_run_algorithm(struct target
*target
, int num_mem_params
,
1831 struct mem_param
*mem_params
, int num_reg_params
,
1832 struct reg_param
*reg_params
, target_addr_t entry_point
,
1833 target_addr_t exit_point
, unsigned int timeout_ms
, void *arch_info
)
1837 if (num_mem_params
> 0) {
1838 LOG_ERROR("Memory parameters are not supported for RISC-V algorithms.");
1842 if (target
->state
!= TARGET_HALTED
) {
1843 LOG_WARNING("target not halted");
1844 return ERROR_TARGET_NOT_HALTED
;
1847 /* Save registers */
1848 struct reg
*reg_pc
= register_get_by_name(target
->reg_cache
, "pc", true);
1849 if (!reg_pc
|| reg_pc
->type
->get(reg_pc
) != ERROR_OK
)
1851 uint64_t saved_pc
= buf_get_u64(reg_pc
->value
, 0, reg_pc
->size
);
1852 LOG_DEBUG("saved_pc=0x%" PRIx64
, saved_pc
);
1854 uint64_t saved_regs
[32];
1855 for (int i
= 0; i
< num_reg_params
; i
++) {
1856 LOG_DEBUG("save %s", reg_params
[i
].reg_name
);
1857 struct reg
*r
= register_get_by_name(target
->reg_cache
, reg_params
[i
].reg_name
, false);
1859 LOG_ERROR("Couldn't find register named '%s'", reg_params
[i
].reg_name
);
1863 if (r
->size
!= reg_params
[i
].size
) {
1864 LOG_ERROR("Register %s is %d bits instead of %d bits.",
1865 reg_params
[i
].reg_name
, r
->size
, reg_params
[i
].size
);
1869 if (r
->number
> GDB_REGNO_XPR31
) {
1870 LOG_ERROR("Only GPRs can be use as argument registers.");
1874 if (r
->type
->get(r
) != ERROR_OK
)
1876 saved_regs
[r
->number
] = buf_get_u64(r
->value
, 0, r
->size
);
1878 if (reg_params
[i
].direction
== PARAM_OUT
|| reg_params
[i
].direction
== PARAM_IN_OUT
) {
1879 if (r
->type
->set(r
, reg_params
[i
].value
) != ERROR_OK
)
1885 /* Disable Interrupts before attempting to run the algorithm. */
1886 uint64_t current_mstatus
;
1887 uint8_t mstatus_bytes
[8] = { 0 };
1889 LOG_DEBUG("Disabling Interrupts");
1890 struct reg
*reg_mstatus
= register_get_by_name(target
->reg_cache
,
1893 LOG_ERROR("Couldn't find mstatus!");
1897 reg_mstatus
->type
->get(reg_mstatus
);
1898 current_mstatus
= buf_get_u64(reg_mstatus
->value
, 0, reg_mstatus
->size
);
1899 uint64_t ie_mask
= MSTATUS_MIE
| MSTATUS_HIE
| MSTATUS_SIE
| MSTATUS_UIE
;
1900 buf_set_u64(mstatus_bytes
, 0, info
->xlen
, set_field(current_mstatus
,
1903 reg_mstatus
->type
->set(reg_mstatus
, mstatus_bytes
);
1906 LOG_DEBUG("resume at 0x%" TARGET_PRIxADDR
, entry_point
);
1907 if (riscv_resume(target
, 0, entry_point
, 0, 0, true) != ERROR_OK
)
1910 int64_t start
= timeval_ms();
1911 while (target
->state
!= TARGET_HALTED
) {
1912 LOG_DEBUG("poll()");
1913 int64_t now
= timeval_ms();
1914 if (now
- start
> timeout_ms
) {
1915 LOG_ERROR("Algorithm timed out after %" PRId64
" ms.", now
- start
);
1917 old_or_new_riscv_poll(target
);
1918 enum gdb_regno regnums
[] = {
1919 GDB_REGNO_RA
, GDB_REGNO_SP
, GDB_REGNO_GP
, GDB_REGNO_TP
,
1920 GDB_REGNO_T0
, GDB_REGNO_T1
, GDB_REGNO_T2
, GDB_REGNO_FP
,
1921 GDB_REGNO_S1
, GDB_REGNO_A0
, GDB_REGNO_A1
, GDB_REGNO_A2
,
1922 GDB_REGNO_A3
, GDB_REGNO_A4
, GDB_REGNO_A5
, GDB_REGNO_A6
,
1923 GDB_REGNO_A7
, GDB_REGNO_S2
, GDB_REGNO_S3
, GDB_REGNO_S4
,
1924 GDB_REGNO_S5
, GDB_REGNO_S6
, GDB_REGNO_S7
, GDB_REGNO_S8
,
1925 GDB_REGNO_S9
, GDB_REGNO_S10
, GDB_REGNO_S11
, GDB_REGNO_T3
,
1926 GDB_REGNO_T4
, GDB_REGNO_T5
, GDB_REGNO_T6
,
1928 GDB_REGNO_MSTATUS
, GDB_REGNO_MEPC
, GDB_REGNO_MCAUSE
,
1930 for (unsigned i
= 0; i
< ARRAY_SIZE(regnums
); i
++) {
1931 enum gdb_regno regno
= regnums
[i
];
1932 riscv_reg_t reg_value
;
1933 if (riscv_get_register(target
, ®_value
, regno
) != ERROR_OK
)
1935 LOG_ERROR("%s = 0x%" PRIx64
, gdb_regno_name(regno
), reg_value
);
1937 return ERROR_TARGET_TIMEOUT
;
1940 int result
= old_or_new_riscv_poll(target
);
1941 if (result
!= ERROR_OK
)
1945 /* The current hart id might have been changed in poll(). */
1946 if (riscv_select_current_hart(target
) != ERROR_OK
)
1949 if (reg_pc
->type
->get(reg_pc
) != ERROR_OK
)
1951 uint64_t final_pc
= buf_get_u64(reg_pc
->value
, 0, reg_pc
->size
);
1952 if (exit_point
&& final_pc
!= exit_point
) {
1953 LOG_ERROR("PC ended up at 0x%" PRIx64
" instead of 0x%"
1954 TARGET_PRIxADDR
, final_pc
, exit_point
);
1958 /* Restore Interrupts */
1959 LOG_DEBUG("Restoring Interrupts");
1960 buf_set_u64(mstatus_bytes
, 0, info
->xlen
, current_mstatus
);
1961 reg_mstatus
->type
->set(reg_mstatus
, mstatus_bytes
);
1963 /* Restore registers */
1964 uint8_t buf
[8] = { 0 };
1965 buf_set_u64(buf
, 0, info
->xlen
, saved_pc
);
1966 if (reg_pc
->type
->set(reg_pc
, buf
) != ERROR_OK
)
1969 for (int i
= 0; i
< num_reg_params
; i
++) {
1970 if (reg_params
[i
].direction
== PARAM_IN
||
1971 reg_params
[i
].direction
== PARAM_IN_OUT
) {
1972 struct reg
*r
= register_get_by_name(target
->reg_cache
, reg_params
[i
].reg_name
, false);
1973 if (r
->type
->get(r
) != ERROR_OK
) {
1974 LOG_ERROR("get(%s) failed", r
->name
);
1977 buf_cpy(r
->value
, reg_params
[i
].value
, reg_params
[i
].size
);
1979 LOG_DEBUG("restore %s", reg_params
[i
].reg_name
);
1980 struct reg
*r
= register_get_by_name(target
->reg_cache
, reg_params
[i
].reg_name
, false);
1981 buf_set_u64(buf
, 0, info
->xlen
, saved_regs
[r
->number
]);
1982 if (r
->type
->set(r
, buf
) != ERROR_OK
) {
1983 LOG_ERROR("set(%s) failed", r
->name
);
1991 static int riscv_checksum_memory(struct target
*target
,
1992 target_addr_t address
, uint32_t count
,
1995 struct working_area
*crc_algorithm
;
1996 struct reg_param reg_params
[2];
1999 LOG_DEBUG("address=0x%" TARGET_PRIxADDR
"; count=0x%" PRIx32
, address
, count
);
2001 static const uint8_t riscv32_crc_code
[] = {
2002 #include "../../../contrib/loaders/checksum/riscv32_crc.inc"
2004 static const uint8_t riscv64_crc_code
[] = {
2005 #include "../../../contrib/loaders/checksum/riscv64_crc.inc"
2008 static const uint8_t *crc_code
;
2010 unsigned xlen
= riscv_xlen(target
);
2011 unsigned crc_code_size
;
2013 crc_code
= riscv32_crc_code
;
2014 crc_code_size
= sizeof(riscv32_crc_code
);
2016 crc_code
= riscv64_crc_code
;
2017 crc_code_size
= sizeof(riscv64_crc_code
);
2020 if (count
< crc_code_size
* 4) {
2021 /* Don't use the algorithm for relatively small buffers. It's faster
2022 * just to read the memory. target_checksum_memory() will take care of
2023 * that if we fail. */
2027 retval
= target_alloc_working_area(target
, crc_code_size
, &crc_algorithm
);
2028 if (retval
!= ERROR_OK
)
2031 if (crc_algorithm
->address
+ crc_algorithm
->size
> address
&&
2032 crc_algorithm
->address
< address
+ count
) {
2033 /* Region to checksum overlaps with the work area we've been assigned.
2034 * Bail. (Would be better to manually checksum what we read there, and
2035 * use the algorithm for the rest.) */
2036 target_free_working_area(target
, crc_algorithm
);
2040 retval
= target_write_buffer(target
, crc_algorithm
->address
, crc_code_size
,
2042 if (retval
!= ERROR_OK
) {
2043 LOG_ERROR("Failed to write code to " TARGET_ADDR_FMT
": %d",
2044 crc_algorithm
->address
, retval
);
2045 target_free_working_area(target
, crc_algorithm
);
2049 init_reg_param(®_params
[0], "a0", xlen
, PARAM_IN_OUT
);
2050 init_reg_param(®_params
[1], "a1", xlen
, PARAM_OUT
);
2051 buf_set_u64(reg_params
[0].value
, 0, xlen
, address
);
2052 buf_set_u64(reg_params
[1].value
, 0, xlen
, count
);
2054 /* 20 second timeout/megabyte */
2055 unsigned int timeout
= 20000 * (1 + (count
/ (1024 * 1024)));
2057 retval
= target_run_algorithm(target
, 0, NULL
, 2, reg_params
,
2058 crc_algorithm
->address
,
2059 0, /* Leave exit point unspecified because we don't know. */
2062 if (retval
== ERROR_OK
)
2063 *checksum
= buf_get_u32(reg_params
[0].value
, 0, 32);
2065 LOG_ERROR("error executing RISC-V CRC algorithm");
2067 destroy_reg_param(®_params
[0]);
2068 destroy_reg_param(®_params
[1]);
2070 target_free_working_area(target
, crc_algorithm
);
2072 LOG_DEBUG("checksum=0x%" PRIx32
", result=%d", *checksum
, retval
);
2077 /*** OpenOCD Helper Functions ***/
2079 enum riscv_poll_hart
{
2081 RPH_DISCOVERED_HALTED
,
2082 RPH_DISCOVERED_RUNNING
,
2085 static enum riscv_poll_hart
riscv_poll_hart(struct target
*target
, int hartid
)
2088 if (riscv_set_current_hartid(target
, hartid
) != ERROR_OK
)
2091 LOG_DEBUG("polling hart %d, target->state=%d", hartid
, target
->state
);
2093 /* If OpenOCD thinks we're running but this hart is halted then it's time
2094 * to raise an event. */
2095 bool halted
= riscv_is_halted(target
);
2096 if (target
->state
!= TARGET_HALTED
&& halted
) {
2097 LOG_DEBUG(" triggered a halt");
2099 return RPH_DISCOVERED_HALTED
;
2100 } else if (target
->state
!= TARGET_RUNNING
&& !halted
) {
2101 LOG_DEBUG(" triggered running");
2102 target
->state
= TARGET_RUNNING
;
2103 target
->debug_reason
= DBG_REASON_NOTHALTED
;
2104 return RPH_DISCOVERED_RUNNING
;
2107 return RPH_NO_CHANGE
;
2110 static int set_debug_reason(struct target
*target
, enum riscv_halt_reason halt_reason
)
2112 switch (halt_reason
) {
2113 case RISCV_HALT_BREAKPOINT
:
2114 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
2116 case RISCV_HALT_TRIGGER
:
2117 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
2119 case RISCV_HALT_INTERRUPT
:
2120 case RISCV_HALT_GROUP
:
2121 target
->debug_reason
= DBG_REASON_DBGRQ
;
2123 case RISCV_HALT_SINGLESTEP
:
2124 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
2126 case RISCV_HALT_UNKNOWN
:
2127 target
->debug_reason
= DBG_REASON_UNDEFINED
;
2129 case RISCV_HALT_ERROR
:
2132 LOG_DEBUG("[%s] debug_reason=%d", target_name(target
), target
->debug_reason
);
2136 static int sample_memory(struct target
*target
)
2140 if (!r
->sample_buf
.buf
|| !r
->sample_config
.enabled
)
2143 LOG_DEBUG("buf used/size: %d/%d", r
->sample_buf
.used
, r
->sample_buf
.size
);
2145 uint64_t start
= timeval_ms();
2146 riscv_sample_buf_maybe_add_timestamp(target
, true);
2147 int result
= ERROR_OK
;
2148 if (r
->sample_memory
) {
2149 result
= r
->sample_memory(target
, &r
->sample_buf
, &r
->sample_config
,
2150 start
+ TARGET_DEFAULT_POLLING_INTERVAL
);
2151 if (result
!= ERROR_NOT_IMPLEMENTED
)
2155 /* Default slow path. */
2156 while (timeval_ms() - start
< TARGET_DEFAULT_POLLING_INTERVAL
) {
2157 for (unsigned int i
= 0; i
< ARRAY_SIZE(r
->sample_config
.bucket
); i
++) {
2158 if (r
->sample_config
.bucket
[i
].enabled
&&
2159 r
->sample_buf
.used
+ 1 + r
->sample_config
.bucket
[i
].size_bytes
< r
->sample_buf
.size
) {
2160 assert(i
< RISCV_SAMPLE_BUF_TIMESTAMP_BEFORE
);
2161 r
->sample_buf
.buf
[r
->sample_buf
.used
] = i
;
2162 result
= riscv_read_phys_memory(
2163 target
, r
->sample_config
.bucket
[i
].address
,
2164 r
->sample_config
.bucket
[i
].size_bytes
, 1,
2165 r
->sample_buf
.buf
+ r
->sample_buf
.used
+ 1);
2166 if (result
== ERROR_OK
)
2167 r
->sample_buf
.used
+= 1 + r
->sample_config
.bucket
[i
].size_bytes
;
2175 riscv_sample_buf_maybe_add_timestamp(target
, false);
2176 if (result
!= ERROR_OK
) {
2177 LOG_INFO("Turning off memory sampling because it failed.");
2178 r
->sample_config
.enabled
= false;
2183 /*** OpenOCD Interface ***/
2184 int riscv_openocd_poll(struct target
*target
)
2186 LOG_DEBUG("polling all harts");
2187 int halted_hart
= -1;
2190 unsigned should_remain_halted
= 0;
2191 unsigned should_resume
= 0;
2192 struct target_list
*list
;
2193 foreach_smp_target(list
, target
->smp_targets
) {
2194 struct target
*t
= list
->target
;
2195 struct riscv_info
*r
= riscv_info(t
);
2196 enum riscv_poll_hart out
= riscv_poll_hart(t
, r
->current_hartid
);
2200 case RPH_DISCOVERED_RUNNING
:
2201 t
->state
= TARGET_RUNNING
;
2202 t
->debug_reason
= DBG_REASON_NOTHALTED
;
2204 case RPH_DISCOVERED_HALTED
:
2205 t
->state
= TARGET_HALTED
;
2206 enum riscv_halt_reason halt_reason
=
2207 riscv_halt_reason(t
, r
->current_hartid
);
2208 if (set_debug_reason(t
, halt_reason
) != ERROR_OK
)
2211 if (halt_reason
== RISCV_HALT_BREAKPOINT
) {
2213 switch (riscv_semihosting(t
, &retval
)) {
2214 case SEMIHOSTING_NONE
:
2215 case SEMIHOSTING_WAITING
:
2216 /* This hart should remain halted. */
2217 should_remain_halted
++;
2219 case SEMIHOSTING_HANDLED
:
2220 /* This hart should be resumed, along with any other
2221 * harts that halted due to haltgroups. */
2224 case SEMIHOSTING_ERROR
:
2227 } else if (halt_reason
!= RISCV_HALT_GROUP
) {
2228 should_remain_halted
++;
2237 LOG_DEBUG("should_remain_halted=%d, should_resume=%d",
2238 should_remain_halted
, should_resume
);
2239 if (should_remain_halted
&& should_resume
) {
2240 LOG_WARNING("%d harts should remain halted, and %d should resume.",
2241 should_remain_halted
, should_resume
);
2243 if (should_remain_halted
) {
2244 LOG_DEBUG("halt all");
2246 } else if (should_resume
) {
2247 LOG_DEBUG("resume all");
2248 riscv_resume(target
, true, 0, 0, 0, false);
2251 /* Sample memory if any target is running. */
2252 foreach_smp_target(list
, target
->smp_targets
) {
2253 struct target
*t
= list
->target
;
2254 if (t
->state
== TARGET_RUNNING
) {
2255 sample_memory(target
);
2263 enum riscv_poll_hart out
= riscv_poll_hart(target
,
2264 riscv_current_hartid(target
));
2265 if (out
== RPH_NO_CHANGE
|| out
== RPH_DISCOVERED_RUNNING
) {
2266 if (target
->state
== TARGET_RUNNING
)
2267 sample_memory(target
);
2269 } else if (out
== RPH_ERROR
) {
2273 halted_hart
= riscv_current_hartid(target
);
2274 LOG_DEBUG(" hart %d halted", halted_hart
);
2276 enum riscv_halt_reason halt_reason
= riscv_halt_reason(target
, halted_hart
);
2277 if (set_debug_reason(target
, halt_reason
) != ERROR_OK
)
2279 target
->state
= TARGET_HALTED
;
2282 if (target
->debug_reason
== DBG_REASON_BREAKPOINT
) {
2284 switch (riscv_semihosting(target
, &retval
)) {
2285 case SEMIHOSTING_NONE
:
2286 case SEMIHOSTING_WAITING
:
2287 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
2289 case SEMIHOSTING_HANDLED
:
2290 if (riscv_resume(target
, true, 0, 0, 0, false) != ERROR_OK
)
2293 case SEMIHOSTING_ERROR
:
2297 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
2303 int riscv_openocd_step(struct target
*target
, int current
,
2304 target_addr_t address
, int handle_breakpoints
)
2306 LOG_DEBUG("stepping rtos hart");
2309 riscv_set_register(target
, GDB_REGNO_PC
, address
);
2311 riscv_reg_t trigger_state
[RISCV_MAX_HWBPS
] = {0};
2312 if (disable_triggers(target
, trigger_state
) != ERROR_OK
)
2315 int out
= riscv_step_rtos_hart(target
);
2316 if (out
!= ERROR_OK
) {
2317 LOG_ERROR("unable to step rtos hart");
2321 register_cache_invalidate(target
->reg_cache
);
2323 if (enable_triggers(target
, trigger_state
) != ERROR_OK
)
2326 target
->state
= TARGET_RUNNING
;
2327 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
2328 target
->state
= TARGET_HALTED
;
2329 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
2330 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
2334 /* Command Handlers */
2335 COMMAND_HANDLER(riscv_set_command_timeout_sec
)
2337 if (CMD_ARGC
!= 1) {
2338 LOG_ERROR("Command takes exactly 1 parameter");
2339 return ERROR_COMMAND_SYNTAX_ERROR
;
2341 int timeout
= atoi(CMD_ARGV
[0]);
2343 LOG_ERROR("%s is not a valid integer argument for command.", CMD_ARGV
[0]);
2347 riscv_command_timeout_sec
= timeout
;
2352 COMMAND_HANDLER(riscv_set_reset_timeout_sec
)
2354 if (CMD_ARGC
!= 1) {
2355 LOG_ERROR("Command takes exactly 1 parameter");
2356 return ERROR_COMMAND_SYNTAX_ERROR
;
2358 int timeout
= atoi(CMD_ARGV
[0]);
2360 LOG_ERROR("%s is not a valid integer argument for command.", CMD_ARGV
[0]);
2364 riscv_reset_timeout_sec
= timeout
;
2368 COMMAND_HANDLER(riscv_set_mem_access
)
2370 struct target
*target
= get_current_target(CMD_CTX
);
2372 int progbuf_cnt
= 0;
2374 int abstract_cnt
= 0;
2376 if (CMD_ARGC
< 1 || CMD_ARGC
> RISCV_NUM_MEM_ACCESS_METHODS
) {
2377 LOG_ERROR("Command takes 1 to %d parameters", RISCV_NUM_MEM_ACCESS_METHODS
);
2378 return ERROR_COMMAND_SYNTAX_ERROR
;
2381 /* Check argument validity */
2382 for (unsigned int i
= 0; i
< CMD_ARGC
; i
++) {
2383 if (strcmp("progbuf", CMD_ARGV
[i
]) == 0) {
2385 } else if (strcmp("sysbus", CMD_ARGV
[i
]) == 0) {
2387 } else if (strcmp("abstract", CMD_ARGV
[i
]) == 0) {
2390 LOG_ERROR("Unknown argument '%s'. "
2391 "Must be one of: 'progbuf', 'sysbus' or 'abstract'.", CMD_ARGV
[i
]);
2392 return ERROR_COMMAND_SYNTAX_ERROR
;
2395 if (progbuf_cnt
> 1 || sysbus_cnt
> 1 || abstract_cnt
> 1) {
2396 LOG_ERROR("Syntax error - duplicate arguments to `riscv set_mem_access`.");
2397 return ERROR_COMMAND_SYNTAX_ERROR
;
2400 /* Args are valid, store them */
2401 for (unsigned int i
= 0; i
< RISCV_NUM_MEM_ACCESS_METHODS
; i
++)
2402 r
->mem_access_methods
[i
] = RISCV_MEM_ACCESS_UNSPECIFIED
;
2403 for (unsigned int i
= 0; i
< CMD_ARGC
; i
++) {
2404 if (strcmp("progbuf", CMD_ARGV
[i
]) == 0)
2405 r
->mem_access_methods
[i
] = RISCV_MEM_ACCESS_PROGBUF
;
2406 else if (strcmp("sysbus", CMD_ARGV
[i
]) == 0)
2407 r
->mem_access_methods
[i
] = RISCV_MEM_ACCESS_SYSBUS
;
2408 else if (strcmp("abstract", CMD_ARGV
[i
]) == 0)
2409 r
->mem_access_methods
[i
] = RISCV_MEM_ACCESS_ABSTRACT
;
2412 /* Reset warning flags */
2413 r
->mem_access_progbuf_warn
= true;
2414 r
->mem_access_sysbus_warn
= true;
2415 r
->mem_access_abstract_warn
= true;
2420 COMMAND_HANDLER(riscv_set_enable_virtual
)
2422 if (CMD_ARGC
!= 1) {
2423 LOG_ERROR("Command takes exactly 1 parameter");
2424 return ERROR_COMMAND_SYNTAX_ERROR
;
2426 COMMAND_PARSE_ON_OFF(CMD_ARGV
[0], riscv_enable_virtual
);
2430 static int parse_ranges(struct list_head
*ranges
, const char *tcl_arg
, const char *reg_type
, unsigned int max_val
)
2432 char *args
= strdup(tcl_arg
);
2436 /* For backward compatibility, allow multiple parameters within one TCL argument, separated by ',' */
2437 char *arg
= strtok(args
, ",");
2443 char *dash
= strchr(arg
, '-');
2444 char *equals
= strchr(arg
, '=');
2447 if (!dash
&& !equals
) {
2448 /* Expecting single register number. */
2449 if (sscanf(arg
, "%u%n", &low
, &pos
) != 1 || pos
!= strlen(arg
)) {
2450 LOG_ERROR("Failed to parse single register number from '%s'.", arg
);
2452 return ERROR_COMMAND_SYNTAX_ERROR
;
2454 } else if (dash
&& !equals
) {
2455 /* Expecting register range - two numbers separated by a dash: ##-## */
2458 if (sscanf(arg
, "%u%n", &low
, &pos
) != 1 || pos
!= strlen(arg
)) {
2459 LOG_ERROR("Failed to parse single register number from '%s'.", arg
);
2461 return ERROR_COMMAND_SYNTAX_ERROR
;
2463 if (sscanf(dash
, "%u%n", &high
, &pos
) != 1 || pos
!= strlen(dash
)) {
2464 LOG_ERROR("Failed to parse single register number from '%s'.", dash
);
2466 return ERROR_COMMAND_SYNTAX_ERROR
;
2469 LOG_ERROR("Incorrect range encountered [%u, %u].", low
, high
);
2473 } else if (!dash
&& equals
) {
2474 /* Expecting single register number with textual name specified: ##=name */
2477 if (sscanf(arg
, "%u%n", &low
, &pos
) != 1 || pos
!= strlen(arg
)) {
2478 LOG_ERROR("Failed to parse single register number from '%s'.", arg
);
2480 return ERROR_COMMAND_SYNTAX_ERROR
;
2483 name
= calloc(1, strlen(equals
) + strlen(reg_type
) + 2);
2485 LOG_ERROR("Failed to allocate register name.");
2490 /* Register prefix: "csr_" or "custom_" */
2491 strcpy(name
, reg_type
);
2492 name
[strlen(reg_type
)] = '_';
2494 if (sscanf(equals
, "%[_a-zA-Z0-9]%n", name
+ strlen(reg_type
) + 1, &pos
) != 1 || pos
!= strlen(equals
)) {
2495 LOG_ERROR("Failed to parse register name from '%s'.", equals
);
2498 return ERROR_COMMAND_SYNTAX_ERROR
;
2501 LOG_ERROR("Invalid argument '%s'.", arg
);
2503 return ERROR_COMMAND_SYNTAX_ERROR
;
2506 high
= high
> low
? high
: low
;
2508 if (high
> max_val
) {
2509 LOG_ERROR("Cannot expose %s register number %u, maximum allowed value is %u.", reg_type
, high
, max_val
);
2515 /* Check for overlap, name uniqueness. */
2516 range_list_t
*entry
;
2517 list_for_each_entry(entry
, ranges
, list
) {
2518 if ((entry
->low
<= high
) && (low
<= entry
->high
)) {
2520 LOG_WARNING("Duplicate %s register number - "
2521 "Register %u has already been exposed previously", reg_type
, low
);
2523 LOG_WARNING("Overlapping register ranges - Register range starting from %u overlaps "
2524 "with already exposed register/range at %u.", low
, entry
->low
);
2527 if (entry
->name
&& name
&& (strcasecmp(entry
->name
, name
) == 0)) {
2528 LOG_ERROR("Duplicate register name \"%s\" found.", name
);
2535 range_list_t
*range
= calloc(1, sizeof(range_list_t
));
2537 LOG_ERROR("Failed to allocate range list.");
2546 list_add(&range
->list
, ranges
);
2548 arg
= strtok(NULL
, ",");
2555 COMMAND_HANDLER(riscv_set_expose_csrs
)
2557 if (CMD_ARGC
== 0) {
2558 LOG_ERROR("Command expects parameters");
2559 return ERROR_COMMAND_SYNTAX_ERROR
;
2562 struct target
*target
= get_current_target(CMD_CTX
);
2566 for (unsigned int i
= 0; i
< CMD_ARGC
; i
++) {
2567 ret
= parse_ranges(&info
->expose_csr
, CMD_ARGV
[i
], "csr", 0xfff);
2568 if (ret
!= ERROR_OK
)
2575 COMMAND_HANDLER(riscv_set_expose_custom
)
2577 if (CMD_ARGC
== 0) {
2578 LOG_ERROR("Command expects parameters");
2579 return ERROR_COMMAND_SYNTAX_ERROR
;
2582 struct target
*target
= get_current_target(CMD_CTX
);
2586 for (unsigned int i
= 0; i
< CMD_ARGC
; i
++) {
2587 ret
= parse_ranges(&info
->expose_custom
, CMD_ARGV
[i
], "custom", 0x3fff);
2588 if (ret
!= ERROR_OK
)
2595 COMMAND_HANDLER(riscv_authdata_read
)
2597 unsigned int index
= 0;
2598 if (CMD_ARGC
== 0) {
2600 } else if (CMD_ARGC
== 1) {
2601 COMMAND_PARSE_NUMBER(uint
, CMD_ARGV
[0], index
);
2603 LOG_ERROR("Command takes at most one parameter");
2604 return ERROR_COMMAND_SYNTAX_ERROR
;
2607 struct target
*target
= get_current_target(CMD_CTX
);
2609 LOG_ERROR("target is NULL!");
2615 LOG_ERROR("riscv_info is NULL!");
2619 if (r
->authdata_read
) {
2621 if (r
->authdata_read(target
, &value
, index
) != ERROR_OK
)
2623 command_print_sameline(CMD
, "0x%08" PRIx32
, value
);
2626 LOG_ERROR("authdata_read is not implemented for this target.");
2631 COMMAND_HANDLER(riscv_authdata_write
)
2634 unsigned int index
= 0;
2636 if (CMD_ARGC
== 0 || CMD_ARGC
> 2)
2637 return ERROR_COMMAND_SYNTAX_ERROR
;
2639 if (CMD_ARGC
== 1) {
2640 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], value
);
2642 COMMAND_PARSE_NUMBER(uint
, CMD_ARGV
[0], index
);
2643 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], value
);
2646 struct target
*target
= get_current_target(CMD_CTX
);
2649 if (!r
->authdata_write
) {
2650 LOG_ERROR("authdata_write is not implemented for this target.");
2654 return r
->authdata_write(target
, value
, index
);
2657 COMMAND_HANDLER(riscv_dmi_read
)
2659 if (CMD_ARGC
!= 1) {
2660 LOG_ERROR("Command takes 1 parameter");
2661 return ERROR_COMMAND_SYNTAX_ERROR
;
2664 struct target
*target
= get_current_target(CMD_CTX
);
2666 LOG_ERROR("target is NULL!");
2672 LOG_ERROR("riscv_info is NULL!");
2677 uint32_t address
, value
;
2678 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], address
);
2679 if (r
->dmi_read(target
, &value
, address
) != ERROR_OK
)
2681 command_print(CMD
, "0x%" PRIx32
, value
);
2684 LOG_ERROR("dmi_read is not implemented for this target.");
2690 COMMAND_HANDLER(riscv_dmi_write
)
2692 if (CMD_ARGC
!= 2) {
2693 LOG_ERROR("Command takes exactly 2 arguments");
2694 return ERROR_COMMAND_SYNTAX_ERROR
;
2697 struct target
*target
= get_current_target(CMD_CTX
);
2700 uint32_t address
, value
;
2701 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], address
);
2702 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], value
);
2705 return r
->dmi_write(target
, address
, value
);
2707 LOG_ERROR("dmi_write is not implemented for this target.");
2712 COMMAND_HANDLER(riscv_reset_delays
)
2717 LOG_ERROR("Command takes at most one argument");
2718 return ERROR_COMMAND_SYNTAX_ERROR
;
2722 COMMAND_PARSE_NUMBER(int, CMD_ARGV
[0], wait
);
2724 struct target
*target
= get_current_target(CMD_CTX
);
2726 r
->reset_delays_wait
= wait
;
2730 COMMAND_HANDLER(riscv_set_ir
)
2732 if (CMD_ARGC
!= 2) {
2733 LOG_ERROR("Command takes exactly 2 arguments");
2734 return ERROR_COMMAND_SYNTAX_ERROR
;
2738 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], value
);
2740 if (!strcmp(CMD_ARGV
[0], "idcode"))
2741 buf_set_u32(ir_idcode
, 0, 32, value
);
2742 else if (!strcmp(CMD_ARGV
[0], "dtmcs"))
2743 buf_set_u32(ir_dtmcontrol
, 0, 32, value
);
2744 else if (!strcmp(CMD_ARGV
[0], "dmi"))
2745 buf_set_u32(ir_dbus
, 0, 32, value
);
2752 COMMAND_HANDLER(riscv_resume_order
)
2755 LOG_ERROR("Command takes at most one argument");
2756 return ERROR_COMMAND_SYNTAX_ERROR
;
2759 if (!strcmp(CMD_ARGV
[0], "normal")) {
2760 resume_order
= RO_NORMAL
;
2761 } else if (!strcmp(CMD_ARGV
[0], "reversed")) {
2762 resume_order
= RO_REVERSED
;
2764 LOG_ERROR("Unsupported resume order: %s", CMD_ARGV
[0]);
2771 COMMAND_HANDLER(riscv_use_bscan_tunnel
)
2774 int tunnel_type
= BSCAN_TUNNEL_NESTED_TAP
;
2777 LOG_ERROR("Command takes at most two arguments");
2778 return ERROR_COMMAND_SYNTAX_ERROR
;
2779 } else if (CMD_ARGC
== 1) {
2780 COMMAND_PARSE_NUMBER(int, CMD_ARGV
[0], irwidth
);
2781 } else if (CMD_ARGC
== 2) {
2782 COMMAND_PARSE_NUMBER(int, CMD_ARGV
[0], irwidth
);
2783 COMMAND_PARSE_NUMBER(int, CMD_ARGV
[1], tunnel_type
);
2785 if (tunnel_type
== BSCAN_TUNNEL_NESTED_TAP
)
2786 LOG_INFO("Nested Tap based Bscan Tunnel Selected");
2787 else if (tunnel_type
== BSCAN_TUNNEL_DATA_REGISTER
)
2788 LOG_INFO("Simple Register based Bscan Tunnel Selected");
2790 LOG_INFO("Invalid Tunnel type selected ! : selecting default Nested Tap Type");
2792 bscan_tunnel_type
= tunnel_type
;
2793 bscan_tunnel_ir_width
= irwidth
;
2797 COMMAND_HANDLER(riscv_set_enable_virt2phys
)
2799 if (CMD_ARGC
!= 1) {
2800 LOG_ERROR("Command takes exactly 1 parameter");
2801 return ERROR_COMMAND_SYNTAX_ERROR
;
2803 COMMAND_PARSE_ON_OFF(CMD_ARGV
[0], riscv_enable_virt2phys
);
2807 COMMAND_HANDLER(riscv_set_ebreakm
)
2809 if (CMD_ARGC
!= 1) {
2810 LOG_ERROR("Command takes exactly 1 parameter");
2811 return ERROR_COMMAND_SYNTAX_ERROR
;
2813 COMMAND_PARSE_ON_OFF(CMD_ARGV
[0], riscv_ebreakm
);
2817 COMMAND_HANDLER(riscv_set_ebreaks
)
2819 if (CMD_ARGC
!= 1) {
2820 LOG_ERROR("Command takes exactly 1 parameter");
2821 return ERROR_COMMAND_SYNTAX_ERROR
;
2823 COMMAND_PARSE_ON_OFF(CMD_ARGV
[0], riscv_ebreaks
);
2827 COMMAND_HANDLER(riscv_set_ebreaku
)
2829 if (CMD_ARGC
!= 1) {
2830 LOG_ERROR("Command takes exactly 1 parameter");
2831 return ERROR_COMMAND_SYNTAX_ERROR
;
2833 COMMAND_PARSE_ON_OFF(CMD_ARGV
[0], riscv_ebreaku
);
2837 COMMAND_HELPER(riscv_print_info_line
, const char *section
, const char *key
,
2841 snprintf(full_key
, sizeof(full_key
), "%s.%s", section
, key
);
2842 command_print(CMD
, "%-21s %3d", full_key
, value
);
2846 COMMAND_HANDLER(handle_info
)
2848 struct target
*target
= get_current_target(CMD_CTX
);
2851 /* This output format can be fed directly into TCL's "array set". */
2853 riscv_print_info_line(CMD
, "hart", "xlen", riscv_xlen(target
));
2854 riscv_enumerate_triggers(target
);
2855 riscv_print_info_line(CMD
, "hart", "trigger_count",
2859 return CALL_COMMAND_HANDLER(r
->print_info
, target
);
2864 static const struct command_registration riscv_exec_command_handlers
[] = {
2867 .handler
= handle_info
,
2868 .mode
= COMMAND_EXEC
,
2870 .help
= "Displays some information OpenOCD detected about the target."
2873 .name
= "set_command_timeout_sec",
2874 .handler
= riscv_set_command_timeout_sec
,
2875 .mode
= COMMAND_ANY
,
2877 .help
= "Set the wall-clock timeout (in seconds) for individual commands"
2880 .name
= "set_reset_timeout_sec",
2881 .handler
= riscv_set_reset_timeout_sec
,
2882 .mode
= COMMAND_ANY
,
2884 .help
= "Set the wall-clock timeout (in seconds) after reset is deasserted"
2887 .name
= "set_mem_access",
2888 .handler
= riscv_set_mem_access
,
2889 .mode
= COMMAND_ANY
,
2890 .usage
= "method1 [method2] [method3]",
2891 .help
= "Set which memory access methods shall be used and in which order "
2892 "of priority. Method can be one of: 'progbuf', 'sysbus' or 'abstract'."
2895 .name
= "set_enable_virtual",
2896 .handler
= riscv_set_enable_virtual
,
2897 .mode
= COMMAND_ANY
,
2899 .help
= "When on, memory accesses are performed on physical or virtual "
2900 "memory depending on the current system configuration. "
2901 "When off (default), all memory accessses are performed on physical memory."
2904 .name
= "expose_csrs",
2905 .handler
= riscv_set_expose_csrs
,
2906 .mode
= COMMAND_CONFIG
,
2907 .usage
= "n0[-m0|=name0][,n1[-m1|=name1]]...",
2908 .help
= "Configure a list of inclusive ranges for CSRs to expose in "
2909 "addition to the standard ones. This must be executed before "
2913 .name
= "expose_custom",
2914 .handler
= riscv_set_expose_custom
,
2915 .mode
= COMMAND_CONFIG
,
2916 .usage
= "n0[-m0|=name0][,n1[-m1|=name1]]...",
2917 .help
= "Configure a list of inclusive ranges for custom registers to "
2918 "expose. custom0 is accessed as abstract register number 0xc000, "
2919 "etc. This must be executed before `init`."
2922 .name
= "authdata_read",
2923 .handler
= riscv_authdata_read
,
2925 .mode
= COMMAND_ANY
,
2926 .help
= "Return the 32-bit value read from authdata or authdata0 "
2927 "(index=0), or authdata1 (index=1)."
2930 .name
= "authdata_write",
2931 .handler
= riscv_authdata_write
,
2932 .mode
= COMMAND_ANY
,
2933 .usage
= "[index] value",
2934 .help
= "Write the 32-bit value to authdata or authdata0 (index=0), "
2935 "or authdata1 (index=1)."
2939 .handler
= riscv_dmi_read
,
2940 .mode
= COMMAND_ANY
,
2942 .help
= "Perform a 32-bit DMI read at address, returning the value."
2945 .name
= "dmi_write",
2946 .handler
= riscv_dmi_write
,
2947 .mode
= COMMAND_ANY
,
2948 .usage
= "address value",
2949 .help
= "Perform a 32-bit DMI write of value at address."
2952 .name
= "reset_delays",
2953 .handler
= riscv_reset_delays
,
2954 .mode
= COMMAND_ANY
,
2956 .help
= "OpenOCD learns how many Run-Test/Idle cycles are required "
2957 "between scans to avoid encountering the target being busy. This "
2958 "command resets those learned values after `wait` scans. It's only "
2959 "useful for testing OpenOCD itself."
2962 .name
= "resume_order",
2963 .handler
= riscv_resume_order
,
2964 .mode
= COMMAND_ANY
,
2965 .usage
= "normal|reversed",
2966 .help
= "Choose the order that harts are resumed in when `hasel` is not "
2967 "supported. Normal order is from lowest hart index to highest. "
2968 "Reversed order is from highest hart index to lowest."
2972 .handler
= riscv_set_ir
,
2973 .mode
= COMMAND_ANY
,
2974 .usage
= "[idcode|dtmcs|dmi] value",
2975 .help
= "Set IR value for specified JTAG register."
2978 .name
= "use_bscan_tunnel",
2979 .handler
= riscv_use_bscan_tunnel
,
2980 .mode
= COMMAND_ANY
,
2981 .usage
= "value [type]",
2982 .help
= "Enable or disable use of a BSCAN tunnel to reach DM. Supply "
2983 "the width of the DM transport TAP's instruction register to "
2984 "enable. Supply a value of 0 to disable. Pass A second argument "
2985 "(optional) to indicate Bscan Tunnel Type {0:(default) NESTED_TAP , "
2989 .name
= "set_enable_virt2phys",
2990 .handler
= riscv_set_enable_virt2phys
,
2991 .mode
= COMMAND_ANY
,
2993 .help
= "When on (default), enable translation from virtual address to "
2997 .name
= "set_ebreakm",
2998 .handler
= riscv_set_ebreakm
,
2999 .mode
= COMMAND_ANY
,
3001 .help
= "Control dcsr.ebreakm. When off, M-mode ebreak instructions "
3002 "don't trap to OpenOCD. Defaults to on."
3005 .name
= "set_ebreaks",
3006 .handler
= riscv_set_ebreaks
,
3007 .mode
= COMMAND_ANY
,
3009 .help
= "Control dcsr.ebreaks. When off, S-mode ebreak instructions "
3010 "don't trap to OpenOCD. Defaults to on."
3013 .name
= "set_ebreaku",
3014 .handler
= riscv_set_ebreaku
,
3015 .mode
= COMMAND_ANY
,
3017 .help
= "Control dcsr.ebreaku. When off, U-mode ebreak instructions "
3018 "don't trap to OpenOCD. Defaults to on."
3020 COMMAND_REGISTRATION_DONE
3024 * To be noted that RISC-V targets use the same semihosting commands as
3027 * The main reason is compatibility with existing tools. For example the
3028 * Eclipse OpenOCD/SEGGER J-Link/QEMU plug-ins have several widgets to
3029 * configure semihosting, which generate commands like `arm semihosting
3031 * A secondary reason is the fact that the protocol used is exactly the
3032 * one specified by ARM. If RISC-V will ever define its own semihosting
3033 * protocol, then a command like `riscv semihosting enable` will make
3034 * sense, but for now all semihosting commands are prefixed with `arm`.
3037 static const struct command_registration riscv_command_handlers
[] = {
3040 .mode
= COMMAND_ANY
,
3041 .help
= "RISC-V Command Group",
3043 .chain
= riscv_exec_command_handlers
3047 .mode
= COMMAND_ANY
,
3048 .help
= "ARM Command Group",
3050 .chain
= semihosting_common_handlers
3052 COMMAND_REGISTRATION_DONE
3055 static unsigned riscv_xlen_nonconst(struct target
*target
)
3057 return riscv_xlen(target
);
3060 static unsigned int riscv_data_bits(struct target
*target
)
3064 return r
->data_bits(target
);
3065 return riscv_xlen(target
);
3068 struct target_type riscv_target
= {
3071 .target_create
= riscv_create_target
,
3072 .init_target
= riscv_init_target
,
3073 .deinit_target
= riscv_deinit_target
,
3074 .examine
= riscv_examine
,
3076 /* poll current target status */
3077 .poll
= old_or_new_riscv_poll
,
3080 .resume
= riscv_target_resume
,
3081 .step
= old_or_new_riscv_step
,
3083 .assert_reset
= riscv_assert_reset
,
3084 .deassert_reset
= riscv_deassert_reset
,
3086 .read_memory
= riscv_read_memory
,
3087 .write_memory
= riscv_write_memory
,
3088 .read_phys_memory
= riscv_read_phys_memory
,
3089 .write_phys_memory
= riscv_write_phys_memory
,
3091 .checksum_memory
= riscv_checksum_memory
,
3094 .virt2phys
= riscv_virt2phys
,
3096 .get_gdb_arch
= riscv_get_gdb_arch
,
3097 .get_gdb_reg_list
= riscv_get_gdb_reg_list
,
3098 .get_gdb_reg_list_noread
= riscv_get_gdb_reg_list_noread
,
3100 .add_breakpoint
= riscv_add_breakpoint
,
3101 .remove_breakpoint
= riscv_remove_breakpoint
,
3103 .add_watchpoint
= riscv_add_watchpoint
,
3104 .remove_watchpoint
= riscv_remove_watchpoint
,
3105 .hit_watchpoint
= riscv_hit_watchpoint
,
3107 .arch_state
= riscv_arch_state
,
3109 .run_algorithm
= riscv_run_algorithm
,
3111 .commands
= riscv_command_handlers
,
3113 .address_bits
= riscv_xlen_nonconst
,
3114 .data_bits
= riscv_data_bits
3117 /*** RISC-V Interface ***/
3119 /* Initializes the shared RISC-V structure. */
3120 static void riscv_info_init(struct target
*target
, struct riscv_info
*r
)
3122 memset(r
, 0, sizeof(*r
));
3124 r
->common_magic
= RISCV_COMMON_MAGIC
;
3127 r
->current_hartid
= target
->coreid
;
3128 r
->version_specific
= NULL
;
3130 memset(r
->trigger_unique_id
, 0xff, sizeof(r
->trigger_unique_id
));
3134 r
->mem_access_methods
[0] = RISCV_MEM_ACCESS_PROGBUF
;
3135 r
->mem_access_methods
[1] = RISCV_MEM_ACCESS_SYSBUS
;
3136 r
->mem_access_methods
[2] = RISCV_MEM_ACCESS_ABSTRACT
;
3138 r
->mem_access_progbuf_warn
= true;
3139 r
->mem_access_sysbus_warn
= true;
3140 r
->mem_access_abstract_warn
= true;
3142 INIT_LIST_HEAD(&r
->expose_csr
);
3143 INIT_LIST_HEAD(&r
->expose_custom
);
3146 static int riscv_resume_go_all_harts(struct target
*target
)
3150 LOG_DEBUG("[%s] resuming hart", target_name(target
));
3151 if (riscv_select_current_hart(target
) != ERROR_OK
)
3153 if (riscv_is_halted(target
)) {
3154 if (r
->resume_go(target
) != ERROR_OK
)
3157 LOG_DEBUG("[%s] hart requested resume, but was already resumed",
3158 target_name(target
));
3161 riscv_invalidate_register_cache(target
);
3165 /* Steps the hart that's currently selected in the RTOS, or if there is no RTOS
3166 * then the only hart. */
3167 static int riscv_step_rtos_hart(struct target
*target
)
3170 if (riscv_select_current_hart(target
) != ERROR_OK
)
3172 LOG_DEBUG("[%s] stepping", target_name(target
));
3174 if (!riscv_is_halted(target
)) {
3175 LOG_ERROR("Hart isn't halted before single step!");
3178 riscv_invalidate_register_cache(target
);
3180 if (r
->step_current_hart(target
) != ERROR_OK
)
3182 riscv_invalidate_register_cache(target
);
3184 if (!riscv_is_halted(target
)) {
3185 LOG_ERROR("Hart was not halted after single step!");
3191 bool riscv_supports_extension(struct target
*target
, char letter
)
3195 if (letter
>= 'a' && letter
<= 'z')
3197 else if (letter
>= 'A' && letter
<= 'Z')
3201 return r
->misa
& BIT(num
);
3204 unsigned riscv_xlen(const struct target
*target
)
3210 int riscv_set_current_hartid(struct target
*target
, int hartid
)
3213 if (!r
->select_current_hart
)
3216 int previous_hartid
= riscv_current_hartid(target
);
3217 r
->current_hartid
= hartid
;
3218 LOG_DEBUG("setting hartid to %d, was %d", hartid
, previous_hartid
);
3219 if (r
->select_current_hart(target
) != ERROR_OK
)
3225 /* Invalidates the register cache. */
3226 static void riscv_invalidate_register_cache(struct target
*target
)
3228 LOG_DEBUG("[%d]", target
->coreid
);
3229 register_cache_invalidate(target
->reg_cache
);
3230 for (size_t i
= 0; i
< target
->reg_cache
->num_regs
; ++i
) {
3231 struct reg
*reg
= &target
->reg_cache
->reg_list
[i
];
3236 int riscv_current_hartid(const struct target
*target
)
3239 return r
->current_hartid
;
3242 int riscv_count_harts(struct target
*target
)
3247 if (!r
|| !r
->hart_count
)
3249 return r
->hart_count(target
);
3254 * return true iff we are guaranteed that the register will contain exactly
3255 * the value we just wrote when it's read.
3256 * If write is false:
3257 * return true iff we are guaranteed that the register will read the same
3258 * value in the future as the value we just read.
3260 static bool gdb_regno_cacheable(enum gdb_regno regno
, bool write
)
3262 /* GPRs, FPRs, vector registers are just normal data stores. */
3263 if (regno
<= GDB_REGNO_XPR31
||
3264 (regno
>= GDB_REGNO_FPR0
&& regno
<= GDB_REGNO_FPR31
) ||
3265 (regno
>= GDB_REGNO_V0
&& regno
<= GDB_REGNO_V31
))
3268 /* Most CSRs won't change value on us, but we can't assume it about arbitrary
3274 case GDB_REGNO_VSTART
:
3275 case GDB_REGNO_VXSAT
:
3276 case GDB_REGNO_VXRM
:
3277 case GDB_REGNO_VLENB
:
3279 case GDB_REGNO_VTYPE
:
3280 case GDB_REGNO_MISA
:
3281 case GDB_REGNO_DCSR
:
3282 case GDB_REGNO_DSCRATCH0
:
3283 case GDB_REGNO_MSTATUS
:
3284 case GDB_REGNO_MEPC
:
3285 case GDB_REGNO_MCAUSE
:
3286 case GDB_REGNO_SATP
:
3288 * WARL registers might not contain the value we just wrote, but
3289 * these ones won't spontaneously change their value either. *
3293 case GDB_REGNO_TSELECT
: /* I think this should be above, but then it doesn't work. */
3294 case GDB_REGNO_TDATA1
: /* Changes value when tselect is changed. */
3295 case GDB_REGNO_TDATA2
: /* Changse value when tselect is changed. */
3302 * This function is called when the debug user wants to change the value of a
3303 * register. The new value may be cached, and may not be written until the hart
3305 int riscv_set_register(struct target
*target
, enum gdb_regno regid
, riscv_reg_t value
)
3308 LOG_DEBUG("[%s] %s <- %" PRIx64
, target_name(target
), gdb_regno_name(regid
), value
);
3309 assert(r
->set_register
);
3313 /* TODO: Hack to deal with gdb that thinks these registers still exist. */
3314 if (regid
> GDB_REGNO_XPR15
&& regid
<= GDB_REGNO_XPR31
&& value
== 0 &&
3315 riscv_supports_extension(target
, 'E'))
3318 struct reg
*reg
= &target
->reg_cache
->reg_list
[regid
];
3319 buf_set_u64(reg
->value
, 0, reg
->size
, value
);
3321 int result
= r
->set_register(target
, regid
, value
);
3322 if (result
== ERROR_OK
)
3323 reg
->valid
= gdb_regno_cacheable(regid
, true);
3326 LOG_DEBUG("[%s] wrote 0x%" PRIx64
" to %s valid=%d",
3327 target_name(target
), value
, reg
->name
, reg
->valid
);
3331 int riscv_get_register(struct target
*target
, riscv_reg_t
*value
,
3332 enum gdb_regno regid
)
3338 struct reg
*reg
= &target
->reg_cache
->reg_list
[regid
];
3340 LOG_DEBUG("[%s] %s does not exist.",
3341 target_name(target
), gdb_regno_name(regid
));
3345 if (reg
&& reg
->valid
) {
3346 *value
= buf_get_u64(reg
->value
, 0, reg
->size
);
3347 LOG_DEBUG("[%s] %s: %" PRIx64
" (cached)", target_name(target
),
3348 gdb_regno_name(regid
), *value
);
3352 /* TODO: Hack to deal with gdb that thinks these registers still exist. */
3353 if (regid
> GDB_REGNO_XPR15
&& regid
<= GDB_REGNO_XPR31
&&
3354 riscv_supports_extension(target
, 'E')) {
3359 int result
= r
->get_register(target
, value
, regid
);
3361 if (result
== ERROR_OK
)
3362 reg
->valid
= gdb_regno_cacheable(regid
, false);
3364 LOG_DEBUG("[%s] %s: %" PRIx64
, target_name(target
),
3365 gdb_regno_name(regid
), *value
);
3369 bool riscv_is_halted(struct target
*target
)
3372 assert(r
->is_halted
);
3373 return r
->is_halted(target
);
3376 static enum riscv_halt_reason
riscv_halt_reason(struct target
*target
, int hartid
)
3379 if (riscv_set_current_hartid(target
, hartid
) != ERROR_OK
)
3380 return RISCV_HALT_ERROR
;
3381 if (!riscv_is_halted(target
)) {
3382 LOG_ERROR("Hart is not halted!");
3383 return RISCV_HALT_UNKNOWN
;
3385 return r
->halt_reason(target
);
3388 size_t riscv_debug_buffer_size(struct target
*target
)
3391 return r
->debug_buffer_size
;
3394 int riscv_write_debug_buffer(struct target
*target
, int index
, riscv_insn_t insn
)
3397 r
->write_debug_buffer(target
, index
, insn
);
3401 riscv_insn_t
riscv_read_debug_buffer(struct target
*target
, int index
)
3404 return r
->read_debug_buffer(target
, index
);
3407 int riscv_execute_debug_buffer(struct target
*target
)
3410 return r
->execute_debug_buffer(target
);
3413 void riscv_fill_dmi_write_u64(struct target
*target
, char *buf
, int a
, uint64_t d
)
3416 r
->fill_dmi_write_u64(target
, buf
, a
, d
);
3419 void riscv_fill_dmi_read_u64(struct target
*target
, char *buf
, int a
)
3422 r
->fill_dmi_read_u64(target
, buf
, a
);
3425 void riscv_fill_dmi_nop_u64(struct target
*target
, char *buf
)
3428 r
->fill_dmi_nop_u64(target
, buf
);
3431 int riscv_dmi_write_u64_bits(struct target
*target
)
3434 return r
->dmi_write_u64_bits(target
);
3438 * Count triggers, and initialize trigger_count for each hart.
3439 * trigger_count is initialized even if this function fails to discover
3441 * Disable any hardware triggers that have dmode set. We can't have set them
3442 * ourselves. Maybe they're left over from some killed debug session.
3444 int riscv_enumerate_triggers(struct target
*target
)
3448 if (r
->triggers_enumerated
)
3451 r
->triggers_enumerated
= true; /* At the very least we tried. */
3453 riscv_reg_t tselect
;
3454 int result
= riscv_get_register(target
, &tselect
, GDB_REGNO_TSELECT
);
3455 /* If tselect is not readable, the trigger module is likely not
3456 * implemented. There are no triggers to enumerate then and no error
3457 * should be thrown. */
3458 if (result
!= ERROR_OK
) {
3459 LOG_DEBUG("[%s] Cannot access tselect register. "
3460 "Assuming that triggers are not implemented.", target_name(target
));
3461 r
->trigger_count
= 0;
3465 for (unsigned int t
= 0; t
< RISCV_MAX_TRIGGERS
; ++t
) {
3466 r
->trigger_count
= t
;
3468 /* If we can't write tselect, then this hart does not support triggers. */
3469 if (riscv_set_register(target
, GDB_REGNO_TSELECT
, t
) != ERROR_OK
)
3471 uint64_t tselect_rb
;
3472 result
= riscv_get_register(target
, &tselect_rb
, GDB_REGNO_TSELECT
);
3473 if (result
!= ERROR_OK
)
3475 /* Mask off the top bit, which is used as tdrmode in old
3476 * implementations. */
3477 tselect_rb
&= ~(1ULL << (riscv_xlen(target
) - 1));
3478 if (tselect_rb
!= t
)
3481 result
= riscv_get_register(target
, &tdata1
, GDB_REGNO_TDATA1
);
3482 if (result
!= ERROR_OK
)
3485 int type
= get_field(tdata1
, MCONTROL_TYPE(riscv_xlen(target
)));
3490 /* On these older cores we don't support software using
3492 riscv_set_register(target
, GDB_REGNO_TDATA1
, 0);
3495 if (tdata1
& MCONTROL_DMODE(riscv_xlen(target
)))
3496 riscv_set_register(target
, GDB_REGNO_TDATA1
, 0);
3499 if (tdata1
& MCONTROL_DMODE(riscv_xlen(target
)))
3500 riscv_set_register(target
, GDB_REGNO_TDATA1
, 0);
3505 riscv_set_register(target
, GDB_REGNO_TSELECT
, tselect
);
3507 LOG_INFO("[%s] Found %d triggers", target_name(target
), r
->trigger_count
);
3512 const char *gdb_regno_name(enum gdb_regno regno
)
3514 static char buf
[32];
3517 case GDB_REGNO_ZERO
:
3583 case GDB_REGNO_FPR0
:
3585 case GDB_REGNO_FPR31
:
3587 case GDB_REGNO_CSR0
:
3589 case GDB_REGNO_TSELECT
:
3591 case GDB_REGNO_TDATA1
:
3593 case GDB_REGNO_TDATA2
:
3595 case GDB_REGNO_MISA
:
3599 case GDB_REGNO_DCSR
:
3601 case GDB_REGNO_DSCRATCH0
:
3603 case GDB_REGNO_MSTATUS
:
3605 case GDB_REGNO_MEPC
:
3607 case GDB_REGNO_MCAUSE
:
3609 case GDB_REGNO_PRIV
:
3611 case GDB_REGNO_SATP
:
3613 case GDB_REGNO_VTYPE
:
3682 if (regno
<= GDB_REGNO_XPR31
)
3683 sprintf(buf
, "x%d", regno
- GDB_REGNO_ZERO
);
3684 else if (regno
>= GDB_REGNO_CSR0
&& regno
<= GDB_REGNO_CSR4095
)
3685 sprintf(buf
, "csr%d", regno
- GDB_REGNO_CSR0
);
3686 else if (regno
>= GDB_REGNO_FPR0
&& regno
<= GDB_REGNO_FPR31
)
3687 sprintf(buf
, "f%d", regno
- GDB_REGNO_FPR0
);
3689 sprintf(buf
, "gdb_regno_%d", regno
);
3694 static int register_get(struct reg
*reg
)
3696 riscv_reg_info_t
*reg_info
= reg
->arch_info
;
3697 struct target
*target
= reg_info
->target
;
3700 if (reg
->number
>= GDB_REGNO_V0
&& reg
->number
<= GDB_REGNO_V31
) {
3701 if (!r
->get_register_buf
) {
3702 LOG_ERROR("Reading register %s not supported on this RISC-V target.",
3703 gdb_regno_name(reg
->number
));
3707 if (r
->get_register_buf(target
, reg
->value
, reg
->number
) != ERROR_OK
)
3711 int result
= riscv_get_register(target
, &value
, reg
->number
);
3712 if (result
!= ERROR_OK
)
3714 buf_set_u64(reg
->value
, 0, reg
->size
, value
);
3716 reg
->valid
= gdb_regno_cacheable(reg
->number
, false);
3717 char *str
= buf_to_hex_str(reg
->value
, reg
->size
);
3718 LOG_DEBUG("[%s] read 0x%s from %s (valid=%d)", target_name(target
),
3719 str
, reg
->name
, reg
->valid
);
3724 static int register_set(struct reg
*reg
, uint8_t *buf
)
3726 riscv_reg_info_t
*reg_info
= reg
->arch_info
;
3727 struct target
*target
= reg_info
->target
;
3730 char *str
= buf_to_hex_str(buf
, reg
->size
);
3731 LOG_DEBUG("[%s] write 0x%s to %s (valid=%d)", target_name(target
),
3732 str
, reg
->name
, reg
->valid
);
3735 /* Exit early for writing x0, which on the hardware would be ignored, and we
3736 * don't want to update our cache. */
3737 if (reg
->number
== GDB_REGNO_ZERO
)
3740 memcpy(reg
->value
, buf
, DIV_ROUND_UP(reg
->size
, 8));
3741 reg
->valid
= gdb_regno_cacheable(reg
->number
, true);
3743 if (reg
->number
== GDB_REGNO_TDATA1
||
3744 reg
->number
== GDB_REGNO_TDATA2
) {
3745 r
->manual_hwbp_set
= true;
3746 /* When enumerating triggers, we clear any triggers with DMODE set,
3747 * assuming they were left over from a previous debug session. So make
3748 * sure that is done before a user might be setting their own triggers.
3750 if (riscv_enumerate_triggers(target
) != ERROR_OK
)
3754 if (reg
->number
>= GDB_REGNO_V0
&& reg
->number
<= GDB_REGNO_V31
) {
3755 if (!r
->set_register_buf
) {
3756 LOG_ERROR("Writing register %s not supported on this RISC-V target.",
3757 gdb_regno_name(reg
->number
));
3761 if (r
->set_register_buf(target
, reg
->number
, reg
->value
) != ERROR_OK
)
3764 uint64_t value
= buf_get_u64(buf
, 0, reg
->size
);
3765 if (riscv_set_register(target
, reg
->number
, value
) != ERROR_OK
)
3772 static struct reg_arch_type riscv_reg_arch_type
= {
3773 .get
= register_get
,
3782 static int cmp_csr_info(const void *p1
, const void *p2
)
3784 return (int) (((struct csr_info
*)p1
)->number
) - (int) (((struct csr_info
*)p2
)->number
);
3787 int riscv_init_registers(struct target
*target
)
3791 riscv_free_registers(target
);
3793 target
->reg_cache
= calloc(1, sizeof(*target
->reg_cache
));
3794 if (!target
->reg_cache
)
3796 target
->reg_cache
->name
= "RISC-V Registers";
3797 target
->reg_cache
->num_regs
= GDB_REGNO_COUNT
;
3799 if (!list_empty(&info
->expose_custom
)) {
3800 range_list_t
*entry
;
3801 list_for_each_entry(entry
, &info
->expose_custom
, list
)
3802 target
->reg_cache
->num_regs
+= entry
->high
- entry
->low
+ 1;
3805 LOG_DEBUG("create register cache for %d registers",
3806 target
->reg_cache
->num_regs
);
3808 target
->reg_cache
->reg_list
=
3809 calloc(target
->reg_cache
->num_regs
, sizeof(struct reg
));
3810 if (!target
->reg_cache
->reg_list
)
3813 const unsigned int max_reg_name_len
= 12;
3814 free(info
->reg_names
);
3816 calloc(target
->reg_cache
->num_regs
, max_reg_name_len
);
3817 if (!info
->reg_names
)
3819 char *reg_name
= info
->reg_names
;
3821 static struct reg_feature feature_cpu
= {
3822 .name
= "org.gnu.gdb.riscv.cpu"
3824 static struct reg_feature feature_fpu
= {
3825 .name
= "org.gnu.gdb.riscv.fpu"
3827 static struct reg_feature feature_csr
= {
3828 .name
= "org.gnu.gdb.riscv.csr"
3830 static struct reg_feature feature_vector
= {
3831 .name
= "org.gnu.gdb.riscv.vector"
3833 static struct reg_feature feature_virtual
= {
3834 .name
= "org.gnu.gdb.riscv.virtual"
3836 static struct reg_feature feature_custom
= {
3837 .name
= "org.gnu.gdb.riscv.custom"
3840 /* These types are built into gdb. */
3841 static struct reg_data_type type_ieee_single
= { .type
= REG_TYPE_IEEE_SINGLE
, .id
= "ieee_single" };
3842 static struct reg_data_type type_ieee_double
= { .type
= REG_TYPE_IEEE_DOUBLE
, .id
= "ieee_double" };
3843 static struct reg_data_type_union_field single_double_fields
[] = {
3844 {"float", &type_ieee_single
, single_double_fields
+ 1},
3845 {"double", &type_ieee_double
, NULL
},
3847 static struct reg_data_type_union single_double_union
= {
3848 .fields
= single_double_fields
3850 static struct reg_data_type type_ieee_single_double
= {
3851 .type
= REG_TYPE_ARCH_DEFINED
,
3853 .type_class
= REG_TYPE_CLASS_UNION
,
3854 .reg_type_union
= &single_double_union
3856 static struct reg_data_type type_uint8
= { .type
= REG_TYPE_UINT8
, .id
= "uint8" };
3857 static struct reg_data_type type_uint16
= { .type
= REG_TYPE_UINT16
, .id
= "uint16" };
3858 static struct reg_data_type type_uint32
= { .type
= REG_TYPE_UINT32
, .id
= "uint32" };
3859 static struct reg_data_type type_uint64
= { .type
= REG_TYPE_UINT64
, .id
= "uint64" };
3860 static struct reg_data_type type_uint128
= { .type
= REG_TYPE_UINT128
, .id
= "uint128" };
3862 /* This is roughly the XML we want:
3863 * <vector id="bytes" type="uint8" count="16"/>
3864 * <vector id="shorts" type="uint16" count="8"/>
3865 * <vector id="words" type="uint32" count="4"/>
3866 * <vector id="longs" type="uint64" count="2"/>
3867 * <vector id="quads" type="uint128" count="1"/>
3868 * <union id="riscv_vector_type">
3869 * <field name="b" type="bytes"/>
3870 * <field name="s" type="shorts"/>
3871 * <field name="w" type="words"/>
3872 * <field name="l" type="longs"/>
3873 * <field name="q" type="quads"/>
3877 info
->vector_uint8
.type
= &type_uint8
;
3878 info
->vector_uint8
.count
= info
->vlenb
;
3879 info
->type_uint8_vector
.type
= REG_TYPE_ARCH_DEFINED
;
3880 info
->type_uint8_vector
.id
= "bytes";
3881 info
->type_uint8_vector
.type_class
= REG_TYPE_CLASS_VECTOR
;
3882 info
->type_uint8_vector
.reg_type_vector
= &info
->vector_uint8
;
3884 info
->vector_uint16
.type
= &type_uint16
;
3885 info
->vector_uint16
.count
= info
->vlenb
/ 2;
3886 info
->type_uint16_vector
.type
= REG_TYPE_ARCH_DEFINED
;
3887 info
->type_uint16_vector
.id
= "shorts";
3888 info
->type_uint16_vector
.type_class
= REG_TYPE_CLASS_VECTOR
;
3889 info
->type_uint16_vector
.reg_type_vector
= &info
->vector_uint16
;
3891 info
->vector_uint32
.type
= &type_uint32
;
3892 info
->vector_uint32
.count
= info
->vlenb
/ 4;
3893 info
->type_uint32_vector
.type
= REG_TYPE_ARCH_DEFINED
;
3894 info
->type_uint32_vector
.id
= "words";
3895 info
->type_uint32_vector
.type_class
= REG_TYPE_CLASS_VECTOR
;
3896 info
->type_uint32_vector
.reg_type_vector
= &info
->vector_uint32
;
3898 info
->vector_uint64
.type
= &type_uint64
;
3899 info
->vector_uint64
.count
= info
->vlenb
/ 8;
3900 info
->type_uint64_vector
.type
= REG_TYPE_ARCH_DEFINED
;
3901 info
->type_uint64_vector
.id
= "longs";
3902 info
->type_uint64_vector
.type_class
= REG_TYPE_CLASS_VECTOR
;
3903 info
->type_uint64_vector
.reg_type_vector
= &info
->vector_uint64
;
3905 info
->vector_uint128
.type
= &type_uint128
;
3906 info
->vector_uint128
.count
= info
->vlenb
/ 16;
3907 info
->type_uint128_vector
.type
= REG_TYPE_ARCH_DEFINED
;
3908 info
->type_uint128_vector
.id
= "quads";
3909 info
->type_uint128_vector
.type_class
= REG_TYPE_CLASS_VECTOR
;
3910 info
->type_uint128_vector
.reg_type_vector
= &info
->vector_uint128
;
3912 info
->vector_fields
[0].name
= "b";
3913 info
->vector_fields
[0].type
= &info
->type_uint8_vector
;
3914 if (info
->vlenb
>= 2) {
3915 info
->vector_fields
[0].next
= info
->vector_fields
+ 1;
3916 info
->vector_fields
[1].name
= "s";
3917 info
->vector_fields
[1].type
= &info
->type_uint16_vector
;
3919 info
->vector_fields
[0].next
= NULL
;
3921 if (info
->vlenb
>= 4) {
3922 info
->vector_fields
[1].next
= info
->vector_fields
+ 2;
3923 info
->vector_fields
[2].name
= "w";
3924 info
->vector_fields
[2].type
= &info
->type_uint32_vector
;
3926 info
->vector_fields
[1].next
= NULL
;
3928 if (info
->vlenb
>= 8) {
3929 info
->vector_fields
[2].next
= info
->vector_fields
+ 3;
3930 info
->vector_fields
[3].name
= "l";
3931 info
->vector_fields
[3].type
= &info
->type_uint64_vector
;
3933 info
->vector_fields
[2].next
= NULL
;
3935 if (info
->vlenb
>= 16) {
3936 info
->vector_fields
[3].next
= info
->vector_fields
+ 4;
3937 info
->vector_fields
[4].name
= "q";
3938 info
->vector_fields
[4].type
= &info
->type_uint128_vector
;
3940 info
->vector_fields
[3].next
= NULL
;
3942 info
->vector_fields
[4].next
= NULL
;
3944 info
->vector_union
.fields
= info
->vector_fields
;
3946 info
->type_vector
.type
= REG_TYPE_ARCH_DEFINED
;
3947 info
->type_vector
.id
= "riscv_vector";
3948 info
->type_vector
.type_class
= REG_TYPE_CLASS_UNION
;
3949 info
->type_vector
.reg_type_union
= &info
->vector_union
;
3951 struct csr_info csr_info
[] = {
3952 #define DECLARE_CSR(name, number) { number, #name },
3953 #include "encoding.h"
3956 /* encoding.h does not contain the registers in sorted order. */
3957 qsort(csr_info
, ARRAY_SIZE(csr_info
), sizeof(*csr_info
), cmp_csr_info
);
3958 unsigned csr_info_index
= 0;
3960 int custom_within_range
= 0;
3962 riscv_reg_info_t
*shared_reg_info
= calloc(1, sizeof(riscv_reg_info_t
));
3963 if (!shared_reg_info
)
3965 shared_reg_info
->target
= target
;
3967 /* When gdb requests register N, gdb_get_register_packet() assumes that this
3968 * is register at index N in reg_list. So if there are certain registers
3969 * that don't exist, we need to leave holes in the list (or renumber, but
3970 * it would be nice not to have yet another set of numbers to translate
3972 for (uint32_t number
= 0; number
< target
->reg_cache
->num_regs
; number
++) {
3973 struct reg
*r
= &target
->reg_cache
->reg_list
[number
];
3977 r
->type
= &riscv_reg_arch_type
;
3978 r
->arch_info
= shared_reg_info
;
3980 r
->size
= riscv_xlen(target
);
3981 /* r->size is set in riscv_invalidate_register_cache, maybe because the
3982 * target is in theory allowed to change XLEN on us. But I expect a lot
3983 * of other things to break in that case as well. */
3984 if (number
<= GDB_REGNO_XPR31
) {
3985 r
->exist
= number
<= GDB_REGNO_XPR15
||
3986 !riscv_supports_extension(target
, 'E');
3987 /* TODO: For now we fake that all GPRs exist because otherwise gdb
3990 r
->caller_save
= true;
3992 case GDB_REGNO_ZERO
:
4089 r
->group
= "general";
4090 r
->feature
= &feature_cpu
;
4091 } else if (number
== GDB_REGNO_PC
) {
4092 r
->caller_save
= true;
4093 sprintf(reg_name
, "pc");
4094 r
->group
= "general";
4095 r
->feature
= &feature_cpu
;
4096 } else if (number
>= GDB_REGNO_FPR0
&& number
<= GDB_REGNO_FPR31
) {
4097 r
->caller_save
= true;
4098 if (riscv_supports_extension(target
, 'D')) {
4100 if (riscv_supports_extension(target
, 'F'))
4101 r
->reg_data_type
= &type_ieee_single_double
;
4103 r
->reg_data_type
= &type_ieee_double
;
4104 } else if (riscv_supports_extension(target
, 'F')) {
4105 r
->reg_data_type
= &type_ieee_single
;
4189 case GDB_REGNO_FS10
:
4192 case GDB_REGNO_FS11
:
4201 case GDB_REGNO_FT10
:
4204 case GDB_REGNO_FT11
:
4209 r
->feature
= &feature_fpu
;
4210 } else if (number
>= GDB_REGNO_CSR0
&& number
<= GDB_REGNO_CSR4095
) {
4212 r
->feature
= &feature_csr
;
4213 unsigned csr_number
= number
- GDB_REGNO_CSR0
;
4215 while (csr_info
[csr_info_index
].number
< csr_number
&&
4216 csr_info_index
< ARRAY_SIZE(csr_info
) - 1) {
4219 if (csr_info
[csr_info_index
].number
== csr_number
) {
4220 r
->name
= csr_info
[csr_info_index
].name
;
4222 sprintf(reg_name
, "csr%d", csr_number
);
4223 /* Assume unnamed registers don't exist, unless we have some
4224 * configuration that tells us otherwise. That's important
4225 * because eg. Eclipse crashes if a target has too many
4226 * registers, and apparently has no way of only showing a
4227 * subset of registers in any case. */
4231 switch (csr_number
) {
4235 r
->exist
= riscv_supports_extension(target
, 'F');
4237 r
->feature
= &feature_fpu
;
4243 case CSR_SCOUNTEREN
:
4249 r
->exist
= riscv_supports_extension(target
, 'S');
4253 /* "In systems with only M-mode, or with both M-mode and
4254 * U-mode but without U-mode trap support, the medeleg and
4255 * mideleg registers should not exist." */
4256 r
->exist
= riscv_supports_extension(target
, 'S') ||
4257 riscv_supports_extension(target
, 'N');
4265 case CSR_HPMCOUNTER3H
:
4266 case CSR_HPMCOUNTER4H
:
4267 case CSR_HPMCOUNTER5H
:
4268 case CSR_HPMCOUNTER6H
:
4269 case CSR_HPMCOUNTER7H
:
4270 case CSR_HPMCOUNTER8H
:
4271 case CSR_HPMCOUNTER9H
:
4272 case CSR_HPMCOUNTER10H
:
4273 case CSR_HPMCOUNTER11H
:
4274 case CSR_HPMCOUNTER12H
:
4275 case CSR_HPMCOUNTER13H
:
4276 case CSR_HPMCOUNTER14H
:
4277 case CSR_HPMCOUNTER15H
:
4278 case CSR_HPMCOUNTER16H
:
4279 case CSR_HPMCOUNTER17H
:
4280 case CSR_HPMCOUNTER18H
:
4281 case CSR_HPMCOUNTER19H
:
4282 case CSR_HPMCOUNTER20H
:
4283 case CSR_HPMCOUNTER21H
:
4284 case CSR_HPMCOUNTER22H
:
4285 case CSR_HPMCOUNTER23H
:
4286 case CSR_HPMCOUNTER24H
:
4287 case CSR_HPMCOUNTER25H
:
4288 case CSR_HPMCOUNTER26H
:
4289 case CSR_HPMCOUNTER27H
:
4290 case CSR_HPMCOUNTER28H
:
4291 case CSR_HPMCOUNTER29H
:
4292 case CSR_HPMCOUNTER30H
:
4293 case CSR_HPMCOUNTER31H
:
4296 case CSR_MHPMCOUNTER3H
:
4297 case CSR_MHPMCOUNTER4H
:
4298 case CSR_MHPMCOUNTER5H
:
4299 case CSR_MHPMCOUNTER6H
:
4300 case CSR_MHPMCOUNTER7H
:
4301 case CSR_MHPMCOUNTER8H
:
4302 case CSR_MHPMCOUNTER9H
:
4303 case CSR_MHPMCOUNTER10H
:
4304 case CSR_MHPMCOUNTER11H
:
4305 case CSR_MHPMCOUNTER12H
:
4306 case CSR_MHPMCOUNTER13H
:
4307 case CSR_MHPMCOUNTER14H
:
4308 case CSR_MHPMCOUNTER15H
:
4309 case CSR_MHPMCOUNTER16H
:
4310 case CSR_MHPMCOUNTER17H
:
4311 case CSR_MHPMCOUNTER18H
:
4312 case CSR_MHPMCOUNTER19H
:
4313 case CSR_MHPMCOUNTER20H
:
4314 case CSR_MHPMCOUNTER21H
:
4315 case CSR_MHPMCOUNTER22H
:
4316 case CSR_MHPMCOUNTER23H
:
4317 case CSR_MHPMCOUNTER24H
:
4318 case CSR_MHPMCOUNTER25H
:
4319 case CSR_MHPMCOUNTER26H
:
4320 case CSR_MHPMCOUNTER27H
:
4321 case CSR_MHPMCOUNTER28H
:
4322 case CSR_MHPMCOUNTER29H
:
4323 case CSR_MHPMCOUNTER30H
:
4324 case CSR_MHPMCOUNTER31H
:
4325 r
->exist
= riscv_xlen(target
) == 32;
4334 r
->exist
= riscv_supports_extension(target
, 'V');
4338 if (!r
->exist
&& !list_empty(&info
->expose_csr
)) {
4339 range_list_t
*entry
;
4340 list_for_each_entry(entry
, &info
->expose_csr
, list
)
4341 if ((entry
->low
<= csr_number
) && (csr_number
<= entry
->high
)) {
4344 r
->name
= entry
->name
;
4347 LOG_DEBUG("Exposing additional CSR %d (name=%s)",
4348 csr_number
, entry
->name
? entry
->name
: reg_name
);
4355 } else if (number
== GDB_REGNO_PRIV
) {
4356 sprintf(reg_name
, "priv");
4357 r
->group
= "general";
4358 r
->feature
= &feature_virtual
;
4361 } else if (number
>= GDB_REGNO_V0
&& number
<= GDB_REGNO_V31
) {
4362 r
->caller_save
= false;
4363 r
->exist
= riscv_supports_extension(target
, 'V') && info
->vlenb
;
4364 r
->size
= info
->vlenb
* 8;
4365 sprintf(reg_name
, "v%d", number
- GDB_REGNO_V0
);
4366 r
->group
= "vector";
4367 r
->feature
= &feature_vector
;
4368 r
->reg_data_type
= &info
->type_vector
;
4370 } else if (number
>= GDB_REGNO_COUNT
) {
4371 /* Custom registers. */
4372 assert(!list_empty(&info
->expose_custom
));
4374 range_list_t
*range
= list_first_entry(&info
->expose_custom
, range_list_t
, list
);
4376 unsigned custom_number
= range
->low
+ custom_within_range
;
4378 r
->group
= "custom";
4379 r
->feature
= &feature_custom
;
4380 r
->arch_info
= calloc(1, sizeof(riscv_reg_info_t
));
4383 ((riscv_reg_info_t
*) r
->arch_info
)->target
= target
;
4384 ((riscv_reg_info_t
*) r
->arch_info
)->custom_number
= custom_number
;
4385 sprintf(reg_name
, "custom%d", custom_number
);
4389 r
->name
= range
->name
;
4392 LOG_DEBUG("Exposing additional custom register %d (name=%s)",
4393 number
, range
->name
? range
->name
: reg_name
);
4395 custom_within_range
++;
4396 if (custom_within_range
> range
->high
- range
->low
) {
4397 custom_within_range
= 0;
4398 list_rotate_left(&info
->expose_custom
);
4404 reg_name
+= strlen(reg_name
) + 1;
4405 assert(reg_name
< info
->reg_names
+ target
->reg_cache
->num_regs
*
4408 r
->value
= calloc(1, DIV_ROUND_UP(r
->size
, 8));
4415 void riscv_add_bscan_tunneled_scan(struct target
*target
, struct scan_field
*field
,
4416 riscv_bscan_tunneled_scan_context_t
*ctxt
)
4418 jtag_add_ir_scan(target
->tap
, &select_user4
, TAP_IDLE
);
4420 memset(ctxt
->tunneled_dr
, 0, sizeof(ctxt
->tunneled_dr
));
4421 if (bscan_tunnel_type
== BSCAN_TUNNEL_DATA_REGISTER
) {
4422 ctxt
->tunneled_dr
[3].num_bits
= 1;
4423 ctxt
->tunneled_dr
[3].out_value
= bscan_one
;
4424 ctxt
->tunneled_dr
[2].num_bits
= 7;
4425 ctxt
->tunneled_dr_width
= field
->num_bits
;
4426 ctxt
->tunneled_dr
[2].out_value
= &ctxt
->tunneled_dr_width
;
4427 /* for BSCAN tunnel, there is a one-TCK skew between shift in and shift out, so
4428 scanning num_bits + 1, and then will right shift the input field after executing the queues */
4430 ctxt
->tunneled_dr
[1].num_bits
= field
->num_bits
+ 1;
4431 ctxt
->tunneled_dr
[1].out_value
= field
->out_value
;
4432 ctxt
->tunneled_dr
[1].in_value
= field
->in_value
;
4434 ctxt
->tunneled_dr
[0].num_bits
= 3;
4435 ctxt
->tunneled_dr
[0].out_value
= bscan_zero
;
4437 /* BSCAN_TUNNEL_NESTED_TAP */
4438 ctxt
->tunneled_dr
[0].num_bits
= 1;
4439 ctxt
->tunneled_dr
[0].out_value
= bscan_one
;
4440 ctxt
->tunneled_dr
[1].num_bits
= 7;
4441 ctxt
->tunneled_dr_width
= field
->num_bits
;
4442 ctxt
->tunneled_dr
[1].out_value
= &ctxt
->tunneled_dr_width
;
4443 /* for BSCAN tunnel, there is a one-TCK skew between shift in and shift out, so
4444 scanning num_bits + 1, and then will right shift the input field after executing the queues */
4445 ctxt
->tunneled_dr
[2].num_bits
= field
->num_bits
+ 1;
4446 ctxt
->tunneled_dr
[2].out_value
= field
->out_value
;
4447 ctxt
->tunneled_dr
[2].in_value
= field
->in_value
;
4448 ctxt
->tunneled_dr
[3].num_bits
= 3;
4449 ctxt
->tunneled_dr
[3].out_value
= bscan_zero
;
4451 jtag_add_dr_scan(target
->tap
, ARRAY_SIZE(ctxt
->tunneled_dr
), ctxt
->tunneled_dr
, TAP_IDLE
);