1 # script for stm32f3x family
4 # stm32 devices support both JTAG and SWD transports.
6 source [find target/swj-dp.tcl]
8 if { [info exists CHIPNAME] } {
9 set _CHIPNAME $CHIPNAME
11 set _CHIPNAME stm32f3x
14 if { [info exists ENDIAN] } {
20 # Work-area is a space in RAM used for flash programming
22 if { [info exists WORKAREASIZE] } {
23 set _WORKAREASIZE $WORKAREASIZE
25 set _WORKAREASIZE 0x4000
28 # JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
30 # Since we may be running of an RC oscilator, we crank down the speed a
31 # bit more to be on the safe side. Perhaps superstition, but if are
32 # running off a crystal, we can run closer to the limit. Note
33 # that there can be a pretty wide band where things are more or less stable.
36 adapter_nsrst_delay 100
42 if { [info exists CPUTAPID] } {
43 set _CPUTAPID $CPUTAPID
45 # See STM Document RM0316
46 # Section 29.6.3 - corresponds to Cortex-M4 r0p1
47 set _CPUTAPID 0x4ba00477
50 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
52 if { [info exists BSTAPID] } {
55 # STM Document RM0316 rev 2 Section 30.6.2 says 0x06432041
56 # but STM32F303VCT6 rev Y has 0x06422041
57 set _BSTAPID1 0x06422041
58 set _BSTAPID2 0x06432041
62 jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 -expected-id $_BSTAPID2
65 set _TARGETNAME $_CHIPNAME.cpu
66 target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
68 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
70 set _FLASHNAME $_CHIPNAME.flash
71 flash bank $_FLASHNAME stm32f1x 0 0 0 0 $_TARGETNAME
73 # if srst is not fitted use SYSRESETREQ to
74 # perform a soft reset
75 cortex_m reset_config sysresetreq
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