1 # SPDX-License-Identifier: GPL-2.0-or-later
4 # M0+ devices only have SW-DP, but swj-dp code works, just don't
5 # set any jtag related features
8 source [find target/swj-dp.tcl]
9 source [find mem_helper.tcl]
11 if { [info exists CHIPNAME] } {
12 set _CHIPNAME $CHIPNAME
19 # Work-area is a space in RAM used for flash programming
20 # By default use 2kB (max ram on smallest part)
21 if { [info exists WORKAREASIZE] } {
22 set _WORKAREASIZE $WORKAREASIZE
24 set _WORKAREASIZE 0x800
27 # JTAG speed should be <= F_CPU/6.
28 # F_CPU after reset is ~2MHz, so use F_JTAG max = 333kHz
31 adapter srst delay 100
33 if { [info exists CPUTAPID] } {
34 set _CPUTAPID $CPUTAPID
36 # Arm, m0+, non-multidrop.
37 # http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/ka16088.html
38 set _CPUTAPID 0x0bc11477
41 swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
42 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
44 set _TARGETNAME $_CHIPNAME.cpu
45 target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
47 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
49 # flash size will be probed
50 set _FLASHNAME $_CHIPNAME.flash
51 flash bank $_FLASHNAME stm32lx 0x08000000 0 0 0 $_TARGETNAME
53 reset_config srst_nogate
56 # if srst is not fitted use SYSRESETREQ to
57 # perform a soft reset
58 cortex_m reset_config sysresetreq
61 proc stm32l0_enable_HSI16 {} {
62 # Enable HSI16 as clock source
63 echo "STM32L0: Enabling HSI16"
65 # Set HSI16ON in RCC_CR (leave MSI enabled)
66 mmw 0x40021000 0x00000101 0
68 # Set HSI16 as SYSCLK (RCC_CFGR)
69 mmw 0x4002100c 0x00000001 0
71 # Wait until System clock switches to HSI16
72 while { ([ mrw 0x4002100c ] & 0x0c) != 0x04 } { }
78 $_TARGETNAME configure -event reset-init {
82 $_TARGETNAME configure -event reset-start {
86 $_TARGETNAME configure -event examine-end {
87 # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
88 mmw 0x40015804 0x00000007 0
90 # Stop watchdog counters during halt
91 # DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
92 mmw 0x40015808 0x00001800 0
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