tcl/target/stm32l0.cfg

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 #
   4 # M0+ devices only have SW-DP, but swj-dp code works, just don't
   5 # set any jtag related features
   6 #
   7
   8 source [find target/swj-dp.tcl]
   9 source [find mem_helper.tcl]
  10
  11 if { [info exists CHIPNAME] } {
  12    set _CHIPNAME $CHIPNAME
  13 } else {
  14    set _CHIPNAME stm32l0
  15 }
  16
  17 set _ENDIAN little
  18
  19 # Work-area is a space in RAM used for flash programming
  20 # By default use 2kB (max ram on smallest part)
  21 if { [info exists WORKAREASIZE] } {
  22    set _WORKAREASIZE $WORKAREASIZE
  23 } else {
  24    set _WORKAREASIZE 0x800
  25 }
  26
  27 # JTAG speed should be <= F_CPU/6.
  28 # F_CPU after reset is ~2MHz, so use F_JTAG max = 333kHz
  29 adapter speed 300
  30
  31 adapter srst delay 100
  32
  33 if { [info exists CPUTAPID] } {
  34     set _CPUTAPID $CPUTAPID
  35 } else {
  36     # Arm, m0+, non-multidrop.
  37     # http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/ka16088.html
  38     set _CPUTAPID 0x0bc11477
  39 }
  40
  41 swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
  42 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
  43
  44 set _TARGETNAME $_CHIPNAME.cpu
  45 target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
  46
  47 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
  48
  49 # flash size will be probed
  50 set _FLASHNAME $_CHIPNAME.flash
  51 flash bank $_FLASHNAME stm32lx 0x08000000 0 0 0 $_TARGETNAME
  52
  53 reset_config srst_nogate
  54
  55 if {![using_hla]} {
  56    # if srst is not fitted use SYSRESETREQ to
  57    # perform a soft reset
  58    cortex_m reset_config sysresetreq
  59 }
  60
  61 proc stm32l0_enable_HSI16 {} {
  62         # Enable HSI16 as clock source
  63         echo "STM32L0: Enabling HSI16"
  64
  65         # Set HSI16ON in RCC_CR (leave MSI enabled)
  66     mmw 0x40021000 0x00000101 0
  67
  68         # Set HSI16 as SYSCLK (RCC_CFGR)
  69         mmw 0x4002100c 0x00000001 0
  70
  71         # Wait until System clock switches to HSI16
  72         while { ([ mrw 0x4002100c ] & 0x0c) != 0x04 } { }
  73
  74         # Increase speed
  75         adapter speed 2500
  76 }
  77
  78 $_TARGETNAME configure -event reset-init {
  79         stm32l0_enable_HSI16
  80 }
  81
  82 $_TARGETNAME configure -event reset-start {
  83         adapter speed 300
  84 }
  85
  86 $_TARGETNAME configure -event examine-end {
  87         # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
  88         mmw 0x40015804 0x00000007 0
  89
  90         # Stop watchdog counters during halt
  91         # DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
  92         mmw 0x40015808 0x00001800 0
  93 }