+/* offsets into armv7m core register cache */
+enum {
+ /* for convenience, the first set of indices match
+ * the Cortex-M DCRSR.REGSEL selectors
+ */
+ ARMV7M_R0 = ARMV7M_REGSEL_R0,
+ ARMV7M_R1 = ARMV7M_REGSEL_R1,
+ ARMV7M_R2 = ARMV7M_REGSEL_R2,
+ ARMV7M_R3 = ARMV7M_REGSEL_R3,
+
+ ARMV7M_R4 = ARMV7M_REGSEL_R4,
+ ARMV7M_R5 = ARMV7M_REGSEL_R5,
+ ARMV7M_R6 = ARMV7M_REGSEL_R6,
+ ARMV7M_R7 = ARMV7M_REGSEL_R7,
+
+ ARMV7M_R8 = ARMV7M_REGSEL_R8,
+ ARMV7M_R9 = ARMV7M_REGSEL_R9,
+ ARMV7M_R10 = ARMV7M_REGSEL_R10,
+ ARMV7M_R11 = ARMV7M_REGSEL_R11,
+
+ ARMV7M_R12 = ARMV7M_REGSEL_R12,
+ ARMV7M_R13 = ARMV7M_REGSEL_R13,
+ ARMV7M_R14 = ARMV7M_REGSEL_R14,
+ ARMV7M_PC = ARMV7M_REGSEL_PC,
+
+ ARMV7M_XPSR = ARMV7M_REGSEL_XPSR,
+ ARMV7M_MSP = ARMV7M_REGSEL_MSP,
+ ARMV7M_PSP = ARMV7M_REGSEL_PSP,
+
+ /* following indices are arbitrary, do not match DCRSR.REGSEL selectors */
+
+ /* A block of container and contained registers follows:
+ * THE ORDER IS IMPORTANT to the end of the block ! */
+ /* working register for packing/unpacking special regs, hidden from gdb */
+ ARMV7M_PMSK_BPRI_FLTMSK_CTRL,
+
+ /* WARNING: If you use armv7m_write_core_reg() on one of 4 following
+ * special registers, the new data go to ARMV7M_PMSK_BPRI_FLTMSK_CTRL
+ * cache only and are not flushed to CPU HW register.
+ * To trigger write to CPU HW register, add
+ * armv7m_write_core_reg(,,ARMV7M_PMSK_BPRI_FLTMSK_CTRL,);
+ */
+ ARMV7M_PRIMASK,
+ ARMV7M_BASEPRI,
+ ARMV7M_FAULTMASK,
+ ARMV7M_CONTROL,
+ /* The end of block of container and contained registers */
+
+ /* ARMv8-M specific registers */
+ ARMV8M_MSP_NS,
+ ARMV8M_PSP_NS,
+ ARMV8M_MSP_S,
+ ARMV8M_PSP_S,
+ ARMV8M_MSPLIM_S,
+ ARMV8M_PSPLIM_S,
+ ARMV8M_MSPLIM_NS,
+ ARMV8M_PSPLIM_NS,
+
+ /* A block of container and contained registers follows:
+ * THE ORDER IS IMPORTANT to the end of the block ! */
+ ARMV8M_PMSK_BPRI_FLTMSK_CTRL_S,
+ ARMV8M_PRIMASK_S,
+ ARMV8M_BASEPRI_S,
+ ARMV8M_FAULTMASK_S,
+ ARMV8M_CONTROL_S,
+ /* The end of block of container and contained registers */
+
+ /* A block of container and contained registers follows:
+ * THE ORDER IS IMPORTANT to the end of the block ! */
+ ARMV8M_PMSK_BPRI_FLTMSK_CTRL_NS,
+ ARMV8M_PRIMASK_NS,
+ ARMV8M_BASEPRI_NS,
+ ARMV8M_FAULTMASK_NS,
+ ARMV8M_CONTROL_NS,
+ /* The end of block of container and contained registers */
+
+ /* 64bit Floating-point registers */
+ ARMV7M_D0,
+ ARMV7M_D1,
+ ARMV7M_D2,
+ ARMV7M_D3,
+ ARMV7M_D4,
+ ARMV7M_D5,
+ ARMV7M_D6,
+ ARMV7M_D7,
+ ARMV7M_D8,
+ ARMV7M_D9,
+ ARMV7M_D10,
+ ARMV7M_D11,
+ ARMV7M_D12,
+ ARMV7M_D13,
+ ARMV7M_D14,
+ ARMV7M_D15,
+
+ /* Floating-point status register */
+ ARMV7M_FPSCR,
+
+ /* for convenience add registers' block delimiters */
+ ARMV7M_LAST_REG,
+ ARMV7M_CORE_FIRST_REG = ARMV7M_R0,
+ ARMV7M_CORE_LAST_REG = ARMV7M_XPSR,
+ ARMV7M_FPU_FIRST_REG = ARMV7M_D0,
+ ARMV7M_FPU_LAST_REG = ARMV7M_FPSCR,
+ ARMV8M_FIRST_REG = ARMV8M_MSP_NS,
+ ARMV8M_LAST_REG = ARMV8M_CONTROL_NS,
+};