target: fix minor typos and duplicated words

[openocd.git] / src / target / arm_adi_v5.h

diff --git a/src/target/arm_adi_v5.h b/src/target/arm_adi_v5.h
index 0b61b757ac9b572730d205d11917ff4e3a7ad0d4..17365bddb5a062d294bb09434050636178cf9a94 100644 (file)
--- a/src/target/arm_adi_v5.h
+++ b/src/target/arm_adi_v5.h
@@ -112,15 +112,34 @@
 #define CSW_ADDRINC_PACKED  (2UL << 4)
 #define CSW_DEVICE_EN       (1UL << 6)
 #define CSW_TRIN_PROG       (1UL << 7)
-/* all fields in bits 12 and above are implementation-defined! */
+
+/* All fields in bits 12 and above are implementation-defined
+ * Defaults for AHB/AXI in "Standard Memory Access Port Definitions" from ADI
+ * Some bits are shared between buses
+ */
 #define CSW_SPIDEN          (1UL << 23)
-#define CSW_HPROT1          (1UL << 25) /* AHB: Privileged */
-#define CSW_MASTER_DEBUG    (1UL << 29) /* AHB: set HMASTER signals to AHB-AP ID */
-#define CSW_SPROT           (1UL << 30)
 #define CSW_DBGSWENABLE     (1UL << 31)
 
-/* initial value of csw_default used for MEM-AP transfers */
-#define CSW_DEFAULT                    (CSW_HPROT1 | CSW_MASTER_DEBUG | CSW_DBGSWENABLE)
+/* AHB: Privileged */
+#define CSW_AHB_HPROT1          (1UL << 25)
+/* AHB: set HMASTER signals to AHB-AP ID */
+#define CSW_AHB_MASTER_DEBUG    (1UL << 29)
+/* AHB5: non-secure access via HNONSEC
+ * AHB3: SBO, UNPREDICTABLE if zero */
+#define CSW_AHB_SPROT           (1UL << 30)
+/* AHB: initial value of csw_default */
+#define CSW_AHB_DEFAULT         (CSW_AHB_HPROT1 | CSW_AHB_MASTER_DEBUG | CSW_DBGSWENABLE)
+
+/* AXI: Privileged */
+#define CSW_AXI_ARPROT0_PRIV    (1UL << 28)
+/* AXI: Non-secure */
+#define CSW_AXI_ARPROT1_NONSEC  (1UL << 29)
+/* AXI: initial value of csw_default */
+#define CSW_AXI_DEFAULT         (CSW_AXI_ARPROT0_PRIV | CSW_AXI_ARPROT1_NONSEC | CSW_DBGSWENABLE)
+
+/* APB: initial value of csw_default */
+#define CSW_APB_DEFAULT         (CSW_DBGSWENABLE)
+
 
 /* Fields of the MEM-AP's IDR register */
 #define IDR_REV     (0xFUL << 28)
@@ -139,6 +158,15 @@
 #define DP_APSEL_MAX        (255)
 #define DP_APSEL_INVALID    (-1)
 
+/* FIXME: not SWD specific; should be renamed, e.g. adiv5_special_seq */
+enum swd_special_seq {
+       LINE_RESET,
+       JTAG_TO_SWD,
+       SWD_TO_JTAG,
+       SWD_TO_DORMANT,
+       DORMANT_TO_SWD,
+};
+
 /**
  * This represents an ARM Debug Interface (v5) Access Port (AP).
  * Most common is a MEM-AP, for memory access.
@@ -215,6 +243,12 @@ struct adiv5_dap {
        /* dap transaction list for WAIT support */
        struct list_head cmd_journal;
 
+       /* pool for dap_cmd objects */
+       struct list_head cmd_pool;
+
+       /* number of dap_cmd objects in the pool */
+       size_t cmd_pool_size;
+
        struct jtag_tap *tap;
        /* Control config */
        uint32_t dp_ctrl_stat;
@@ -245,6 +279,12 @@ struct adiv5_dap {
         * swizzle appropriately. */
        bool ti_be_32_quirks;
 
+       /**
+        * STLINK adapter need to know if last AP operation was read or write, and
+        * in case of write has to flush it with a dummy read from DP_RDBUFF
+        */
+       bool stlink_flush_ap_write;
+
        /**
         * Signals that an attempt to reestablish communication afresh
         * should be performed before the next access.
@@ -266,6 +306,10 @@ struct adiv5_dap {
 struct dap_ops {
        /** connect operation for SWD */
        int (*connect)(struct adiv5_dap *dap);
+
+       /** send a sequence to the DAP */
+       int (*send_sequence)(struct adiv5_dap *dap, enum swd_special_seq seq);
+
        /** DP register read. */
        int (*queue_dp_read)(struct adiv5_dap *dap, unsigned reg,
                        uint32_t *data);
@@ -307,11 +351,27 @@ enum ap_class {
  */
 enum ap_type {
        AP_TYPE_JTAG_AP = 0x0,  /* JTAG-AP - JTAG master for controlling other JTAG devices */
-       AP_TYPE_AHB_AP  = 0x1,  /* AHB Memory-AP */
+       AP_TYPE_AHB3_AP = 0x1,  /* AHB3 Memory-AP */
        AP_TYPE_APB_AP  = 0x2,  /* APB Memory-AP */
        AP_TYPE_AXI_AP  = 0x4,  /* AXI Memory-AP */
+       AP_TYPE_AHB5_AP = 0x5,  /* AHB5 Memory-AP. */
 };
 
+/**
+ * Send an adi-v5 sequence to the DAP.
+ *
+ * @param dap The DAP used for reading.
+ * @param seq The sequence to send.
+ *
+ * @return ERROR_OK for success, else a fault code.
+ */
+static inline int dap_send_sequence(struct adiv5_dap *dap,
+               enum swd_special_seq seq)
+{
+       assert(dap->ops != NULL);
+       return dap->ops->send_sequence(dap, seq);
+}
+
 /**
  * Queue a DP register read.
  * Note that not all DP registers are readable; also, that JTAG and SWD