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Matt Hsu <matt@0xlab.org> cortex_a8_exec_opcode is writing the ARM instruction into
[openocd.git] / src / target / arm_disassembler.c
diff --git a/src/target/arm_disassembler.c b/src/target/arm_disassembler.c
index 13ffcfa5a7eaa76e80ff8a2f71566a962f8b7493..a994d3160fc9a0b3d36b5d82afd8b9d4be6c6d2c 100644 (file)
--- a/src/target/arm_disassembler.c
+++ b/src/target/arm_disassembler.c
@@ -1395,6 +1395,7 @@ int evaluate_add_sub_thumb(uint16_t opcode, uint32_t address, arm_instruction_t
        }
        else
        {
+               /* REVISIT:  if reg_imm == 0, display as "MOVS" */
                instruction->type = ARM_ADD;
                mnemonic = "ADDS";
        }
@@ -1644,7 +1645,7 @@ int evaluate_data_proc_thumb(uint16_t opcode, uint32_t address, arm_instruction_
                                break;
                        case 0x9:
                                instruction->type = ARM_RSB;
-                               mnemonic = "NEGS";
+                               mnemonic = "RSBS";
                                instruction->info.data_proc.variant = 0 /*immediate*/;
                                instruction->info.data_proc.shifter_operand.immediate.immediate = 0;
                                instruction->info.data_proc.Rn = Rm;
@@ -1944,17 +1945,21 @@ int evaluate_load_store_multiple_thumb(uint16_t opcode, uint32_t address, arm_in
 
        if ((opcode & 0xf000) == 0xc000)
        { /* generic load/store multiple */
+               char *wback = "!";
+
                if (L)
                {
                        instruction->type = ARM_LDM;
                        mnemonic = "LDM";
+                       if (opcode & (1 << Rn))
+                               wback = "";
                }
                else
                {
                        instruction->type = ARM_STM;
                        mnemonic = "STM";
                }
-               snprintf(ptr_name,7,"r%i!, ",Rn);
+               snprintf(ptr_name, sizeof ptr_name, "r%i%s, ", Rn, wback);
        }
        else
        { /* push/pop */
@@ -2098,7 +2103,7 @@ static int evaluate_byterev_thumb(uint16_t opcode, uint32_t address,
        char *suffix;
 
        /* added in ARMv6 */
-       switch (opcode & 0x00c0) {
+       switch ((opcode >> 6) & 3) {
        case 0:
                suffix = "";
                break;
@@ -2600,7 +2605,6 @@ static int t2ev_data_mod_immed(uint32_t opcode, uint32_t address,
                        mnemonic = "TST";
                        one = true;
                        suffix = "";
-                       suffix2 = ".W";
                        rd = rn;
                } else {
                        instruction->type = ARM_AND;
@@ -2660,6 +2664,7 @@ static int t2ev_data_mod_immed(uint32_t opcode, uint32_t address,
        case 10:
                instruction->type = ARM_ADC;
                mnemonic = "ADC";
+               suffix2 = ".W";
                break;
        case 11:
                instruction->type = ARM_SBC;
@@ -2708,8 +2713,8 @@ static int t2ev_data_immed(uint32_t opcode, uint32_t address,
        bool add = false;
        bool is_signed = false;
 
-       immed = (opcode & 0x0ff) | ((opcode & 0x7000) >> 12);
-       if (opcode & (1 << 27))
+       immed = (opcode & 0x0ff) | ((opcode & 0x7000) >> 4);
+       if (opcode & (1 << 26))
                immed |= (1 << 11);
 
        switch ((opcode >> 20) & 0x1f) {
@@ -2718,15 +2723,16 @@ static int t2ev_data_immed(uint32_t opcode, uint32_t address,
                        add = true;
                        goto do_adr;
                }
-               mnemonic = "ADD.W";
+               mnemonic = "ADDW";
                break;
        case 4:
-               mnemonic = "MOV.W";
-               break;
+               immed |= (opcode >> 4) & 0xf000;
+               sprintf(cp, "MOVW\tr%d, #%d\t; %#3.3x", rd, immed, immed);
+               return ERROR_OK;
        case 0x0a:
                if (rn == 0xf)
                        goto do_adr;
-               mnemonic = "SUB.W";
+               mnemonic = "SUBW";
                break;
        case 0x0c:
                /* move constant to top 16 bits of register */
@@ -2743,7 +2749,7 @@ static int t2ev_data_immed(uint32_t opcode, uint32_t address,
                immed |= (opcode >> 10) & 0x1c;
                sprintf(cp, "%sSAT\tr%d, #%d, r%d, %s #%d\t",
                                is_signed ? "S" : "U",
-                               rd, (int) (opcode & 0x1f) + 1, rn,
+                               rd, (int) (opcode & 0x1f) + is_signed, rn,
                                (opcode & (1 << 21)) ? "ASR" : "LSL",
                                immed ? immed : 32);
                return ERROR_OK;
@@ -2848,6 +2854,7 @@ static int t2ev_store_single(uint32_t opcode, uint32_t address,
        sprintf(cp, "STR%s.W\tr%d, [r%d, r%d, LSL #%d]",
                        size, rt, rn, (int) opcode & 0x0f,
                        (int) (opcode >> 4) & 0x03);
+       return ERROR_OK;
 
 imm12:
        immed = opcode & 0x0fff;
@@ -2964,22 +2971,22 @@ static int t2ev_ldm_stm(uint32_t opcode, uint32_t address,
 
        switch (op) {
        case 2:
-               sprintf(cp, "STMB\tr%d%s, ", rn, t ? "!" : "");
+               sprintf(cp, "STM.W\tr%d%s, ", rn, t ? "!" : "");
                break;
        case 3:
                if (rn == 13 && t)
-                       sprintf(cp, "POP\t");
+                       sprintf(cp, "POP.W\t");
                else
                        sprintf(cp, "LDM.W\tr%d%s, ", rn, t ? "!" : "");
                break;
        case 4:
                if (rn == 13 && t)
-                       sprintf(cp, "PUSH\t");
+                       sprintf(cp, "PUSH.W\t");
                else
-                       sprintf(cp, "STM.W\tr%d%s, ", rn, t ? "!" : "");
+                       sprintf(cp, "STMDB\tr%d%s, ", rn, t ? "!" : "");
                break;
        case 5:
-               sprintf(cp, "LDMB\tr%d%s, ", rn, t ? "!" : "");
+               sprintf(cp, "LDMDB.W\tr%d%s, ", rn, t ? "!" : "");
                break;
        default:
                return ERROR_INVALID_ARGUMENTS;
@@ -3000,6 +3007,133 @@ static int t2ev_ldm_stm(uint32_t opcode, uint32_t address,
        return ERROR_OK;
 }
 
+/* load/store dual or exclusive, table branch */
+static int t2ev_ldrex_strex(uint32_t opcode, uint32_t address,
+               arm_instruction_t *instruction, char *cp)
+{
+       unsigned op1op2 = (opcode >> 20) & 0x3;
+       unsigned op3 = (opcode >> 4) & 0xf;
+       char *mnemonic;
+       unsigned rn = (opcode >> 16) & 0xf;
+       unsigned rt = (opcode >> 12) & 0xf;
+       unsigned rd = (opcode >> 8) & 0xf;
+       unsigned imm = opcode & 0xff;
+       char *p1 = "";
+       char *p2 = "]";
+
+       op1op2 |= (opcode >> 21) & 0xc;
+       switch (op1op2) {
+       case 0:
+               mnemonic = "STREX";
+               goto strex;
+       case 1:
+               mnemonic = "LDREX";
+               goto ldrex;
+       case 2:
+       case 6:
+       case 8:
+       case 10:
+       case 12:
+       case 14:
+               mnemonic = "STRD";
+               goto immediate;
+       case 3:
+       case 7:
+       case 9:
+       case 11:
+       case 13:
+       case 15:
+               mnemonic = "LDRD";
+               if (rn == 15)
+                       goto literal;
+               else
+                       goto immediate;
+       case 4:
+               switch (op3) {
+               case 4:
+                       mnemonic = "STREXB";
+                       break;
+               case 5:
+                       mnemonic = "STREXH";
+                       break;
+               default:
+                       return ERROR_INVALID_ARGUMENTS;
+               }
+               rd = opcode & 0xf;
+               imm = 0;
+               goto strex;
+       case 5:
+               switch (op3) {
+               case 0:
+                       sprintf(cp, "TBB\t[r%u, r%u]", rn, imm & 0xf);
+                       return ERROR_OK;
+               case 1:
+                       sprintf(cp, "TBH\t[r%u, r%u, LSL #1]", rn, imm & 0xf);
+                       return ERROR_OK;
+               case 4:
+                       mnemonic = "LDREXB";
+                       break;
+               case 5:
+                       mnemonic = "LDREXH";
+                       break;
+               default:
+                       return ERROR_INVALID_ARGUMENTS;
+               }
+               imm = 0;
+               goto ldrex;
+       }
+       return ERROR_INVALID_ARGUMENTS;
+
+strex:
+       imm <<= 2;
+       if (imm)
+               sprintf(cp, "%s\tr%u, r%u, [r%u, #%u]\t; %#2.2x",
+                               mnemonic, rd, rt, rn, imm, imm);
+       else
+               sprintf(cp, "%s\tr%u, r%u, [r%u]",
+                               mnemonic, rd, rt, rn);
+       return ERROR_OK;
+
+ldrex:
+       imm <<= 2;
+       if (imm)
+               sprintf(cp, "%s\tr%u, [r%u, #%u]\t; %#2.2x",
+                               mnemonic, rt, rn, imm, imm);
+       else
+               sprintf(cp, "%s\tr%u, [r%u]",
+                               mnemonic, rt, rn);
+       return ERROR_OK;
+
+immediate:
+       /* two indexed modes will write back rn */
+       if (opcode & (1 << 21)) {
+               if (opcode & (1 << 24)) /* pre-indexed */
+                       p2 = "]!";
+               else {                  /* post-indexed */
+                       p1 = "]";
+                       p2 = "";
+               }
+       }
+
+       imm <<= 2;
+       sprintf(cp, "%s\tr%u, r%u, [r%u%s, #%s%u%s\t; %#2.2x",
+                       mnemonic, rt, rd, rn, p1,
+                       (opcode & (1 << 23)) ? "" : "-",
+                       imm, p2, imm);
+       return ERROR_OK;
+
+literal:
+       address = thumb_alignpc4(address);
+       imm <<= 2;
+       if (opcode & (1 << 23))
+               address += imm;
+       else
+               address -= imm;
+       sprintf(cp, "%s\tr%u, r%u, %#8.8" PRIx32,
+                       mnemonic, rt, rd, address);
+       return ERROR_OK;
+}
+
 static int t2ev_data_shift(uint32_t opcode, uint32_t address,
                arm_instruction_t *instruction, char *cp)
 {
@@ -3011,17 +3145,18 @@ static int t2ev_data_shift(uint32_t opcode, uint32_t address,
        char *mnemonic;
        char *suffix = "";
 
-       immed |= (opcode >> 10) & 0x7;
-       if (opcode & (1 << 21))
+       immed |= (opcode >> 10) & 0x1c;
+       if (opcode & (1 << 20))
                suffix = "S";
 
        switch (op) {
        case 0:
                if (rd == 0xf) {
-                       if (!(opcode & (1 << 21)))
+                       if (!(opcode & (1 << 20)))
                                return ERROR_INVALID_ARGUMENTS;
                        instruction->type = ARM_TST;
                        mnemonic = "TST";
+                       suffix = "";
                        goto two;
                }
                instruction->type = ARM_AND;
@@ -3052,7 +3187,7 @@ static int t2ev_data_shift(uint32_t opcode, uint32_t address,
                                break;
                        default:
                                if (immed == 0) {
-                                       sprintf(cp, "RRX%s.W\tr%d, r%d",
+                                       sprintf(cp, "RRX%s\tr%d, r%d",
                                                suffix, rd,
                                                (int) (opcode & 0xf));
                                        return ERROR_OK;
@@ -3079,10 +3214,11 @@ static int t2ev_data_shift(uint32_t opcode, uint32_t address,
                break;
        case 4:
                if (rd == 0xf) {
-                       if (!(opcode & (1 << 21)))
+                       if (!(opcode & (1 << 20)))
                                return ERROR_INVALID_ARGUMENTS;
                        instruction->type = ARM_TEQ;
                        mnemonic = "TEQ";
+                       suffix = "";
                        goto two;
                }
                instruction->type = ARM_EOR;
@@ -3090,10 +3226,11 @@ static int t2ev_data_shift(uint32_t opcode, uint32_t address,
                break;
        case 8:
                if (rd == 0xf) {
-                       if (!(opcode & (1 << 21)))
+                       if (!(opcode & (1 << 20)))
                                return ERROR_INVALID_ARGUMENTS;
                        instruction->type = ARM_CMN;
                        mnemonic = "CMN";
+                       suffix = "";
                        goto two;
                }
                instruction->type = ARM_ADD;
@@ -3113,6 +3250,7 @@ static int t2ev_data_shift(uint32_t opcode, uint32_t address,
                                return ERROR_INVALID_ARGUMENTS;
                        instruction->type = ARM_CMP;
                        mnemonic = "CMP";
+                       suffix = "";
                        goto two;
                }
                instruction->type = ARM_SUB;
@@ -3140,13 +3278,17 @@ shift:
                break;
        case 1:
                suffix = "LSR";
+               if (immed == 32)
+                       immed = 0;
                break;
        case 2:
                suffix = "ASR";
+               if (immed == 32)
+                       immed = 0;
                break;
        case 3:
                if (immed == 0) {
-                       strcpy(cp, "RRX");
+                       strcpy(cp, ", RRX");
                        return ERROR_OK;
                }
                suffix = "ROR";
@@ -3201,7 +3343,7 @@ static int t2ev_data_reg(uint32_t opcode, uint32_t address,
                                (int) (opcode >> 0) & 0xf);
 
        } else if (opcode & (1 << 7)) {
-               switch ((opcode >> 24) & 0xf) {
+               switch ((opcode >> 20) & 0xf) {
                case 0:
                case 1:
                case 4:
@@ -3221,7 +3363,7 @@ static int t2ev_data_reg(uint32_t opcode, uint32_t address,
                                        (opcode & (1 << 24)) ? 'U' : 'S',
                                        (opcode & (1 << 26)) ? 'B' : 'H',
                                        (int) (opcode >> 8) & 0xf,
-                                       (int) (opcode >> 16) & 0xf,
+                                       (int) (opcode >> 0) & 0xf,
                                        suffix);
                        break;
                case 8:
@@ -3230,7 +3372,7 @@ static int t2ev_data_reg(uint32_t opcode, uint32_t address,
                case 0xb:
                        if (opcode & (1 << 6))
                                return ERROR_INVALID_ARGUMENTS;
-                       if (~opcode & (0xff << 12))
+                       if (((opcode >> 12) & 0xf) != 0xf)
                                return ERROR_INVALID_ARGUMENTS;
                        if (!(opcode & (1 << 20)))
                                return ERROR_INVALID_ARGUMENTS;
@@ -3278,7 +3420,7 @@ static int t2ev_load_word(uint32_t opcode, uint32_t address,
 
        if (rn == 0xf) {
                immed = opcode & 0x0fff;
-               if (opcode & (1 << 23))
+               if ((opcode & (1 << 23)) == 0)
                        immed = -immed;
                sprintf(cp, "LDR\tr%d, %#8.8" PRIx32,
                                (int) (opcode >> 12) & 0xf,
@@ -3316,7 +3458,7 @@ static int t2ev_load_word(uint32_t opcode, uint32_t address,
        if (((opcode >> 8) & 0xf) == 0xc || (opcode & 0x0900) == 0x0900) {
                char *p1 = "]", *p2 = "";
 
-               if (!(opcode & 0x0600))
+               if (!(opcode & 0x0500))
                        return ERROR_INVALID_ARGUMENTS;
 
                immed = opcode & 0x00ff;
@@ -3349,18 +3491,21 @@ static int t2ev_load_byte_hints(uint32_t opcode, uint32_t address,
        int rt = (opcode >> 12) & 0xf;
        int op2 = (opcode >> 6) & 0x3f;
        unsigned immed;
-       char *p1 = "]", *p2 = "";
+       char *p1 = "", *p2 = "]";
        char *mnemonic;
 
        switch ((opcode >> 23) & 0x3) {
        case 0:
                if ((rn & rt) == 0xf) {
-preload_immediate_t2:
+pld_literal:
                        immed = opcode & 0xfff;
-preload_immediate_t1:
-                       p1 = (opcode & (1 << 21)) ? "W" : "";
-                       sprintf(cp, "PLD%s\t[r%d, #%d]\t; %#6.6x",
-                                       p1, rn, immed, immed);
+                       address = thumb_alignpc4(address);
+                       if (opcode & (1 << 23))
+                               address += immed;
+                       else
+                               address -= immed;
+                       sprintf(cp, "PLD\tr%d, %#8.8" PRIx32,
+                                       rt, address);
                        return ERROR_OK;
                }
                if (rn == 0x0f && rt != 0x0f) {
@@ -3386,12 +3531,17 @@ ldrb_literal:
                if ((op2 & 0x3c) == 0x30) {
                        if (rt == 0x0f) {
                                immed = opcode & 0xff;
-                               goto preload_immediate_t1;
+                               immed = -immed;
+preload_immediate:
+                               p1 = (opcode & (1 << 21)) ? "W" : "";
+                               sprintf(cp, "PLD%s\t[r%d, #%d]\t; %#6.6x",
+                                               p1, rn, immed, immed);
+                               return ERROR_OK;
                        }
                        mnemonic = "LDRB";
 ldrxb_immediate_t3:
                        immed = opcode & 0xff;
-                       if (opcode & 0x200)
+                       if (!(opcode & 0x200))
                                immed = -immed;
 
                        /* two indexed modes will write back rn */
@@ -3427,8 +3577,12 @@ ldrxb_immediate_t2:
                }
                break;
        case 1:
-               if (rt == 0xf)
-                       goto preload_immediate_t2;
+               if ((rn & rt) == 0xf)
+                       goto pld_literal;
+               if (rt == 0xf) {
+                       immed = opcode & 0xfff;
+                       goto preload_immediate;
+               }
                if (rn == 0x0f)
                        goto ldrb_literal;
                mnemonic = "LDRB.W";
@@ -3436,7 +3590,6 @@ ldrxb_immediate_t2:
                goto ldrxb_immediate_t2;
        case 2:
                if ((rn & rt) == 0xf) {
-pli_immediate:
                        immed = opcode & 0xfff;
                        address = thumb_alignpc4(address);
                        if (opcode & (1 << 23))
@@ -3461,7 +3614,7 @@ ldrsb_literal:
                        break;
                if ((op2 & 0x3c) == 0x38) {
                        immed = opcode & 0xff;
-                       sprintf(cp, "LDRSBT\tr%d, [r%d, #%d]\t; %2.2x",
+                       sprintf(cp, "LDRSBT\tr%d, [r%d, #%d]\t; %#2.2x",
                                        rt, rn, immed, immed);
                        return ERROR_OK;
                }
@@ -3469,8 +3622,8 @@ ldrsb_literal:
                        if (rt == 0xf) {
                                immed = opcode & 0xff;
                                immed = -immed; // pli
-                               sprintf(cp, "PLI\t[r%d, #-%d]\t; %2.2x",
-                                               rn, immed, immed);
+                               sprintf(cp, "PLI\t[r%d, #%d]\t; -%#2.2x",
+                                               rn, immed, -immed);
                                return ERROR_OK;
                        }
                        mnemonic = "LDRSB";
@@ -3494,8 +3647,12 @@ ldrsb_literal:
                }
                break;
        case 3:
-               if (rt == 0xf)
-                       goto pli_immediate;
+               if (rt == 0xf) {
+                       immed = opcode & 0xfff;
+                       sprintf(cp, "PLI\t[r%d, #%d]\t; %#3.3x",
+                                       rn, immed, immed);
+                       return ERROR_OK;
+               }
                if (rn == 0xf)
                        goto ldrsb_literal;
                immed = opcode & 0xfff;
@@ -3506,6 +3663,84 @@ ldrsb_literal:
        return ERROR_INVALID_ARGUMENTS;
 }
 
+static int t2ev_load_halfword(uint32_t opcode, uint32_t address,
+               arm_instruction_t *instruction, char *cp)
+{
+       int rn = (opcode >> 16) & 0xf;
+       int rt = (opcode >> 12) & 0xf;
+       int op2 = (opcode >> 6) & 0x3f;
+       char *sign = "";
+       unsigned immed;
+
+       if (rt == 0xf) {
+               sprintf(cp, "HINT (UNALLOCATED)");
+               return ERROR_OK;
+       }
+
+       if (opcode & (1 << 24))
+               sign = "S";
+
+       if ((opcode & (1 << 23)) == 0) {
+               if (rn == 0xf) {
+ldrh_literal:
+                       immed = opcode & 0xfff;
+                       address = thumb_alignpc4(address);
+                       if (opcode & (1 << 23))
+                               address += immed;
+                       else
+                               address -= immed;
+                       sprintf(cp, "LDR%sH\tr%d, %#8.8" PRIx32,
+                                       sign, rt, address);
+                       return ERROR_OK;
+               }
+               if (op2 == 0) {
+                       int rm = opcode & 0xf;
+
+                       immed = (opcode >> 4) & 0x3;
+                       sprintf(cp, "LDR%sH.W\tr%d, [r%d, r%d, LSL #%d]",
+                                       sign, rt, rn, rm, immed);
+                       return ERROR_OK;
+               }
+               if ((op2 & 0x3c) == 0x38) {
+                       immed = opcode & 0xff;
+                       sprintf(cp, "LDR%sHT\tr%d, [r%d, #%d]\t; %#2.2x",
+                                       sign, rt, rn, immed, immed);
+                       return ERROR_OK;
+               }
+               if ((op2 & 0x3c) == 0x30 || (op2 & 0x24) == 0x24) {
+                       char *p1 = "", *p2 = "]";
+
+                       immed = opcode & 0xff;
+                       if (!(opcode & 0x200))
+                               immed = -immed;
+
+                       /* two indexed modes will write back rn */
+                       if (opcode & 0x100) {
+                               if (opcode & 0x400)     /* pre-indexed */
+                                       p2 = "]!";
+                               else {                  /* post-indexed */
+                                       p1 = "]";
+                                       p2 = "";
+                               }
+                       }
+                       sprintf(cp, "LDR%sH\tr%d, [r%d%s, #%d%s\t; %#8.8x",
+                                       sign, rt, rn, p1, immed, p2, immed);
+                       return ERROR_OK;
+               }
+       } else {
+               if (rn == 0xf)
+                       goto ldrh_literal;
+
+               immed = opcode & 0xfff;
+               sprintf(cp, "LDR%sH%s\tr%d, [r%d, #%d]\t; %#6.6x",
+                               sign, *sign ? "" : ".W",
+                               rt, rn, immed, immed);
+               return ERROR_OK;
+       }
+
+       return ERROR_INVALID_ARGUMENTS;
+}
+
 /*
  * REVISIT for Thumb2 instructions, instruction->type and friends aren't
  * always set.  That means eventual arm_simulate_step() support for Thumb2
@@ -3569,10 +3804,18 @@ int thumb2_opcode(target_t *target, uint32_t address, arm_instruction_t *instruc
        else if ((opcode & 0x1e400000) == 0x08000000)
                retval = t2ev_ldm_stm(opcode, address, instruction, cp);
 
+       /* ARMv7-M: A5.3.6 Load/store dual or exclusive, table branch */
+       else if ((opcode & 0x1e400000) == 0x08400000)
+               retval = t2ev_ldrex_strex(opcode, address, instruction, cp);
+
        /* ARMv7-M: A5.3.7 Load word */
        else if ((opcode & 0x1f700000) == 0x18500000)
                retval = t2ev_load_word(opcode, address, instruction, cp);
 
+       /* ARMv7-M: A5.3.8 Load halfword, unallocated memory hints */
+       else if ((opcode & 0x1e700000) == 0x18300000)
+               retval = t2ev_load_halfword(opcode, address, instruction, cp);
+
        /* ARMv7-M: A5.3.9 Load byte, memory hints */
        else if ((opcode & 0x1e700000) == 0x18100000)
                retval = t2ev_load_byte_hints(opcode, address, instruction, cp);
@@ -3585,7 +3828,9 @@ int thumb2_opcode(target_t *target, uint32_t address, arm_instruction_t *instruc
        else if ((opcode & 0x1e000000) == 0x0a000000)
                retval = t2ev_data_shift(opcode, address, instruction, cp);
 
-       /* ARMv7-M: A5.3.12 Data processing (register) */
+       /* ARMv7-M: A5.3.12 Data processing (register)
+        * and      A5.3.13 Miscellaneous operations
+        */
        else if ((opcode & 0x1f000000) == 0x1a000000)
                retval = t2ev_data_reg(opcode, address, instruction, cp);
 
@@ -3597,11 +3842,14 @@ int thumb2_opcode(target_t *target, uint32_t address, arm_instruction_t *instruc
        else if ((opcode & 0x1f800000) == 0x1b800000)
                retval = t2ev_mul64_div(opcode, address, instruction, cp);
 
-       /* FIXME decode more 32-bit instructions */
-
        if (retval == ERROR_OK)
                return retval;
 
+       /*
+        * Thumb2 also supports coprocessor, ThumbEE, and DSP/Media (SIMD)
+        * instructions; not yet handled here.
+        */
+
        if (retval == ERROR_INVALID_ARGUMENTS) {
                instruction->type = ARM_UNDEFINED_INSTRUCTION;
                strcpy(cp, "UNDEFINED OPCODE");
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