Improve Makefile rules for XScale debug handler; fixes 'make distcheck'.
[openocd.git] / src / target / armv7m.h
index 17e3ff382f05b9bc0fafddb2ba6ace5ea097cf81..f3a74221ce9d3ea06bba73b5a680efbaa218b2ef 100644 (file)
@@ -50,27 +50,43 @@ enum armv7m_regtype
        ARMV7M_REGISTER_MEMMAP
 };
 
-extern char* armv7m_exception_strings[];
-
 extern char *armv7m_exception_string(int number);
 
 /* offsets into armv7m core register cache */
 enum
 {
+       /* for convenience, the first set of indices match
+        * the Cortex-M3 DCRSR selectors
+        */
+       ARMV7M_R0,
+       ARMV7M_R1,
+       ARMV7M_R2,
+       ARMV7M_R3,
+
+       ARMV7M_R4,
+       ARMV7M_R5,
+       ARMV7M_R6,
+       ARMV7M_R7,
+
+       ARMV7M_R8,
+       ARMV7M_R9,
+       ARMV7M_R10,
+       ARMV7M_R11,
+
+       ARMV7M_R12,
+       ARMV7M_R13,
+       ARMV7M_R14,
        ARMV7M_PC = 15,
+
        ARMV7M_xPSR = 16,
        ARMV7M_MSP,
        ARMV7M_PSP,
 
-       /* FIXME the register numbers here are core-specific.  Cortex-M3
-        * through r1p1 only defines registers up to PSP; see ARM DDI 0337E.
-        *
-        * It's r2p0 (see ARM DDI 0337G) which defines the register that's
-        * called SPEC20 here, with four single-byte fields with CONTROL
-        * (highest byte), FAULTMASK, BASEPRI, and PRIMASK (lowest byte).
-        */
-       ARMV7M_SPEC20 = 20,
-       ARMV7NUMCOREREGS
+       /* this next set of indices is arbitrary */
+       ARMV7M_PRIMASK,
+       ARMV7M_BASEPRI,
+       ARMV7M_FAULTMASK,
+       ARMV7M_CONTROL,
 };
 
 #define ARMV7M_COMMON_MAGIC 0x2A452A45
@@ -83,7 +99,6 @@ typedef struct armv7m_common_s
        int exception_number;
        swjdp_common_t swjdp_info;
 
-       bool has_spec20;
 
        /* Direct processor core register read and writes */
        int (*load_core_reg_u32)(struct target_s *target, enum armv7m_regtype type, uint32_t num, uint32_t *value);
@@ -113,7 +128,6 @@ typedef struct armv7m_core_reg_s
 {
        uint32_t num;
        enum armv7m_regtype type;
-       enum armv7m_mode mode;
        target_t *target;
        armv7m_common_t *armv7m_common;
 } armv7m_core_reg_t;

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