fields[1].in_check_value = NULL;
fields[1].in_check_mask = NULL;
- jtag_add_dr_scan(2, fields, -1, NULL);
+ jtag_add_dr_scan(2, fields, -1);
return ERROR_OK;
}
fields[1].in_check_value = NULL;
fields[1].in_check_mask = NULL;
- jtag_add_dr_scan(2, fields, -1, NULL);
+ jtag_add_dr_scan(2, fields, -1);
return ERROR_OK;
}
int ahbap_read_coreregister_u32(swjdp_common_t *swjdp, u32 *value, int regnum)
{
+ int retval;
+ u32 dcrdr;
+
+ ahbap_read_system_atomic_u32(swjdp, DCB_DCRDR, &dcrdr);
+
swjdp->trans_mode = TRANS_MODE_COMPOSITE;
/* ahbap_write_system_u32(swjdp, DCB_DCRSR, regnum); */
ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
ahbap_read_reg_u32(swjdp, AHBAP_BD0 | (DCB_DCRDR & 0xC), value );
- return swjdp_transaction_endcheck(swjdp);
+ retval = swjdp_transaction_endcheck(swjdp);
+ ahbap_write_system_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
+ return retval;
}
int ahbap_write_coreregister_u32(swjdp_common_t *swjdp, u32 value, int regnum)
{
+ int retval;
+ u32 dcrdr;
+
+ ahbap_read_system_atomic_u32(swjdp, DCB_DCRDR, &dcrdr);
+
swjdp->trans_mode = TRANS_MODE_COMPOSITE;
/* ahbap_write_system_u32(swjdp, DCB_DCRDR, core_regs[i]); */
/* ahbap_write_system_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR ); */
ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
ahbap_write_reg_u32(swjdp, AHBAP_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR );
-
- return swjdp_transaction_endcheck(swjdp);
+
+ retval = swjdp_transaction_endcheck(swjdp);
+ ahbap_write_system_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
+ return retval;
}
int ahbap_debugport_init(swjdp_common_t *swjdp)