jtag/vdebug: adding xtensa config

[openocd.git] / tcl / target / efm32.cfg

diff --git a/tcl/target/efm32.cfg b/tcl/target/efm32.cfg
index 33610d5a81c9a263202dea3652ebd3262752b23c..2187c0aca4e8a5b3f62ed68fd6981ca049b22c66 100644 (file)
--- a/tcl/target/efm32.cfg
+++ b/tcl/target/efm32.cfg
@@ -1,5 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Silicon Labs (formerly Energy Micro) EFM32 target
 #
-# efm32 target
+# Note: All EFM32 chips have SWD support, but only newer series 1
+# chips have JTAG support.
 #
 
 source [find target/swj-dp.tcl]
@@ -21,20 +26,27 @@ if { [info exists WORKAREASIZE] } {
 if { [info exists CPUTAPID] } {
    set _CPUTAPID $CPUTAPID
 } else {
-   set _CPUTAPID 0x2ba01477
+   if { [using_jtag] } {
+      set _CPUTAPID 0x4ba00477
+   } {
+      set _CPUTAPID 0x2ba01477
+   }
 }
 
-swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 
-adapter_khz 1000
+adapter speed 1000
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
 
 $_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME efm32 0 0 0 0 $_TARGETNAME
+flash bank userdata.flash efm32 0x0FE00000 0 0 0 $_TARGETNAME
+flash bank lockbits.flash efm32 0x0FE04000 0 0 0 $_TARGETNAME
 
 if {![using_hla]} {
    # if srst is not fitted use SYSRESETREQ to