jtag/vdebug: adding xtensa config

[openocd.git] / tcl / target / esp32.cfg

diff --git a/tcl/target/esp32.cfg b/tcl/target/esp32.cfg
index f5ca78ac86094d08d7261acb9cf97878f80c16ea..f4c13aa5b97f247b3c3899d3e452e3a504dcf31c 100644 (file)
--- a/tcl/target/esp32.cfg
+++ b/tcl/target/esp32.cfg
@@ -3,6 +3,9 @@
 # The ESP32 only supports JTAG.
 transport select jtag
 
+# Source the ESP common configuration file
+source [find target/esp_common.cfg]
+
 if { [info exists CHIPNAME] } {
        set _CHIPNAME $CHIPNAME
 } else {
@@ -67,4 +70,30 @@ if { $_ONLYCPU != 1 } {
        $_TARGETNAME_1 configure -event reset-assert-post { soft_reset_halt }
 }
 
+$_TARGETNAME_0 configure -event examine-end {
+    # Need to enable to set 'semihosting_basedir'
+    arm semihosting enable
+    arm semihosting_resexit enable
+    if { [info exists _SEMIHOST_BASEDIR] } {
+        if { $_SEMIHOST_BASEDIR != "" } {
+            arm semihosting_basedir $_SEMIHOST_BASEDIR
+        }
+    }
+}
+
+if { $_ONLYCPU != 1 } {
+       $_TARGETNAME_1 configure -event examine-end {
+               # Need to enable to set 'semihosting_basedir'
+               arm semihosting enable
+               arm semihosting_resexit enable
+               if { [info exists _SEMIHOST_BASEDIR] } {
+                       if { $_SEMIHOST_BASEDIR != "" } {
+                               arm semihosting_basedir $_SEMIHOST_BASEDIR
+                       }
+               }
+       }
+}
+
 gdb_breakpoint_override hard
+
+source [find target/xtensa-core-esp32.cfg]