jtag/vdebug: adding xtensa config

[openocd.git] / tcl / target / esp32s2.cfg

diff --git a/tcl/target/esp32s2.cfg b/tcl/target/esp32s2.cfg
index 8c5835da60a6ae2076c2241bdcbcc2d19b40dc8d..e478a6d39d52950442ef3af76ca0bf62ccb61b03 100644 (file)
--- a/tcl/target/esp32s2.cfg
+++ b/tcl/target/esp32s2.cfg
@@ -7,6 +7,8 @@ set CPU_MAX_ADDRESS 0xFFFFFFFF
 source [find bitsbytes.tcl]
 source [find memory.tcl]
 source [find mmr_helpers.tcl]
+# Source the ESP common configuration file
+source [find target/esp_common.cfg]
 
 if { [info exists CHIPNAME] } {
        set _CHIPNAME $CHIPNAME
@@ -60,6 +62,19 @@ $_TARGETNAME configure -event gdb-attach {
 
 xtensa maskisr on
 
+$_TARGETNAME configure -event examine-end {
+       # Need to enable to set 'semihosting_basedir'
+       arm semihosting enable
+       arm semihosting_resexit enable
+       if { [info exists _SEMIHOST_BASEDIR] } {
+               if { $_SEMIHOST_BASEDIR != "" } {
+                       arm semihosting_basedir $_SEMIHOST_BASEDIR
+               }
+       }
+}
+
 $_TARGETNAME configure -event reset-assert-post { soft_reset_halt }
 
 gdb_breakpoint_override hard
+
+source [find target/xtensa-core-esp32s2.cfg]