jtag/vdebug: adding xtensa config

[openocd.git] / tcl / target / psoc5lp.cfg

diff --git a/tcl/target/psoc5lp.cfg b/tcl/target/psoc5lp.cfg
index b4e8d05fa688707ce6899754159e1c2783cc34c1..fe441749000f0a4f4aa97ae1a8e25059d302ab66 100644 (file)
--- a/tcl/target/psoc5lp.cfg
+++ b/tcl/target/psoc5lp.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Cypress PSoC 5LP
 #
@@ -34,7 +36,7 @@ if { [info exists WORKAREASIZE] } {
        set _WORKAREASIZE 0x2000
 }
 
-$_TARGETNAME configure -work-area-phys [expr 0x20000000 - $_WORKAREASIZE / 2] \
+$_TARGETNAME configure -work-area-phys [expr {0x20000000 - $_WORKAREASIZE / 2}] \
                        -work-area-size $_WORKAREASIZE -work-area-backup 0
 
 source [find mem_helper.tcl]
@@ -43,15 +45,15 @@ $_TARGETNAME configure -event reset-init {
        # Configure Target Device (PSoC 5LP Device Programming Specification 5.2)
 
        set PANTHER_DBG_CFG 0x4008000C
-       set PANTHER_DBG_CFG_BYPASS [expr 1 << 1]
+       set PANTHER_DBG_CFG_BYPASS [expr {1 << 1}]
        mmw $PANTHER_DBG_CFG $PANTHER_DBG_CFG_BYPASS 0
 
        set PM_ACT_CFG0 0x400043A0
        mww $PM_ACT_CFG0 0xBF
 
        set FASTCLK_IMO_CR 0x40004200
-       set FASTCLK_IMO_CR_F_RANGE_2    [expr 2 << 0]
-       set FASTCLK_IMO_CR_F_RANGE_MASK [expr 7 << 0]
+       set FASTCLK_IMO_CR_F_RANGE_2    [expr {2 << 0}]
+       set FASTCLK_IMO_CR_F_RANGE_MASK [expr {7 << 0}]
        mmw $FASTCLK_IMO_CR $FASTCLK_IMO_CR_F_RANGE_2 $FASTCLK_IMO_CR_F_RANGE_MASK
 }