Code Review / openocd.git / blobdiff
? search:
summary | shortlog | log | commit | commitdiff | review | tree
raw | inline | side by side
jtag/vdebug: adding xtensa config
[openocd.git] / tcl / target / ti_k3.cfg
diff --git a/tcl/target/ti_k3.cfg b/tcl/target/ti_k3.cfg
index e397d2255cae037cfdc5a1d708d29dfbcbd7cb00..2454357fc34cf871a9c49f5bf544824c8851212b 100644 (file)
--- a/tcl/target/ti_k3.cfg
+++ b/tcl/target/ti_k3.cfg
@@ -12,6 +12,8 @@
 #  Has 2 ARMV8 Cores and 4 R5 Cores, M4F and an M3
 #
 
+source [find target/swj-dp.tcl]
+
 if { [info exists SOC] } {
        set _soc $SOC
 } else {
@@ -42,6 +44,7 @@ set ARMV8_CTIBASE {0x90420000 0x90520000 0x90820000 0x90920000}
 #              (0)MCU 0   (1)MCU 1   (2)MAIN_0_0 (3)MAIN_0_1 (4)MAIN_1_0 (5)MAIN_1_1
 set R5_DBGBASE {0x9d010000 0x9d012000 0x9d410000 0x9d412000 0x9d510000 0x9d512000}
 set R5_CTIBASE {0x9d018000 0x9d019000 0x9d418000 0x9d419000 0x9d518000 0x9d519000}
+set R5_NAMES {mcu_r5.0 mcu_r5.1 main0_r5.0 main0_r5.1 main1_r5.0 main1_r5.1}
 
 # Finally an General Purpose(GP) MCU
 set CM4_CTIBASE                {0x20001000}
@@ -63,12 +66,7 @@ switch $_soc {
 
                # AM654 has 1 cluster of 2 R5s cores.
                set _r5_cores 2
-               set _mcu_r5_cores 2
-               set _mcu_base_core_id 0
-               set _main0_r5_cores 0
-               set _main0_base_core_id 0
-               set _main1_r5_cores 0
-               set _main1_base_core_id 0
+               set R5_NAMES {mcu_r5.0 mcu_r5.1}
 
                # Sysctrl power-ap unlock offsets
                set _sysctrl_ap_unlock_offsets {0xf0 0x50}
@@ -85,18 +83,38 @@ switch $_soc {
 
                # AM642 has 2 cluster of 2 R5s cores.
                set _r5_cores 4
-               set _mcu_r5_cores 0
-               set _mcu_base_core_id 0
-               set _main0_r5_cores 2
-               set _main0_base_core_id 0
-               set _main1_r5_cores 2
-               set _main1_base_core_id 2
+               set R5_NAMES {main0_r5.0 main0_r5.1 main1_r5.0 main1_r5.1}
                set R5_DBGBASE {0x9d410000 0x9d412000 0x9d510000 0x9d512000}
                set R5_CTIBASE {0x9d418000 0x9d419000 0x9d518000 0x9d519000}
 
                # M4 processor
                set _gp_mcu_cores 1
        }
+       am625 {
+               set _CHIPNAME am625
+               set _K3_DAP_TAPID 0x0bb7e02f
+
+               # AM625 has 1 clusters of 4 A53 cores.
+               set _armv8_cpu_name a53
+               set _armv8_cores 4
+               set ARMV8_DBGBASE {0x90010000 0x90110000 0x90210000 0x90310000}
+               set ARMV8_CTIBASE {0x90020000 0x90120000 0x90220000 0x90320000}
+
+               # AM625 has 1 cluster of 1 R5s core.
+               set _r5_cores 1
+               set R5_NAMES {main0_r5.0}
+               set R5_DBGBASE {0x9d410000}
+               set R5_CTIBASE {0x9d418000}
+
+               # sysctrl CTI base
+               set CM3_CTIBASE {0x20001000}
+               # Sysctrl power-ap unlock offsets
+               set _sysctrl_ap_unlock_offsets {0xf0 0x78}
+
+               # M4 processor
+               set _gp_mcu_cores 1
+               set _gp_mcu_ap_unlock_offsets {0xf0 0x7c}
+       }
        j721e {
                set _CHIPNAME j721e
                set _K3_DAP_TAPID 0x0bb6402f
@@ -106,12 +124,6 @@ switch $_soc {
 
                # J721E has 3 clusters of 2 R5 cores each.
                set _r5_cores 6
-               set _mcu_r5_cores 2
-               set _mcu_base_core_id 0
-               set _main0_r5_cores 2
-               set _main0_base_core_id 2
-               set _main1_r5_cores 2
-               set _main1_base_core_id 4
        }
        j7200 {
                set _CHIPNAME j7200
@@ -123,24 +135,39 @@ switch $_soc {
 
                # J7200 has 2 clusters of 2 R5 cores each.
                set _r5_cores 4
-               set _mcu_r5_cores 2
-               set _mcu_base_core_id 0
-               set _main0_r5_cores 2
-               set _main0_base_core_id 2
-               set _main1_r5_cores 0
-               set _main1_base_core_id 0
                set R5_DBGBASE {0x9d010000 0x9d012000 0x9d110000 0x9d112000}
                set R5_CTIBASE {0x9d018000 0x9d019000 0x9d118000 0x9d119000}
 
                # M3 CTI base
                set CM3_CTIBASE {0x20001000}
        }
+       j721s2 {
+               set _CHIPNAME j721s2
+               set _K3_DAP_TAPID 0x0bb7502f
+
+               # J721s2 has 1 cluster of 2 A72 cores.
+               set _armv8_cpu_name a72
+               set _armv8_cores 2
+
+               # J721s2 has 3 clusters of 2 R5 cores each.
+               set _r5_cores 6
+
+               # sysctrl CTI base
+               set CM3_CTIBASE {0x20001000}
+               # Sysctrl power-ap unlock offsets
+               set _sysctrl_ap_unlock_offsets {0xf0 0x78}
+
+               # M4 processor
+               set _gp_mcu_cores 1
+               set _gp_mcu_ap_unlock_offsets {0xf0 0x7c}
+       }
        default {
                echo "'$_soc' is invalid!"
        }
 }
 
-jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_K3_DAP_TAPID -ignore-version
+swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_K3_DAP_TAPID -ignore-version
+
 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 
 set _TARGETNAME $_CHIPNAME.cpu
@@ -167,6 +194,24 @@ $_TARGETNAME.sysctrl configure -event gdb-attach {
        halt 1000
 }
 
+proc _cpu_no_smp_up {} {
+       set _current_target [target current]
+       set _current_type [$_current_target cget -type]
+
+       $_current_target arp_examine
+       $_current_target $_current_type dbginit
+}
+
+proc _armv8_smp_up {} {
+       for { set _core 0 } { $_core < $::_armv8_cores } { incr _core } {
+               $::_TARGETNAME.$::_armv8_cpu_name.$_core arp_examine
+               $::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 dbginit
+               $::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 smp on
+       }
+       # Set Default target as core 0
+       targets $::_TARGETNAME.$::_armv8_cpu_name.0
+}
+
 set _v8_smp_targets ""
 
 for { set _core 0 } { $_core < $_armv8_cores } { incr _core } {
@@ -178,6 +223,20 @@ for { set _core 0 } { $_core < $_armv8_cores } { incr _core } {
                -dbgbase [lindex $ARMV8_DBGBASE $_core] -cti $_CTINAME.$_armv8_cpu_name.$_core -defer-examine
 
        set _v8_smp_targets "$_v8_smp_targets $_TARGETNAME.$_armv8_cpu_name.$_core"
+
+       if { $_v8_smp_debug == 0 } {
+               $_TARGETNAME.$_armv8_cpu_name.$_core configure -event gdb-attach {
+                       _cpu_no_smp_up
+                       # gdb-attach default rule
+                       halt 1000
+               }
+       } else {
+               $_TARGETNAME.$_armv8_cpu_name.$_core configure -event gdb-attach {
+                       _armv8_smp_up
+                       # gdb-attach default rule
+                       halt 1000
+               }
+       }
 }
 
 # Setup ARMV8 proc commands based on CPU to prevent people confusing SoCs
@@ -187,62 +246,39 @@ set _armv8_smp_cmd "$_armv8_cpu_name"_smp
 
 if { $_v8_smp_debug == 0 } {
        proc $_armv8_up_cmd { args } {
-               foreach { _core } [set args] {
-                       $::_TARGETNAME.$::_armv8_cpu_name.$_core arp_examine
-                       $::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 dbginit
+               foreach _core $args {
+                       targets $_core
+                       _cpu_no_smp_up
                }
        }
 } else {
        proc $_armv8_smp_cmd { args } {
-               for { set _core 0 } { $_core < $::_armv8_cores } { incr _core } {
-                       $::_TARGETNAME.$::_armv8_cpu_name.$_core arp_examine
-                       $::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 dbginit
-                       $::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 smp on
-               }
-               # Set Default target are core 0
-               targets $::_TARGETNAME.$::_armv8_cpu_name.0
+               _armv8_smp_up
        }
-
        # Declare SMP
        target smp $:::_v8_smp_targets
 }
 
 for { set _core 0 } { $_core < $_r5_cores } { incr _core } {
-       cti create $_CTINAME.r5.$_core -dap $_CHIPNAME.dap -ap-num 1 \
+       set _r5_name [lindex $R5_NAMES $_core]
+       cti create $_CTINAME.$_r5_name -dap $_CHIPNAME.dap -ap-num 1 \
                -baseaddr [lindex $R5_CTIBASE $_core]
 
        # inactive core examination will fail - wait till startup of additional core
-       target create $_TARGETNAME.r5.$_core cortex_r4 -dap $_CHIPNAME.dap \
+       target create $_TARGETNAME.$_r5_name cortex_r4 -dap $_CHIPNAME.dap \
                -dbgbase [lindex $R5_DBGBASE $_core] -ap-num 1 -defer-examine
-}
 
-if { $_mcu_r5_cores != 0 } {
-       proc mcu_r5_up { args } {
-               foreach { _core } [set args] {
-                       set _core [expr {$_core + $::_mcu_base_core_id}]
-                       $::_TARGETNAME.r5.$_core arp_examine
-                       $::_TARGETNAME.r5.$_core cortex_r4 dbginit
-               }
-       }
-}
-
-if { $_main0_r5_cores != 0 } {
-       proc main0_r5_up { args } {
-               foreach { _core } [set args] {
-                       set _core [expr {$_core + $::_main0_base_core_id}]
-                       $::_TARGETNAME.r5.$_core arp_examine
-                       $::_TARGETNAME.r5.$_core cortex_r4 dbginit
-               }
+       $_TARGETNAME.$_r5_name configure -event gdb-attach {
+               _cpu_no_smp_up
+               # gdb-attach default rule
+               halt 1000
        }
 }
 
-if { $_main1_r5_cores != 0 } {
-       proc main1_r5_up { args } {
-               foreach { _core } [set args] {
-                       set _core [expr {$_core + $::_main1_base_core_id}]
-                       $::_TARGETNAME.r5.$_core arp_examine
-                       $::_TARGETNAME.r5.$_core cortex_r4 dbginit
-               }
+proc r5_up { args } {
+       foreach  _core $args {
+               targets $_core
+               _cpu_no_smp_up
        }
 }
 
Open On-Chip Debugger

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)