jtag/vdebug: adding xtensa config

[openocd.git] / tcl / target / xilinx_zynqmp.cfg

diff --git a/tcl/target/xilinx_zynqmp.cfg b/tcl/target/xilinx_zynqmp.cfg
index e66289a707b96e7d3bef414c76381232f10e1195..9734a18376d13f92ab7919174e2d643ae0e6f2ec 100644 (file)
--- a/tcl/target/xilinx_zynqmp.cfg
+++ b/tcl/target/xilinx_zynqmp.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # target configuration for
 # Xilinx ZynqMP (UltraScale+ / A53)
@@ -84,8 +86,7 @@ for { set _core 0 } { $_core < $_cores } { incr _core } {
         set _command "$_command -defer-examine"
         set _smp_command "$_smp_command $_TARGETNAME.$_core"
     } else {
-        # uncomment when "hawt" rtos is merged
-        #set _command "$_command -rtos hawt"
+        set _command "$_command -rtos hwthread"
         set _smp_command "target smp $_TARGETNAME.$_core"
     }
 
@@ -99,7 +100,7 @@ targets $_TARGETNAME.0
 
 proc core_up { args } {
     global _TARGETNAME
-    foreach { core } [set args] {
+    foreach core $args {
         $_TARGETNAME.$core arp_examine
     }
 }