contrib/firmware/angie/hdl/Makefile

   1 # SPDX-License-Identifier: BSD-3-Clause
   2 # Copyright (C) 2023 by NanoXplore, France - all rights reserved
   3
   4 # Needed by timing test
   5 export PROJECT := angie_openocd
   6 TARGET_PART := xc6slx9-2tqg144
   7 export TOPLEVEL := S609
   8
   9 # Detects the ROOT dir from the .git marker
  10 sp :=
  11 sp +=
  12 _walk = $(if $1,$(wildcard /$(subst $(sp),/,$1)/$2) $(call _walk,$(wordlist 2,$(words $1),x $1),$2))
  13 _find = $(firstword $(call _walk,$(strip $(subst /, ,$1)),$2))
  14 _ROOT := $(patsubst %/.git,%,$(call _find,$(CURDIR),.git))
  15
  16 SHELL := /bin/bash
  17 TOP_DIR := $(realpath $(_ROOT))
  18 HDL_DIR := $(CURDIR)
  19 SRC_DIR := $(HDL_DIR)/src
  20 TOOLS_DIR := $(TOP_DIR)/tools/build
  21 COMMON_DIR := $(TOP_DIR)/common/hdl
  22 COMMON_HDL_DIR := $(COMMON_DIR)/src
  23 COMMON_LIBS := $(COMMON_DIR)/libs
  24 HDL_BUILD_DIR := $(HDL_DIR)/build
  25 OUTPUT_DIR ?= $(HDL_BUILD_DIR)/output
  26 FINAL_OUTPUT_DIR := $(OUTPUT_DIR)/$(PROJECT)
  27
  28 # Tools
  29 MKDIR := mkdir -p
  30 CP := cp -f
  31
  32 HDL_SRC_PATH := $(addprefix $(COMMON_DIR)/ips/, $(HDL_IPS)) $(HDL_DIR)
  33 VHDSOURCE += $(foreach ip,$(HDL_SRC_PATH),$(wildcard $(ip)/src/*.vhd))
  34 VSOURCE += $(foreach ip,$(HDL_SRC_PATH),$(wildcard $(ip)/src/*.v))
  35 VSOURCE += $(foreach ip,$(HDL_SRC_PATH),$(wildcard $(ip)/src/*.vh))
  36
  37 CONSTRAINTS ?= $(SRC_DIR)/$(PROJECT).ucf
  38
  39 COMMON_OPTS := -intstyle xflow
  40 XST_OPTS :=
  41 NGDBUILD_OPTS :=
  42 MAP_OPTS := -mt 2
  43 PAR_OPTS := -mt 4
  44 BITGEN_OPTS := -g Binary:Yes
  45
  46 XILINX_PLATFORM := lin64
  47 PATH := $(PATH):$(XILINX_HOME)/bin/$(XILINX_PLATFORM)
  48
  49 RUN = @echo -ne "\n\n\e[1;33m======== $(1) ========\e[m\n\n"; \
  50         cd $(HDL_BUILD_DIR) && $(XILINX_HOME)/bin/$(XILINX_PLATFORM)/$(1)
  51
  52 compile: $(HDL_BUILD_DIR)/$(PROJECT).bin
  53
  54 install: $(HDL_BUILD_DIR)/$(PROJECT).bin
  55         $(MKDIR) $(FINAL_OUTPUT_DIR)
  56         $(CP) $(HDL_BUILD_DIR)/$(PROJECT).bin $(FINAL_OUTPUT_DIR)
  57
  58 clean:
  59         rm -rf $(HDL_BUILD_DIR)
  60
  61 $(HDL_BUILD_DIR)/$(PROJECT).bin: $(HDL_BUILD_DIR)/$(PROJECT).ncd
  62         $(call RUN,bitgen) $(COMMON_OPTS) $(BITGEN_OPTS) \
  63         -w $(PROJECT).ncd $(PROJECT).bit
  64
  65 $(HDL_BUILD_DIR)/$(PROJECT).ncd: $(HDL_BUILD_DIR)/$(PROJECT).map.ncd
  66         $(call RUN,par) $(COMMON_OPTS) $(PAR_OPTS) \
  67                 -w $(PROJECT).map.ncd $(PROJECT).ncd $(PROJECT).pcf
  68
  69 $(HDL_BUILD_DIR)/$(PROJECT).map.ncd: $(HDL_BUILD_DIR)/$(PROJECT).ngd
  70         $(call RUN,map) $(COMMON_OPTS) $(MAP_OPTS) \
  71                 -p $(TARGET_PART) \
  72                 -w $(PROJECT).ngd -o $(PROJECT).map.ncd $(PROJECT).pcf
  73
  74 $(HDL_BUILD_DIR)/$(PROJECT).ngd: $(HDL_BUILD_DIR)/$(PROJECT).ngc
  75         $(call RUN,ngdbuild) $(COMMON_OPTS) $(NGDBUILD_OPTS) \
  76                 -p $(TARGET_PART) -uc $(CONSTRAINTS) \
  77                 $(PROJECT).ngc $(PROJECT).ngd
  78
  79 $(HDL_BUILD_DIR)/$(PROJECT).ngc: $(HDL_BUILD_DIR)/$(PROJECT).prj $(HDL_BUILD_DIR)/$(PROJECT).scr
  80         $(call RUN,xst) $(COMMON_OPTS) -ifn $(PROJECT).scr
  81
  82 $(HDL_BUILD_DIR)/$(PROJECT).scr: | $(HDL_BUILD_DIR)
  83         @echo "Updating $@"
  84         @mkdir -p $(HDL_BUILD_DIR)
  85         @rm -f $@
  86         @echo "run" \
  87             "-ifn $(PROJECT).prj" \
  88             "-ofn $(PROJECT).ngc" \
  89             "-ifmt mixed" \
  90             "$(XST_OPTS)" \
  91             "-top $(TOPLEVEL)" \
  92             "-ofmt NGC" \
  93             "-p $(TARGET_PART)" \
  94         > $(HDL_BUILD_DIR)/$(PROJECT).scr
  95
  96 $(HDL_BUILD_DIR)/$(PROJECT).prj: | $(HDL_BUILD_DIR)
  97         @echo "Updating $@"
  98         @rm -f $@
  99         @$(foreach file,$(VSOURCE),echo "verilog work \"$(file)\"" >> $@;)
 100         @$(foreach file,$(VHDSOURCE),echo "vhdl work \"$(file)\"" >> $@;)
 101         @$(foreach lib,$(HDL_LIBS),$(foreach file,$(wildcard $(COMMON_LIBS)/$(lib)/src/*.vhd),echo "vhdl $(lib) \"$(file)\"" >> $@;))
 102         @$(foreach lib,$(HDL_LIBS),$(foreach file,$(wildcard $(COMMON_LIBS)/$(lib)/src/*.v),echo "verilog $(lib) \"$(file)\"" >> $@;))
 103         @$(foreach lib,$(HDL_LIBS),$(foreach file,$(wildcard $(COMMON_LIBS)/$(lib)/src/*.vh),echo "verilog $(lib) \"$(file)\"" >> $@;))
 104
 105 $(HDL_BUILD_DIR):
 106         $(MKDIR) $(HDL_BUILD_DIR)
 107
 108 .PHONY: clean compile install
 109