contrib/firmware/angie/hdl/src/angie_openocd.vhd

   1 -- SPDX-License-Identifier: BSD-3-Clause
   2 ----------------------------------------------------------------------------
   3 -- Project Context: nanoXplore USB-JTAG Adapter Board, Spartan6
   4 -- Design Name:     NJTAG USB-JTAG Adapter FPGA source code
   5 -- Module Name:     _angie_openocd.vhd
   6 -- Target Device:   XC6SLX9-2 TQ144
   7 -- Tool versions:   ISE Webpack 13.2 -> 14.2
   8 -- Author:          Ahmed BOUDJELIDA    nanoXplore SAS
   9 ----------------------------------------------------------------------------
  10
  11 library ieee;
  12 use ieee.std_logic_1164.all;
  13 use ieee.std_logic_arith.all;
  14 use ieee.std_logic_unsigned.all;
  15 library UNISIM;
  16 use UNISIM.VComponents.all;
  17
  18 entity S609 is port(
  19   TRST   : in std_logic;
  20   TMS    : in std_logic;
  21   TCK    : in std_logic;
  22   TDI    : in std_logic;
  23   TDO    : out std_logic;
  24   SRST   : in std_logic;
  25   FTP    : out std_logic_vector(7 downto 0); -- Test points
  26   SI_TDO : in  std_logic;
  27   ST_0   : out std_logic;
  28   ST_1   : out std_logic;
  29   ST_2   : out std_logic;
  30   SO_TRST : out std_logic;
  31   SO_TMS  : out std_logic;
  32   SO_TCK  : out std_logic;
  33   SO_TDI : out std_logic;
  34   SO_SRST :out std_logic
  35 );
  36 end S609;
  37
  38 architecture A_S609 of S609 is
  39 begin
  40
  41 --Directions:
  42 ST_0 <= '0';
  43 ST_1 <= '1';
  44
  45 --TDO:
  46 TDO <= not SI_TDO;
  47
  48 --TRST - TCK - TMS - TDI:
  49 SO_TRST <= TRST;
  50 SO_TMS <= TMS;
  51 SO_TCK <= TCK;
  52 SO_TDI <= TDI;
  53 ST_2 <= SRST;
  54 SO_SRST <= '0';
  55
  56 --Points de test:
  57 FTP(0) <= TRST;
  58 FTP(1) <= TMS;
  59 FTP(2) <= TCK;
  60 FTP(3) <= TDI;
  61 FTP(5) <= SRST;
  62 FTP(4) <= SI_TDO;
  63 FTP(6) <= '1';
  64 FTP(7) <= '1';
  65
  66 end A_S609;