contrib/loaders/flash/at91sam7x/crt.s

   1 /* SPDX-License-Identifier: BSD-3-Clause */
   2
   3 /****************************************************************************
   4 *  Copyright (c) 2006 by Michael Fischer. All rights reserved.
   5 ****************************************************************************
   6 *
   7 *  History:
   8 *
   9 *  18.12.06  mifi   First Version
  10 *                   The hardware initialization is based on the startup file
  11 *                   crtat91sam7x256_rom.S from NutOS 4.2.1.
  12 *                   Therefore partial copyright by egnite Software GmbH.
  13 ****************************************************************************/
  14
  15 /*
  16  * Some defines for the program status registers
  17  */
  18    ARM_MODE_USER  = 0x10      /* Normal User Mode                             */
  19    ARM_MODE_FIQ   = 0x11      /* FIQ Fast Interrupts Mode                     */
  20    ARM_MODE_IRQ   = 0x12      /* IRQ Standard Interrupts Mode                 */
  21    ARM_MODE_SVC   = 0x13      /* Supervisor Interrupts Mode                   */
  22    ARM_MODE_ABORT = 0x17      /* Abort Processing memory Faults Mode          */
  23    ARM_MODE_UNDEF = 0x1B      /* Undefined Instructions Mode                  */
  24    ARM_MODE_SYS   = 0x1F      /* System Running in Privileged Operating Mode  */
  25    ARM_MODE_MASK  = 0x1F
  26
  27    I_BIT          = 0x80      /* disable IRQ when I bit is set */
  28    F_BIT          = 0x40      /* disable IRQ when I bit is set */
  29
  30 /*
  31  * Register Base Address
  32  */
  33    AIC_BASE         = 0xFFFFF000
  34    AIC_EOICR_OFF    = 0x130
  35    AIC_IDCR_OFF     = 0x124
  36
  37    RSTC_MR          = 0xFFFFFD08
  38    RSTC_KEY         = 0xA5000000
  39    RSTC_URSTEN      = 0x00000001
  40
  41    WDT_BASE         = 0xFFFFFD40
  42    WDT_MR_OFF       = 0x00000004
  43    WDT_WDDIS        = 0x00008000
  44
  45    MC_BASE          = 0xFFFFFF00
  46    MC_FMR_OFF       = 0x00000060
  47    MC_FWS_1FWS      = 0x00480100
  48
  49    .section .vectors,"ax"
  50    .code 32
  51
  52 /****************************************************************************/
  53 /*               Vector table and reset entry                               */
  54 /****************************************************************************/
  55 _vectors:
  56    ldr pc, ResetAddr    /* Reset                 */
  57    ldr pc, UndefAddr    /* Undefined instruction */
  58    ldr pc, SWIAddr      /* Software interrupt    */
  59    ldr pc, PAbortAddr   /* Prefetch abort        */
  60    ldr pc, DAbortAddr   /* Data abort            */
  61    ldr pc, ReservedAddr /* Reserved              */
  62    ldr pc, IRQAddr      /* IRQ interrupt         */
  63    ldr pc, FIQAddr      /* FIQ interrupt         */
  64
  65
  66 ResetAddr:     .word ResetHandler
  67 UndefAddr:     .word UndefHandler
  68 SWIAddr:       .word SWIHandler
  69 PAbortAddr:    .word PAbortHandler
  70 DAbortAddr:    .word DAbortHandler
  71 ReservedAddr:  .word 0
  72 IRQAddr:       .word IRQHandler
  73 FIQAddr:       .word FIQHandler
  74
  75    .ltorg
  76
  77    .section .init, "ax"
  78    .code 32
  79
  80    .global ResetHandler
  81    .global ExitFunction
  82    .extern main
  83 /****************************************************************************/
  84 /*                           Reset handler                                  */
  85 /****************************************************************************/
  86 ResetHandler:
  87    /*
  88     * The watchdog is enabled after processor reset. Disable it.
  89     */
  90    ldr   r1, =WDT_BASE
  91    ldr   r0, =WDT_WDDIS
  92    str   r0, [r1, #WDT_MR_OFF]
  93
  94
  95    /*
  96     * Enable user reset: assertion length programmed to 1ms
  97     */
  98    ldr   r0, =(RSTC_KEY | RSTC_URSTEN | (4 << 8))
  99    ldr   r1, =RSTC_MR
 100    str   r0, [r1, #0]
 101
 102
 103    /*
 104     * Use 2 cycles for flash access.
 105     */
 106    ldr   r1, =MC_BASE
 107    ldr   r0, =MC_FWS_1FWS
 108    str   r0, [r1, #MC_FMR_OFF]
 109
 110
 111    /*
 112     * Disable all interrupts. Useful for debugging w/o target reset.
 113     */
 114    ldr   r1, =AIC_BASE
 115    mvn   r0, #0
 116    str   r0, [r1, #AIC_EOICR_OFF]
 117    str   r0, [r1, #AIC_IDCR_OFF]
 118
 119
 120    /*
 121     * Setup a stack for each mode
 122     */
 123    msr   CPSR_c, #ARM_MODE_UNDEF | I_BIT | F_BIT   /* Undefined Instruction Mode */
 124    ldr   sp, =__stack_und_end
 125
 126    msr   CPSR_c, #ARM_MODE_ABORT | I_BIT | F_BIT   /* Abort Mode */
 127    ldr   sp, =__stack_abt_end
 128
 129    msr   CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT     /* FIQ Mode */
 130    ldr   sp, =__stack_fiq_end
 131
 132    msr   CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT     /* IRQ Mode */
 133    ldr   sp, =__stack_irq_end
 134
 135    msr   CPSR_c, #ARM_MODE_SVC | I_BIT | F_BIT     /* Supervisor Mode */
 136    ldr   sp, =__stack_svc_end
 137
 138
 139    /*
 140     * Clear .bss section
 141     */
 142    ldr   r1, =__bss_start
 143    ldr   r2, =__bss_end
 144    ldr   r3, =0
 145 bss_clear_loop:
 146    cmp   r1, r2
 147    strne r3, [r1], #+4
 148    bne   bss_clear_loop
 149
 150
 151    /*
 152     * Jump to main
 153     */
 154    mrs   r0, cpsr
 155    bic   r0, r0, #I_BIT | F_BIT     /* Enable FIQ and IRQ interrupt */
 156    msr   cpsr, r0
 157
 158    mov   r0, #0 /* No arguments */
 159    mov   r1, #0 /* No arguments */
 160    ldr   r2, =main
 161    mov   lr, pc
 162    bx    r2     /* And jump... */
 163
 164 ExitFunction:
 165    nop
 166    nop
 167    nop
 168    b ExitFunction
 169
 170
 171 /****************************************************************************/
 172 /*                         Default interrupt handler                        */
 173 /****************************************************************************/
 174
 175 UndefHandler:
 176    b UndefHandler
 177
 178 SWIHandler:
 179    b SWIHandler
 180
 181 PAbortHandler:
 182    b PAbortHandler
 183
 184 DAbortHandler:
 185    b DAbortHandler
 186
 187 IRQHandler:
 188    b IRQHandler
 189
 190 FIQHandler:
 191    b FIQHandler
 192
 193    .weak ExitFunction
 194    .weak UndefHandler, PAbortHandler, DAbortHandler
 195    .weak IRQHandler, FIQHandler
 196
 197    .ltorg
 198 /*** EOF ***/