contrib/loaders/flash/msp432/msp432e4x.h

   1 /******************************************************************************
   2 *
   3 * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
   4 *
   5 * Redistribution and use in source and binary forms, with or without
   6 * modification, are permitted provided that the following conditions
   7 * are met:
   8 *
   9 *  Redistributions of source code must retain the above copyright
  10 *  notice, this list of conditions and the following disclaimer.
  11 *
  12 *  Redistributions in binary form must reproduce the above copyright
  13 *  notice, this list of conditions and the following disclaimer in the
  14 *  documentation and/or other materials provided with the
  15 *  distribution.
  16 *
  17 *  Neither the name of Texas Instruments Incorporated nor the names of
  18 *  its contributors may be used to endorse or promote products derived
  19 *  from this software without specific prior written permission.
  20 *
  21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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  30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32 *
  33 ******************************************************************************/
  34
  35 #ifndef OPENOCD_LOADERS_FLASH_MSP432_MSP432E4X_H
  36 #define OPENOCD_LOADERS_FLASH_MSP432_MSP432E4X_H
  37
  38 #include <stdint.h>
  39
  40 #ifdef __cplusplus
  41 extern "C" {
  42 #endif
  43
  44 /* Register map for FLASH_CTRL peripheral (FLASH_CTRL) */
  45 struct flash_ctrl {
  46         volatile uint32_t FMA;       /* Flash Memory Address */
  47         volatile uint32_t FMD;       /* Flash Memory Data */
  48         volatile uint32_t FMC;       /* Flash Memory Control */
  49         volatile uint32_t FCRIS;     /* Flash Controller Raw Interrupt Status */
  50         volatile uint32_t FCIM;      /* Flash Controller Interrupt Mask */
  51         volatile uint32_t FCMISC;    /* Flash Cont. Masked Int. Status and Clear */
  52         volatile uint32_t RESERVED0[2];
  53         volatile uint32_t FMC2;      /* Flash Memory Control 2 */
  54         volatile uint32_t RESERVED1[3];
  55         volatile uint32_t FWBVAL;    /* Flash Write Buffer Valid */
  56         volatile uint32_t RESERVED2[2];
  57         volatile uint32_t FLPEKEY;   /* Flash Program/Erase Key */
  58         volatile uint32_t RESERVED3[48];
  59         volatile uint32_t FWBN[32];  /* Flash Write Buffer n */
  60 };
  61
  62 /* Register map for SYSCTL peripheral (SYSCTL) */
  63 struct sys_ctrl {
  64         volatile uint32_t DID0;      /* Device Identification 0 */
  65         volatile uint32_t DID1;      /* Device Identification 1 */
  66         volatile uint32_t RESERVED0[12];
  67         volatile uint32_t PTBOCTL;   /* Power-Temp Brown Out Control */
  68         volatile uint32_t RESERVED1[5];
  69         volatile uint32_t RIS;       /* Raw Interrupt Status */
  70         volatile uint32_t IMC;       /* Interrupt Mask Control */
  71         volatile uint32_t MISC;      /* Masked Interrupt Status and Clear */
  72         volatile uint32_t RESC;      /* Reset Cause */
  73         volatile uint32_t PWRTC;     /* Power-Temperature Cause */
  74         volatile uint32_t NMIC;      /* NMI Cause Register */
  75         volatile uint32_t RESERVED2[5];
  76         volatile uint32_t MOSCCTL;   /* Main Oscillator Control */
  77         volatile uint32_t RESERVED3[12];
  78         volatile uint32_t RSCLKCFG;  /* Run and Sleep Mode Configuration Register */
  79         volatile uint32_t RESERVED4[3];
  80         volatile uint32_t MEMTIM0;   /* Memory Timing Register 0 for Main Flash */
  81         volatile uint32_t RESERVED5[29];
  82         volatile uint32_t ALTCLKCFG; /* Alternate Clock Configuration */
  83         volatile uint32_t RESERVED6[2];
  84         union {
  85                 volatile uint32_t DSLPCLKCFG; /* Deep Sleep Clock Configuration */
  86                 volatile uint32_t DSCLKCFG;   /* Deep Sleep Clock Register */
  87         };
  88         volatile uint32_t DIVSCLK;   /* Divisor and Source Clock Configuration */
  89         volatile uint32_t SYSPROP;   /* System Properties */
  90         volatile uint32_t PIOSCCAL;  /* Precision Internal Oscillator Calibration */
  91         volatile uint32_t PIOSCSTAT; /* Precision Internal Oscillator Statistics */
  92         volatile uint32_t RESERVED7[2];
  93         volatile uint32_t PLLFREQ0;  /* PLL Frequency 0 */
  94         volatile uint32_t PLLFREQ1;  /* PLL Frequency 1 */
  95         volatile uint32_t PLLSTAT;   /* PLL Status */
  96         volatile uint32_t RESERVED8[7];
  97         volatile uint32_t SLPPWRCFG; /* Sleep Power Configuration */
  98         volatile uint32_t DSLPPWRCFG; /* Deep-Sleep Power Configuration */
  99         volatile uint32_t RESERVED9[4];
 100         volatile uint32_t NVMSTAT;   /* Non-Volatile Memory Information */
 101         volatile uint32_t RESERVED10[4];
 102         volatile uint32_t LDOSPCTL;  /* LDO Sleep Power Control */
 103         volatile uint32_t RESERVED11;
 104         volatile uint32_t LDODPCTL;  /* LDO Deep-Sleep Power Control */
 105         volatile uint32_t RESERVED12[6];
 106         volatile uint32_t RESBEHAVCTL; /* Reset Behavior Control Register */
 107         volatile uint32_t RESERVED13[6];
 108         volatile uint32_t HSSR;      /* Hardware System Service Request */
 109         volatile uint32_t RESERVED14[34];
 110         volatile uint32_t USBPDS;    /* USB Power Domain Status */
 111         volatile uint32_t USBMPC;    /* USB Memory Power Control */
 112         volatile uint32_t EMACPDS;   /* Ethernet MAC Power Domain Status */
 113         volatile uint32_t EMACMPC;   /* Ethernet MAC Memory Power Control */
 114         volatile uint32_t RESERVED15;
 115         volatile uint32_t LCDMPC;    /* LCD Memory Power Control */
 116         volatile uint32_t RESERVED16[26];
 117         volatile uint32_t PPWD;      /* Watchdog Timer Peripheral Present */
 118         volatile uint32_t PPTIMER;   /* General-Purpose Timer Peripheral Present */
 119         volatile uint32_t PPGPIO;    /* General-Purpose I/O Peripheral Present */
 120         volatile uint32_t PPDMA;     /* Micro DMA Peripheral Present */
 121         volatile uint32_t PPEPI;     /* EPI Peripheral Present */
 122         volatile uint32_t PPHIB;     /* Hibernation Peripheral Present */
 123         volatile uint32_t PPUART;    /* UART Peripheral Present */
 124         volatile uint32_t PPSSI;     /* Synchronous Serial Inter. Periph. Present */
 125         volatile uint32_t PPI2C;     /* Inter-Integrated Circuit Periph. Present */
 126         volatile uint32_t RESERVED17;
 127         volatile uint32_t PPUSB;     /* Universal Serial Bus Peripheral Present */
 128         volatile uint32_t RESERVED18;
 129         volatile uint32_t PPEPHY;    /* Ethernet PHY Peripheral Present */
 130         volatile uint32_t PPCAN;     /* Controller Area Network Periph. Present */
 131         volatile uint32_t PPADC;     /* Analog-to-Dig. Converter Periph. Present */
 132         volatile uint32_t PPACMP;    /* Analog Comparator Peripheral Present */
 133         volatile uint32_t PPPWM;     /* Pulse Width Modulator Peripheral Present */
 134         volatile uint32_t PPQEI;     /* Quadrature Encoder Inter. Periph. Present */
 135         volatile uint32_t RESERVED19[4];
 136         volatile uint32_t PPEEPROM;  /* EEPROM Peripheral Present */
 137         volatile uint32_t RESERVED20[6];
 138         volatile uint32_t PPCCM;     /* CRC/Cryptographic Modules Periph. Present */
 139         volatile uint32_t RESERVED21[6];
 140         volatile uint32_t PPLCD;     /* LCD Peripheral Present */
 141         volatile uint32_t RESERVED22;
 142         volatile uint32_t PPOWIRE;   /* 1-Wire Peripheral Present */
 143         volatile uint32_t PPEMAC;    /* Ethernet MAC Peripheral Present */
 144         volatile uint32_t RESERVED23[88];
 145         volatile uint32_t SRWD;      /* Watchdog Timer Software Reset */
 146         volatile uint32_t SRTIMER;   /* General-Purpose Timer Software Reset */
 147         volatile uint32_t SRGPIO;    /* General-Purpose I/O Software Reset */
 148         volatile uint32_t SRDMA;     /* Micro Direct Memory Access Software Reset */
 149         volatile uint32_t SREPI;     /* EPI Software Reset */
 150         volatile uint32_t SRHIB;     /* Hibernation Software Reset */
 151         volatile uint32_t SRUART;    /* UART Software Reset */
 152         volatile uint32_t SRSSI;     /* Synchronous Serial Inter. Software Reset */
 153         volatile uint32_t SRI2C;     /* Inter-Integrated Circuit Software Reset */
 154         volatile uint32_t RESERVED24;
 155         volatile uint32_t SRUSB;     /* Universal Serial Bus Software Reset */
 156         volatile uint32_t RESERVED25;
 157         volatile uint32_t SREPHY;    /* Ethernet PHY Software Reset */
 158         volatile uint32_t SRCAN;     /* Controller Area Network Software Reset */
 159         volatile uint32_t SRADC;     /* Analog-to-Dig. Converter Software Reset */
 160         volatile uint32_t SRACMP;    /* Analog Comparator Software Reset */
 161         volatile uint32_t SRPWM;     /* Pulse Width Modulator Software Reset */
 162         volatile uint32_t SRQEI;     /* Quadrature Encoder Inter. Software Reset */
 163         volatile uint32_t RESERVED26[4];
 164         volatile uint32_t SREEPROM;  /* EEPROM Software Reset */
 165         volatile uint32_t RESERVED27[6];
 166         volatile uint32_t SRCCM;     /* CRC/Cryptographic Modules Software Reset */
 167         volatile uint32_t RESERVED28[6];
 168         volatile uint32_t SRLCD;     /* LCD Controller Software Reset */
 169         volatile uint32_t RESERVED29;
 170         volatile uint32_t SROWIRE;   /* 1-Wire Software Reset */
 171         volatile uint32_t SREMAC;    /* Ethernet MAC Software Reset */
 172         volatile uint32_t RESERVED30[24];
 173         volatile uint32_t RCGCWD;    /* Watchdog Run Mode Clock Gating Control */
 174 };
 175
 176 /* Peripheral Memory Map */
 177 #define FLASH_CTRL_BASE 0x400FD000UL
 178 #define SYSCTL_BASE     0x400FE000UL
 179
 180 /* Peripheral Declarations */
 181 #define FLASH_CTRL ((struct flash_ctrl *) FLASH_CTRL_BASE)
 182 #define SYSCTL     ((struct sys_ctrl *) SYSCTL_BASE)
 183
 184 /* The following are defines for the bit fields in the FLASH_FMC register. */
 185 #define FLASH_FMC_WRKEY  0xA4420000 /* FLASH write key */
 186 #define FLASH_FMC_COMT   0x00000008 /* Commit Register Value */
 187 #define FLASH_FMC_MERASE 0x00000004 /* Mass Erase Flash Memory */
 188 #define FLASH_FMC_ERASE  0x00000002 /* Erase a Page of Flash Memory */
 189 #define FLASH_FMC_WRITE  0x00000001 /* Write a Word into Flash Memory */
 190
 191 /* The following are defines for the bit fields in the FLASH_FCRIS register. */
 192 #define FLASH_FCRIS_PROGRIS 0x00002000 /* Program Verify Raw Interrupt Status */
 193 #define FLASH_FCRIS_ERRIS   0x00000800 /* Erase Verify Raw Interrupt Status */
 194 #define FLASH_FCRIS_INVDRIS 0x00000400 /* Invalid Data Raw Interrupt Status */
 195 #define FLASH_FCRIS_VOLTRIS 0x00000200 /* Pump Voltage Raw Interrupt Status */
 196 #define FLASH_FCRIS_ERIS    0x00000004 /* EEPROM Raw Interrupt Status */
 197 #define FLASH_FCRIS_PRIS    0x00000002 /* Programming Raw Interrupt Status */
 198 #define FLASH_FCRIS_ARIS    0x00000001 /* Access Raw Interrupt Status */
 199
 200 /* The following are defines for the bit fields in the FLASH_FCIM register. */
 201 #define FLASH_FCIM_PROGMASK 0x00002000 /* PROGVER Interrupt Mask */
 202 #define FLASH_FCIM_ERMASK   0x00000800 /* ERVER Interrupt Mask */
 203 #define FLASH_FCIM_INVDMASK 0x00000400 /* Invalid Data Interrupt Mask */
 204 #define FLASH_FCIM_VOLTMASK 0x00000200 /* VOLT Interrupt Mask */
 205 #define FLASH_FCIM_EMASK    0x00000004 /* EEPROM Interrupt Mask */
 206 #define FLASH_FCIM_PMASK    0x00000002 /* Programming Interrupt Mask */
 207 #define FLASH_FCIM_AMASK    0x00000001 /* Access Interrupt Mask */
 208
 209 /* The following are defines for the bit fields in the FLASH_FCMISC register. */
 210 #define FLASH_FCMISC_PROGMISC 0x00002000 /* PROGVER Interrupt Status/Clear */
 211 #define FLASH_FCMISC_ERMISC   0x00000800 /* ERVER Interrupt Status/Clear */
 212 #define FLASH_FCMISC_INVDMISC 0x00000400 /* Invalid Data Int. Status/Clear */
 213 #define FLASH_FCMISC_VOLTMISC 0x00000200 /* VOLT Interrupt Status/Clear */
 214 #define FLASH_FCMISC_EMISC    0x00000004 /* EEPROM Interrupt Status/Clear */
 215 #define FLASH_FCMISC_PMISC    0x00000002 /* Programming Int. Status/Clear */
 216 #define FLASH_FCMISC_AMISC    0x00000001 /* Access Interrupt Status/Clear */
 217
 218 /* The following are defines for the bit fields in the FLASH_FMC2 register. */
 219 #define FLASH_FMC2_WRBUF 0x00000001 /* Buffered Flash Memory Write */
 220
 221 /* The following are defines for the bit fields in the SYSCTL_RCGCWD reg. */
 222 #define SYSCTL_RCGCWD_R1 0x00000002 /* Watchdog 1 Run Mode Clock Gating Cont. */
 223 #define SYSCTL_RCGCWD_R0 0x00000001 /* Watchdog 0 Run Mode Clock Gating Cont. */
 224
 225 #ifdef __cplusplus
 226 }
 227 #endif
 228
 229 #endif  /* OPENOCD_LOADERS_FLASH_MSP432_MSP432E4X_H */