contrib/loaders/flash/msp432/msp432e4x.h

   1 /* SPDX-License-Identifier: BSD-3-Clause */
   2
   3 /******************************************************************************
   4 *
   5 * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
   6 *
   7 ******************************************************************************/
   8
   9 #ifndef OPENOCD_LOADERS_FLASH_MSP432_MSP432E4X_H
  10 #define OPENOCD_LOADERS_FLASH_MSP432_MSP432E4X_H
  11
  12 #include <stdint.h>
  13
  14 #ifdef __cplusplus
  15 extern "C" {
  16 #endif
  17
  18 /* Register map for FLASH_CTRL peripheral (FLASH_CTRL) */
  19 struct flash_ctrl {
  20         volatile uint32_t FMA;       /* Flash Memory Address */
  21         volatile uint32_t FMD;       /* Flash Memory Data */
  22         volatile uint32_t FMC;       /* Flash Memory Control */
  23         volatile uint32_t FCRIS;     /* Flash Controller Raw Interrupt Status */
  24         volatile uint32_t FCIM;      /* Flash Controller Interrupt Mask */
  25         volatile uint32_t FCMISC;    /* Flash Cont. Masked Int. Status and Clear */
  26         volatile uint32_t RESERVED0[2];
  27         volatile uint32_t FMC2;      /* Flash Memory Control 2 */
  28         volatile uint32_t RESERVED1[3];
  29         volatile uint32_t FWBVAL;    /* Flash Write Buffer Valid */
  30         volatile uint32_t RESERVED2[2];
  31         volatile uint32_t FLPEKEY;   /* Flash Program/Erase Key */
  32         volatile uint32_t RESERVED3[48];
  33         volatile uint32_t FWBN[32];  /* Flash Write Buffer n */
  34 };
  35
  36 /* Register map for SYSCTL peripheral (SYSCTL) */
  37 struct sys_ctrl {
  38         volatile uint32_t DID0;      /* Device Identification 0 */
  39         volatile uint32_t DID1;      /* Device Identification 1 */
  40         volatile uint32_t RESERVED0[12];
  41         volatile uint32_t PTBOCTL;   /* Power-Temp Brown Out Control */
  42         volatile uint32_t RESERVED1[5];
  43         volatile uint32_t RIS;       /* Raw Interrupt Status */
  44         volatile uint32_t IMC;       /* Interrupt Mask Control */
  45         volatile uint32_t MISC;      /* Masked Interrupt Status and Clear */
  46         volatile uint32_t RESC;      /* Reset Cause */
  47         volatile uint32_t PWRTC;     /* Power-Temperature Cause */
  48         volatile uint32_t NMIC;      /* NMI Cause Register */
  49         volatile uint32_t RESERVED2[5];
  50         volatile uint32_t MOSCCTL;   /* Main Oscillator Control */
  51         volatile uint32_t RESERVED3[12];
  52         volatile uint32_t RSCLKCFG;  /* Run and Sleep Mode Configuration Register */
  53         volatile uint32_t RESERVED4[3];
  54         volatile uint32_t MEMTIM0;   /* Memory Timing Register 0 for Main Flash */
  55         volatile uint32_t RESERVED5[29];
  56         volatile uint32_t ALTCLKCFG; /* Alternate Clock Configuration */
  57         volatile uint32_t RESERVED6[2];
  58         union {
  59                 volatile uint32_t DSLPCLKCFG; /* Deep Sleep Clock Configuration */
  60                 volatile uint32_t DSCLKCFG;   /* Deep Sleep Clock Register */
  61         };
  62         volatile uint32_t DIVSCLK;   /* Divisor and Source Clock Configuration */
  63         volatile uint32_t SYSPROP;   /* System Properties */
  64         volatile uint32_t PIOSCCAL;  /* Precision Internal Oscillator Calibration */
  65         volatile uint32_t PIOSCSTAT; /* Precision Internal Oscillator Statistics */
  66         volatile uint32_t RESERVED7[2];
  67         volatile uint32_t PLLFREQ0;  /* PLL Frequency 0 */
  68         volatile uint32_t PLLFREQ1;  /* PLL Frequency 1 */
  69         volatile uint32_t PLLSTAT;   /* PLL Status */
  70         volatile uint32_t RESERVED8[7];
  71         volatile uint32_t SLPPWRCFG; /* Sleep Power Configuration */
  72         volatile uint32_t DSLPPWRCFG; /* Deep-Sleep Power Configuration */
  73         volatile uint32_t RESERVED9[4];
  74         volatile uint32_t NVMSTAT;   /* Non-Volatile Memory Information */
  75         volatile uint32_t RESERVED10[4];
  76         volatile uint32_t LDOSPCTL;  /* LDO Sleep Power Control */
  77         volatile uint32_t RESERVED11;
  78         volatile uint32_t LDODPCTL;  /* LDO Deep-Sleep Power Control */
  79         volatile uint32_t RESERVED12[6];
  80         volatile uint32_t RESBEHAVCTL; /* Reset Behavior Control Register */
  81         volatile uint32_t RESERVED13[6];
  82         volatile uint32_t HSSR;      /* Hardware System Service Request */
  83         volatile uint32_t RESERVED14[34];
  84         volatile uint32_t USBPDS;    /* USB Power Domain Status */
  85         volatile uint32_t USBMPC;    /* USB Memory Power Control */
  86         volatile uint32_t EMACPDS;   /* Ethernet MAC Power Domain Status */
  87         volatile uint32_t EMACMPC;   /* Ethernet MAC Memory Power Control */
  88         volatile uint32_t RESERVED15;
  89         volatile uint32_t LCDMPC;    /* LCD Memory Power Control */
  90         volatile uint32_t RESERVED16[26];
  91         volatile uint32_t PPWD;      /* Watchdog Timer Peripheral Present */
  92         volatile uint32_t PPTIMER;   /* General-Purpose Timer Peripheral Present */
  93         volatile uint32_t PPGPIO;    /* General-Purpose I/O Peripheral Present */
  94         volatile uint32_t PPDMA;     /* Micro DMA Peripheral Present */
  95         volatile uint32_t PPEPI;     /* EPI Peripheral Present */
  96         volatile uint32_t PPHIB;     /* Hibernation Peripheral Present */
  97         volatile uint32_t PPUART;    /* UART Peripheral Present */
  98         volatile uint32_t PPSSI;     /* Synchronous Serial Inter. Periph. Present */
  99         volatile uint32_t PPI2C;     /* Inter-Integrated Circuit Periph. Present */
 100         volatile uint32_t RESERVED17;
 101         volatile uint32_t PPUSB;     /* Universal Serial Bus Peripheral Present */
 102         volatile uint32_t RESERVED18;
 103         volatile uint32_t PPEPHY;    /* Ethernet PHY Peripheral Present */
 104         volatile uint32_t PPCAN;     /* Controller Area Network Periph. Present */
 105         volatile uint32_t PPADC;     /* Analog-to-Dig. Converter Periph. Present */
 106         volatile uint32_t PPACMP;    /* Analog Comparator Peripheral Present */
 107         volatile uint32_t PPPWM;     /* Pulse Width Modulator Peripheral Present */
 108         volatile uint32_t PPQEI;     /* Quadrature Encoder Inter. Periph. Present */
 109         volatile uint32_t RESERVED19[4];
 110         volatile uint32_t PPEEPROM;  /* EEPROM Peripheral Present */
 111         volatile uint32_t RESERVED20[6];
 112         volatile uint32_t PPCCM;     /* CRC/Cryptographic Modules Periph. Present */
 113         volatile uint32_t RESERVED21[6];
 114         volatile uint32_t PPLCD;     /* LCD Peripheral Present */
 115         volatile uint32_t RESERVED22;
 116         volatile uint32_t PPOWIRE;   /* 1-Wire Peripheral Present */
 117         volatile uint32_t PPEMAC;    /* Ethernet MAC Peripheral Present */
 118         volatile uint32_t RESERVED23[88];
 119         volatile uint32_t SRWD;      /* Watchdog Timer Software Reset */
 120         volatile uint32_t SRTIMER;   /* General-Purpose Timer Software Reset */
 121         volatile uint32_t SRGPIO;    /* General-Purpose I/O Software Reset */
 122         volatile uint32_t SRDMA;     /* Micro Direct Memory Access Software Reset */
 123         volatile uint32_t SREPI;     /* EPI Software Reset */
 124         volatile uint32_t SRHIB;     /* Hibernation Software Reset */
 125         volatile uint32_t SRUART;    /* UART Software Reset */
 126         volatile uint32_t SRSSI;     /* Synchronous Serial Inter. Software Reset */
 127         volatile uint32_t SRI2C;     /* Inter-Integrated Circuit Software Reset */
 128         volatile uint32_t RESERVED24;
 129         volatile uint32_t SRUSB;     /* Universal Serial Bus Software Reset */
 130         volatile uint32_t RESERVED25;
 131         volatile uint32_t SREPHY;    /* Ethernet PHY Software Reset */
 132         volatile uint32_t SRCAN;     /* Controller Area Network Software Reset */
 133         volatile uint32_t SRADC;     /* Analog-to-Dig. Converter Software Reset */
 134         volatile uint32_t SRACMP;    /* Analog Comparator Software Reset */
 135         volatile uint32_t SRPWM;     /* Pulse Width Modulator Software Reset */
 136         volatile uint32_t SRQEI;     /* Quadrature Encoder Inter. Software Reset */
 137         volatile uint32_t RESERVED26[4];
 138         volatile uint32_t SREEPROM;  /* EEPROM Software Reset */
 139         volatile uint32_t RESERVED27[6];
 140         volatile uint32_t SRCCM;     /* CRC/Cryptographic Modules Software Reset */
 141         volatile uint32_t RESERVED28[6];
 142         volatile uint32_t SRLCD;     /* LCD Controller Software Reset */
 143         volatile uint32_t RESERVED29;
 144         volatile uint32_t SROWIRE;   /* 1-Wire Software Reset */
 145         volatile uint32_t SREMAC;    /* Ethernet MAC Software Reset */
 146         volatile uint32_t RESERVED30[24];
 147         volatile uint32_t RCGCWD;    /* Watchdog Run Mode Clock Gating Control */
 148 };
 149
 150 /* Peripheral Memory Map */
 151 #define FLASH_CTRL_BASE 0x400FD000UL
 152 #define SYSCTL_BASE     0x400FE000UL
 153
 154 /* Peripheral Declarations */
 155 #define FLASH_CTRL ((struct flash_ctrl *) FLASH_CTRL_BASE)
 156 #define SYSCTL     ((struct sys_ctrl *) SYSCTL_BASE)
 157
 158 /* The following are defines for the bit fields in the FLASH_FMC register. */
 159 #define FLASH_FMC_WRKEY  0xA4420000 /* FLASH write key */
 160 #define FLASH_FMC_COMT   0x00000008 /* Commit Register Value */
 161 #define FLASH_FMC_MERASE 0x00000004 /* Mass Erase Flash Memory */
 162 #define FLASH_FMC_ERASE  0x00000002 /* Erase a Page of Flash Memory */
 163 #define FLASH_FMC_WRITE  0x00000001 /* Write a Word into Flash Memory */
 164
 165 /* The following are defines for the bit fields in the FLASH_FCRIS register. */
 166 #define FLASH_FCRIS_PROGRIS 0x00002000 /* Program Verify Raw Interrupt Status */
 167 #define FLASH_FCRIS_ERRIS   0x00000800 /* Erase Verify Raw Interrupt Status */
 168 #define FLASH_FCRIS_INVDRIS 0x00000400 /* Invalid Data Raw Interrupt Status */
 169 #define FLASH_FCRIS_VOLTRIS 0x00000200 /* Pump Voltage Raw Interrupt Status */
 170 #define FLASH_FCRIS_ERIS    0x00000004 /* EEPROM Raw Interrupt Status */
 171 #define FLASH_FCRIS_PRIS    0x00000002 /* Programming Raw Interrupt Status */
 172 #define FLASH_FCRIS_ARIS    0x00000001 /* Access Raw Interrupt Status */
 173
 174 /* The following are defines for the bit fields in the FLASH_FCIM register. */
 175 #define FLASH_FCIM_PROGMASK 0x00002000 /* PROGVER Interrupt Mask */
 176 #define FLASH_FCIM_ERMASK   0x00000800 /* ERVER Interrupt Mask */
 177 #define FLASH_FCIM_INVDMASK 0x00000400 /* Invalid Data Interrupt Mask */
 178 #define FLASH_FCIM_VOLTMASK 0x00000200 /* VOLT Interrupt Mask */
 179 #define FLASH_FCIM_EMASK    0x00000004 /* EEPROM Interrupt Mask */
 180 #define FLASH_FCIM_PMASK    0x00000002 /* Programming Interrupt Mask */
 181 #define FLASH_FCIM_AMASK    0x00000001 /* Access Interrupt Mask */
 182
 183 /* The following are defines for the bit fields in the FLASH_FCMISC register. */
 184 #define FLASH_FCMISC_PROGMISC 0x00002000 /* PROGVER Interrupt Status/Clear */
 185 #define FLASH_FCMISC_ERMISC   0x00000800 /* ERVER Interrupt Status/Clear */
 186 #define FLASH_FCMISC_INVDMISC 0x00000400 /* Invalid Data Int. Status/Clear */
 187 #define FLASH_FCMISC_VOLTMISC 0x00000200 /* VOLT Interrupt Status/Clear */
 188 #define FLASH_FCMISC_EMISC    0x00000004 /* EEPROM Interrupt Status/Clear */
 189 #define FLASH_FCMISC_PMISC    0x00000002 /* Programming Int. Status/Clear */
 190 #define FLASH_FCMISC_AMISC    0x00000001 /* Access Interrupt Status/Clear */
 191
 192 /* The following are defines for the bit fields in the FLASH_FMC2 register. */
 193 #define FLASH_FMC2_WRBUF 0x00000001 /* Buffered Flash Memory Write */
 194
 195 /* The following are defines for the bit fields in the SYSCTL_RCGCWD reg. */
 196 #define SYSCTL_RCGCWD_R1 0x00000002 /* Watchdog 1 Run Mode Clock Gating Cont. */
 197 #define SYSCTL_RCGCWD_R0 0x00000001 /* Watchdog 0 Run Mode Clock Gating Cont. */
 198
 199 #ifdef __cplusplus
 200 }
 201 #endif
 202
 203 #endif  /* OPENOCD_LOADERS_FLASH_MSP432_MSP432E4X_H */