contrib/loaders/flash/stm32/stm32h7x.S

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 /***************************************************************************
   4  *   Copyright (C) 2017 by STMicroelectronics                              *
   5  ***************************************************************************/
   6
   7         .text
   8         .syntax unified
   9         .cpu cortex-m4
  10         .thumb
  11
  12 /*
  13  * Code limitations:
  14  * The workarea must have size multiple of 4 bytes, since R/W
  15  * operations are all at 32 bits.
  16  * The workarea must be big enough to contain rp, wp and data, thus the minimum
  17  * workarea size is: min_wa_size = sizeof(rp, wp, data) = 4 + 4 + sizeof(data).
  18  *  - for 0x450 devices: sizeof(data) = 32 bytes, thus min_wa_size = 40 bytes.
  19  *  - for 0x480 devices: sizeof(data) = 16 bytes, thus min_wa_size = 24 bytes.
  20  * To benefit from concurrent host write-to-buffer and target
  21  * write-to-flash, the workarea must be way bigger than the minimum.
  22  *
  23  * To avoid confusions the write word size is got from .block_size member of
  24  * struct stm32h7x_part_info defined in stm32h7x.c
  25 */
  26
  27 /*
  28  * Params :
  29  * r0 = workarea start, status (out)
  30  * r1 = workarea end
  31  * r2 = target address
  32  * r3 = count (of write words)
  33  * r4 = size of write word
  34  * r5 = flash reg base
  35  *
  36  * Clobbered:
  37  * r6 - rp
  38  * r7 - wp, status, tmp
  39  * r8 - loop index, tmp
  40  */
  41
  42 #define STM32_FLASH_CR_OFFSET   0x0C    /* offset of CR register in FLASH struct */
  43 #define STM32_FLASH_SR_OFFSET   0x10    /* offset of SR register in FLASH struct */
  44 #define STM32_CR_PROG                   0x00000002      /* PG */
  45 #define STM32_SR_QW_MASK                0x00000004      /* QW */
  46 #define STM32_SR_ERROR_MASK             0x07ee0000      /* DBECCERR | SNECCERR | RDSERR | RDPERR | OPERR
  47                                                                                            | INCERR | STRBERR | PGSERR | WRPERR */
  48
  49         .thumb_func
  50         .global _start
  51 _start:
  52         ldr             r6, [r0, #4]            /* read rp */
  53
  54 wait_fifo:
  55         ldr             r7, [r0, #0]            /* read wp */
  56         cbz             r7, exit                        /* abort if wp == 0, status = 0 */
  57         subs    r7, r7, r6                      /* number of bytes available for read in r7 */
  58         ittt    mi                                      /* if wrapped around */
  59         addmi   r7, r1                          /* add size of buffer */
  60         submi   r7, r0
  61         submi   r7, #8
  62         cmp             r7, r4                          /* wait until data buffer is full */
  63         bcc             wait_fifo
  64
  65         mov             r7, #STM32_CR_PROG
  66         str             r7, [r5, #STM32_FLASH_CR_OFFSET]
  67
  68         mov             r8, #4
  69         udiv    r8, r4, r8                      /* number of words is size of write word divided by 4*/
  70 write_flash:
  71         dsb
  72         ldr             r7, [r6], #0x04         /* read one word from src, increment ptr */
  73         str             r7, [r2], #0x04         /* write one word to dst, increment ptr */
  74         dsb
  75         cmp             r6, r1                          /* if rp >= end of buffer ... */
  76         it              cs
  77         addcs   r6, r0, #8                      /* ... then wrap at buffer start */
  78         subs    r8, r8, #1                      /* decrement loop index */
  79         bne             write_flash                     /* loop if not done */
  80
  81 busy:
  82         ldr             r7, [r5, #STM32_FLASH_SR_OFFSET]
  83         tst             r7, #STM32_SR_QW_MASK
  84         bne             busy                            /* operation in progress, wait ... */
  85
  86         ldr             r8, =STM32_SR_ERROR_MASK
  87         tst             r7, r8
  88         bne             error                           /* fail... */
  89
  90         str             r6, [r0, #4]            /* store rp */
  91         subs    r3, r3, #1                      /* decrement count */
  92         bne             wait_fifo                       /* loop if not done */
  93         b               exit
  94
  95 error:
  96         movs    r8, #0
  97         str             r8, [r0, #4]            /* set rp = 0 on error */
  98
  99 exit:
 100         mov             r0, r7                          /* return status in r0 */
 101         bkpt    #0x00
 102
 103         .pool