contrib/loaders/reset/espressif/esp32/esp32_cpu_reset_handler.S

   1 /***************************************************************************
   2  *   Reset stub used by esp32 target                                       *
   3  *   Copyright (C) 2017 Espressif Systems Ltd.                             *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  17  ***************************************************************************/
  18
  19 #define RTC_CNTL_RESET_STATE_REG    0x3ff48034
  20 #define RTC_CNTL_RESET_STATE_DEF    0x3000
  21 #define RTC_CNTL_CLK_CONF_REG       0x3ff48070
  22 #define RTC_CNTL_CLK_CONF_DEF       0x2210
  23 #define RTC_CNTL_STORE4_REG         0x3ff480b0
  24 #define RTC_CNTL_STORE5_REG         0x3ff480b4
  25 #define WDT_WKEY_VALUE              0x50D83AA1
  26 #define TIMG0_WDTWPROTECT_REG       0x3ff5f064
  27 #define TIMG0_WDTCONFIG0_REG        0x3ff5f048
  28 #define TIMG1_WDTWPROTECT_REG       0x3FF60064
  29 #define TIMG1_WDTCONFIG0_REG        0x3ff60048
  30 #define RTC_CNTL_WDTCONFIG0_REG     0x3ff4808c
  31 #define RTC_CNTL_WDTWPROTECT_REG    0x3ff480a4
  32 #define JTAG_ENABLE_REG             0x3ff5a1fc
  33 #define RTC_CNTL_OPTIONS0_REG       0x3ff48000
  34 #define RTC_CNTL_OPTIONS0_DEF       0x1c492000
  35 #define RTC_CNTL_SW_SYS_RST         0x80000000
  36 #define DPORT_APPCPU_CTRL_A_REG     0x3ff0002c
  37 #define DPORT_APPCPU_RST_EN         0x1
  38 #define DPORT_APPCPU_CTRL_B_REG     0x3ff00030
  39 #define DPORT_APPCPU_CLKGATE_EN     0x1
  40 #define DPORT_APPCPU_CTRL_C_REG     0x3ff00034
  41 #define DPORT_APPCPU_CTRL_D_REG     0x3ff00038
  42
  43
  44 /* This stub is copied to RTC_SLOW_MEM by OpenOCD, and the CPU starts executing
  45  * it instead of the ROM code (0x40000400). This stub disables watchdogs and
  46  * goes into a loop.
  47  * OpenOCD will then halt the target and perform CPU reset using OCD.
  48  */
  49
  50
  51 /* Has to be at offset 0. This is the entry point of the CPU, once
  52  * RTC_CNTL_PROCPU_STAT_VECTOR_SEL is cleared.
  53  * CPU will come here after the system reset, triggered by RTC_CNTL_SW_SYS_RST.
  54  */
  55     .global     cpu_at_start_handler
  56     .type       cpu_at_start_handler,@function
  57     .align      4
  58 cpu_at_start_handler:
  59     j start
  60
  61
  62 /* Has to be at offset 4. Once the stub code has been uploaded into RTC Slow
  63  * memory, OpenOCD will set the PC to this address, and resume execution.
  64  * The stub will then jump to 'reset' label and perform the reset.
  65  */
  66     .global     cpu_reset_handler
  67     .type       cpu_reset_handler,@function
  68     .align      4
  69 cpu_reset_handler:
  70     j reset
  71
  72     .align 4
  73     .literal_position
  74
  75     .align 4
  76 reset:
  77     /* Use a5 as a zero register */
  78     xor a5, a5, a5
  79     /* Select static reset vector 0 (XCHAL_RESET_VECTOR0_VADDR, 0x50000000) */
  80     movi a4, RTC_CNTL_RESET_STATE_REG
  81     s32i a5, a4, 0
  82     /* Set some clock-related RTC registers to the default values */
  83     movi a4, RTC_CNTL_STORE4_REG
  84     s32i a5, a4, 0
  85     movi a4, RTC_CNTL_STORE5_REG
  86     s32i a5, a4, 0
  87     movi a4, RTC_CNTL_CLK_CONF_REG
  88     movi a3, RTC_CNTL_CLK_CONF_DEF
  89     s32i a3, a4, 0
  90     /* Reset the digital part of the chip (RTC controller doesn't get reset) */
  91     movi a3, (RTC_CNTL_OPTIONS0_DEF | RTC_CNTL_SW_SYS_RST)
  92     movi a4, RTC_CNTL_OPTIONS0_REG
  93     s32i a3, a4, 0
  94     /* Doesn't reach beyond this instruction */
  95
  96     .align 4
  97 start:
  98     /* If running on the APP CPU, skip directly to the parking loop */
  99     rsr.prid a6
 100     extui a6, a6, 1, 1
 101     bnez a6, parking_loop
 102
 103     /* Use a5 as a zero register */
 104     xor a5, a5, a5
 105     /* Disable the watchdogs */
 106     movi a3, WDT_WKEY_VALUE
 107     movi a4, RTC_CNTL_WDTWPROTECT_REG
 108     s32i.n a3, a4, 0
 109     movi a4, TIMG0_WDTWPROTECT_REG
 110     s32i.n a3, a4, 0
 111     movi a4, TIMG1_WDTWPROTECT_REG
 112     s32i.n a3, a4, 0
 113     movi a4, RTC_CNTL_WDTCONFIG0_REG
 114     s32i.n a5, a4, 0
 115     movi a4, TIMG0_WDTCONFIG0_REG
 116     s32i.n a5, a4, 0
 117     movi a4, TIMG1_WDTCONFIG0_REG
 118     s32i.n a5, a4, 0
 119     /* Enable JTAG (needed since rev. 3) */
 120     movi a4, JTAG_ENABLE_REG
 121     s32i.n a5, a4, 0
 122     /* Clear APP_CPU boot address */
 123     movi a4, DPORT_APPCPU_CTRL_D_REG
 124     s32i.n a5, a4, 0
 125     /* Clear APP_CPU clock gating */
 126     movi a4, DPORT_APPCPU_CTRL_B_REG
 127     movi a3, DPORT_APPCPU_CLKGATE_EN
 128     s32i.n a3, a4, 0
 129     /* Set and clear APP_CPU reset */
 130     movi a4, DPORT_APPCPU_CTRL_A_REG
 131     movi a3, DPORT_APPCPU_RST_EN
 132     s32i.n a3, a4, 0
 133     s32i.n a5, a4, 0
 134     /* Restore the reset vector to ROM */
 135     movi a4, RTC_CNTL_RESET_STATE_REG
 136     movi a3, RTC_CNTL_RESET_STATE_DEF
 137     s32i.n a3, a4, 0
 138
 139
 140 parking_loop:
 141     /* PRO and APP CPU will be in this loop, until OpenOCD
 142      * finds the JTAG taps and puts the CPUs into debug mode.
 143      */
 144     waiti 0
 145     j parking_loop