contrib/loaders/reset/espressif/esp32s3/esp32s3_cpu_reset_handler.S

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 /***************************************************************************
   4  *   Reset stub used by esp32s3 target                                     *
   5  *   Copyright (C) 2020 Espressif Systems (Shanghai) Co. Ltd.              *
   6  ***************************************************************************/
   7
   8 #define RTC_CNTL_RESET_STATE_REG            0x60008038
   9 #define RTC_CNTL_RESET_STATE_DEF            0x3000
  10 #define RTC_CNTL_CLK_CONF_REG               0x60008074
  11 #define RTC_CNTL_CLK_CONF_DEF               0x1583218
  12 #define RTC_CNTL_STORE4_REG                 0x600080C0
  13 #define RTC_CNTL_STORE5_REG                 0x600080C4
  14 #define WDT_WKEY_VALUE                      0x50D83AA1
  15 #define TIMG0_WDTWPROTECT_REG               0x6001F064
  16 #define TIMG0_WDTCONFIG0_REG                0x6001F048
  17 #define TIMG1_WDTWPROTECT_REG               0x60020064
  18 #define TIMG1_WDTCONFIG0_REG                0x60020048
  19 #define RTC_CNTL_WDTCONFIG0_REG             0x60008094
  20 #define RTC_CNTL_WDTWPROTECT_REG            0x600080AC
  21 #define RTC_CNTL_OPTIONS0_REG               0x60008000
  22 #define RTC_CNTL_OPTIONS0_DEF               0x1C00A000
  23 #define RTC_CNTL_SW_SYS_RST                 0x80000000
  24 #define RTC_CNTL_DIG_PWC_REG                0x60008090
  25 #define RTC_CNTL_SWD_CONF_REG               0x600080B0
  26 #define RTC_CNTL_SWD_CONF_VAL               0x84B00000
  27 #define RTC_CNTL_SWD_WPROTECT_REG           0x600080B4
  28 #define RTC_CNTL_SWD_WKEY_VALUE             0x8F1D312A
  29 #define SYSTEM_CORE_1_CONTROL_0_REG         0x600C0000
  30 #define SYSTEM_CONTROL_CORE_1_RESETING      0x4
  31 #define SYSTEM_CONTROL_CORE_1_CLKGATE_EN    0x2
  32 #define SYSTEM_CORE_1_CONTROL_1_REG         0x600C0004
  33
  34
  35 /* This stub is copied to RTC_SLOW_MEM by OpenOCD, and the CPU starts executing
  36  * it instead of the ROM code (0x40000400). This stub disables watchdogs and
  37  * goes into a loop.
  38  * OpenOCD will then halt the target and perform CPU reset using OCD.
  39  */
  40
  41
  42 /* Has to be at offset 0. This is the entry point of the CPU, once
  43  * RTC_CNTL_PROCPU_STAT_VECTOR_SEL is cleared.
  44  * CPU will come here after the system reset, triggered by RTC_CNTL_SW_SYS_RST.
  45  */
  46     .global     cpu_at_start_handler
  47     .type       cpu_at_start_handler,@function
  48     .align      4
  49 cpu_at_start_handler:
  50     j start
  51
  52
  53 /* Has to be at offset 4. Once the stub code has been uploaded into RTC Slow
  54  * memory, OpenOCD will set the PC to this address, and resume execution.
  55  * The stub will then jump to 'reset' label and perform the reset.
  56  */
  57     .global     cpu_reset_handler
  58     .type       cpu_reset_handler,@function
  59     .align      4
  60 cpu_reset_handler:
  61     j reset
  62
  63     .align 4
  64     .literal_position
  65
  66     .align 4
  67 reset:
  68     /* Use a5 as a zero register */
  69     xor a5, a5, a5
  70     /* Select static reset vector 0 (XCHAL_RESET_VECTOR0_VADDR, 0x50000000) */
  71     movi a4, RTC_CNTL_RESET_STATE_REG
  72     s32i a5, a4, 0
  73     /* Set some clock-related RTC registers to the default values */
  74     movi a4, RTC_CNTL_STORE4_REG
  75     s32i a5, a4, 0
  76     movi a4, RTC_CNTL_STORE5_REG
  77     s32i a5, a4, 0
  78     movi a4, RTC_CNTL_DIG_PWC_REG
  79     s32i a5, a4, 0
  80     movi a4, RTC_CNTL_CLK_CONF_REG
  81     movi a3, RTC_CNTL_CLK_CONF_DEF
  82     s32i a3, a4, 0
  83     /* Reset the digital part of the chip (RTC controller doesn't get reset) */
  84     movi a3, (RTC_CNTL_OPTIONS0_DEF | RTC_CNTL_SW_SYS_RST)
  85     movi a4, RTC_CNTL_OPTIONS0_REG
  86     s32i a3, a4, 0
  87     /* Doesn't reach beyond this instruction */
  88
  89     .align 4
  90 start:
  91     /* If running on the APP CPU, skip directly to the parking loop */
  92     rsr.prid a6
  93     extui a6, a6, 1, 1
  94     bnez a6, parking_loop
  95
  96     /* Use a5 as a zero register */
  97     xor a5, a5, a5
  98     /* Disable the watchdogs */
  99     movi a3, WDT_WKEY_VALUE
 100     movi a4, RTC_CNTL_WDTWPROTECT_REG
 101     s32i.n a3, a4, 0
 102     movi a4, TIMG0_WDTWPROTECT_REG
 103     s32i.n a3, a4, 0
 104     movi a4, TIMG1_WDTWPROTECT_REG
 105     s32i.n a3, a4, 0
 106     movi a4, RTC_CNTL_WDTCONFIG0_REG
 107     s32i.n a5, a4, 0
 108     movi a4, TIMG0_WDTCONFIG0_REG
 109     s32i.n a5, a4, 0
 110     movi a4, TIMG1_WDTCONFIG0_REG
 111     s32i.n a5, a4, 0
 112     movi a4, RTC_CNTL_SWD_WPROTECT_REG
 113     movi a3, RTC_CNTL_SWD_WKEY_VALUE
 114     s32i.n a3, a4, 0
 115     movi a4, RTC_CNTL_SWD_CONF_REG
 116     movi a3, RTC_CNTL_SWD_CONF_VAL
 117     s32i.n a3, a4, 0
 118     /* Clear APP_CPU boot address */
 119     movi a4, SYSTEM_CORE_1_CONTROL_1_REG
 120     s32i.n a5, a4, 0
 121     /* Clear APP_CPU clock gating */
 122     movi a4, SYSTEM_CORE_1_CONTROL_0_REG
 123     movi a3, SYSTEM_CONTROL_CORE_1_CLKGATE_EN
 124     s32i.n a3, a4, 0
 125     /* Set and clear APP_CPU reset */
 126     movi a4, SYSTEM_CORE_1_CONTROL_0_REG
 127     movi a3, SYSTEM_CONTROL_CORE_1_RESETING
 128     s32i.n a3, a4, 0
 129     s32i.n a5, a4, 0
 130     /* Restore the reset vector to ROM */
 131     movi a4, RTC_CNTL_RESET_STATE_REG
 132     movi a3, RTC_CNTL_RESET_STATE_DEF
 133     s32i.n a3, a4, 0
 134
 135
 136 parking_loop:
 137     /* PRO and APP CPU will be in this loop, until OpenOCD
 138      * finds the JTAG taps and puts the CPUs into debug mode.
 139      */
 140     waiti 0
 141     j parking_loop