doc/manual/primer/jtag.txt

   1 /** @page primerjtag OpenOCD JTAG Primer
   2
   3 JTAG is unnecessarily confusing, because JTAG is often confused with
   4 boundary scan, which is just one of its possible functions.
   5
   6 JTAG is simply a communication interface designed to allow communication
   7 to functions contained on devices, for the designed purposes of
   8 initialisation, programming, testing, debugging, and anything else you
   9 want to use it for (as a chip designer).
  10
  11 Think of JTAG as I2C for testing.  It doesn't define what it can do,
  12 just a logical interface that allows a uniform channel for communication.
  13
  14 See:
  15
  16         http://en.wikipedia.org/wiki/Joint_Test_Action_Group
  17
  18 and
  19
  20         http://www.inaccessnetworks.com/projects/ianjtag/jtag-intro/jtag-state-machine-large.png
  21
  22 The first page (among other things) shows a logical representation
  23 describing how multiple devices are wired up using JTAG.  JTAG does not
  24 specify, data rates or interface levels (3.3V/1.8V, etc) each device can
  25 support different data rates/interface logic levels.  How to wire them
  26 in a compatible way is an exercise for an engineer.
  27
  28 Basically TMS controls which shift register is placed on the device,
  29 between TDI and TDO.  The second diagram shows the state transitions on
  30 TMS which will select different shift registers.
  31
  32 The first thing you need to do is reset the state machine, because when
  33 you connect to a chip you do not know what state the controller is in,you need
  34 to clock TMS as 1, at least 7 times.  This will put you into "Test Logic
  35 Reset" State.  Knowing this, you can, once reset, then track what each
  36 transition on TMS will do, and hence know what state the JTAG state
  37 machine is in.
  38
  39 There are 2 "types" of shift registers.  The Instruction shift register
  40 and the data shift register.  The sizes of these are undefined, and can
  41 change from chip to chip.  The Instruction register is used to select
  42 which Data register/data register function is used, and the data
  43 register is used to read data from that function or write data to it.
  44
  45 Each of the states control what happens to either the data register or
  46 instruction register.
  47
  48 For example, one of the data registers will be known as "bypass" this is
  49 (usually) a single bit which has no function and is used to bypass the
  50 chip.  Assume we have 3 identical chips, wired up like the picture
  51 and each has a 3 bit instruction register, and there are 2 known
  52 instructions (110 = bypass, 010 = some other function) if we want to use
  53 "some other function", on the second chip in the line, and not change
  54 the other chips we would do the following transitions.
  55
  56 From Test Logic Reset, TMS goes:
  57
  58   0 1 1 0 0
  59
  60 which puts every chip in the chain into the "Shift IR state"
  61 Then (while holding TMS as 0) TDI goes:
  62
  63   0 1 1  0 1 0  0 1 1
  64
  65 which puts the following values in the instruction shift register for
  66 each chip [110] [010] [110]
  67
  68 The order is reversed, because we shift out the least significant bit
  69 first.  Then we transition TMS:
  70
  71   1 1 1 1 0 0
  72
  73 which puts us in the "Shift DR state".
  74
  75 Now when we clock data onto TDI (again while holding TMS to 0) , the
  76 data shifts through the data registers, and because of the instruction
  77 registers we selected (some other function has 8 bits in its data
  78 register), our total data register in the chain looks like this:
  79
  80   0 00000000 0
  81
  82 The first and last bit are in the "bypassed" chips, so values read from
  83 them are irrelevant and data written to them is ignored.  But we need to
  84 write bits for those registers, because they are in the chain.
  85
  86 If we wanted to write 0xF5 to the data register we would clock out of
  87 TDI (holding TMS to 0):
  88
  89   0 1 0 1 0 1 1 1 1 0
  90
  91 Again, we are clocking the least-significant bit first.  Then we would
  92 clock TMS:
  93
  94   1 1 0
  95
  96 which updates the selected data register with the value 0xF5 and returns
  97 us to run test idle.
  98
  99 If we needed to read the data register before over-writing it with F5,
 100 no sweat, that's already done, because the TDI/TDO are set up as a
 101 circular shift register, so if you write enough bits to fill the shift
 102 register, you will receive the "captured" contents of the data registers
 103 simultaneously on TDO.
 104
 105 That's JTAG in a nutshell.  On top of this, you need to get specs for
 106 target chips and work out what the various instruction registers/data
 107 registers do, so you can actually do something useful.  That's where it
 108 gets interesting.  But in and of itself, JTAG is actually very simple.
 109
 110  */