XCF (Xilinx platfrom flash) support.
[openocd.git] / doc / openocd.texi
1 \input texinfo @c -*-texinfo-*-
2 @c %**start of header
3 @setfilename openocd.info
4 @settitle OpenOCD User's Guide
5 @dircategory Development
6 @direntry
7 * OpenOCD: (openocd). OpenOCD User's Guide
8 @end direntry
9 @paragraphindent 0
10 @c %**end of header
12 @include version.texi
14 @copying
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
21 @itemize @bullet
22 @item Copyright @copyright{} 2008 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk}
24 @item Copyright @copyright{} 2008-2010 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
26 @item Copyright @copyright{} 2009-2010 David Brownell
27 @end itemize
29 @quotation
30 Permission is granted to copy, distribute and/or modify this document
31 under the terms of the GNU Free Documentation License, Version 1.2 or
32 any later version published by the Free Software Foundation; with no
33 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
34 Texts. A copy of the license is included in the section entitled ``GNU
35 Free Documentation License''.
36 @end quotation
37 @end copying
39 @titlepage
40 @titlefont{@emph{Open On-Chip Debugger:}}
41 @sp 1
42 @title OpenOCD User's Guide
43 @subtitle for release @value{VERSION}
44 @subtitle @value{UPDATED}
46 @page
47 @vskip 0pt plus 1filll
48 @insertcopying
49 @end titlepage
51 @summarycontents
52 @contents
54 @ifnottex
55 @node Top
56 @top OpenOCD User's Guide
58 @insertcopying
59 @end ifnottex
61 @menu
62 * About:: About OpenOCD
63 * Developers:: OpenOCD Developer Resources
64 * Debug Adapter Hardware:: Debug Adapter Hardware
65 * About Jim-Tcl:: About Jim-Tcl
66 * Running:: Running OpenOCD
67 * OpenOCD Project Setup:: OpenOCD Project Setup
68 * Config File Guidelines:: Config File Guidelines
69 * Server Configuration:: Server Configuration
70 * Debug Adapter Configuration:: Debug Adapter Configuration
71 * Reset Configuration:: Reset Configuration
72 * TAP Declaration:: TAP Declaration
73 * CPU Configuration:: CPU Configuration
74 * Flash Commands:: Flash Commands
75 * Flash Programming:: Flash Programming
76 * PLD/FPGA Commands:: PLD/FPGA Commands
77 * General Commands:: General Commands
78 * Architecture and Core Commands:: Architecture and Core Commands
79 * JTAG Commands:: JTAG Commands
80 * Boundary Scan Commands:: Boundary Scan Commands
81 * Utility Commands:: Utility Commands
82 * TFTP:: TFTP
83 * GDB and OpenOCD:: Using GDB and OpenOCD
84 * Tcl Scripting API:: Tcl Scripting API
85 * FAQ:: Frequently Asked Questions
86 * Tcl Crash Course:: Tcl Crash Course
87 * License:: GNU Free Documentation License
89 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
90 @comment case issue with ``Index.html'' and ``index.html''
91 @comment Occurs when creating ``--html --no-split'' output
92 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
93 * OpenOCD Concept Index:: Concept Index
94 * Command and Driver Index:: Command and Driver Index
95 @end menu
97 @node About
98 @unnumbered About
99 @cindex about
101 OpenOCD was created by Dominic Rath as part of a 2005 diploma thesis written
102 at the University of Applied Sciences Augsburg (@uref{http://www.hs-augsburg.de}).
103 Since that time, the project has grown into an active open-source project,
104 supported by a diverse community of software and hardware developers from
105 around the world.
107 @section What is OpenOCD?
108 @cindex TAP
109 @cindex JTAG
111 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
112 in-system programming and boundary-scan testing for embedded target
113 devices.
115 It does so with the assistance of a @dfn{debug adapter}, which is
116 a small hardware module which helps provide the right kind of
117 electrical signaling to the target being debugged. These are
118 required since the debug host (on which OpenOCD runs) won't
119 usually have native support for such signaling, or the connector
120 needed to hook up to the target.
122 Such debug adapters support one or more @dfn{transport} protocols,
123 each of which involves different electrical signaling (and uses
124 different messaging protocols on top of that signaling). There
125 are many types of debug adapter, and little uniformity in what
126 they are called. (There are also product naming differences.)
128 These adapters are sometimes packaged as discrete dongles, which
129 may generically be called @dfn{hardware interface dongles}.
130 Some development boards also integrate them directly, which may
131 let the development board connect directly to the debug
132 host over USB (and sometimes also to power it over USB).
134 For example, a @dfn{JTAG Adapter} supports JTAG
135 signaling, and is used to communicate
136 with JTAG (IEEE 1149.1) compliant TAPs on your target board.
137 A @dfn{TAP} is a ``Test Access Port'', a module which processes
138 special instructions and data. TAPs are daisy-chained within and
139 between chips and boards. JTAG supports debugging and boundary
140 scan operations.
142 There are also @dfn{SWD Adapters} that support Serial Wire Debug (SWD)
143 signaling to communicate with some newer ARM cores, as well as debug
144 adapters which support both JTAG and SWD transports. SWD supports only
145 debugging, whereas JTAG also supports boundary scan operations.
147 For some chips, there are also @dfn{Programming Adapters} supporting
148 special transports used only to write code to flash memory, without
149 support for on-chip debugging or boundary scan.
150 (At this writing, OpenOCD does not support such non-debug adapters.)
153 @b{Dongles:} OpenOCD currently supports many types of hardware dongles:
154 USB-based, parallel port-based, and other standalone boxes that run
155 OpenOCD internally. @xref{Debug Adapter Hardware}.
157 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
158 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x), Cortex-M3
159 (Stellaris LM3, ST STM32 and Energy Micro EFM32) and Intel Quark (x10xx)
160 based cores to be debugged via the GDB protocol.
162 @b{Flash Programming:} Flash writing is supported for external
163 CFI-compatible NOR flashes (Intel and AMD/Spansion command set) and several
164 internal flashes (LPC1700, LPC1800, LPC2000, LPC4300, AT91SAM7, AT91SAM3U,
165 STR7x, STR9x, LM3, STM32x and EFM32). Preliminary support for various NAND flash
166 controllers (LPC3180, Orion, S3C24xx, more) is included.
168 @section OpenOCD Web Site
170 The OpenOCD web site provides the latest public news from the community:
172 @uref{http://openocd.org/}
174 @section Latest User's Guide:
176 The user's guide you are now reading may not be the latest one
177 available. A version for more recent code may be available.
178 Its HTML form is published regularly at:
180 @uref{http://openocd.org/doc/html/index.html}
182 PDF form is likewise published at:
184 @uref{http://openocd.org/doc/pdf/openocd.pdf}
186 @section OpenOCD User's Forum
188 There is an OpenOCD forum (phpBB) hosted by SparkFun,
189 which might be helpful to you. Note that if you want
190 anything to come to the attention of developers, you
191 should post it to the OpenOCD Developer Mailing List
192 instead of this forum.
194 @uref{http://forum.sparkfun.com/viewforum.php?f=18}
196 @section OpenOCD User's Mailing List
198 The OpenOCD User Mailing List provides the primary means of
199 communication between users:
201 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-user}
203 @section OpenOCD IRC
205 Support can also be found on irc:
206 @uref{irc://irc.freenode.net/openocd}
208 @node Developers
209 @chapter OpenOCD Developer Resources
210 @cindex developers
212 If you are interested in improving the state of OpenOCD's debugging and
213 testing support, new contributions will be welcome. Motivated developers
214 can produce new target, flash or interface drivers, improve the
215 documentation, as well as more conventional bug fixes and enhancements.
217 The resources in this chapter are available for developers wishing to explore
218 or expand the OpenOCD source code.
220 @section OpenOCD Git Repository
222 During the 0.3.x release cycle, OpenOCD switched from Subversion to
223 a Git repository hosted at SourceForge. The repository URL is:
225 @uref{git://git.code.sf.net/p/openocd/code}
227 or via http
229 @uref{http://git.code.sf.net/p/openocd/code}
231 You may prefer to use a mirror and the HTTP protocol:
233 @uref{http://repo.or.cz/r/openocd.git}
235 With standard Git tools, use @command{git clone} to initialize
236 a local repository, and @command{git pull} to update it.
237 There are also gitweb pages letting you browse the repository
238 with a web browser, or download arbitrary snapshots without
239 needing a Git client:
241 @uref{http://repo.or.cz/w/openocd.git}
243 The @file{README} file contains the instructions for building the project
244 from the repository or a snapshot.
246 Developers that want to contribute patches to the OpenOCD system are
247 @b{strongly} encouraged to work against mainline.
248 Patches created against older versions may require additional
249 work from their submitter in order to be updated for newer releases.
251 @section Doxygen Developer Manual
253 During the 0.2.x release cycle, the OpenOCD project began
254 providing a Doxygen reference manual. This document contains more
255 technical information about the software internals, development
256 processes, and similar documentation:
258 @uref{http://openocd.org/doc/doxygen/html/index.html}
260 This document is a work-in-progress, but contributions would be welcome
261 to fill in the gaps. All of the source files are provided in-tree,
262 listed in the Doxyfile configuration at the top of the source tree.
264 @section Gerrit Review System
266 All changes in the OpenOCD Git repository go through the web-based Gerrit
267 Code Review System:
269 @uref{http://openocd.zylin.com/}
271 After a one-time registration and repository setup, anyone can push commits
272 from their local Git repository directly into Gerrit.
273 All users and developers are encouraged to review, test, discuss and vote
274 for changes in Gerrit. The feedback provides the basis for a maintainer to
275 eventually submit the change to the main Git repository.
277 The @file{HACKING} file, also available as the Patch Guide in the Doxygen
278 Developer Manual, contains basic information about how to connect a
279 repository to Gerrit, prepare and push patches. Patch authors are expected to
280 maintain their changes while they're in Gerrit, respond to feedback and if
281 necessary rework and push improved versions of the change.
283 @section OpenOCD Developer Mailing List
285 The OpenOCD Developer Mailing List provides the primary means of
286 communication between developers:
288 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-devel}
290 @section OpenOCD Bug Tracker
292 The OpenOCD Bug Tracker is hosted on SourceForge:
294 @uref{http://bugs.openocd.org/}
297 @node Debug Adapter Hardware
298 @chapter Debug Adapter Hardware
299 @cindex dongles
300 @cindex FTDI
301 @cindex wiggler
302 @cindex zy1000
303 @cindex printer port
304 @cindex USB Adapter
305 @cindex RTCK
307 Defined: @b{dongle}: A small device that plugs into a computer and serves as
308 an adapter .... [snip]
310 In the OpenOCD case, this generally refers to @b{a small adapter} that
311 attaches to your computer via USB or the parallel port. One
312 exception is the Ultimate Solutions ZY1000, packaged as a small box you
313 attach via an ethernet cable. The ZY1000 has the advantage that it does not
314 require any drivers to be installed on the developer PC. It also has
315 a built in web interface. It supports RTCK/RCLK or adaptive clocking
316 and has a built-in relay to power cycle targets remotely.
319 @section Choosing a Dongle
321 There are several things you should keep in mind when choosing a dongle.
323 @enumerate
324 @item @b{Transport} Does it support the kind of communication that you need?
325 OpenOCD focusses mostly on JTAG. Your version may also support
326 other ways to communicate with target devices.
327 @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
328 Does your dongle support it? You might need a level converter.
329 @item @b{Pinout} What pinout does your target board use?
330 Does your dongle support it? You may be able to use jumper
331 wires, or an "octopus" connector, to convert pinouts.
332 @item @b{Connection} Does your computer have the USB, parallel, or
333 Ethernet port needed?
334 @item @b{RTCK} Do you expect to use it with ARM chips and boards with
335 RTCK support (also known as ``adaptive clocking'')?
336 @end enumerate
338 @section Stand-alone JTAG Probe
340 The ZY1000 from Ultimate Solutions is technically not a dongle but a
341 stand-alone JTAG probe that, unlike most dongles, doesn't require any drivers
342 running on the developer's host computer.
343 Once installed on a network using DHCP or a static IP assignment, users can
344 access the ZY1000 probe locally or remotely from any host with access to the
345 IP address assigned to the probe.
346 The ZY1000 provides an intuitive web interface with direct access to the
347 OpenOCD debugger.
348 Users may also run a GDBSERVER directly on the ZY1000 to take full advantage
349 of GCC & GDB to debug any distribution of embedded Linux or NetBSD running on
350 the target.
351 The ZY1000 supports RTCK & RCLK or adaptive clocking and has a built-in relay
352 to power cycle the target remotely.
354 For more information, visit:
356 @b{ZY1000} See: @url{http://www.ultsol.com/index.php/component/content/article/8/210-zylin-zy1000-main}
358 @section USB FT2232 Based
360 There are many USB JTAG dongles on the market, many of them based
361 on a chip from ``Future Technology Devices International'' (FTDI)
362 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
363 See: @url{http://www.ftdichip.com} for more information.
364 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
365 chips started to become available in JTAG adapters. Around 2012, a new
366 variant appeared - FT232H - this is a single-channel version of FT2232H.
367 (Adapters using those high speed FT2232H or FT232H chips may support adaptive
368 clocking.)
370 The FT2232 chips are flexible enough to support some other
371 transport options, such as SWD or the SPI variants used to
372 program some chips. They have two communications channels,
373 and one can be used for a UART adapter at the same time the
374 other one is used to provide a debug adapter.
376 Also, some development boards integrate an FT2232 chip to serve as
377 a built-in low-cost debug adapter and USB-to-serial solution.
379 @itemize @bullet
380 @item @b{usbjtag}
381 @* Link @url{http://elk.informatik.fh-augsburg.de/hhweb/doc/openocd/usbjtag/usbjtag.html}
382 @item @b{jtagkey}
383 @* See: @url{http://www.amontec.com/jtagkey.shtml}
384 @item @b{jtagkey2}
385 @* See: @url{http://www.amontec.com/jtagkey2.shtml}
386 @item @b{oocdlink}
387 @* See: @url{http://www.oocdlink.com} By Joern Kaipf
388 @item @b{signalyzer}
389 @* See: @url{http://www.signalyzer.com}
390 @item @b{Stellaris Eval Boards}
391 @* See: @url{http://www.ti.com} - The Stellaris eval boards
392 bundle FT2232-based JTAG and SWD support, which can be used to debug
393 the Stellaris chips. Using separate JTAG adapters is optional.
394 These boards can also be used in a "pass through" mode as JTAG adapters
395 to other target boards, disabling the Stellaris chip.
396 @item @b{TI/Luminary ICDI}
397 @* See: @url{http://www.ti.com} - TI/Luminary In-Circuit Debug
398 Interface (ICDI) Boards are included in Stellaris LM3S9B9x
399 Evaluation Kits. Like the non-detachable FT2232 support on the other
400 Stellaris eval boards, they can be used to debug other target boards.
401 @item @b{olimex-jtag}
402 @* See: @url{http://www.olimex.com}
403 @item @b{Flyswatter/Flyswatter2}
404 @* See: @url{http://www.tincantools.com}
405 @item @b{turtelizer2}
406 @* See:
407 @uref{http://www.ethernut.de/en/hardware/turtelizer/index.html, Turtelizer 2}, or
408 @url{http://www.ethernut.de}
409 @item @b{comstick}
410 @* Link: @url{http://www.hitex.com/index.php?id=383}
411 @item @b{stm32stick}
412 @* Link @url{http://www.hitex.com/stm32-stick}
413 @item @b{axm0432_jtag}
414 @* Axiom AXM-0432 Link @url{http://www.axman.com} - NOTE: This JTAG does not appear
415 to be available anymore as of April 2012.
416 @item @b{cortino}
417 @* Link @url{http://www.hitex.com/index.php?id=cortino}
418 @item @b{dlp-usb1232h}
419 @* Link @url{http://www.dlpdesign.com/usb/usb1232h.shtml}
420 @item @b{digilent-hs1}
421 @* Link @url{http://www.digilentinc.com/Products/Detail.cfm?Prod=JTAG-HS1}
422 @item @b{opendous}
423 @* Link @url{http://code.google.com/p/opendous/wiki/JTAG} FT2232H-based
424 (OpenHardware).
425 @item @b{JTAG-lock-pick Tiny 2}
426 @* Link @url{http://www.distortec.com/jtag-lock-pick-tiny-2} FT232H-based
428 @item @b{GW16042}
429 @* Link: @url{http://shop.gateworks.com/index.php?route=product/product&path=70_80&product_id=64}
430 FT2232H-based
432 @end itemize
433 @section USB-JTAG / Altera USB-Blaster compatibles
435 These devices also show up as FTDI devices, but are not
436 protocol-compatible with the FT2232 devices. They are, however,
437 protocol-compatible among themselves. USB-JTAG devices typically consist
438 of a FT245 followed by a CPLD that understands a particular protocol,
439 or emulates this protocol using some other hardware.
441 They may appear under different USB VID/PID depending on the particular
442 product. The driver can be configured to search for any VID/PID pair
443 (see the section on driver commands).
445 @itemize
446 @item @b{USB-JTAG} Kolja Waschk's USB Blaster-compatible adapter
447 @* Link: @url{http://ixo-jtag.sourceforge.net/}
448 @item @b{Altera USB-Blaster}
449 @* Link: @url{http://www.altera.com/literature/ug/ug_usb_blstr.pdf}
450 @end itemize
452 @section USB J-Link based
453 There are several OEM versions of the SEGGER @b{J-Link} adapter. It is
454 an example of a microcontroller based JTAG adapter, it uses an
455 AT91SAM764 internally.
457 @itemize @bullet
458 @item @b{SEGGER J-Link}
459 @* Link: @url{http://www.segger.com/jlink.html}
460 @item @b{Atmel SAM-ICE} (Only works with Atmel chips!)
461 @* Link: @url{http://www.atmel.com/tools/atmelsam-ice.aspx}
462 @item @b{IAR J-Link}
463 @end itemize
465 @section USB RLINK based
466 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer,
467 permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for
468 SWD and not JTAG, thus not supported.
470 @itemize @bullet
471 @item @b{Raisonance RLink}
472 @* Link: @url{http://www.mcu-raisonance.com/~rlink-debugger-programmer__@/microcontrollers__tool~tool__T018:4cn9ziz4bnx6.html}
473 @item @b{STM32 Primer}
474 @* Link: @url{http://www.stm32circle.com/resources/stm32primer.php}
475 @item @b{STM32 Primer2}
476 @* Link: @url{http://www.stm32circle.com/resources/stm32primer2.php}
477 @end itemize
479 @section USB ST-LINK based
480 ST Micro has an adapter called @b{ST-LINK}.
481 They only work with ST Micro chips, notably STM32 and STM8.
483 @itemize @bullet
484 @item @b{ST-LINK}
485 @* This is available standalone and as part of some kits, eg. STM32VLDISCOVERY.
486 @* Link: @url{http://www.st.com/internet/evalboard/product/219866.jsp}
487 @item @b{ST-LINK/V2}
488 @* This is available standalone and as part of some kits, eg. STM32F4DISCOVERY.
489 @* Link: @url{http://www.st.com/internet/evalboard/product/251168.jsp}
490 @end itemize
492 For info the original ST-LINK enumerates using the mass storage usb class; however,
493 its implementation is completely broken. The result is this causes issues under Linux.
494 The simplest solution is to get Linux to ignore the ST-LINK using one of the following methods:
495 @itemize @bullet
496 @item modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i
497 @item add "options usb-storage quirks=483:3744:i" to /etc/modprobe.conf
498 @end itemize
500 @section USB TI/Stellaris ICDI based
501 Texas Instruments has an adapter called @b{ICDI}.
502 It is not to be confused with the FTDI based adapters that were originally fitted to their
503 evaluation boards. This is the adapter fitted to the Stellaris LaunchPad.
505 @section USB CMSIS-DAP based
506 ARM has released a interface standard called CMSIS-DAP that simplifies connecting
507 debuggers to ARM Cortex based targets @url{http://www.keil.com/support/man/docs/dapdebug/dapdebug_introduction.htm}.
509 @section USB Other
510 @itemize @bullet
511 @item @b{USBprog}
512 @* Link: @url{http://shop.embedded-projects.net/} - which uses an Atmel MEGA32 and a UBN9604
514 @item @b{USB - Presto}
515 @* Link: @url{http://tools.asix.net/prg_presto.htm}
517 @item @b{Versaloon-Link}
518 @* Link: @url{http://www.versaloon.com}
520 @item @b{ARM-JTAG-EW}
521 @* Link: @url{http://www.olimex.com/dev/arm-jtag-ew.html}
523 @item @b{Buspirate}
524 @* Link: @url{http://dangerousprototypes.com/bus-pirate-manual/}
526 @item @b{opendous}
527 @* Link: @url{http://code.google.com/p/opendous-jtag/} - which uses an AT90USB162
529 @item @b{estick}
530 @* Link: @url{http://code.google.com/p/estick-jtag/}
532 @item @b{Keil ULINK v1}
533 @* Link: @url{http://www.keil.com/ulink1/}
534 @end itemize
536 @section IBM PC Parallel Printer Port Based
538 The two well-known ``JTAG Parallel Ports'' cables are the Xilinx DLC5
539 and the Macraigor Wiggler. There are many clones and variations of
540 these on the market.
542 Note that parallel ports are becoming much less common, so if you
543 have the choice you should probably avoid these adapters in favor
544 of USB-based ones.
546 @itemize @bullet
548 @item @b{Wiggler} - There are many clones of this.
549 @* Link: @url{http://www.macraigor.com/wiggler.htm}
551 @item @b{DLC5} - From XILINX - There are many clones of this
552 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
553 produced, PDF schematics are easily found and it is easy to make.
555 @item @b{Amontec - JTAG Accelerator}
556 @* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
558 @item @b{Wiggler2}
559 @* Link: @url{http://www.ccac.rwth-aachen.de/~michaels/index.php/hardware/armjtag}
561 @item @b{Wiggler_ntrst_inverted}
562 @* Yet another variation - See the source code, src/jtag/parport.c
564 @item @b{old_amt_wiggler}
565 @* Unknown - probably not on the market today
567 @item @b{arm-jtag}
568 @* Link: Most likely @url{http://www.olimex.com/dev/arm-jtag.html} [another wiggler clone]
570 @item @b{chameleon}
571 @* Link: @url{http://www.amontec.com/chameleon.shtml}
573 @item @b{Triton}
574 @* Unknown.
576 @item @b{Lattice}
577 @* ispDownload from Lattice Semiconductor
578 @url{http://www.latticesemi.com/lit/docs/@/devtools/dlcable.pdf}
580 @item @b{flashlink}
581 @* From ST Microsystems;
582 @* Link: @url{http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/DATA_BRIEF/DM00039500.pdf}
584 @end itemize
586 @section Other...
587 @itemize @bullet
589 @item @b{ep93xx}
590 @* An EP93xx based Linux machine using the GPIO pins directly.
592 @item @b{at91rm9200}
593 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
595 @item @b{bcm2835gpio}
596 @* A BCM2835-based board (e.g. Raspberry Pi) using the GPIO pins of the expansion header.
598 @item @b{imx_gpio}
599 @* A NXP i.MX-based board (e.g. Wandboard) using the GPIO pins (should work on any i.MX processor).
601 @item @b{jtag_vpi}
602 @* A JTAG driver acting as a client for the JTAG VPI server interface.
603 @* Link: @url{http://github.com/fjullien/jtag_vpi}
605 @end itemize
607 @node About Jim-Tcl
608 @chapter About Jim-Tcl
609 @cindex Jim-Tcl
610 @cindex tcl
612 OpenOCD uses a small ``Tcl Interpreter'' known as Jim-Tcl.
613 This programming language provides a simple and extensible
614 command interpreter.
616 All commands presented in this Guide are extensions to Jim-Tcl.
617 You can use them as simple commands, without needing to learn
618 much of anything about Tcl.
619 Alternatively, you can write Tcl programs with them.
621 You can learn more about Jim at its website, @url{http://jim.tcl.tk}.
622 There is an active and responsive community, get on the mailing list
623 if you have any questions. Jim-Tcl maintainers also lurk on the
624 OpenOCD mailing list.
626 @itemize @bullet
627 @item @b{Jim vs. Tcl}
628 @* Jim-Tcl is a stripped down version of the well known Tcl language,
629 which can be found here: @url{http://www.tcl.tk}. Jim-Tcl has far
630 fewer features. Jim-Tcl is several dozens of .C files and .H files and
631 implements the basic Tcl command set. In contrast: Tcl 8.6 is a
632 4.2 MB .zip file containing 1540 files.
634 @item @b{Missing Features}
635 @* Our practice has been: Add/clone the real Tcl feature if/when
636 needed. We welcome Jim-Tcl improvements, not bloat. Also there
637 are a large number of optional Jim-Tcl features that are not
638 enabled in OpenOCD.
640 @item @b{Scripts}
641 @* OpenOCD configuration scripts are Jim-Tcl Scripts. OpenOCD's
642 command interpreter today is a mixture of (newer)
643 Jim-Tcl commands, and the (older) original command interpreter.
645 @item @b{Commands}
646 @* At the OpenOCD telnet command line (or via the GDB monitor command) one
647 can type a Tcl for() loop, set variables, etc.
648 Some of the commands documented in this guide are implemented
649 as Tcl scripts, from a @file{startup.tcl} file internal to the server.
651 @item @b{Historical Note}
652 @* Jim-Tcl was introduced to OpenOCD in spring 2008. Fall 2010,
653 before OpenOCD 0.5 release, OpenOCD switched to using Jim-Tcl
654 as a Git submodule, which greatly simplified upgrading Jim-Tcl
655 to benefit from new features and bugfixes in Jim-Tcl.
657 @item @b{Need a crash course in Tcl?}
658 @*@xref{Tcl Crash Course}.
659 @end itemize
661 @node Running
662 @chapter Running
663 @cindex command line options
664 @cindex logfile
665 @cindex directory search
667 Properly installing OpenOCD sets up your operating system to grant it access
668 to the debug adapters. On Linux, this usually involves installing a file
669 in @file{/etc/udev/rules.d,} so OpenOCD has permissions. An example rules file
670 that works for many common adapters is shipped with OpenOCD in the
671 @file{contrib} directory. MS-Windows needs
672 complex and confusing driver configuration for every peripheral. Such issues
673 are unique to each operating system, and are not detailed in this User's Guide.
675 Then later you will invoke the OpenOCD server, with various options to
676 tell it how each debug session should work.
677 The @option{--help} option shows:
678 @verbatim
679 bash$ openocd --help
681 --help | -h display this help
682 --version | -v display OpenOCD version
683 --file | -f use configuration file <name>
684 --search | -s dir to search for config files and scripts
685 --debug | -d set debug level to 3
686 | -d<n> set debug level to <level>
687 --log_output | -l redirect log output to file <name>
688 --command | -c run <command>
689 @end verbatim
691 If you don't give any @option{-f} or @option{-c} options,
692 OpenOCD tries to read the configuration file @file{openocd.cfg}.
693 To specify one or more different
694 configuration files, use @option{-f} options. For example:
696 @example
697 openocd -f config1.cfg -f config2.cfg -f config3.cfg
698 @end example
700 Configuration files and scripts are searched for in
701 @enumerate
702 @item the current directory,
703 @item any search dir specified on the command line using the @option{-s} option,
704 @item any search dir specified using the @command{add_script_search_dir} command,
705 @item @file{$HOME/.openocd} (not on Windows),
706 @item a directory in the @env{OPENOCD_SCRIPTS} environment variable (if set),
707 @item the site wide script library @file{$pkgdatadir/site} and
708 @item the OpenOCD-supplied script library @file{$pkgdatadir/scripts}.
709 @end enumerate
710 The first found file with a matching file name will be used.
712 @quotation Note
713 Don't try to use configuration script names or paths which
714 include the "#" character. That character begins Tcl comments.
715 @end quotation
717 @section Simple setup, no customization
719 In the best case, you can use two scripts from one of the script
720 libraries, hook up your JTAG adapter, and start the server ... and
721 your JTAG setup will just work "out of the box". Always try to
722 start by reusing those scripts, but assume you'll need more
723 customization even if this works. @xref{OpenOCD Project Setup}.
725 If you find a script for your JTAG adapter, and for your board or
726 target, you may be able to hook up your JTAG adapter then start
727 the server with some variation of one of the following:
729 @example
730 openocd -f interface/ADAPTER.cfg -f board/MYBOARD.cfg
731 openocd -f interface/ftdi/ADAPTER.cfg -f board/MYBOARD.cfg
732 @end example
734 You might also need to configure which reset signals are present,
735 using @option{-c 'reset_config trst_and_srst'} or something similar.
736 If all goes well you'll see output something like
738 @example
739 Open On-Chip Debugger 0.4.0 (2010-01-14-15:06)
740 For bug reports, read
741 http://openocd.org/doc/doxygen/bugs.html
742 Info : JTAG tap: lm3s.cpu tap/device found: 0x3ba00477
743 (mfg: 0x23b, part: 0xba00, ver: 0x3)
744 @end example
746 Seeing that "tap/device found" message, and no warnings, means
747 the JTAG communication is working. That's a key milestone, but
748 you'll probably need more project-specific setup.
750 @section What OpenOCD does as it starts
752 OpenOCD starts by processing the configuration commands provided
753 on the command line or, if there were no @option{-c command} or
754 @option{-f file.cfg} options given, in @file{openocd.cfg}.
755 @xref{configurationstage,,Configuration Stage}.
756 At the end of the configuration stage it verifies the JTAG scan
757 chain defined using those commands; your configuration should
758 ensure that this always succeeds.
759 Normally, OpenOCD then starts running as a server.
760 Alternatively, commands may be used to terminate the configuration
761 stage early, perform work (such as updating some flash memory),
762 and then shut down without acting as a server.
764 Once OpenOCD starts running as a server, it waits for connections from
765 clients (Telnet, GDB, RPC) and processes the commands issued through
766 those channels.
768 If you are having problems, you can enable internal debug messages via
769 the @option{-d} option.
771 Also it is possible to interleave Jim-Tcl commands w/config scripts using the
772 @option{-c} command line switch.
774 To enable debug output (when reporting problems or working on OpenOCD
775 itself), use the @option{-d} command line switch. This sets the
776 @option{debug_level} to "3", outputting the most information,
777 including debug messages. The default setting is "2", outputting only
778 informational messages, warnings and errors. You can also change this
779 setting from within a telnet or gdb session using @command{debug_level<n>}
780 (@pxref{debuglevel,,debug_level}).
782 You can redirect all output from the server to a file using the
783 @option{-l <logfile>} switch.
785 Note! OpenOCD will launch the GDB & telnet server even if it can not
786 establish a connection with the target. In general, it is possible for
787 the JTAG controller to be unresponsive until the target is set up
788 correctly via e.g. GDB monitor commands in a GDB init script.
790 @node OpenOCD Project Setup
791 @chapter OpenOCD Project Setup
793 To use OpenOCD with your development projects, you need to do more than
794 just connect the JTAG adapter hardware (dongle) to your development board
795 and start the OpenOCD server.
796 You also need to configure your OpenOCD server so that it knows
797 about your adapter and board, and helps your work.
798 You may also want to connect OpenOCD to GDB, possibly
799 using Eclipse or some other GUI.
801 @section Hooking up the JTAG Adapter
803 Today's most common case is a dongle with a JTAG cable on one side
804 (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
805 and a USB cable on the other.
806 Instead of USB, some cables use Ethernet;
807 older ones may use a PC parallel port, or even a serial port.
809 @enumerate
810 @item @emph{Start with power to your target board turned off},
811 and nothing connected to your JTAG adapter.
812 If you're particularly paranoid, unplug power to the board.
813 It's important to have the ground signal properly set up,
814 unless you are using a JTAG adapter which provides
815 galvanic isolation between the target board and the
816 debugging host.
818 @item @emph{Be sure it's the right kind of JTAG connector.}
819 If your dongle has a 20-pin ARM connector, you need some kind
820 of adapter (or octopus, see below) to hook it up to
821 boards using 14-pin or 10-pin connectors ... or to 20-pin
822 connectors which don't use ARM's pinout.
824 In the same vein, make sure the voltage levels are compatible.
825 Not all JTAG adapters have the level shifters needed to work
826 with 1.2 Volt boards.
828 @item @emph{Be certain the cable is properly oriented} or you might
829 damage your board. In most cases there are only two possible
830 ways to connect the cable.
831 Connect the JTAG cable from your adapter to the board.
832 Be sure it's firmly connected.
834 In the best case, the connector is keyed to physically
835 prevent you from inserting it wrong.
836 This is most often done using a slot on the board's male connector
837 housing, which must match a key on the JTAG cable's female connector.
838 If there's no housing, then you must look carefully and
839 make sure pin 1 on the cable hooks up to pin 1 on the board.
840 Ribbon cables are frequently all grey except for a wire on one
841 edge, which is red. The red wire is pin 1.
843 Sometimes dongles provide cables where one end is an ``octopus'' of
844 color coded single-wire connectors, instead of a connector block.
845 These are great when converting from one JTAG pinout to another,
846 but are tedious to set up.
847 Use these with connector pinout diagrams to help you match up the
848 adapter signals to the right board pins.
850 @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
851 A USB, parallel, or serial port connector will go to the host which
852 you are using to run OpenOCD.
853 For Ethernet, consult the documentation and your network administrator.
855 For USB-based JTAG adapters you have an easy sanity check at this point:
856 does the host operating system see the JTAG adapter? If you're running
857 Linux, try the @command{lsusb} command. If that host is an
858 MS-Windows host, you'll need to install a driver before OpenOCD works.
860 @item @emph{Connect the adapter's power supply, if needed.}
861 This step is primarily for non-USB adapters,
862 but sometimes USB adapters need extra power.
864 @item @emph{Power up the target board.}
865 Unless you just let the magic smoke escape,
866 you're now ready to set up the OpenOCD server
867 so you can use JTAG to work with that board.
869 @end enumerate
871 Talk with the OpenOCD server using
872 telnet (@code{telnet localhost 4444} on many systems) or GDB.
873 @xref{GDB and OpenOCD}.
875 @section Project Directory
877 There are many ways you can configure OpenOCD and start it up.
879 A simple way to organize them all involves keeping a
880 single directory for your work with a given board.
881 When you start OpenOCD from that directory,
882 it searches there first for configuration files, scripts,
883 files accessed through semihosting,
884 and for code you upload to the target board.
885 It is also the natural place to write files,
886 such as log files and data you download from the board.
888 @section Configuration Basics
890 There are two basic ways of configuring OpenOCD, and
891 a variety of ways you can mix them.
892 Think of the difference as just being how you start the server:
894 @itemize
895 @item Many @option{-f file} or @option{-c command} options on the command line
896 @item No options, but a @dfn{user config file}
897 in the current directory named @file{openocd.cfg}
898 @end itemize
900 Here is an example @file{openocd.cfg} file for a setup
901 using a Signalyzer FT2232-based JTAG adapter to talk to
902 a board with an Atmel AT91SAM7X256 microcontroller:
904 @example
905 source [find interface/ftdi/signalyzer.cfg]
907 # GDB can also flash my flash!
908 gdb_memory_map enable
909 gdb_flash_program enable
911 source [find target/sam7x256.cfg]
912 @end example
914 Here is the command line equivalent of that configuration:
916 @example
917 openocd -f interface/ftdi/signalyzer.cfg \
918 -c "gdb_memory_map enable" \
919 -c "gdb_flash_program enable" \
920 -f target/sam7x256.cfg
921 @end example
923 You could wrap such long command lines in shell scripts,
924 each supporting a different development task.
925 One might re-flash the board with a specific firmware version.
926 Another might set up a particular debugging or run-time environment.
928 @quotation Important
929 At this writing (October 2009) the command line method has
930 problems with how it treats variables.
931 For example, after @option{-c "set VAR value"}, or doing the
932 same in a script, the variable @var{VAR} will have no value
933 that can be tested in a later script.
934 @end quotation
936 Here we will focus on the simpler solution: one user config
937 file, including basic configuration plus any TCL procedures
938 to simplify your work.
940 @section User Config Files
941 @cindex config file, user
942 @cindex user config file
943 @cindex config file, overview
945 A user configuration file ties together all the parts of a project
946 in one place.
947 One of the following will match your situation best:
949 @itemize
950 @item Ideally almost everything comes from configuration files
951 provided by someone else.
952 For example, OpenOCD distributes a @file{scripts} directory
953 (probably in @file{/usr/share/openocd/scripts} on Linux).
954 Board and tool vendors can provide these too, as can individual
955 user sites; the @option{-s} command line option lets you say
956 where to find these files. (@xref{Running}.)
957 The AT91SAM7X256 example above works this way.
959 Three main types of non-user configuration file each have their
960 own subdirectory in the @file{scripts} directory:
962 @enumerate
963 @item @b{interface} -- one for each different debug adapter;
964 @item @b{board} -- one for each different board
965 @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
966 @end enumerate
968 Best case: include just two files, and they handle everything else.
969 The first is an interface config file.
970 The second is board-specific, and it sets up the JTAG TAPs and
971 their GDB targets (by deferring to some @file{target.cfg} file),
972 declares all flash memory, and leaves you nothing to do except
973 meet your deadline:
975 @example
976 source [find interface/olimex-jtag-tiny.cfg]
977 source [find board/csb337.cfg]
978 @end example
980 Boards with a single microcontroller often won't need more
981 than the target config file, as in the AT91SAM7X256 example.
982 That's because there is no external memory (flash, DDR RAM), and
983 the board differences are encapsulated by application code.
985 @item Maybe you don't know yet what your board looks like to JTAG.
986 Once you know the @file{interface.cfg} file to use, you may
987 need help from OpenOCD to discover what's on the board.
988 Once you find the JTAG TAPs, you can just search for appropriate
989 target and board
990 configuration files ... or write your own, from the bottom up.
991 @xref{autoprobing,,Autoprobing}.
993 @item You can often reuse some standard config files but
994 need to write a few new ones, probably a @file{board.cfg} file.
995 You will be using commands described later in this User's Guide,
996 and working with the guidelines in the next chapter.
998 For example, there may be configuration files for your JTAG adapter
999 and target chip, but you need a new board-specific config file
1000 giving access to your particular flash chips.
1001 Or you might need to write another target chip configuration file
1002 for a new chip built around the Cortex-M3 core.
1004 @quotation Note
1005 When you write new configuration files, please submit
1006 them for inclusion in the next OpenOCD release.
1007 For example, a @file{board/newboard.cfg} file will help the
1008 next users of that board, and a @file{target/newcpu.cfg}
1009 will help support users of any board using that chip.
1010 @end quotation
1012 @item
1013 You may may need to write some C code.
1014 It may be as simple as supporting a new FT2232 or parport
1015 based adapter; a bit more involved, like a NAND or NOR flash
1016 controller driver; or a big piece of work like supporting
1017 a new chip architecture.
1018 @end itemize
1020 Reuse the existing config files when you can.
1021 Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
1022 You may find a board configuration that's a good example to follow.
1024 When you write config files, separate the reusable parts
1025 (things every user of that interface, chip, or board needs)
1026 from ones specific to your environment and debugging approach.
1027 @itemize
1029 @item
1030 For example, a @code{gdb-attach} event handler that invokes
1031 the @command{reset init} command will interfere with debugging
1032 early boot code, which performs some of the same actions
1033 that the @code{reset-init} event handler does.
1035 @item
1036 Likewise, the @command{arm9 vector_catch} command (or
1037 @cindex vector_catch
1038 its siblings @command{xscale vector_catch}
1039 and @command{cortex_m vector_catch}) can be a timesaver
1040 during some debug sessions, but don't make everyone use that either.
1041 Keep those kinds of debugging aids in your user config file,
1042 along with messaging and tracing setup.
1043 (@xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.)
1045 @item
1046 You might need to override some defaults.
1047 For example, you might need to move, shrink, or back up the target's
1048 work area if your application needs much SRAM.
1050 @item
1051 TCP/IP port configuration is another example of something which
1052 is environment-specific, and should only appear in
1053 a user config file. @xref{tcpipports,,TCP/IP Ports}.
1054 @end itemize
1056 @section Project-Specific Utilities
1058 A few project-specific utility
1059 routines may well speed up your work.
1060 Write them, and keep them in your project's user config file.
1062 For example, if you are making a boot loader work on a
1063 board, it's nice to be able to debug the ``after it's
1064 loaded to RAM'' parts separately from the finicky early
1065 code which sets up the DDR RAM controller and clocks.
1066 A script like this one, or a more GDB-aware sibling,
1067 may help:
1069 @example
1070 proc ramboot @{ @} @{
1071 # Reset, running the target's "reset-init" scripts
1072 # to initialize clocks and the DDR RAM controller.
1073 # Leave the CPU halted.
1074 reset init
1076 # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
1077 load_image u-boot.bin 0x20000000
1079 # Start running.
1080 resume 0x20000000
1081 @}
1082 @end example
1084 Then once that code is working you will need to make it
1085 boot from NOR flash; a different utility would help.
1086 Alternatively, some developers write to flash using GDB.
1087 (You might use a similar script if you're working with a flash
1088 based microcontroller application instead of a boot loader.)
1090 @example
1091 proc newboot @{ @} @{
1092 # Reset, leaving the CPU halted. The "reset-init" event
1093 # proc gives faster access to the CPU and to NOR flash;
1094 # "reset halt" would be slower.
1095 reset init
1097 # Write standard version of U-Boot into the first two
1098 # sectors of NOR flash ... the standard version should
1099 # do the same lowlevel init as "reset-init".
1100 flash protect 0 0 1 off
1101 flash erase_sector 0 0 1
1102 flash write_bank 0 u-boot.bin 0x0
1103 flash protect 0 0 1 on
1105 # Reboot from scratch using that new boot loader.
1106 reset run
1107 @}
1108 @end example
1110 You may need more complicated utility procedures when booting
1111 from NAND.
1112 That often involves an extra bootloader stage,
1113 running from on-chip SRAM to perform DDR RAM setup so it can load
1114 the main bootloader code (which won't fit into that SRAM).
1116 Other helper scripts might be used to write production system images,
1117 involving considerably more than just a three stage bootloader.
1119 @section Target Software Changes
1121 Sometimes you may want to make some small changes to the software
1122 you're developing, to help make JTAG debugging work better.
1123 For example, in C or assembly language code you might
1124 use @code{#ifdef JTAG_DEBUG} (or its converse) around code
1125 handling issues like:
1127 @itemize @bullet
1129 @item @b{Watchdog Timers}...
1130 Watchog timers are typically used to automatically reset systems if
1131 some application task doesn't periodically reset the timer. (The
1132 assumption is that the system has locked up if the task can't run.)
1133 When a JTAG debugger halts the system, that task won't be able to run
1134 and reset the timer ... potentially causing resets in the middle of
1135 your debug sessions.
1137 It's rarely a good idea to disable such watchdogs, since their usage
1138 needs to be debugged just like all other parts of your firmware.
1139 That might however be your only option.
1141 Look instead for chip-specific ways to stop the watchdog from counting
1142 while the system is in a debug halt state. It may be simplest to set
1143 that non-counting mode in your debugger startup scripts. You may however
1144 need a different approach when, for example, a motor could be physically
1145 damaged by firmware remaining inactive in a debug halt state. That might
1146 involve a type of firmware mode where that "non-counting" mode is disabled
1147 at the beginning then re-enabled at the end; a watchdog reset might fire
1148 and complicate the debug session, but hardware (or people) would be
1149 protected.@footnote{Note that many systems support a "monitor mode" debug
1150 that is a somewhat cleaner way to address such issues. You can think of
1151 it as only halting part of the system, maybe just one task,
1152 instead of the whole thing.
1153 At this writing, January 2010, OpenOCD based debugging does not support
1154 monitor mode debug, only "halt mode" debug.}
1156 @item @b{ARM Semihosting}...
1157 @cindex ARM semihosting
1158 When linked with a special runtime library provided with many
1159 toolchains@footnote{See chapter 8 "Semihosting" in
1160 @uref{http://infocenter.arm.com/help/topic/com.arm.doc.dui0203i/DUI0203I_rvct_developer_guide.pdf,
1161 ARM DUI 0203I}, the "RealView Compilation Tools Developer Guide".
1162 The CodeSourcery EABI toolchain also includes a semihosting library.},
1163 your target code can use I/O facilities on the debug host. That library
1164 provides a small set of system calls which are handled by OpenOCD.
1165 It can let the debugger provide your system console and a file system,
1166 helping with early debugging or providing a more capable environment
1167 for sometimes-complex tasks like installing system firmware onto
1168 NAND or SPI flash.
1170 @item @b{ARM Wait-For-Interrupt}...
1171 Many ARM chips synchronize the JTAG clock using the core clock.
1172 Low power states which stop that core clock thus prevent JTAG access.
1173 Idle loops in tasking environments often enter those low power states
1174 via the @code{WFI} instruction (or its coprocessor equivalent, before ARMv7).
1176 You may want to @emph{disable that instruction} in source code,
1177 or otherwise prevent using that state,
1178 to ensure you can get JTAG access at any time.@footnote{As a more
1179 polite alternative, some processors have special debug-oriented
1180 registers which can be used to change various features including
1181 how the low power states are clocked while debugging.
1182 The STM32 DBGMCU_CR register is an example; at the cost of extra
1183 power consumption, JTAG can be used during low power states.}
1184 For example, the OpenOCD @command{halt} command may not
1185 work for an idle processor otherwise.
1187 @item @b{Delay after reset}...
1188 Not all chips have good support for debugger access
1189 right after reset; many LPC2xxx chips have issues here.
1190 Similarly, applications that reconfigure pins used for
1191 JTAG access as they start will also block debugger access.
1193 To work with boards like this, @emph{enable a short delay loop}
1194 the first thing after reset, before "real" startup activities.
1195 For example, one second's delay is usually more than enough
1196 time for a JTAG debugger to attach, so that
1197 early code execution can be debugged
1198 or firmware can be replaced.
1200 @item @b{Debug Communications Channel (DCC)}...
1201 Some processors include mechanisms to send messages over JTAG.
1202 Many ARM cores support these, as do some cores from other vendors.
1203 (OpenOCD may be able to use this DCC internally, speeding up some
1204 operations like writing to memory.)
1206 Your application may want to deliver various debugging messages
1207 over JTAG, by @emph{linking with a small library of code}
1208 provided with OpenOCD and using the utilities there to send
1209 various kinds of message.
1210 @xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.
1212 @end itemize
1214 @section Target Hardware Setup
1216 Chip vendors often provide software development boards which
1217 are highly configurable, so that they can support all options
1218 that product boards may require. @emph{Make sure that any
1219 jumpers or switches match the system configuration you are
1220 working with.}
1222 Common issues include:
1224 @itemize @bullet
1226 @item @b{JTAG setup} ...
1227 Boards may support more than one JTAG configuration.
1228 Examples include jumpers controlling pullups versus pulldowns
1229 on the nTRST and/or nSRST signals, and choice of connectors
1230 (e.g. which of two headers on the base board,
1231 or one from a daughtercard).
1232 For some Texas Instruments boards, you may need to jumper the
1233 EMU0 and EMU1 signals (which OpenOCD won't currently control).
1235 @item @b{Boot Modes} ...
1236 Complex chips often support multiple boot modes, controlled
1237 by external jumpers. Make sure this is set up correctly.
1238 For example many i.MX boards from NXP need to be jumpered
1239 to "ATX mode" to start booting using the on-chip ROM, when
1240 using second stage bootloader code stored in a NAND flash chip.
1242 Such explicit configuration is common, and not limited to
1243 booting from NAND. You might also need to set jumpers to
1244 start booting using code loaded from an MMC/SD card; external
1245 SPI flash; Ethernet, UART, or USB links; NOR flash; OneNAND
1246 flash; some external host; or various other sources.
1249 @item @b{Memory Addressing} ...
1250 Boards which support multiple boot modes may also have jumpers
1251 to configure memory addressing. One board, for example, jumpers
1252 external chipselect 0 (used for booting) to address either
1253 a large SRAM (which must be pre-loaded via JTAG), NOR flash,
1254 or NAND flash. When it's jumpered to address NAND flash, that
1255 board must also be told to start booting from on-chip ROM.
1257 Your @file{board.cfg} file may also need to be told this jumper
1258 configuration, so that it can know whether to declare NOR flash
1259 using @command{flash bank} or instead declare NAND flash with
1260 @command{nand device}; and likewise which probe to perform in
1261 its @code{reset-init} handler.
1263 A closely related issue is bus width. Jumpers might need to
1264 distinguish between 8 bit or 16 bit bus access for the flash
1265 used to start booting.
1267 @item @b{Peripheral Access} ...
1268 Development boards generally provide access to every peripheral
1269 on the chip, sometimes in multiple modes (such as by providing
1270 multiple audio codec chips).
1271 This interacts with software
1272 configuration of pin multiplexing, where for example a
1273 given pin may be routed either to the MMC/SD controller
1274 or the GPIO controller. It also often interacts with
1275 configuration jumpers. One jumper may be used to route
1276 signals to an MMC/SD card slot or an expansion bus (which
1277 might in turn affect booting); others might control which
1278 audio or video codecs are used.
1280 @end itemize
1282 Plus you should of course have @code{reset-init} event handlers
1283 which set up the hardware to match that jumper configuration.
1284 That includes in particular any oscillator or PLL used to clock
1285 the CPU, and any memory controllers needed to access external
1286 memory and peripherals. Without such handlers, you won't be
1287 able to access those resources without working target firmware
1288 which can do that setup ... this can be awkward when you're
1289 trying to debug that target firmware. Even if there's a ROM
1290 bootloader which handles a few issues, it rarely provides full
1291 access to all board-specific capabilities.
1294 @node Config File Guidelines
1295 @chapter Config File Guidelines
1297 This chapter is aimed at any user who needs to write a config file,
1298 including developers and integrators of OpenOCD and any user who
1299 needs to get a new board working smoothly.
1300 It provides guidelines for creating those files.
1302 You should find the following directories under
1303 @t{$(INSTALLDIR)/scripts}, with config files maintained upstream. Use
1304 them as-is where you can; or as models for new files.
1305 @itemize @bullet
1306 @item @file{interface} ...
1307 These are for debug adapters. Files that specify configuration to use
1308 specific JTAG, SWD and other adapters go here.
1309 @item @file{board} ...
1310 Think Circuit Board, PWA, PCB, they go by many names. Board files
1311 contain initialization items that are specific to a board.
1313 They reuse target configuration files, since the same
1314 microprocessor chips are used on many boards,
1315 but support for external parts varies widely. For
1316 example, the SDRAM initialization sequence for the board, or the type
1317 of external flash and what address it uses. Any initialization
1318 sequence to enable that external flash or SDRAM should be found in the
1319 board file. Boards may also contain multiple targets: two CPUs; or
1320 a CPU and an FPGA.
1321 @item @file{target} ...
1322 Think chip. The ``target'' directory represents the JTAG TAPs
1323 on a chip
1324 which OpenOCD should control, not a board. Two common types of targets
1325 are ARM chips and FPGA or CPLD chips.
1326 When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
1327 the target config file defines all of them.
1328 @item @emph{more} ... browse for other library files which may be useful.
1329 For example, there are various generic and CPU-specific utilities.
1330 @end itemize
1332 The @file{openocd.cfg} user config
1333 file may override features in any of the above files by
1334 setting variables before sourcing the target file, or by adding
1335 commands specific to their situation.
1337 @section Interface Config Files
1339 The user config file
1340 should be able to source one of these files with a command like this:
1342 @example
1343 source [find interface/FOOBAR.cfg]
1344 @end example
1346 A preconfigured interface file should exist for every debug adapter
1347 in use today with OpenOCD.
1348 That said, perhaps some of these config files
1349 have only been used by the developer who created it.
1351 A separate chapter gives information about how to set these up.
1352 @xref{Debug Adapter Configuration}.
1353 Read the OpenOCD source code (and Developer's Guide)
1354 if you have a new kind of hardware interface
1355 and need to provide a driver for it.
1357 @section Board Config Files
1358 @cindex config file, board
1359 @cindex board config file
1361 The user config file
1362 should be able to source one of these files with a command like this:
1364 @example
1365 source [find board/FOOBAR.cfg]
1366 @end example
1368 The point of a board config file is to package everything
1369 about a given board that user config files need to know.
1370 In summary the board files should contain (if present)
1372 @enumerate
1373 @item One or more @command{source [find target/...cfg]} statements
1374 @item NOR flash configuration (@pxref{norconfiguration,,NOR Configuration})
1375 @item NAND flash configuration (@pxref{nandconfiguration,,NAND Configuration})
1376 @item Target @code{reset} handlers for SDRAM and I/O configuration
1377 @item JTAG adapter reset configuration (@pxref{Reset Configuration})
1378 @item All things that are not ``inside a chip''
1379 @end enumerate
1381 Generic things inside target chips belong in target config files,
1382 not board config files. So for example a @code{reset-init} event
1383 handler should know board-specific oscillator and PLL parameters,
1384 which it passes to target-specific utility code.
1386 The most complex task of a board config file is creating such a
1387 @code{reset-init} event handler.
1388 Define those handlers last, after you verify the rest of the board
1389 configuration works.
1391 @subsection Communication Between Config files
1393 In addition to target-specific utility code, another way that
1394 board and target config files communicate is by following a
1395 convention on how to use certain variables.
1397 The full Tcl/Tk language supports ``namespaces'', but Jim-Tcl does not.
1398 Thus the rule we follow in OpenOCD is this: Variables that begin with
1399 a leading underscore are temporary in nature, and can be modified and
1400 used at will within a target configuration file.
1402 Complex board config files can do the things like this,
1403 for a board with three chips:
1405 @example
1406 # Chip #1: PXA270 for network side, big endian
1407 set CHIPNAME network
1408 set ENDIAN big
1409 source [find target/pxa270.cfg]
1410 # on return: _TARGETNAME = network.cpu
1411 # other commands can refer to the "network.cpu" target.
1412 $_TARGETNAME configure .... events for this CPU..
1414 # Chip #2: PXA270 for video side, little endian
1415 set CHIPNAME video
1416 set ENDIAN little
1417 source [find target/pxa270.cfg]
1418 # on return: _TARGETNAME = video.cpu
1419 # other commands can refer to the "video.cpu" target.
1420 $_TARGETNAME configure .... events for this CPU..
1422 # Chip #3: Xilinx FPGA for glue logic
1423 set CHIPNAME xilinx
1424 unset ENDIAN
1425 source [find target/spartan3.cfg]
1426 @end example
1428 That example is oversimplified because it doesn't show any flash memory,
1429 or the @code{reset-init} event handlers to initialize external DRAM
1430 or (assuming it needs it) load a configuration into the FPGA.
1431 Such features are usually needed for low-level work with many boards,
1432 where ``low level'' implies that the board initialization software may
1433 not be working. (That's a common reason to need JTAG tools. Another
1434 is to enable working with microcontroller-based systems, which often
1435 have no debugging support except a JTAG connector.)
1437 Target config files may also export utility functions to board and user
1438 config files. Such functions should use name prefixes, to help avoid
1439 naming collisions.
1441 Board files could also accept input variables from user config files.
1442 For example, there might be a @code{J4_JUMPER} setting used to identify
1443 what kind of flash memory a development board is using, or how to set
1444 up other clocks and peripherals.
1446 @subsection Variable Naming Convention
1447 @cindex variable names
1449 Most boards have only one instance of a chip.
1450 However, it should be easy to create a board with more than
1451 one such chip (as shown above).
1452 Accordingly, we encourage these conventions for naming
1453 variables associated with different @file{target.cfg} files,
1454 to promote consistency and
1455 so that board files can override target defaults.
1457 Inputs to target config files include:
1459 @itemize @bullet
1460 @item @code{CHIPNAME} ...
1461 This gives a name to the overall chip, and is used as part of
1462 tap identifier dotted names.
1463 While the default is normally provided by the chip manufacturer,
1464 board files may need to distinguish between instances of a chip.
1465 @item @code{ENDIAN} ...
1466 By default @option{little} - although chips may hard-wire @option{big}.
1467 Chips that can't change endianness don't need to use this variable.
1468 @item @code{CPUTAPID} ...
1469 When OpenOCD examines the JTAG chain, it can be told verify the
1470 chips against the JTAG IDCODE register.
1471 The target file will hold one or more defaults, but sometimes the
1472 chip in a board will use a different ID (perhaps a newer revision).
1473 @end itemize
1475 Outputs from target config files include:
1477 @itemize @bullet
1478 @item @code{_TARGETNAME} ...
1479 By convention, this variable is created by the target configuration
1480 script. The board configuration file may make use of this variable to
1481 configure things like a ``reset init'' script, or other things
1482 specific to that board and that target.
1483 If the chip has 2 targets, the names are @code{_TARGETNAME0},
1484 @code{_TARGETNAME1}, ... etc.
1485 @end itemize
1487 @subsection The reset-init Event Handler
1488 @cindex event, reset-init
1489 @cindex reset-init handler
1491 Board config files run in the OpenOCD configuration stage;
1492 they can't use TAPs or targets, since they haven't been
1493 fully set up yet.
1494 This means you can't write memory or access chip registers;
1495 you can't even verify that a flash chip is present.
1496 That's done later in event handlers, of which the target @code{reset-init}
1497 handler is one of the most important.
1499 Except on microcontrollers, the basic job of @code{reset-init} event
1500 handlers is setting up flash and DRAM, as normally handled by boot loaders.
1501 Microcontrollers rarely use boot loaders; they run right out of their
1502 on-chip flash and SRAM memory. But they may want to use one of these
1503 handlers too, if just for developer convenience.
1505 @quotation Note
1506 Because this is so very board-specific, and chip-specific, no examples
1507 are included here.
1508 Instead, look at the board config files distributed with OpenOCD.
1509 If you have a boot loader, its source code will help; so will
1510 configuration files for other JTAG tools
1511 (@pxref{translatingconfigurationfiles,,Translating Configuration Files}).
1512 @end quotation
1514 Some of this code could probably be shared between different boards.
1515 For example, setting up a DRAM controller often doesn't differ by
1516 much except the bus width (16 bits or 32?) and memory timings, so a
1517 reusable TCL procedure loaded by the @file{target.cfg} file might take
1518 those as parameters.
1519 Similarly with oscillator, PLL, and clock setup;
1520 and disabling the watchdog.
1521 Structure the code cleanly, and provide comments to help
1522 the next developer doing such work.
1523 (@emph{You might be that next person} trying to reuse init code!)
1525 The last thing normally done in a @code{reset-init} handler is probing
1526 whatever flash memory was configured. For most chips that needs to be
1527 done while the associated target is halted, either because JTAG memory
1528 access uses the CPU or to prevent conflicting CPU access.
1530 @subsection JTAG Clock Rate
1532 Before your @code{reset-init} handler has set up
1533 the PLLs and clocking, you may need to run with
1534 a low JTAG clock rate.
1535 @xref{jtagspeed,,JTAG Speed}.
1536 Then you'd increase that rate after your handler has
1537 made it possible to use the faster JTAG clock.
1538 When the initial low speed is board-specific, for example
1539 because it depends on a board-specific oscillator speed, then
1540 you should probably set it up in the board config file;
1541 if it's target-specific, it belongs in the target config file.
1543 For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
1544 @uref{http://www.arm.com/support/faqdev/4170.html} gives details.}
1545 is one sixth of the CPU clock; or one eighth for ARM11 cores.
1546 Consult chip documentation to determine the peak JTAG clock rate,
1547 which might be less than that.
1549 @quotation Warning
1550 On most ARMs, JTAG clock detection is coupled to the core clock, so
1551 software using a @option{wait for interrupt} operation blocks JTAG access.
1552 Adaptive clocking provides a partial workaround, but a more complete
1553 solution just avoids using that instruction with JTAG debuggers.
1554 @end quotation
1556 If both the chip and the board support adaptive clocking,
1557 use the @command{jtag_rclk}
1558 command, in case your board is used with JTAG adapter which
1559 also supports it. Otherwise use @command{adapter_khz}.
1560 Set the slow rate at the beginning of the reset sequence,
1561 and the faster rate as soon as the clocks are at full speed.
1563 @anchor{theinitboardprocedure}
1564 @subsection The init_board procedure
1565 @cindex init_board procedure
1567 The concept of @code{init_board} procedure is very similar to @code{init_targets}
1568 (@xref{theinittargetsprocedure,,The init_targets procedure}.) - it's a replacement of ``linear''
1569 configuration scripts. This procedure is meant to be executed when OpenOCD enters run stage
1570 (@xref{enteringtherunstage,,Entering the Run Stage},) after @code{init_targets}. The idea to have
1571 separate @code{init_targets} and @code{init_board} procedures is to allow the first one to configure
1572 everything target specific (internal flash, internal RAM, etc.) and the second one to configure
1573 everything board specific (reset signals, chip frequency, reset-init event handler, external memory, etc.).
1574 Additionally ``linear'' board config file will most likely fail when target config file uses
1575 @code{init_targets} scheme (``linear'' script is executed before @code{init} and @code{init_targets} - after),
1576 so separating these two configuration stages is very convenient, as the easiest way to overcome this
1577 problem is to convert board config file to use @code{init_board} procedure. Board config scripts don't
1578 need to override @code{init_targets} defined in target config files when they only need to add some specifics.
1580 Just as @code{init_targets}, the @code{init_board} procedure can be overridden by ``next level'' script (which sources
1581 the original), allowing greater code reuse.
1583 @example
1584 ### board_file.cfg ###
1586 # source target file that does most of the config in init_targets
1587 source [find target/target.cfg]
1589 proc enable_fast_clock @{@} @{
1590 # enables fast on-board clock source
1591 # configures the chip to use it
1592 @}
1594 # initialize only board specifics - reset, clock, adapter frequency
1595 proc init_board @{@} @{
1596 reset_config trst_and_srst trst_pulls_srst
1598 $_TARGETNAME configure -event reset-init @{
1599 adapter_khz 1
1600 enable_fast_clock
1601 adapter_khz 10000
1602 @}
1603 @}
1604 @end example
1606 @section Target Config Files
1607 @cindex config file, target
1608 @cindex target config file
1610 Board config files communicate with target config files using
1611 naming conventions as described above, and may source one or
1612 more target config files like this:
1614 @example
1615 source [find target/FOOBAR.cfg]
1616 @end example
1618 The point of a target config file is to package everything
1619 about a given chip that board config files need to know.
1620 In summary the target files should contain
1622 @enumerate
1623 @item Set defaults
1624 @item Add TAPs to the scan chain
1625 @item Add CPU targets (includes GDB support)
1626 @item CPU/Chip/CPU-Core specific features
1627 @item On-Chip flash
1628 @end enumerate
1630 As a rule of thumb, a target file sets up only one chip.
1631 For a microcontroller, that will often include a single TAP,
1632 which is a CPU needing a GDB target, and its on-chip flash.
1634 More complex chips may include multiple TAPs, and the target
1635 config file may need to define them all before OpenOCD
1636 can talk to the chip.
1637 For example, some phone chips have JTAG scan chains that include
1638 an ARM core for operating system use, a DSP,
1639 another ARM core embedded in an image processing engine,
1640 and other processing engines.
1642 @subsection Default Value Boiler Plate Code
1644 All target configuration files should start with code like this,
1645 letting board config files express environment-specific
1646 differences in how things should be set up.
1648 @example
1649 # Boards may override chip names, perhaps based on role,
1650 # but the default should match what the vendor uses
1651 if @{ [info exists CHIPNAME] @} @{
1653 @} else @{
1654 set _CHIPNAME sam7x256
1655 @}
1657 # ONLY use ENDIAN with targets that can change it.
1658 if @{ [info exists ENDIAN] @} @{
1659 set _ENDIAN $ENDIAN
1660 @} else @{
1661 set _ENDIAN little
1662 @}
1664 # TAP identifiers may change as chips mature, for example with
1665 # new revision fields (the "3" here). Pick a good default; you
1666 # can pass several such identifiers to the "jtag newtap" command.
1667 if @{ [info exists CPUTAPID ] @} @{
1669 @} else @{
1670 set _CPUTAPID 0x3f0f0f0f
1671 @}
1672 @end example
1673 @c but 0x3f0f0f0f is for an str73x part ...
1675 @emph{Remember:} Board config files may include multiple target
1676 config files, or the same target file multiple times
1677 (changing at least @code{CHIPNAME}).
1679 Likewise, the target configuration file should define
1680 @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
1681 use it later on when defining debug targets:
1683 @example
1685 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1686 @end example
1688 @subsection Adding TAPs to the Scan Chain
1689 After the ``defaults'' are set up,
1690 add the TAPs on each chip to the JTAG scan chain.
1691 @xref{TAP Declaration}, and the naming convention
1692 for taps.
1694 In the simplest case the chip has only one TAP,
1695 probably for a CPU or FPGA.
1696 The config file for the Atmel AT91SAM7X256
1697 looks (in part) like this:
1699 @example
1700 jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
1701 @end example
1703 A board with two such at91sam7 chips would be able
1704 to source such a config file twice, with different
1705 values for @code{CHIPNAME}, so
1706 it adds a different TAP each time.
1708 If there are nonzero @option{-expected-id} values,
1709 OpenOCD attempts to verify the actual tap id against those values.
1710 It will issue error messages if there is mismatch, which
1711 can help to pinpoint problems in OpenOCD configurations.
1713 @example
1714 JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
1715 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
1716 ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
1717 ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
1718 ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
1719 @end example
1721 There are more complex examples too, with chips that have
1722 multiple TAPs. Ones worth looking at include:
1724 @itemize
1725 @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
1726 plus a JRC to enable them
1727 @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
1728 @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
1729 is not currently used)
1730 @end itemize
1732 @subsection Add CPU targets
1734 After adding a TAP for a CPU, you should set it up so that
1735 GDB and other commands can use it.
1736 @xref{CPU Configuration}.
1737 For the at91sam7 example above, the command can look like this;
1738 note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
1739 to little endian, and this chip doesn't support changing that.
1741 @example
1743 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1744 @end example
1746 Work areas are small RAM areas associated with CPU targets.
1747 They are used by OpenOCD to speed up downloads,
1748 and to download small snippets of code to program flash chips.
1749 If the chip includes a form of ``on-chip-ram'' - and many do - define
1750 a work area if you can.
1751 Again using the at91sam7 as an example, this can look like:
1753 @example
1754 $_TARGETNAME configure -work-area-phys 0x00200000 \
1755 -work-area-size 0x4000 -work-area-backup 0
1756 @end example
1758 @anchor{definecputargetsworkinginsmp}
1759 @subsection Define CPU targets working in SMP
1760 @cindex SMP
1761 After setting targets, you can define a list of targets working in SMP.
1763 @example
1764 set _TARGETNAME_1 $_CHIPNAME.cpu1
1765 set _TARGETNAME_2 $_CHIPNAME.cpu2
1766 target create $_TARGETNAME_1 cortex_a -chain-position $_CHIPNAME.dap \
1767 -coreid 0 -dbgbase $_DAP_DBG1
1768 target create $_TARGETNAME_2 cortex_a -chain-position $_CHIPNAME.dap \
1769 -coreid 1 -dbgbase $_DAP_DBG2
1770 #define 2 targets working in smp.
1771 target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
1772 @end example
1773 In the above example on cortex_a, 2 cpus are working in SMP.
1774 In SMP only one GDB instance is created and :
1775 @itemize @bullet
1776 @item a set of hardware breakpoint sets the same breakpoint on all targets in the list.
1777 @item halt command triggers the halt of all targets in the list.
1778 @item resume command triggers the write context and the restart of all targets in the list.
1779 @item following a breakpoint: the target stopped by the breakpoint is displayed to the GDB session.
1780 @item dedicated GDB serial protocol packets are implemented for switching/retrieving the target
1781 displayed by the GDB session @pxref{usingopenocdsmpwithgdb,,Using OpenOCD SMP with GDB}.
1782 @end itemize
1784 The SMP behaviour can be disabled/enabled dynamically. On cortex_a following
1785 command have been implemented.
1786 @itemize @bullet
1787 @item cortex_a smp_on : enable SMP mode, behaviour is as described above.
1788 @item cortex_a smp_off : disable SMP mode, the current target is the one
1789 displayed in the GDB session, only this target is now controlled by GDB
1790 session. This behaviour is useful during system boot up.
1791 @item cortex_a smp_gdb : display/fix the core id displayed in GDB session see
1792 following example.
1793 @end itemize
1795 @example
1796 >cortex_a smp_gdb
1797 gdb coreid 0 -> -1
1798 #0 : coreid 0 is displayed to GDB ,
1799 #-> -1 : next resume triggers a real resume
1800 > cortex_a smp_gdb 1
1801 gdb coreid 0 -> 1
1802 #0 :coreid 0 is displayed to GDB ,
1803 #->1 : next resume displays coreid 1 to GDB
1804 > resume
1805 > cortex_a smp_gdb
1806 gdb coreid 1 -> 1
1807 #1 :coreid 1 is displayed to GDB ,
1808 #->1 : next resume displays coreid 1 to GDB
1809 > cortex_a smp_gdb -1
1810 gdb coreid 1 -> -1
1811 #1 :coreid 1 is displayed to GDB,
1812 #->-1 : next resume triggers a real resume
1813 @end example
1816 @subsection Chip Reset Setup
1818 As a rule, you should put the @command{reset_config} command
1819 into the board file. Most things you think you know about a
1820 chip can be tweaked by the board.
1822 Some chips have specific ways the TRST and SRST signals are
1823 managed. In the unusual case that these are @emph{chip specific}
1824 and can never be changed by board wiring, they could go here.
1825 For example, some chips can't support JTAG debugging without
1826 both signals.
1828 Provide a @code{reset-assert} event handler if you can.
1829 Such a handler uses JTAG operations to reset the target,
1830 letting this target config be used in systems which don't
1831 provide the optional SRST signal, or on systems where you
1832 don't want to reset all targets at once.
1833 Such a handler might write to chip registers to force a reset,
1834 use a JRC to do that (preferable -- the target may be wedged!),
1835 or force a watchdog timer to trigger.
1836 (For Cortex-M targets, this is not necessary. The target
1837 driver knows how to use trigger an NVIC reset when SRST is
1838 not available.)
1840 Some chips need special attention during reset handling if
1841 they're going to be used with JTAG.
1842 An example might be needing to send some commands right
1843 after the target's TAP has been reset, providing a
1844 @code{reset-deassert-post} event handler that writes a chip
1845 register to report that JTAG debugging is being done.
1846 Another would be reconfiguring the watchdog so that it stops
1847 counting while the core is halted in the debugger.
1849 JTAG clocking constraints often change during reset, and in
1850 some cases target config files (rather than board config files)
1851 are the right places to handle some of those issues.
1852 For example, immediately after reset most chips run using a
1853 slower clock than they will use later.
1854 That means that after reset (and potentially, as OpenOCD
1855 first starts up) they must use a slower JTAG clock rate
1856 than they will use later.
1857 @xref{jtagspeed,,JTAG Speed}.
1859 @quotation Important
1860 When you are debugging code that runs right after chip
1861 reset, getting these issues right is critical.
1862 In particular, if you see intermittent failures when
1863 OpenOCD verifies the scan chain after reset,
1864 look at how you are setting up JTAG clocking.
1865 @end quotation
1867 @anchor{theinittargetsprocedure}
1868 @subsection The init_targets procedure
1869 @cindex init_targets procedure
1871 Target config files can either be ``linear'' (script executed line-by-line when parsed in
1872 configuration stage, @xref{configurationstage,,Configuration Stage},) or they can contain a special
1873 procedure called @code{init_targets}, which will be executed when entering run stage
1874 (after parsing all config files or after @code{init} command, @xref{enteringtherunstage,,Entering the Run Stage}.)
1875 Such procedure can be overriden by ``next level'' script (which sources the original).
1876 This concept faciliates code reuse when basic target config files provide generic configuration
1877 procedures and @code{init_targets} procedure, which can then be sourced and enchanced or changed in
1878 a ``more specific'' target config file. This is not possible with ``linear'' config scripts,
1879 because sourcing them executes every initialization commands they provide.
1881 @example
1882 ### generic_file.cfg ###
1884 proc setup_my_chip @{chip_name flash_size ram_size@} @{
1885 # basic initialization procedure ...
1886 @}
1888 proc init_targets @{@} @{
1889 # initializes generic chip with 4kB of flash and 1kB of RAM
1890 setup_my_chip MY_GENERIC_CHIP 4096 1024
1891 @}
1893 ### specific_file.cfg ###
1895 source [find target/generic_file.cfg]
1897 proc init_targets @{@} @{
1898 # initializes specific chip with 128kB of flash and 64kB of RAM
1899 setup_my_chip MY_CHIP_WITH_128K_FLASH_64KB_RAM 131072 65536
1900 @}
1901 @end example
1903 The easiest way to convert ``linear'' config files to @code{init_targets} version is to
1904 enclose every line of ``code'' (i.e. not @code{source} commands, procedures, etc.) in this procedure.
1906 For an example of this scheme see LPC2000 target config files.
1908 The @code{init_boards} procedure is a similar concept concerning board config files
1909 (@xref{theinitboardprocedure,,The init_board procedure}.)
1911 @anchor{theinittargeteventsprocedure}
1912 @subsection The init_target_events procedure
1913 @cindex init_target_events procedure
1915 A special procedure called @code{init_target_events} is run just after
1916 @code{init_targets} (@xref{theinittargetsprocedure,,The init_targets
1917 procedure}.) and before @code{init_board}
1918 (@xref{theinitboardprocedure,,The init_board procedure}.) It is used
1919 to set up default target events for the targets that do not have those
1920 events already assigned.
1922 @subsection ARM Core Specific Hacks
1924 If the chip has a DCC, enable it. If the chip is an ARM9 with some
1925 special high speed download features - enable it.
1927 If present, the MMU, the MPU and the CACHE should be disabled.
1929 Some ARM cores are equipped with trace support, which permits
1930 examination of the instruction and data bus activity. Trace
1931 activity is controlled through an ``Embedded Trace Module'' (ETM)
1932 on one of the core's scan chains. The ETM emits voluminous data
1933 through a ``trace port''. (@xref{armhardwaretracing,,ARM Hardware Tracing}.)
1934 If you are using an external trace port,
1935 configure it in your board config file.
1936 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
1937 configure it in your target config file.
1939 @example
1940 etm config $_TARGETNAME 16 normal full etb
1941 etb config $_TARGETNAME $_CHIPNAME.etb
1942 @end example
1944 @subsection Internal Flash Configuration
1946 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
1948 @b{Never ever} in the ``target configuration file'' define any type of
1949 flash that is external to the chip. (For example a BOOT flash on
1950 Chip Select 0.) Such flash information goes in a board file - not
1951 the TARGET (chip) file.
1953 Examples:
1954 @itemize @bullet
1955 @item at91sam7x256 - has 256K flash YES enable it.
1956 @item str912 - has flash internal YES enable it.
1957 @item imx27 - uses boot flash on CS0 - it goes in the board file.
1958 @item pxa270 - again - CS0 flash - it goes in the board file.
1959 @end itemize
1961 @anchor{translatingconfigurationfiles}
1962 @section Translating Configuration Files
1963 @cindex translation
1964 If you have a configuration file for another hardware debugger
1965 or toolset (Abatron, BDI2000, BDI3000, CCS,
1966 Lauterbach, SEGGER, Macraigor, etc.), translating
1967 it into OpenOCD syntax is often quite straightforward. The most tricky
1968 part of creating a configuration script is oftentimes the reset init
1969 sequence where e.g. PLLs, DRAM and the like is set up.
1971 One trick that you can use when translating is to write small
1972 Tcl procedures to translate the syntax into OpenOCD syntax. This
1973 can avoid manual translation errors and make it easier to
1974 convert other scripts later on.
1976 Example of transforming quirky arguments to a simple search and
1977 replace job:
1979 @example
1980 # Lauterbach syntax(?)
1981 #
1982 # Data.Set c15:0x042f %long 0x40000015
1983 #
1984 # OpenOCD syntax when using procedure below.
1985 #
1986 # setc15 0x01 0x00050078
1988 proc setc15 @{regs value@} @{
1989 global TARGETNAME
1991 echo [format "set p15 0x%04x, 0x%08x" $regs $value]
1993 arm mcr 15 [expr ($regs>>12)&0x7] \
1994 [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] \
1995 [expr ($regs>>8)&0x7] $value
1996 @}
1997 @end example
2001 @node Server Configuration
2002 @chapter Server Configuration
2003 @cindex initialization
2004 The commands here are commonly found in the openocd.cfg file and are
2005 used to specify what TCP/IP ports are used, and how GDB should be
2006 supported.
2008 @anchor{configurationstage}
2009 @section Configuration Stage
2010 @cindex configuration stage
2011 @cindex config command
2013 When the OpenOCD server process starts up, it enters a
2014 @emph{configuration stage} which is the only time that
2015 certain commands, @emph{configuration commands}, may be issued.
2016 Normally, configuration commands are only available
2017 inside startup scripts.
2019 In this manual, the definition of a configuration command is
2020 presented as a @emph{Config Command}, not as a @emph{Command}
2021 which may be issued interactively.
2022 The runtime @command{help} command also highlights configuration
2023 commands, and those which may be issued at any time.
2025 Those configuration commands include declaration of TAPs,
2026 flash banks,
2027 the interface used for JTAG communication,
2028 and other basic setup.
2029 The server must leave the configuration stage before it
2030 may access or activate TAPs.
2031 After it leaves this stage, configuration commands may no
2032 longer be issued.
2034 @anchor{enteringtherunstage}
2035 @section Entering the Run Stage
2037 The first thing OpenOCD does after leaving the configuration
2038 stage is to verify that it can talk to the scan chain
2039 (list of TAPs) which has been configured.
2040 It will warn if it doesn't find TAPs it expects to find,
2041 or finds TAPs that aren't supposed to be there.
2042 You should see no errors at this point.
2043 If you see errors, resolve them by correcting the
2044 commands you used to configure the server.
2045 Common errors include using an initial JTAG speed that's too
2046 fast, and not providing the right IDCODE values for the TAPs
2047 on the scan chain.
2049 Once OpenOCD has entered the run stage, a number of commands
2050 become available.
2051 A number of these relate to the debug targets you may have declared.
2052 For example, the @command{mww} command will not be available until
2053 a target has been successfuly instantiated.
2054 If you want to use those commands, you may need to force
2055 entry to the run stage.
2057 @deffn {Config Command} init
2058 This command terminates the configuration stage and
2059 enters the run stage. This helps when you need to have
2060 the startup scripts manage tasks such as resetting the target,
2061 programming flash, etc. To reset the CPU upon startup, add "init" and
2062 "reset" at the end of the config script or at the end of the OpenOCD
2063 command line using the @option{-c} command line switch.
2065 If this command does not appear in any startup/configuration file
2066 OpenOCD executes the command for you after processing all
2067 configuration files and/or command line options.
2069 @b{NOTE:} This command normally occurs at or near the end of your
2070 openocd.cfg file to force OpenOCD to ``initialize'' and make the
2071 targets ready. For example: If your openocd.cfg file needs to
2072 read/write memory on your target, @command{init} must occur before
2073 the memory read/write commands. This includes @command{nand probe}.
2074 @end deffn
2076 @deffn {Overridable Procedure} jtag_init
2077 This is invoked at server startup to verify that it can talk
2078 to the scan chain (list of TAPs) which has been configured.
2080 The default implementation first tries @command{jtag arp_init},
2081 which uses only a lightweight JTAG reset before examining the
2082 scan chain.
2083 If that fails, it tries again, using a harder reset
2084 from the overridable procedure @command{init_reset}.
2086 Implementations must have verified the JTAG scan chain before
2087 they return.
2088 This is done by calling @command{jtag arp_init}
2089 (or @command{jtag arp_init-reset}).
2090 @end deffn
2092 @anchor{tcpipports}
2093 @section TCP/IP Ports
2094 @cindex TCP port
2095 @cindex server
2096 @cindex port
2097 @cindex security
2098 The OpenOCD server accepts remote commands in several syntaxes.
2099 Each syntax uses a different TCP/IP port, which you may specify
2100 only during configuration (before those ports are opened).
2102 For reasons including security, you may wish to prevent remote
2103 access using one or more of these ports.
2104 In such cases, just specify the relevant port number as "disabled".
2105 If you disable all access through TCP/IP, you will need to
2106 use the command line @option{-pipe} option.
2108 @deffn {Command} gdb_port [number]
2109 @cindex GDB server
2110 Normally gdb listens to a TCP/IP port, but GDB can also
2111 communicate via pipes(stdin/out or named pipes). The name
2112 "gdb_port" stuck because it covers probably more than 90% of
2113 the normal use cases.
2115 No arguments reports GDB port. "pipe" means listen to stdin
2116 output to stdout, an integer is base port number, "disabled"
2117 disables the gdb server.
2119 When using "pipe", also use log_output to redirect the log
2120 output to a file so as not to flood the stdin/out pipes.
2122 The -p/--pipe option is deprecated and a warning is printed
2123 as it is equivalent to passing in -c "gdb_port pipe; log_output openocd.log".
2125 Any other string is interpreted as named pipe to listen to.
2126 Output pipe is the same name as input pipe, but with 'o' appended,
2127 e.g. /var/gdb, /var/gdbo.
2129 The GDB port for the first target will be the base port, the
2130 second target will listen on gdb_port + 1, and so on.
2131 When not specified during the configuration stage,
2132 the port @var{number} defaults to 3333.
2134 Note: when using "gdb_port pipe", increasing the default remote timeout in
2135 gdb (with 'set remotetimeout') is recommended. An insufficient timeout may
2136 cause initialization to fail with "Unknown remote qXfer reply: OK".
2138 @end deffn
2140 @deffn {Command} tcl_port [number]
2141 Specify or query the port used for a simplified RPC
2142 connection that can be used by clients to issue TCL commands and get the
2143 output from the Tcl engine.
2144 Intended as a machine interface.
2145 When not specified during the configuration stage,
2146 the port @var{number} defaults to 6666.
2147 When specified as "disabled", this service is not activated.
2148 @end deffn
2150 @deffn {Command} telnet_port [number]
2151 Specify or query the
2152 port on which to listen for incoming telnet connections.
2153 This port is intended for interaction with one human through TCL commands.
2154 When not specified during the configuration stage,
2155 the port @var{number} defaults to 4444.
2156 When specified as "disabled", this service is not activated.
2157 @end deffn
2159 @anchor{gdbconfiguration}
2160 @section GDB Configuration
2161 @cindex GDB
2162 @cindex GDB configuration
2163 You can reconfigure some GDB behaviors if needed.
2164 The ones listed here are static and global.
2165 @xref{targetconfiguration,,Target Configuration}, about configuring individual targets.
2166 @xref{targetevents,,Target Events}, about configuring target-specific event handling.
2168 @anchor{gdbbreakpointoverride}
2169 @deffn {Command} gdb_breakpoint_override [@option{hard}|@option{soft}|@option{disable}]
2170 Force breakpoint type for gdb @command{break} commands.
2171 This option supports GDB GUIs which don't
2172 distinguish hard versus soft breakpoints, if the default OpenOCD and
2173 GDB behaviour is not sufficient. GDB normally uses hardware
2174 breakpoints if the memory map has been set up for flash regions.
2175 @end deffn
2177 @anchor{gdbflashprogram}
2178 @deffn {Config Command} gdb_flash_program (@option{enable}|@option{disable})
2179 Set to @option{enable} to cause OpenOCD to program the flash memory when a
2180 vFlash packet is received.
2181 The default behaviour is @option{enable}.
2182 @end deffn
2184 @deffn {Config Command} gdb_memory_map (@option{enable}|@option{disable})
2185 Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
2186 requested. GDB will then know when to set hardware breakpoints, and program flash
2187 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
2188 for flash programming to work.
2189 Default behaviour is @option{enable}.
2190 @xref{gdbflashprogram,,gdb_flash_program}.
2191 @end deffn
2193 @deffn {Config Command} gdb_report_data_abort (@option{enable}|@option{disable})
2194 Specifies whether data aborts cause an error to be reported
2195 by GDB memory read packets.
2196 The default behaviour is @option{disable};
2197 use @option{enable} see these errors reported.
2198 @end deffn
2200 @deffn {Config Command} gdb_target_description (@option{enable}|@option{disable})
2201 Set to @option{enable} to cause OpenOCD to send the target descriptions to gdb via qXfer:features:read packet.
2202 The default behaviour is @option{enable}.
2203 @end deffn
2205 @deffn {Command} gdb_save_tdesc
2206 Saves the target descripton file to the local file system.
2208 The file name is @i{target_name}.xml.
2209 @end deffn
2211 @anchor{eventpolling}
2212 @section Event Polling
2214 Hardware debuggers are parts of asynchronous systems,
2215 where significant events can happen at any time.
2216 The OpenOCD server needs to detect some of these events,
2217 so it can report them to through TCL command line
2218 or to GDB.
2220 Examples of such events include:
2222 @itemize
2223 @item One of the targets can stop running ... maybe it triggers
2224 a code breakpoint or data watchpoint, or halts itself.
2225 @item Messages may be sent over ``debug message'' channels ... many
2226 targets support such messages sent over JTAG,
2227 for receipt by the person debugging or tools.
2228 @item Loss of power ... some adapters can detect these events.
2229 @item Resets not issued through JTAG ... such reset sources
2230 can include button presses or other system hardware, sometimes
2231 including the target itself (perhaps through a watchdog).
2232 @item Debug instrumentation sometimes supports event triggering
2233 such as ``trace buffer full'' (so it can quickly be emptied)
2234 or other signals (to correlate with code behavior).
2235 @end itemize
2237 None of those events are signaled through standard JTAG signals.
2238 However, most conventions for JTAG connectors include voltage
2239 level and system reset (SRST) signal detection.
2240 Some connectors also include instrumentation signals, which
2241 can imply events when those signals are inputs.
2243 In general, OpenOCD needs to periodically check for those events,
2244 either by looking at the status of signals on the JTAG connector
2245 or by sending synchronous ``tell me your status'' JTAG requests
2246 to the various active targets.
2247 There is a command to manage and monitor that polling,
2248 which is normally done in the background.
2250 @deffn Command poll [@option{on}|@option{off}]
2251 Poll the current target for its current state.
2252 (Also, @pxref{targetcurstate,,target curstate}.)
2253 If that target is in debug mode, architecture
2254 specific information about the current state is printed.
2255 An optional parameter
2256 allows background polling to be enabled and disabled.
2258 You could use this from the TCL command shell, or
2259 from GDB using @command{monitor poll} command.
2260 Leave background polling enabled while you're using GDB.
2261 @example
2262 > poll
2263 background polling: on
2264 target state: halted
2265 target halted in ARM state due to debug-request, \
2266 current mode: Supervisor
2267 cpsr: 0x800000d3 pc: 0x11081bfc
2268 MMU: disabled, D-Cache: disabled, I-Cache: enabled
2269 >
2270 @end example
2271 @end deffn
2273 @node Debug Adapter Configuration
2274 @chapter Debug Adapter Configuration
2275 @cindex config file, interface
2276 @cindex interface config file
2278 Correctly installing OpenOCD includes making your operating system give
2279 OpenOCD access to debug adapters. Once that has been done, Tcl commands
2280 are used to select which one is used, and to configure how it is used.
2282 @quotation Note
2283 Because OpenOCD started out with a focus purely on JTAG, you may find
2284 places where it wrongly presumes JTAG is the only transport protocol
2285 in use. Be aware that recent versions of OpenOCD are removing that
2286 limitation. JTAG remains more functional than most other transports.
2287 Other transports do not support boundary scan operations, or may be
2288 specific to a given chip vendor. Some might be usable only for
2289 programming flash memory, instead of also for debugging.
2290 @end quotation
2292 Debug Adapters/Interfaces/Dongles are normally configured
2293 through commands in an interface configuration
2294 file which is sourced by your @file{openocd.cfg} file, or
2295 through a command line @option{-f interface/....cfg} option.
2297 @example
2298 source [find interface/olimex-jtag-tiny.cfg]
2299 @end example
2301 These commands tell
2302 OpenOCD what type of JTAG adapter you have, and how to talk to it.
2303 A few cases are so simple that you only need to say what driver to use:
2305 @example
2306 # jlink interface
2307 interface jlink
2308 @end example
2310 Most adapters need a bit more configuration than that.
2313 @section Interface Configuration
2315 The interface command tells OpenOCD what type of debug adapter you are
2316 using. Depending on the type of adapter, you may need to use one or
2317 more additional commands to further identify or configure the adapter.
2319 @deffn {Config Command} {interface} name
2320 Use the interface driver @var{name} to connect to the
2321 target.
2322 @end deffn
2324 @deffn Command {interface_list}
2325 List the debug adapter drivers that have been built into
2326 the running copy of OpenOCD.
2327 @end deffn
2328 @deffn Command {interface transports} transport_name+
2329 Specifies the transports supported by this debug adapter.
2330 The adapter driver builds-in similar knowledge; use this only
2331 when external configuration (such as jumpering) changes what
2332 the hardware can support.
2333 @end deffn
2337 @deffn Command {adapter_name}
2338 Returns the name of the debug adapter driver being used.
2339 @end deffn
2341 @section Interface Drivers
2343 Each of the interface drivers listed here must be explicitly
2344 enabled when OpenOCD is configured, in order to be made
2345 available at run time.
2347 @deffn {Interface Driver} {amt_jtagaccel}
2348 Amontec Chameleon in its JTAG Accelerator configuration,
2349 connected to a PC's EPP mode parallel port.
2350 This defines some driver-specific commands:
2352 @deffn {Config Command} {parport_port} number
2353 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
2354 the number of the @file{/dev/parport} device.
2355 @end deffn
2357 @deffn {Config Command} rtck [@option{enable}|@option{disable}]
2358 Displays status of RTCK option.
2359 Optionally sets that option first.
2360 @end deffn
2361 @end deffn
2363 @deffn {Interface Driver} {arm-jtag-ew}
2364 Olimex ARM-JTAG-EW USB adapter
2365 This has one driver-specific command:
2367 @deffn Command {armjtagew_info}
2368 Logs some status
2369 @end deffn
2370 @end deffn
2372 @deffn {Interface Driver} {at91rm9200}
2373 Supports bitbanged JTAG from the local system,
2374 presuming that system is an Atmel AT91rm9200
2375 and a specific set of GPIOs is used.
2376 @c command: at91rm9200_device NAME
2377 @c chooses among list of bit configs ... only one option
2378 @end deffn
2380 @deffn {Interface Driver} {cmsis-dap}
2381 ARM CMSIS-DAP compliant based adapter.
2383 @deffn {Config Command} {cmsis_dap_vid_pid} [vid pid]+
2384 The vendor ID and product ID of the CMSIS-DAP device. If not specified
2385 the driver will attempt to auto detect the CMSIS-DAP device.
2386 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2387 @example
2388 cmsis_dap_vid_pid 0xc251 0xf001 0x0d28 0x0204
2389 @end example
2390 @end deffn
2392 @deffn {Config Command} {cmsis_dap_serial} [serial]
2393 Specifies the @var{serial} of the CMSIS-DAP device to use.
2394 If not specified, serial numbers are not considered.
2395 @end deffn
2397 @deffn {Command} {cmsis-dap info}
2398 Display various device information, like hardware version, firmware version, current bus status.
2399 @end deffn
2400 @end deffn
2402 @deffn {Interface Driver} {dummy}
2403 A dummy software-only driver for debugging.
2404 @end deffn
2406 @deffn {Interface Driver} {ep93xx}
2407 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
2408 @end deffn
2410 @deffn {Interface Driver} {ftdi}
2411 This driver is for adapters using the MPSSE (Multi-Protocol Synchronous Serial
2412 Engine) mode built into many FTDI chips, such as the FT2232, FT4232 and FT232H.
2414 The driver is using libusb-1.0 in asynchronous mode to talk to the FTDI device,
2415 bypassing intermediate libraries like libftdi or D2XX.
2417 Support for new FTDI based adapters can be added competely through
2418 configuration files, without the need to patch and rebuild OpenOCD.
2420 The driver uses a signal abstraction to enable Tcl configuration files to
2421 define outputs for one or several FTDI GPIO. These outputs can then be
2422 controlled using the @command{ftdi_set_signal} command. Special signal names
2423 are reserved for nTRST, nSRST and LED (for blink) so that they, if defined,
2424 will be used for their customary purpose. Inputs can be read using the
2425 @command{ftdi_get_signal} command.
2427 To support SWD, a signal named SWD_EN must be defined. It is set to 1 when the
2428 SWD protocol is selected. When set, the adapter should route the SWDIO pin to
2429 the data input. An SWDIO_OE signal, if defined, will be set to 1 or 0 as
2430 required by the protocol, to tell the adapter to drive the data output onto
2431 the SWDIO pin or keep the SWDIO pin Hi-Z, respectively.
2433 Depending on the type of buffer attached to the FTDI GPIO, the outputs have to
2434 be controlled differently. In order to support tristateable signals such as
2435 nSRST, both a data GPIO and an output-enable GPIO can be specified for each
2436 signal. The following output buffer configurations are supported:
2438 @itemize @minus
2439 @item Push-pull with one FTDI output as (non-)inverted data line
2440 @item Open drain with one FTDI output as (non-)inverted output-enable
2441 @item Tristate with one FTDI output as (non-)inverted data line and another
2442 FTDI output as (non-)inverted output-enable
2443 @item Unbuffered, using the FTDI GPIO as a tristate output directly by
2444 switching data and direction as necessary
2445 @end itemize
2447 These interfaces have several commands, used to configure the driver
2448 before initializing the JTAG scan chain:
2450 @deffn {Config Command} {ftdi_vid_pid} [vid pid]+
2451 The vendor ID and product ID of the adapter. Up to eight
2452 [@var{vid}, @var{pid}] pairs may be given, e.g.
2453 @example
2454 ftdi_vid_pid 0x0403 0xcff8 0x15ba 0x0003
2455 @end example
2456 @end deffn
2458 @deffn {Config Command} {ftdi_device_desc} description
2459 Provides the USB device description (the @emph{iProduct string})
2460 of the adapter. If not specified, the device description is ignored
2461 during device selection.
2462 @end deffn
2464 @deffn {Config Command} {ftdi_serial} serial-number
2465 Specifies the @var{serial-number} of the adapter to use,
2466 in case the vendor provides unique IDs and more than one adapter
2467 is connected to the host.
2468 If not specified, serial numbers are not considered.
2469 (Note that USB serial numbers can be arbitrary Unicode strings,
2470 and are not restricted to containing only decimal digits.)
2471 @end deffn
2473 @deffn {Config Command} {ftdi_location} <bus>:<port>[,<port>]...
2474 Specifies the physical USB port of the adapter to use. The path
2475 roots at @var{bus} and walks down the physical ports, with each
2476 @var{port} option specifying a deeper level in the bus topology, the last
2477 @var{port} denoting where the target adapter is actually plugged.
2478 The USB bus topology can be queried with the command @emph{lsusb -t}.
2480 This command is only available if your libusb1 is at least version 1.0.16.
2481 @end deffn
2483 @deffn {Config Command} {ftdi_channel} channel
2484 Selects the channel of the FTDI device to use for MPSSE operations. Most
2485 adapters use the default, channel 0, but there are exceptions.
2486 @end deffn
2488 @deffn {Config Command} {ftdi_layout_init} data direction
2489 Specifies the initial values of the FTDI GPIO data and direction registers.
2490 Each value is a 16-bit number corresponding to the concatenation of the high
2491 and low FTDI GPIO registers. The values should be selected based on the
2492 schematics of the adapter, such that all signals are set to safe levels with
2493 minimal impact on the target system. Avoid floating inputs, conflicting outputs
2494 and initially asserted reset signals.
2495 @end deffn
2497 @deffn {Config Command} {ftdi_layout_signal} name [@option{-data}|@option{-ndata} data_mask] [@option{-input}|@option{-ninput} input_mask] [@option{-oe}|@option{-noe} oe_mask] [@option{-alias}|@option{-nalias} name]
2498 Creates a signal with the specified @var{name}, controlled by one or more FTDI
2499 GPIO pins via a range of possible buffer connections. The masks are FTDI GPIO
2500 register bitmasks to tell the driver the connection and type of the output
2501 buffer driving the respective signal. @var{data_mask} is the bitmask for the
2502 pin(s) connected to the data input of the output buffer. @option{-ndata} is
2503 used with inverting data inputs and @option{-data} with non-inverting inputs.
2504 The @option{-oe} (or @option{-noe}) option tells where the output-enable (or
2505 not-output-enable) input to the output buffer is connected. The options
2506 @option{-input} and @option{-ninput} specify the bitmask for pins to be read
2507 with the method @command{ftdi_get_signal}.
2509 Both @var{data_mask} and @var{oe_mask} need not be specified. For example, a
2510 simple open-collector transistor driver would be specified with @option{-oe}
2511 only. In that case the signal can only be set to drive low or to Hi-Z and the
2512 driver will complain if the signal is set to drive high. Which means that if
2513 it's a reset signal, @command{reset_config} must be specified as
2514 @option{srst_open_drain}, not @option{srst_push_pull}.
2516 A special case is provided when @option{-data} and @option{-oe} is set to the
2517 same bitmask. Then the FTDI pin is considered being connected straight to the
2518 target without any buffer. The FTDI pin is then switched between output and
2519 input as necessary to provide the full set of low, high and Hi-Z
2520 characteristics. In all other cases, the pins specified in a signal definition
2521 are always driven by the FTDI.
2523 If @option{-alias} or @option{-nalias} is used, the signal is created
2524 identical (or with data inverted) to an already specified signal
2525 @var{name}.
2526 @end deffn
2528 @deffn {Command} {ftdi_set_signal} name @option{0}|@option{1}|@option{z}
2529 Set a previously defined signal to the specified level.
2530 @itemize @minus
2531 @item @option{0}, drive low
2532 @item @option{1}, drive high
2533 @item @option{z}, set to high-impedance
2534 @end itemize
2535 @end deffn
2537 @deffn {Command} {ftdi_get_signal} name
2538 Get the value of a previously defined signal.
2539 @end deffn
2541 @deffn {Command} {ftdi_tdo_sample_edge} @option{rising}|@option{falling}
2542 Configure TCK edge at which the adapter samples the value of the TDO signal
2544 Due to signal propagation delays, sampling TDO on rising TCK can become quite
2545 peculiar at high JTAG clock speeds. However, FTDI chips offer a possiblity to sample
2546 TDO on falling edge of TCK. With some board/adapter configurations, this may increase
2547 stability at higher JTAG clocks.
2548 @itemize @minus
2549 @item @option{rising}, sample TDO on rising edge of TCK - this is the default
2550 @item @option{falling}, sample TDO on falling edge of TCK
2551 @end itemize
2552 @end deffn
2554 For example adapter definitions, see the configuration files shipped in the
2555 @file{interface/ftdi} directory.
2557 @end deffn
2559 @deffn {Interface Driver} {remote_bitbang}
2560 Drive JTAG from a remote process. This sets up a UNIX or TCP socket connection
2561 with a remote process and sends ASCII encoded bitbang requests to that process
2562 instead of directly driving JTAG.
2564 The remote_bitbang driver is useful for debugging software running on
2565 processors which are being simulated.
2567 @deffn {Config Command} {remote_bitbang_port} number
2568 Specifies the TCP port of the remote process to connect to or 0 to use UNIX
2569 sockets instead of TCP.
2570 @end deffn
2572 @deffn {Config Command} {remote_bitbang_host} hostname
2573 Specifies the hostname of the remote process to connect to using TCP, or the
2574 name of the UNIX socket to use if remote_bitbang_port is 0.
2575 @end deffn
2577 For example, to connect remotely via TCP to the host foobar you might have
2578 something like:
2580 @example
2581 interface remote_bitbang
2582 remote_bitbang_port 3335
2583 remote_bitbang_host foobar
2584 @end example
2586 To connect to another process running locally via UNIX sockets with socket
2587 named mysocket:
2589 @example
2590 interface remote_bitbang
2591 remote_bitbang_port 0
2592 remote_bitbang_host mysocket
2593 @end example
2594 @end deffn
2596 @deffn {Interface Driver} {usb_blaster}
2597 USB JTAG/USB-Blaster compatibles over one of the userspace libraries
2598 for FTDI chips. These interfaces have several commands, used to
2599 configure the driver before initializing the JTAG scan chain:
2601 @deffn {Config Command} {usb_blaster_device_desc} description
2602 Provides the USB device description (the @emph{iProduct string})
2603 of the FTDI FT245 device. If not
2604 specified, the FTDI default value is used. This setting is only valid
2605 if compiled with FTD2XX support.
2606 @end deffn
2608 @deffn {Config Command} {usb_blaster_vid_pid} vid pid
2609 The vendor ID and product ID of the FTDI FT245 device. If not specified,
2610 default values are used.
2611 Currently, only one @var{vid}, @var{pid} pair may be given, e.g. for
2612 Altera USB-Blaster (default):
2613 @example
2614 usb_blaster_vid_pid 0x09FB 0x6001
2615 @end example
2616 The following VID/PID is for Kolja Waschk's USB JTAG:
2617 @example
2618 usb_blaster_vid_pid 0x16C0 0x06AD
2619 @end example
2620 @end deffn
2622 @deffn {Command} {usb_blaster_pin} (@option{pin6}|@option{pin8}) (@option{0}|@option{1}|@option{s}|@option{t})
2623 Sets the state or function of the unused GPIO pins on USB-Blasters
2624 (pins 6 and 8 on the female JTAG header). These pins can be used as
2625 SRST and/or TRST provided the appropriate connections are made on the
2626 target board.
2628 For example, to use pin 6 as SRST:
2629 @example
2630 usb_blaster_pin pin6 s
2631 reset_config srst_only
2632 @end example
2633 @end deffn
2635 @deffn {Command} {usb_blaster_lowlevel_driver} (@option{ftdi}|@option{ublast2})
2636 Chooses the low level access method for the adapter. If not specified,
2637 @option{ftdi} is selected unless it wasn't enabled during the
2638 configure stage. USB-Blaster II needs @option{ublast2}.
2639 @end deffn
2641 @deffn {Command} {usb_blaster_firmware} @var{path}
2642 This command specifies @var{path} to access USB-Blaster II firmware
2643 image. To be used with USB-Blaster II only.
2644 @end deffn
2646 @end deffn
2648 @deffn {Interface Driver} {gw16012}
2649 Gateworks GW16012 JTAG programmer.
2650 This has one driver-specific command:
2652 @deffn {Config Command} {parport_port} [port_number]
2653 Display either the address of the I/O port
2654 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2655 If a parameter is provided, first switch to use that port.
2656 This is a write-once setting.
2657 @end deffn
2658 @end deffn
2660 @deffn {Interface Driver} {jlink}
2661 SEGGER J-Link family of USB adapters. It currently supports JTAG and SWD
2662 transports.
2664 @quotation Compatibility Note
2665 SEGGER released many firmware versions for the many harware versions they
2666 produced. OpenOCD was extensively tested and intended to run on all of them,
2667 but some combinations were reported as incompatible. As a general
2668 recommendation, it is advisable to use the latest firmware version
2669 available for each hardware version. However the current V8 is a moving
2670 target, and SEGGER firmware versions released after the OpenOCD was
2671 released may not be compatible. In such cases it is recommended to
2672 revert to the last known functional version. For 0.5.0, this is from
2673 "Feb 8 2012 14:30:39", packed with 4.42c. For 0.6.0, the last known
2674 version is from "May 3 2012 18:36:22", packed with 4.46f.
2675 @end quotation
2677 @deffn {Command} {jlink hwstatus}
2678 Display various hardware related information, for example target voltage and pin
2679 states.
2680 @end deffn
2681 @deffn {Command} {jlink freemem}
2682 Display free device internal memory.
2683 @end deffn
2684 @deffn {Command} {jlink jtag} [@option{2}|@option{3}]
2685 Set the JTAG command version to be used. Without argument, show the actual JTAG
2686 command version.
2687 @end deffn
2688 @deffn {Command} {jlink config}
2689 Display the device configuration.
2690 @end deffn
2691 @deffn {Command} {jlink config targetpower} [@option{on}|@option{off}]
2692 Set the target power state on JTAG-pin 19. Without argument, show the target
2693 power state.
2694 @end deffn
2695 @deffn {Command} {jlink config mac} [@option{ff:ff:ff:ff:ff:ff}]
2696 Set the MAC address of the device. Without argument, show the MAC address.
2697 @end deffn
2698 @deffn {Command} {jlink config ip} [@option{A.B.C.D}(@option{/E}|@option{F.G.H.I})]
2699 Set the IP configuration of the device, where A.B.C.D is the IP address, E the
2700 bit of the subnet mask and F.G.H.I the subnet mask. Without arguments, show the
2701 IP configuration.
2702 @end deffn
2703 @deffn {Command} {jlink config usb} [@option{0} to @option{3}]
2704 Set the USB address of the device. This will also change the USB Product ID
2705 (PID) of the device. Without argument, show the USB address.
2706 @end deffn
2707 @deffn {Command} {jlink config reset}
2708 Reset the current configuration.
2709 @end deffn
2710 @deffn {Command} {jlink config write}
2711 Write the current configuration to the internal persistent storage.
2712 @end deffn
2713 @deffn {Command} {jlink emucom write <channel> <data>}
2714 Write data to an EMUCOM channel. The data needs to be encoded as hexadecimal
2715 pairs.
2717 The following example shows how to write the three bytes 0xaa, 0x0b and 0x23 to
2718 the EMUCOM channel 0x10:
2719 @example
2720 > jlink emucom write 0x10 aa0b23
2721 @end example
2722 @end deffn
2723 @deffn {Command} {jlink emucom read <channel> <length>}
2724 Read data from an EMUCOM channel. The read data is encoded as hexadecimal
2725 pairs.
2727 The following example shows how to read 4 bytes from the EMUCOM channel 0x0:
2728 @example
2729 > jlink emucom read 0x0 4
2730 77a90000
2731 @end example
2732 @end deffn
2733 @deffn {Config} {jlink usb} <@option{0} to @option{3}>
2734 Set the USB address of the interface, in case more than one adapter is connected
2735 to the host. If not specified, USB addresses are not considered. Device
2736 selection via USB address is deprecated and the serial number should be used
2737 instead.
2739 As a configuration command, it can be used only before 'init'.
2740 @end deffn
2741 @deffn {Config} {jlink serial} <serial number>
2742 Set the serial number of the interface, in case more than one adapter is
2743 connected to the host. If not specified, serial numbers are not considered.
2745 As a configuration command, it can be used only before 'init'.
2746 @end deffn
2747 @end deffn
2749 @deffn {Interface Driver} {kitprog}
2750 This driver is for Cypress Semiconductor's KitProg adapters. The KitProg is an
2751 SWD-only adapter that is designed to be used with Cypress's PSoC and PRoC device
2752 families, but it is possible to use it with some other devices. If you are using
2753 this adapter with a PSoC or a PRoC, you may need to add
2754 @command{kitprog_init_acquire_psoc} or @command{kitprog acquire_psoc} to your
2755 configuration script.
2757 Note that this driver is for the proprietary KitProg protocol, not the CMSIS-DAP
2758 mode introduced in firmware 2.14. If the KitProg is in CMSIS-DAP mode, it cannot
2759 be used with this driver, and must either be used with the cmsis-dap driver or
2760 switched back to KitProg mode. See the Cypress KitProg User Guide for
2761 instructions on how to switch KitProg modes.
2763 Known limitations:
2764 @itemize @bullet
2765 @item The frequency of SWCLK cannot be configured, and varies between 1.6 MHz
2766 and 2.7 MHz.
2767 @item For firmware versions below 2.14, "JTAG to SWD" sequences are replaced by
2768 "SWD line reset" in the driver. This is for two reasons. First, the KitProg does
2769 not support sending arbitrary SWD sequences, and only firmware 2.14 and later
2770 implement both "JTAG to SWD" and "SWD line reset" in firmware. Earlier firmware
2771 versions only implement "SWD line reset". Second, due to a firmware quirk, an
2772 SWD sequence must be sent after every target reset in order to re-establish
2773 communications with the target.
2774 @item Due in part to the limitation above, KitProg devices with firmware below
2775 version 2.14 will need to use @command{kitprog_init_acquire_psoc} in order to
2776 communicate with PSoC 5LP devices. This is because, assuming debug is not
2777 disabled on the PSoC, the PSoC 5LP needs its JTAG interface switched to SWD
2778 mode before communication can begin, but prior to firmware 2.14, "JTAG to SWD"
2779 could only be sent with an acquisition sequence.
2780 @end itemize
2782 @deffn {Config Command} {kitprog_init_acquire_psoc}
2783 Indicate that a PSoC acquisition sequence needs to be run during adapter init.
2784 Please be aware that the acquisition sequence hard-resets the target.
2785 @end deffn
2787 @deffn {Config Command} {kitprog_serial} serial
2788 Select a KitProg device by its @var{serial}. If left unspecified, the first
2789 device detected by OpenOCD will be used.
2790 @end deffn
2792 @deffn {Command} {kitprog acquire_psoc}
2793 Run a PSoC acquisition sequence immediately. Typically, this should not be used
2794 outside of the target-specific configuration scripts since it hard-resets the
2795 target as a side-effect.
2796 This is necessary for "reset halt" on some PSoC 4 series devices.
2797 @end deffn
2799 @deffn {Command} {kitprog info}
2800 Display various adapter information, such as the hardware version, firmware
2801 version, and target voltage.
2802 @end deffn
2803 @end deffn
2805 @deffn {Interface Driver} {parport}
2806 Supports PC parallel port bit-banging cables:
2807 Wigglers, PLD download cable, and more.
2808 These interfaces have several commands, used to configure the driver
2809 before initializing the JTAG scan chain:
2811 @deffn {Config Command} {parport_cable} name
2812 Set the layout of the parallel port cable used to connect to the target.
2813 This is a write-once setting.
2814 Currently valid cable @var{name} values include:
2816 @itemize @minus
2817 @item @b{altium} Altium Universal JTAG cable.
2818 @item @b{arm-jtag} Same as original wiggler except SRST and
2819 TRST connections reversed and TRST is also inverted.
2820 @item @b{chameleon} The Amontec Chameleon's CPLD when operated
2821 in configuration mode. This is only used to
2822 program the Chameleon itself, not a connected target.
2823 @item @b{dlc5} The Xilinx Parallel cable III.
2824 @item @b{flashlink} The ST Parallel cable.
2825 @item @b{lattice} Lattice ispDOWNLOAD Cable
2826 @item @b{old_amt_wiggler} The Wiggler configuration that comes with
2827 some versions of
2828 Amontec's Chameleon Programmer. The new version available from
2829 the website uses the original Wiggler layout ('@var{wiggler}')
2830 @item @b{triton} The parallel port adapter found on the
2831 ``Karo Triton 1 Development Board''.
2832 This is also the layout used by the HollyGates design
2833 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
2834 @item @b{wiggler} The original Wiggler layout, also supported by
2835 several clones, such as the Olimex ARM-JTAG
2836 @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
2837 @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
2838 @end itemize
2839 @end deffn
2841 @deffn {Config Command} {parport_port} [port_number]
2842 Display either the address of the I/O port
2843 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2844 If a parameter is provided, first switch to use that port.
2845 This is a write-once setting.
2847 When using PPDEV to access the parallel port, use the number of the parallel port:
2848 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
2849 you may encounter a problem.
2850 @end deffn
2852 @deffn Command {parport_toggling_time} [nanoseconds]
2853 Displays how many nanoseconds the hardware needs to toggle TCK;
2854 the parport driver uses this value to obey the
2855 @command{adapter_khz} configuration.
2856 When the optional @var{nanoseconds} parameter is given,
2857 that setting is changed before displaying the current value.
2859 The default setting should work reasonably well on commodity PC hardware.
2860 However, you may want to calibrate for your specific hardware.
2861 @quotation Tip
2862 To measure the toggling time with a logic analyzer or a digital storage
2863 oscilloscope, follow the procedure below:
2864 @example
2865 > parport_toggling_time 1000
2866 > adapter_khz 500
2867 @end example
2868 This sets the maximum JTAG clock speed of the hardware, but
2869 the actual speed probably deviates from the requested 500 kHz.
2870 Now, measure the time between the two closest spaced TCK transitions.
2871 You can use @command{runtest 1000} or something similar to generate a
2872 large set of samples.
2873 Update the setting to match your measurement:
2874 @example
2875 > parport_toggling_time <measured nanoseconds>
2876 @end example
2877 Now the clock speed will be a better match for @command{adapter_khz rate}
2878 commands given in OpenOCD scripts and event handlers.
2880 You can do something similar with many digital multimeters, but note
2881 that you'll probably need to run the clock continuously for several
2882 seconds before it decides what clock rate to show. Adjust the
2883 toggling time up or down until the measured clock rate is a good
2884 match for the adapter_khz rate you specified; be conservative.
2885 @end quotation
2886 @end deffn
2888 @deffn {Config Command} {parport_write_on_exit} (@option{on}|@option{off})
2889 This will configure the parallel driver to write a known
2890 cable-specific value to the parallel interface on exiting OpenOCD.
2891 @end deffn
2893 For example, the interface configuration file for a
2894 classic ``Wiggler'' cable on LPT2 might look something like this:
2896 @example
2897 interface parport
2898 parport_port 0x278
2899 parport_cable wiggler
2900 @end example
2901 @end deffn
2903 @deffn {Interface Driver} {presto}
2904 ASIX PRESTO USB JTAG programmer.
2905 @deffn {Config Command} {presto_serial} serial_string
2906 Configures the USB serial number of the Presto device to use.
2907 @end deffn
2908 @end deffn
2910 @deffn {Interface Driver} {rlink}
2911 Raisonance RLink USB adapter
2912 @end deffn
2914 @deffn {Interface Driver} {usbprog}
2915 usbprog is a freely programmable USB adapter.
2916 @end deffn
2918 @deffn {Interface Driver} {vsllink}
2919 vsllink is part of Versaloon which is a versatile USB programmer.
2921 @quotation Note
2922 This defines quite a few driver-specific commands,
2923 which are not currently documented here.
2924 @end quotation
2925 @end deffn
2927 @anchor{hla_interface}
2928 @deffn {Interface Driver} {hla}
2929 This is a driver that supports multiple High Level Adapters.
2930 This type of adapter does not expose some of the lower level api's
2931 that OpenOCD would normally use to access the target.
2933 Currently supported adapters include the ST STLINK and TI ICDI.
2934 STLINK firmware version >= V2.J21.S4 recommended due to issues with earlier
2935 versions of firmware where serial number is reset after first use. Suggest
2936 using ST firmware update utility to upgrade STLINK firmware even if current
2937 version reported is V2.J21.S4.
2939 @deffn {Config Command} {hla_device_desc} description
2940 Currently Not Supported.
2941 @end deffn
2943 @deffn {Config Command} {hla_serial} serial
2944 Specifies the serial number of the adapter.
2945 @end deffn
2947 @deffn {Config Command} {hla_layout} (@option{stlink}|@option{icdi})
2948 Specifies the adapter layout to use.
2949 @end deffn
2951 @deffn {Config Command} {hla_vid_pid} [vid pid]+
2952 Pairs of vendor IDs and product IDs of the device.
2953 @end deffn
2955 @deffn {Command} {hla_command} command
2956 Execute a custom adapter-specific command. The @var{command} string is
2957 passed as is to the underlying adapter layout handler.
2958 @end deffn
2959 @end deffn
2961 @deffn {Interface Driver} {opendous}
2962 opendous-jtag is a freely programmable USB adapter.
2963 @end deffn
2965 @deffn {Interface Driver} {ulink}
2966 This is the Keil ULINK v1 JTAG debugger.
2967 @end deffn
2969 @deffn {Interface Driver} {ZY1000}
2970 This is the Zylin ZY1000 JTAG debugger.
2971 @end deffn
2973 @quotation Note
2974 This defines some driver-specific commands,
2975 which are not currently documented here.
2976 @end quotation
2978 @deffn Command power [@option{on}|@option{off}]
2979 Turn power switch to target on/off.
2980 No arguments: print status.
2981 @end deffn
2983 @deffn {Interface Driver} {bcm2835gpio}
2984 This SoC is present in Raspberry Pi which is a cheap single-board computer
2985 exposing some GPIOs on its expansion header.
2987 The driver accesses memory-mapped GPIO peripheral registers directly
2988 for maximum performance, but the only possible race condition is for
2989 the pins' modes/muxing (which is highly unlikely), so it should be
2990 able to coexist nicely with both sysfs bitbanging and various
2991 peripherals' kernel drivers. The driver restores the previous
2992 configuration on exit.
2994 See @file{interface/raspberrypi-native.cfg} for a sample config and
2995 pinout.
2997 @end deffn
2999 @deffn {Interface Driver} {imx_gpio}
3000 i.MX SoC is present in many community boards. Wandboard is an example
3001 of the one which is most popular.
3003 This driver is mostly the same as bcm2835gpio.
3005 See @file{interface/imx-native.cfg} for a sample config and
3006 pinout.
3008 @end deffn
3011 @deffn {Interface Driver} {openjtag}
3012 OpenJTAG compatible USB adapter.
3013 This defines some driver-specific commands:
3015 @deffn {Config Command} {openjtag_variant} variant
3016 Specifies the variant of the OpenJTAG adapter (see @uref{http://www.openjtag.org/}).
3017 Currently valid @var{variant} values include:
3019 @itemize @minus
3020 @item @b{standard} Standard variant (default).
3021 @item @b{cy7c65215} Cypress CY7C65215 Dual Channel USB-Serial Bridge Controller
3022 (see @uref{http://www.cypress.com/?rID=82870}).
3023 @end itemize
3024 @end deffn
3026 @deffn {Config Command} {openjtag_device_desc} string
3027 The USB device description string of the adapter.
3028 This value is only used with the standard variant.
3029 @end deffn
3030 @end deffn
3032 @section Transport Configuration
3033 @cindex Transport
3034 As noted earlier, depending on the version of OpenOCD you use,
3035 and the debug adapter you are using,
3036 several transports may be available to
3037 communicate with debug targets (or perhaps to program flash memory).
3038 @deffn Command {transport list}
3039 displays the names of the transports supported by this
3040 version of OpenOCD.
3041 @end deffn
3043 @deffn Command {transport select} @option{transport_name}
3044 Select which of the supported transports to use in this OpenOCD session.
3046 When invoked with @option{transport_name}, attempts to select the named
3047 transport. The transport must be supported by the debug adapter
3048 hardware and by the version of OpenOCD you are using (including the
3049 adapter's driver).
3051 If no transport has been selected and no @option{transport_name} is
3052 provided, @command{transport select} auto-selects the first transport
3053 supported by the debug adapter.
3055 @command{transport select} always returns the name of the session's selected
3056 transport, if any.
3057 @end deffn
3059 @subsection JTAG Transport
3060 @cindex JTAG
3061 JTAG is the original transport supported by OpenOCD, and most
3062 of the OpenOCD commands support it.
3063 JTAG transports expose a chain of one or more Test Access Points (TAPs),
3064 each of which must be explicitly declared.
3065 JTAG supports both debugging and boundary scan testing.
3066 Flash programming support is built on top of debug support.
3068 JTAG transport is selected with the command @command{transport select
3069 jtag}. Unless your adapter uses @ref{hla_interface,the hla interface
3070 driver}, in which case the command is @command{transport select
3071 hla_jtag}.
3073 @subsection SWD Transport
3074 @cindex SWD
3075 @cindex Serial Wire Debug
3076 SWD (Serial Wire Debug) is an ARM-specific transport which exposes one
3077 Debug Access Point (DAP, which must be explicitly declared.
3078 (SWD uses fewer signal wires than JTAG.)
3079 SWD is debug-oriented, and does not support boundary scan testing.
3080 Flash programming support is built on top of debug support.
3081 (Some processors support both JTAG and SWD.)
3083 SWD transport is selected with the command @command{transport select
3084 swd}. Unless your adapter uses @ref{hla_interface,the hla interface
3085 driver}, in which case the command is @command{transport select
3086 hla_swd}.
3088 @deffn Command {swd newdap} ...
3089 Declares a single DAP which uses SWD transport.
3090 Parameters are currently the same as "jtag newtap" but this is
3091 expected to change.
3092 @end deffn
3093 @deffn Command {swd wcr trn prescale}
3094 Updates TRN (turnaraound delay) and prescaling.fields of the
3095 Wire Control Register (WCR).
3096 No parameters: displays current settings.
3097 @end deffn
3099 @subsection SPI Transport
3100 @cindex SPI
3101 @cindex Serial Peripheral Interface
3102 The Serial Peripheral Interface (SPI) is a general purpose transport
3103 which uses four wire signaling. Some processors use it as part of a
3104 solution for flash programming.
3106 @anchor{jtagspeed}
3107 @section JTAG Speed
3108 JTAG clock setup is part of system setup.
3109 It @emph{does not belong with interface setup} since any interface
3110 only knows a few of the constraints for the JTAG clock speed.
3111 Sometimes the JTAG speed is
3112 changed during the target initialization process: (1) slow at
3113 reset, (2) program the CPU clocks, (3) run fast.
3114 Both the "slow" and "fast" clock rates are functions of the
3115 oscillators used, the chip, the board design, and sometimes
3116 power management software that may be active.
3118 The speed used during reset, and the scan chain verification which
3119 follows reset, can be adjusted using a @code{reset-start}
3120 target event handler.
3121 It can then be reconfigured to a faster speed by a
3122 @code{reset-init} target event handler after it reprograms those
3123 CPU clocks, or manually (if something else, such as a boot loader,
3124 sets up those clocks).
3125 @xref{targetevents,,Target Events}.
3126 When the initial low JTAG speed is a chip characteristic, perhaps
3127 because of a required oscillator speed, provide such a handler
3128 in the target config file.
3129 When that speed is a function of a board-specific characteristic
3130 such as which speed oscillator is used, it belongs in the board
3131 config file instead.
3132 In both cases it's safest to also set the initial JTAG clock rate
3133 to that same slow speed, so that OpenOCD never starts up using a
3134 clock speed that's faster than the scan chain can support.
3136 @example
3137 jtag_rclk 3000
3138 $_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
3139 @end example
3141 If your system supports adaptive clocking (RTCK), configuring
3142 JTAG to use that is probably the most robust approach.
3143 However, it introduces delays to synchronize clocks; so it
3144 may not be the fastest solution.
3146 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
3147 instead of @command{adapter_khz}, but only for (ARM) cores and boards
3148 which support adaptive clocking.
3150 @deffn {Command} adapter_khz max_speed_kHz
3151 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
3152 JTAG interfaces usually support a limited number of
3153 speeds. The speed actually used won't be faster
3154 than the speed specified.
3156 Chip data sheets generally include a top JTAG clock rate.
3157 The actual rate is often a function of a CPU core clock,
3158 and is normally less than that peak rate.
3159 For example, most ARM cores accept at most one sixth of the CPU clock.
3161 Speed 0 (khz) selects RTCK method.
3162 @xref{faqrtck,,FAQ RTCK}.
3163 If your system uses RTCK, you won't need to change the
3164 JTAG clocking after setup.
3165 Not all interfaces, boards, or targets support ``rtck''.
3166 If the interface device can not
3167 support it, an error is returned when you try to use RTCK.
3168 @end deffn
3170 @defun jtag_rclk fallback_speed_kHz
3171 @cindex adaptive clocking
3172 @cindex RTCK
3173 This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
3174 If that fails (maybe the interface, board, or target doesn't
3175 support it), falls back to the specified frequency.
3176 @example
3177 # Fall back to 3mhz if RTCK is not supported
3178 jtag_rclk 3000
3179 @end example
3180 @end defun
3182 @node Reset Configuration
3183 @chapter Reset Configuration
3184 @cindex Reset Configuration
3186 Every system configuration may require a different reset
3187 configuration. This can also be quite confusing.
3188 Resets also interact with @var{reset-init} event handlers,
3189 which do things like setting up clocks and DRAM, and
3190 JTAG clock rates. (@xref{jtagspeed,,JTAG Speed}.)
3191 They can also interact with JTAG routers.
3192 Please see the various board files for examples.
3194 @quotation Note
3195 To maintainers and integrators:
3196 Reset configuration touches several things at once.
3197 Normally the board configuration file
3198 should define it and assume that the JTAG adapter supports
3199 everything that's wired up to the board's JTAG connector.
3201 However, the target configuration file could also make note
3202 of something the silicon vendor has done inside the chip,
3203 which will be true for most (or all) boards using that chip.
3204 And when the JTAG adapter doesn't support everything, the
3205 user configuration file will need to override parts of
3206 the reset configuration provided by other files.
3207 @end quotation
3209 @section Types of Reset
3211 There are many kinds of reset possible through JTAG, but
3212 they may not all work with a given board and adapter.
3213 That's part of why reset configuration can be error prone.
3215 @itemize @bullet
3216 @item
3217 @emph{System Reset} ... the @emph{SRST} hardware signal
3218 resets all chips connected to the JTAG adapter, such as processors,
3219 power management chips, and I/O controllers. Normally resets triggered
3220 with this signal behave exactly like pressing a RESET button.
3221 @item
3222 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
3223 just the TAP controllers connected to the JTAG adapter.
3224 Such resets should not be visible to the rest of the system; resetting a
3225 device's TAP controller just puts that controller into a known state.
3226 @item
3227 @emph{Emulation Reset} ... many devices can be reset through JTAG
3228 commands. These resets are often distinguishable from system
3229 resets, either explicitly (a "reset reason" register says so)
3230 or implicitly (not all parts of the chip get reset).
3231 @item
3232 @emph{Other Resets} ... system-on-chip devices often support
3233 several other types of reset.
3234 You may need to arrange that a watchdog timer stops
3235 while debugging, preventing a watchdog reset.
3236 There may be individual module resets.
3237 @end itemize
3239 In the best case, OpenOCD can hold SRST, then reset
3240 the TAPs via TRST and send commands through JTAG to halt the
3241 CPU at the reset vector before the 1st instruction is executed.
3242 Then when it finally releases the SRST signal, the system is
3243 halted under debugger control before any code has executed.
3244 This is the behavior required to support the @command{reset halt}
3245 and @command{reset init} commands; after @command{reset init} a
3246 board-specific script might do things like setting up DRAM.
3247 (@xref{resetcommand,,Reset Command}.)
3249 @anchor{srstandtrstissues}
3250 @section SRST and TRST Issues
3252 Because SRST and TRST are hardware signals, they can have a
3253 variety of system-specific constraints. Some of the most
3254 common issues are:
3256 @itemize @bullet
3258 @item @emph{Signal not available} ... Some boards don't wire
3259 SRST or TRST to the JTAG connector. Some JTAG adapters don't
3260 support such signals even if they are wired up.
3261 Use the @command{reset_config} @var{signals} options to say
3262 when either of those signals is not connected.
3263 When SRST is not available, your code might not be able to rely
3264 on controllers having been fully reset during code startup.
3265 Missing TRST is not a problem, since JTAG-level resets can
3266 be triggered using with TMS signaling.
3268 @item @emph{Signals shorted} ... Sometimes a chip, board, or
3269 adapter will connect SRST to TRST, instead of keeping them separate.
3270 Use the @command{reset_config} @var{combination} options to say
3271 when those signals aren't properly independent.
3273 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
3274 delay circuit, reset supervisor, or on-chip features can extend
3275 the effect of a JTAG adapter's reset for some time after the adapter
3276 stops issuing the reset. For example, there may be chip or board
3277 requirements that all reset pulses last for at least a
3278 certain amount of time; and reset buttons commonly have
3279 hardware debouncing.
3280 Use the @command{adapter_nsrst_delay} and @command{jtag_ntrst_delay}
3281 commands to say when extra delays are needed.
3283 @item @emph{Drive type} ... Reset lines often have a pullup
3284 resistor, letting the JTAG interface treat them as open-drain
3285 signals. But that's not a requirement, so the adapter may need
3286 to use push/pull output drivers.
3287 Also, with weak pullups it may be advisable to drive
3288 signals to both levels (push/pull) to minimize rise times.
3289 Use the @command{reset_config} @var{trst_type} and
3290 @var{srst_type} parameters to say how to drive reset signals.
3292 @item @emph{Special initialization} ... Targets sometimes need
3293 special JTAG initialization sequences to handle chip-specific
3294 issues (not limited to errata).
3295 For example, certain JTAG commands might need to be issued while
3296 the system as a whole is in a reset state (SRST active)
3297 but the JTAG scan chain is usable (TRST inactive).
3298 Many systems treat combined assertion of SRST and TRST as a
3299 trigger for a harder reset than SRST alone.
3300 Such custom reset handling is discussed later in this chapter.
3301 @end itemize
3303 There can also be other issues.
3304 Some devices don't fully conform to the JTAG specifications.
3305 Trivial system-specific differences are common, such as
3306 SRST and TRST using slightly different names.
3307 There are also vendors who distribute key JTAG documentation for
3308 their chips only to developers who have signed a Non-Disclosure
3309 Agreement (NDA).
3311 Sometimes there are chip-specific extensions like a requirement to use
3312 the normally-optional TRST signal (precluding use of JTAG adapters which
3313 don't pass TRST through), or needing extra steps to complete a TAP reset.
3315 In short, SRST and especially TRST handling may be very finicky,
3316 needing to cope with both architecture and board specific constraints.
3318 @section Commands for Handling Resets
3320 @deffn {Command} adapter_nsrst_assert_width milliseconds
3321 Minimum amount of time (in milliseconds) OpenOCD should wait
3322 after asserting nSRST (active-low system reset) before
3323 allowing it to be deasserted.
3324 @end deffn
3326 @deffn {Command} adapter_nsrst_delay milliseconds
3327 How long (in milliseconds) OpenOCD should wait after deasserting
3328 nSRST (active-low system reset) before starting new JTAG operations.
3329 When a board has a reset button connected to SRST line it will
3330 probably have hardware debouncing, implying you should use this.
3331 @end deffn
3333 @deffn {Command} jtag_ntrst_assert_width milliseconds
3334 Minimum amount of time (in milliseconds) OpenOCD should wait
3335 after asserting nTRST (active-low JTAG TAP reset) before
3336 allowing it to be deasserted.
3337 @end deffn
3339 @deffn {Command} jtag_ntrst_delay milliseconds
3340 How long (in milliseconds) OpenOCD should wait after deasserting
3341 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
3342 @end deffn
3344 @deffn {Command} reset_config mode_flag ...
3345 This command displays or modifies the reset configuration
3346 of your combination of JTAG board and target in target
3347 configuration scripts.
3349 Information earlier in this section describes the kind of problems
3350 the command is intended to address (@pxref{srstandtrstissues,,SRST and TRST Issues}).
3351 As a rule this command belongs only in board config files,
3352 describing issues like @emph{board doesn't connect TRST};
3353 or in user config files, addressing limitations derived
3354 from a particular combination of interface and board.
3355 (An unlikely example would be using a TRST-only adapter
3356 with a board that only wires up SRST.)
3358 The @var{mode_flag} options can be specified in any order, but only one
3359 of each type -- @var{signals}, @var{combination}, @var{gates},
3360 @var{trst_type}, @var{srst_type} and @var{connect_type}
3361 -- may be specified at a time.
3362 If you don't provide a new value for a given type, its previous
3363 value (perhaps the default) is unchanged.
3364 For example, this means that you don't need to say anything at all about
3365 TRST just to declare that if the JTAG adapter should want to drive SRST,
3366 it must explicitly be driven high (@option{srst_push_pull}).
3368 @itemize
3369 @item
3370 @var{signals} can specify which of the reset signals are connected.
3371 For example, If the JTAG interface provides SRST, but the board doesn't
3372 connect that signal properly, then OpenOCD can't use it.
3373 Possible values are @option{none} (the default), @option{trst_only},
3374 @option{srst_only} and @option{trst_and_srst}.
3376 @quotation Tip
3377 If your board provides SRST and/or TRST through the JTAG connector,
3378 you must declare that so those signals can be used.
3379 @end quotation
3381 @item
3382 The @var{combination} is an optional value specifying broken reset
3383 signal implementations.
3384 The default behaviour if no option given is @option{separate},
3385 indicating everything behaves normally.
3386 @option{srst_pulls_trst} states that the
3387 test logic is reset together with the reset of the system (e.g. NXP
3388 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
3389 the system is reset together with the test logic (only hypothetical, I
3390 haven't seen hardware with such a bug, and can be worked around).
3391 @option{combined} implies both @option{srst_pulls_trst} and
3392 @option{trst_pulls_srst}.
3394 @item
3395 The @var{gates} tokens control flags that describe some cases where
3396 JTAG may be unvailable during reset.
3397 @option{srst_gates_jtag} (default)
3398 indicates that asserting SRST gates the
3399 JTAG clock. This means that no communication can happen on JTAG
3400 while SRST is asserted.
3401 Its converse is @option{srst_nogate}, indicating that JTAG commands
3402 can safely be issued while SRST is active.
3404 @item
3405 The @var{connect_type} tokens control flags that describe some cases where
3406 SRST is asserted while connecting to the target. @option{srst_nogate}
3407 is required to use this option.
3408 @option{connect_deassert_srst} (default)
3409 indicates that SRST will not be asserted while connecting to the target.
3410 Its converse is @option{connect_assert_srst}, indicating that SRST will
3411 be asserted before any target connection.
3412 Only some targets support this feature, STM32 and STR9 are examples.
3413 This feature is useful if you are unable to connect to your target due
3414 to incorrect options byte config or illegal program execution.
3415 @end itemize
3417 The optional @var{trst_type} and @var{srst_type} parameters allow the
3418 driver mode of each reset line to be specified. These values only affect
3419 JTAG interfaces with support for different driver modes, like the Amontec
3420 JTAGkey and JTAG Accelerator. Also, they are necessarily ignored if the
3421 relevant signal (TRST or SRST) is not connected.
3423 @itemize
3424 @item
3425 Possible @var{trst_type} driver modes for the test reset signal (TRST)
3426 are the default @option{trst_push_pull}, and @option{trst_open_drain}.
3427 Most boards connect this signal to a pulldown, so the JTAG TAPs
3428 never leave reset unless they are hooked up to a JTAG adapter.
3430 @item
3431 Possible @var{srst_type} driver modes for the system reset signal (SRST)
3432 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
3433 Most boards connect this signal to a pullup, and allow the
3434 signal to be pulled low by various events including system
3435 powerup and pressing a reset button.
3436 @end itemize
3437 @end deffn
3439 @section Custom Reset Handling
3440 @cindex events
3442 OpenOCD has several ways to help support the various reset
3443 mechanisms provided by chip and board vendors.
3444 The commands shown in the previous section give standard parameters.
3445 There are also @emph{event handlers} associated with TAPs or Targets.
3446 Those handlers are Tcl procedures you can provide, which are invoked
3447 at particular points in the reset sequence.
3449 @emph{When SRST is not an option} you must set
3450 up a @code{reset-assert} event handler for your target.
3451 For example, some JTAG adapters don't include the SRST signal;
3452 and some boards have multiple targets, and you won't always
3453 want to reset everything at once.
3455 After configuring those mechanisms, you might still
3456 find your board doesn't start up or reset correctly.
3457 For example, maybe it needs a slightly different sequence
3458 of SRST and/or TRST manipulations, because of quirks that
3459 the @command{reset_config} mechanism doesn't address;
3460 or asserting both might trigger a stronger reset, which
3461 needs special attention.
3463 Experiment with lower level operations, such as @command{jtag_reset}
3464 and the @command{jtag arp_*} operations shown here,
3465 to find a sequence of operations that works.
3466 @xref{JTAG Commands}.
3467 When you find a working sequence, it can be used to override
3468 @command{jtag_init}, which fires during OpenOCD startup
3469 (@pxref{configurationstage,,Configuration Stage});
3470 or @command{init_reset}, which fires during reset processing.
3472 You might also want to provide some project-specific reset
3473 schemes. For example, on a multi-target board the standard
3474 @command{reset} command would reset all targets, but you
3475 may need the ability to reset only one target at time and
3476 thus want to avoid using the board-wide SRST signal.
3478 @deffn {Overridable Procedure} init_reset mode
3479 This is invoked near the beginning of the @command{reset} command,
3480 usually to provide as much of a cold (power-up) reset as practical.
3481 By default it is also invoked from @command{jtag_init} if
3482 the scan chain does not respond to pure JTAG operations.
3483 The @var{mode} parameter is the parameter given to the
3484 low level reset command (@option{halt},
3485 @option{init}, or @option{run}), @option{setup},
3486 or potentially some other value.
3488 The default implementation just invokes @command{jtag arp_init-reset}.
3489 Replacements will normally build on low level JTAG
3490 operations such as @command{jtag_reset}.
3491 Operations here must not address individual TAPs
3492 (or their associated targets)
3493 until the JTAG scan chain has first been verified to work.
3495 Implementations must have verified the JTAG scan chain before
3496 they return.
3497 This is done by calling @command{jtag arp_init}
3498 (or @command{jtag arp_init-reset}).
3499 @end deffn
3501 @deffn Command {jtag arp_init}
3502 This validates the scan chain using just the four
3503 standard JTAG signals (TMS, TCK, TDI, TDO).
3504 It starts by issuing a JTAG-only reset.
3505 Then it performs checks to verify that the scan chain configuration
3506 matches the TAPs it can observe.
3507 Those checks include checking IDCODE values for each active TAP,
3508 and verifying the length of their instruction registers using
3509 TAP @code{-ircapture} and @code{-irmask} values.
3510 If these tests all pass, TAP @code{setup} events are
3511 issued to all TAPs with handlers for that event.
3512 @end deffn
3514 @deffn Command {jtag arp_init-reset}
3515 This uses TRST and SRST to try resetting
3516 everything on the JTAG scan chain
3517 (and anything else connected to SRST).
3518 It then invokes the logic of @command{jtag arp_init}.
3519 @end deffn
3522 @node TAP Declaration
3523 @chapter TAP Declaration
3524 @cindex TAP declaration
3525 @cindex TAP configuration
3527 @emph{Test Access Ports} (TAPs) are the core of JTAG.
3528 TAPs serve many roles, including:
3530 @itemize @bullet
3531 @item @b{Debug Target} A CPU TAP can be used as a GDB debug target.
3532 @item @b{Flash Programming} Some chips program the flash directly via JTAG.
3533 Others do it indirectly, making a CPU do it.
3534 @item @b{Program Download} Using the same CPU support GDB uses,
3535 you can initialize a DRAM controller, download code to DRAM, and then
3536 start running that code.
3537 @item @b{Boundary Scan} Most chips support boundary scan, which
3538 helps test for board assembly problems like solder bridges
3539 and missing connections.
3540 @end itemize
3542 OpenOCD must know about the active TAPs on your board(s).
3543 Setting up the TAPs is the core task of your configuration files.
3544 Once those TAPs are set up, you can pass their names to code
3545 which sets up CPUs and exports them as GDB targets,
3546 probes flash memory, performs low-level JTAG operations, and more.
3548 @section Scan Chains
3549 @cindex scan chain
3551 TAPs are part of a hardware @dfn{scan chain},
3552 which is a daisy chain of TAPs.
3553 They also need to be added to
3554 OpenOCD's software mirror of that hardware list,
3555 giving each member a name and associating other data with it.
3556 Simple scan chains, with a single TAP, are common in
3557 systems with a single microcontroller or microprocessor.
3558 More complex chips may have several TAPs internally.
3559 Very complex scan chains might have a dozen or more TAPs:
3560 several in one chip, more in the next, and connecting
3561 to other boards with their own chips and TAPs.
3563 You can display the list with the @command{scan_chain} command.
3564 (Don't confuse this with the list displayed by the @command{targets}
3565 command, presented in the next chapter.
3566 That only displays TAPs for CPUs which are configured as
3567 debugging targets.)
3568 Here's what the scan chain might look like for a chip more than one TAP:
3570 @verbatim
3571 TapName Enabled IdCode Expected IrLen IrCap IrMask
3572 -- ------------------ ------- ---------- ---------- ----- ----- ------
3573 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0x01 0x03
3574 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x01 0x0f
3575 2 omap5912.unknown Y 0x00000000 0x00000000 8 0x01 0x03
3576 @end verbatim
3578 OpenOCD can detect some of that information, but not all
3579 of it. @xref{autoprobing,,Autoprobing}.
3580 Unfortunately, those TAPs can't always be autoconfigured,
3581 because not all devices provide good support for that.
3582 JTAG doesn't require supporting IDCODE instructions, and
3583 chips with JTAG routers may not link TAPs into the chain
3584 until they are told to do so.
3586 The configuration mechanism currently supported by OpenOCD
3587 requires explicit configuration of all TAP devices using
3588 @command{jtag newtap} commands, as detailed later in this chapter.
3589 A command like this would declare one tap and name it @code{chip1.cpu}:
3591 @example
3592 jtag newtap chip1 cpu -irlen 4 -expected-id 0x3ba00477
3593 @end example
3595 Each target configuration file lists the TAPs provided
3596 by a given chip.
3597 Board configuration files combine all the targets on a board,
3598 and so forth.
3599 Note that @emph{the order in which TAPs are declared is very important.}
3600 That declaration order must match the order in the JTAG scan chain,
3601 both inside a single chip and between them.
3602 @xref{faqtaporder,,FAQ TAP Order}.
3604 For example, the ST Microsystems STR912 chip has
3605 three separate TAPs@footnote{See the ST
3606 document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
3607 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
3608 @url{http://eu.st.com/stonline/products/literature/ds/13495.pdf}}.
3609 To configure those taps, @file{target/str912.cfg}
3610 includes commands something like this:
3612 @example
3613 jtag newtap str912 flash ... params ...
3614 jtag newtap str912 cpu ... params ...
3615 jtag newtap str912 bs ... params ...
3616 @end example
3618 Actual config files typically use a variable such as @code{$_CHIPNAME}
3619 instead of literals like @option{str912}, to support more than one chip
3620 of each type. @xref{Config File Guidelines}.
3622 @deffn Command {jtag names}
3623 Returns the names of all current TAPs in the scan chain.
3624 Use @command{jtag cget} or @command{jtag tapisenabled}
3625 to examine attributes and state of each TAP.
3626 @example
3627 foreach t [jtag names] @{
3628 puts [format "TAP: %s\n" $t]
3629 @}
3630 @end example
3631 @end deffn
3633 @deffn Command {scan_chain}
3634 Displays the TAPs in the scan chain configuration,
3635 and their status.
3636 The set of TAPs listed by this command is fixed by
3637 exiting the OpenOCD configuration stage,
3638 but systems with a JTAG router can
3639 enable or disable TAPs dynamically.
3640 @end deffn
3642 @c FIXME! "jtag cget" should be able to return all TAP
3643 @c attributes, like "$target_name cget" does for targets.
3645 @c Probably want "jtag eventlist", and a "tap-reset" event
3646 @c (on entry to RESET state).
3648 @section TAP Names
3649 @cindex dotted name
3651 When TAP objects are declared with @command{jtag newtap},
3652 a @dfn{dotted.name} is created for the TAP, combining the
3653 name of a module (usually a chip) and a label for the TAP.
3654 For example: @code{xilinx.tap}, @code{str912.flash},
3655 @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
3656 Many other commands use that dotted.name to manipulate or
3657 refer to the TAP. For example, CPU configuration uses the
3658 name, as does declaration of NAND or NOR flash banks.
3660 The components of a dotted name should follow ``C'' symbol
3661 name rules: start with an alphabetic character, then numbers
3662 and underscores are OK; while others (including dots!) are not.
3664 @section TAP Declaration Commands
3666 @c shouldn't this be(come) a {Config Command}?
3667 @deffn Command {jtag newtap} chipname tapname configparams...
3668 Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
3669 and configured according to the various @var{configparams}.
3671 The @var{chipname} is a symbolic name for the chip.
3672 Conventionally target config files use @code{$_CHIPNAME},
3673 defaulting to the model name given by the chip vendor but
3674 overridable.
3676 @cindex TAP naming convention
3677 The @var{tapname} reflects the role of that TAP,
3678 and should follow this convention:
3680 @itemize @bullet
3681 @item @code{bs} -- For boundary scan if this is a separate TAP;
3682 @item @code{cpu} -- The main CPU of the chip, alternatively
3683 @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
3684 @code{arm1} and @code{arm2} on chips with two ARMs, and so forth;
3685 @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
3686 @item @code{flash} -- If the chip has a flash TAP, like the str912;
3687 @item @code{jrc} -- For JTAG route controller (example: the ICEPick modules
3688 on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
3689 @item @code{tap} -- Should be used only for FPGA- or CPLD-like devices
3690 with a single TAP;
3691 @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
3692 @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
3693 For example, the Freescale i.MX31 has a SDMA (Smart DMA) with
3694 a JTAG TAP; that TAP should be named @code{sdma}.
3695 @end itemize
3697 Every TAP requires at least the following @var{configparams}:
3699 @itemize @bullet
3700 @item @code{-irlen} @var{NUMBER}
3701 @*The length in bits of the
3702 instruction register, such as 4 or 5 bits.
3703 @end itemize
3705 A TAP may also provide optional @var{configparams}:
3707 @itemize @bullet
3708 @item @code{-disable} (or @code{-enable})
3709 @*Use the @code{-disable} parameter to flag a TAP which is not
3710 linked into the scan chain after a reset using either TRST
3711 or the JTAG state machine's @sc{reset} state.
3712 You may use @code{-enable} to highlight the default state
3713 (the TAP is linked in).
3714 @xref{enablinganddisablingtaps,,Enabling and Disabling TAPs}.
3715 @item @code{-expected-id} @var{NUMBER}
3716 @*A non-zero @var{number} represents a 32-bit IDCODE
3717 which you expect to find when the scan chain is examined.
3718 These codes are not required by all JTAG devices.
3719 @emph{Repeat the option} as many times as required if more than one
3720 ID code could appear (for example, multiple versions).
3721 Specify @var{number} as zero to suppress warnings about IDCODE
3722 values that were found but not included in the list.
3724 Provide this value if at all possible, since it lets OpenOCD
3725 tell when the scan chain it sees isn't right. These values
3726 are provided in vendors' chip documentation, usually a technical
3727 reference manual. Sometimes you may need to probe the JTAG
3728 hardware to find these values.
3729 @xref{autoprobing,,Autoprobing}.
3730 @item @code{-ignore-version}
3731 @*Specify this to ignore the JTAG version field in the @code{-expected-id}
3732 option. When vendors put out multiple versions of a chip, or use the same
3733 JTAG-level ID for several largely-compatible chips, it may be more practical
3734 to ignore the version field than to update config files to handle all of
3735 the various chip IDs. The version field is defined as bit 28-31 of the IDCODE.
3736 @item @code{-ircapture} @var{NUMBER}
3737 @*The bit pattern loaded by the TAP into the JTAG shift register
3738 on entry to the @sc{ircapture} state, such as 0x01.
3739 JTAG requires the two LSBs of this value to be 01.
3740 By default, @code{-ircapture} and @code{-irmask} are set
3741 up to verify that two-bit value. You may provide
3742 additional bits if you know them, or indicate that
3743 a TAP doesn't conform to the JTAG specification.
3744 @item @code{-irmask} @var{NUMBER}
3745 @*A mask used with @code{-ircapture}
3746 to verify that instruction scans work correctly.
3747 Such scans are not used by OpenOCD except to verify that
3748 there seems to be no problems with JTAG scan chain operations.
3749 @end itemize
3750 @end deffn
3752 @section Other TAP commands
3754 @deffn Command {jtag cget} dotted.name @option{-event} event_name
3755 @deffnx Command {jtag configure} dotted.name @option{-event} event_name handler
3756 At this writing this TAP attribute
3757 mechanism is used only for event handling.
3758 (It is not a direct analogue of the @code{cget}/@code{configure}
3759 mechanism for debugger targets.)
3760 See the next section for information about the available events.
3762 The @code{configure} subcommand assigns an event handler,
3763 a TCL string which is evaluated when the event is triggered.
3764 The @code{cget} subcommand returns that handler.
3765 @end deffn
3767 @section TAP Events
3768 @cindex events
3769 @cindex TAP events
3771 OpenOCD includes two event mechanisms.
3772 The one presented here applies to all JTAG TAPs.
3773 The other applies to debugger targets,
3774 which are associated with certain TAPs.
3776 The TAP events currently defined are:
3778 @itemize @bullet
3779 @item @b{post-reset}
3780 @* The TAP has just completed a JTAG reset.
3781 The tap may still be in the JTAG @sc{reset} state.
3782 Handlers for these events might perform initialization sequences
3783 such as issuing TCK cycles, TMS sequences to ensure
3784 exit from the ARM SWD mode, and more.
3786 Because the scan chain has not yet been verified, handlers for these events
3787 @emph{should not issue commands which scan the JTAG IR or DR registers}
3788 of any particular target.
3789 @b{NOTE:} As this is written (September 2009), nothing prevents such access.
3790 @item @b{setup}
3791 @* The scan chain has been reset and verified.
3792 This handler may enable TAPs as needed.
3793 @item @b{tap-disable}
3794 @* The TAP needs to be disabled. This handler should
3795 implement @command{jtag tapdisable}
3796 by issuing the relevant JTAG commands.
3797 @item @b{tap-enable}
3798 @* The TAP needs to be enabled. This handler should
3799 implement @command{jtag tapenable}
3800 by issuing the relevant JTAG commands.
3801 @end itemize
3803 If you need some action after each JTAG reset which isn't actually
3804 specific to any TAP (since you can't yet trust the scan chain's
3805 contents to be accurate), you might:
3807 @example
3808 jtag configure CHIP.jrc -event post-reset @{
3809 echo "JTAG Reset done"
3810 ... non-scan jtag operations to be done after reset
3811 @}
3812 @end example
3815 @anchor{enablinganddisablingtaps}
3816 @section Enabling and Disabling TAPs
3817 @cindex JTAG Route Controller
3818 @cindex jrc
3820 In some systems, a @dfn{JTAG Route Controller} (JRC)
3821 is used to enable and/or disable specific JTAG TAPs.
3822 Many ARM-based chips from Texas Instruments include
3823 an ``ICEPick'' module, which is a JRC.
3824 Such chips include DaVinci and OMAP3 processors.
3826 A given TAP may not be visible until the JRC has been
3827 told to link it into the scan chain; and if the JRC
3828 has been told to unlink that TAP, it will no longer
3829 be visible.
3830 Such routers address problems that JTAG ``bypass mode''
3831 ignores, such as:
3833 @itemize
3834 @item The scan chain can only go as fast as its slowest TAP.
3835 @item Having many TAPs slows instruction scans, since all
3836 TAPs receive new instructions.
3837 @item TAPs in the scan chain must be powered up, which wastes
3838 power and prevents debugging some power management mechanisms.
3839 @end itemize
3841 The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
3842 as implied by the existence of JTAG routers.
3843 However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
3844 does include a kind of JTAG router functionality.
3846 @c (a) currently the event handlers don't seem to be able to
3847 @c fail in a way that could lead to no-change-of-state.
3849 In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
3850 shown below, and is implemented using TAP event handlers.
3851 So for example, when defining a TAP for a CPU connected to
3852 a JTAG router, your @file{target.cfg} file
3853 should define TAP event handlers using
3854 code that looks something like this:
3856 @example
3857 jtag configure CHIP.cpu -event tap-enable @{
3858 ... jtag operations using CHIP.jrc
3859 @}
3860 jtag configure CHIP.cpu -event tap-disable @{
3861 ... jtag operations using CHIP.jrc
3862 @}
3863 @end example
3865 Then you might want that CPU's TAP enabled almost all the time:
3867 @example
3868 jtag configure $CHIP.jrc -event setup "jtag tapenable $CHIP.cpu"
3869 @end example
3871 Note how that particular setup event handler declaration
3872 uses quotes to evaluate @code{$CHIP} when the event is configured.
3873 Using brackets @{ @} would cause it to be evaluated later,
3874 at runtime, when it might have a different value.
3876 @deffn Command {jtag tapdisable} dotted.name
3877 If necessary, disables the tap
3878 by sending it a @option{tap-disable} event.
3879 Returns the string "1" if the tap
3880 specified by @var{dotted.name} is enabled,
3881 and "0" if it is disabled.
3882 @end deffn
3884 @deffn Command {jtag tapenable} dotted.name
3885 If necessary, enables the tap
3886 by sending it a @option{tap-enable} event.
3887 Returns the string "1" if the tap
3888 specified by @var{dotted.name} is enabled,
3889 and "0" if it is disabled.
3890 @end deffn
3892 @deffn Command {jtag tapisenabled} dotted.name
3893 Returns the string "1" if the tap
3894 specified by @var{dotted.name} is enabled,
3895 and "0" if it is disabled.
3897 @quotation Note
3898 Humans will find the @command{scan_chain} command more helpful
3899 for querying the state of the JTAG taps.
3900 @end quotation
3901 @end deffn
3903 @anchor{autoprobing}
3904 @section Autoprobing
3905 @cindex autoprobe
3906 @cindex JTAG autoprobe
3908 TAP configuration is the first thing that needs to be done
3909 after interface and reset configuration. Sometimes it's
3910 hard finding out what TAPs exist, or how they are identified.
3911 Vendor documentation is not always easy to find and use.
3913 To help you get past such problems, OpenOCD has a limited
3914 @emph{autoprobing} ability to look at the scan chain, doing
3915 a @dfn{blind interrogation} and then reporting the TAPs it finds.
3916 To use this mechanism, start the OpenOCD server with only data
3917 that configures your JTAG interface, and arranges to come up
3918 with a slow clock (many devices don't support fast JTAG clocks
3919 right when they come out of reset).
3921 For example, your @file{openocd.cfg} file might have:
3923 @example
3924 source [find interface/olimex-arm-usb-tiny-h.cfg]
3925 reset_config trst_and_srst
3926 jtag_rclk 8
3927 @end example
3929 When you start the server without any TAPs configured, it will
3930 attempt to autoconfigure the TAPs. There are two parts to this:
3932 @enumerate
3933 @item @emph{TAP discovery} ...
3934 After a JTAG reset (sometimes a system reset may be needed too),
3935 each TAP's data registers will hold the contents of either the
3936 IDCODE or BYPASS register.
3937 If JTAG communication is working, OpenOCD will see each TAP,
3938 and report what @option{-expected-id} to use with it.
3939 @item @emph{IR Length discovery} ...
3940 Unfortunately JTAG does not provide a reliable way to find out
3941 the value of the @option{-irlen} parameter to use with a TAP
3942 that is discovered.
3943 If OpenOCD can discover the length of a TAP's instruction
3944 register, it will report it.
3945 Otherwise you may need to consult vendor documentation, such
3946 as chip data sheets or BSDL files.
3947 @end enumerate
3949 In many cases your board will have a simple scan chain with just
3950 a single device. Here's what OpenOCD reported with one board
3951 that's a bit more complex:
3953 @example
3954 clock speed 8 kHz
3955 There are no enabled taps. AUTO PROBING MIGHT NOT WORK!!
3956 AUTO auto0.tap - use "jtag newtap auto0 tap -expected-id 0x2b900f0f ..."
3957 AUTO auto1.tap - use "jtag newtap auto1 tap -expected-id 0x07926001 ..."
3958 AUTO auto2.tap - use "jtag newtap auto2 tap -expected-id 0x0b73b02f ..."
3959 AUTO auto0.tap - use "... -irlen 4"
3960 AUTO auto1.tap - use "... -irlen 4"
3961 AUTO auto2.tap - use "... -irlen 6"
3962 no gdb ports allocated as no target has been specified
3963 @end example
3965 Given that information, you should be able to either find some existing
3966 config files to use, or create your own. If you create your own, you
3967 would configure from the bottom up: first a @file{target.cfg} file
3968 with these TAPs, any targets associated with them, and any on-chip
3969 resources; then a @file{board.cfg} with off-chip resources, clocking,
3970 and so forth.
3972 @node CPU Configuration
3973 @chapter CPU Configuration
3974 @cindex GDB target
3976 This chapter discusses how to set up GDB debug targets for CPUs.
3977 You can also access these targets without GDB
3978 (@pxref{Architecture and Core Commands},
3979 and @ref{targetstatehandling,,Target State handling}) and
3980 through various kinds of NAND and NOR flash commands.
3981 If you have multiple CPUs you can have multiple such targets.
3983 We'll start by looking at how to examine the targets you have,
3984 then look at how to add one more target and how to configure it.
3986 @section Target List
3987 @cindex target, current
3988 @cindex target, list
3990 All targets that have been set up are part of a list,
3991 where each member has a name.
3992 That name should normally be the same as the TAP name.
3993 You can display the list with the @command{targets}
3994 (plural!) command.
3995 This display often has only one CPU; here's what it might
3996 look like with more than one:
3997 @verbatim
3998 TargetName Type Endian TapName State
3999 -- ------------------ ---------- ------ ------------------ ------------
4000 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
4001 1 MyTarget cortex_m little mychip.foo tap-disabled
4002 @end verbatim
4004 One member of that list is the @dfn{current target}, which
4005 is implicitly referenced by many commands.
4006 It's the one marked with a @code{*} near the target name.
4007 In particular, memory addresses often refer to the address
4008 space seen by that current target.
4009 Commands like @command{mdw} (memory display words)
4010 and @command{flash erase_address} (erase NOR flash blocks)
4011 are examples; and there are many more.
4013 Several commands let you examine the list of targets:
4015 @deffn Command {target current}
4016 Returns the name of the current target.
4017 @end deffn
4019 @deffn Command {target names}
4020 Lists the names of all current targets in the list.
4021 @example
4022 foreach t [target names] @{
4023 puts [format "Target: %s\n" $t]
4024 @}
4025 @end example
4026 @end deffn
4028 @c yep, "target list" would have been better.
4029 @c plus maybe "target setdefault".
4031 @deffn Command targets [name]
4032 @emph{Note: the name of this command is plural. Other target
4033 command names are singular.}
4035 With no parameter, this command displays a table of all known
4036 targets in a user friendly form.
4038 With a parameter, this command sets the current target to
4039 the given target with the given @var{name}; this is
4040 only relevant on boards which have more than one target.
4041 @end deffn
4043 @section Target CPU Types
4044 @cindex target type
4045 @cindex CPU type
4047 Each target has a @dfn{CPU type}, as shown in the output of
4048 the @command{targets} command. You need to specify that type
4049 when calling @command{target create}.
4050 The CPU type indicates more than just the instruction set.
4051 It also indicates how that instruction set is implemented,
4052 what kind of debug support it integrates,
4053 whether it has an MMU (and if so, what kind),
4054 what core-specific commands may be available
4055 (@pxref{Architecture and Core Commands}),
4056 and more.
4058 It's easy to see what target types are supported,
4059 since there's a command to list them.
4061 @anchor{targettypes}
4062 @deffn Command {target types}
4063 Lists all supported target types.
4064 At this writing, the supported CPU types are:
4066 @itemize @bullet
4067 @item @code{arm11} -- this is a generation of ARMv6 cores
4068 @item @code{arm720t} -- this is an ARMv4 core with an MMU
4069 @item @code{arm7tdmi} -- this is an ARMv4 core
4070 @item @code{arm920t} -- this is an ARMv4 core with an MMU
4071 @item @code{arm926ejs} -- this is an ARMv5 core with an MMU
4072 @item @code{arm966e} -- this is an ARMv5 core
4073 @item @code{arm9tdmi} -- this is an ARMv4 core
4074 @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
4075 (Support for this is preliminary and incomplete.)
4076 @item @code{cortex_a} -- this is an ARMv7 core with an MMU
4077 @item @code{cortex_m} -- this is an ARMv7 core, supporting only the
4078 compact Thumb2 instruction set.
4079 @item @code{aarch64} -- this is an ARMv8-A core with an MMU
4080 @item @code{dragonite} -- resembles arm966e
4081 @item @code{dsp563xx} -- implements Freescale's 24-bit DSP.
4082 (Support for this is still incomplete.)
4083 @item @code{fa526} -- resembles arm920 (w/o Thumb)
4084 @item @code{feroceon} -- resembles arm926
4085 @item @code{mips_m4k} -- a MIPS core
4086 @item @code{xscale} -- this is actually an architecture,
4087 not a CPU type. It is based on the ARMv5 architecture.
4088 @item @code{openrisc} -- this is an OpenRISC 1000 core.
4089 The current implementation supports three JTAG TAP cores:
4090 @item @code{ls1_sap} -- this is the SAP on NXP LS102x CPUs,
4091 allowing access to physical memory addresses independently of CPU cores.
4092 @itemize @minus
4093 @item @code{OpenCores TAP} (See: @url{http://opencores.org/project,jtag})
4094 @item @code{Altera Virtual JTAG TAP} (See: @url{http://www.altera.com/literature/ug/ug_virtualjtag.pdf})
4095 @item @code{Xilinx BSCAN_* virtual JTAG interface} (See: @url{http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_2/spartan6_hdl.pdf})
4096 @end itemize
4097 And two debug interfaces cores:
4098 @itemize @minus
4099 @item @code{Advanced debug interface} (See: @url{http://opencores.org/project,adv_debug_sys})
4100 @item @code{SoC Debug Interface} (See: @url{http://opencores.org/project,dbg_interface})
4101 @end itemize
4102 @end itemize
4103 @end deffn
4105 To avoid being confused by the variety of ARM based cores, remember
4106 this key point: @emph{ARM is a technology licencing company}.
4107 (See: @url{http://www.arm.com}.)
4108 The CPU name used by OpenOCD will reflect the CPU design that was
4109 licenced, not a vendor brand which incorporates that design.
4110 Name prefixes like arm7, arm9, arm11, and cortex
4111 reflect design generations;
4112 while names like ARMv4, ARMv5, ARMv6, ARMv7 and ARMv8
4113 reflect an architecture version implemented by a CPU design.
4115 @anchor{targetconfiguration}
4116 @section Target Configuration
4118 Before creating a ``target'', you must have added its TAP to the scan chain.
4119 When you've added that TAP, you will have a @code{dotted.name}
4120 which is used to set up the CPU support.
4121 The chip-specific configuration file will normally configure its CPU(s)
4122 right after it adds all of the chip's TAPs to the scan chain.
4124 Although you can set up a target in one step, it's often clearer if you
4125 use shorter commands and do it in two steps: create it, then configure
4126 optional parts.
4127 All operations on the target after it's created will use a new
4128 command, created as part of target creation.
4130 The two main things to configure after target creation are
4131 a work area, which usually has target-specific defaults even
4132 if the board setup code overrides them later;
4133 and event handlers (@pxref{targetevents,,Target Events}), which tend
4134 to be much more board-specific.
4135 The key steps you use might look something like this
4137 @example
4138 target create MyTarget cortex_m -chain-position mychip.cpu
4139 $MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
4140 $MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
4141 $MyTarget configure -event reset-init @{ myboard_reinit @}
4142 @end example
4144 You should specify a working area if you can; typically it uses some
4145 on-chip SRAM.
4146 Such a working area can speed up many things, including bulk
4147 writes to target memory;
4148 flash operations like checking to see if memory needs to be erased;
4149 GDB memory checksumming;
4150 and more.
4152 @quotation Warning
4153 On more complex chips, the work area can become
4154 inaccessible when application code
4155 (such as an operating system)
4156 enables or disables the MMU.
4157 For example, the particular MMU context used to acess the virtual
4158 address will probably matter ... and that context might not have
4159 easy access to other addresses needed.
4160 At this writing, OpenOCD doesn't have much MMU intelligence.
4161 @end quotation
4163 It's often very useful to define a @code{reset-init} event handler.
4164 For systems that are normally used with a boot loader,
4165 common tasks include updating clocks and initializing memory
4166 controllers.
4167 That may be needed to let you write the boot loader into flash,
4168 in order to ``de-brick'' your board; or to load programs into
4169 external DDR memory without having run the boot loader.
4171 @deffn Command {target create} target_name type configparams...
4172 This command creates a GDB debug target that refers to a specific JTAG tap.
4173 It enters that target into a list, and creates a new
4174 command (@command{@var{target_name}}) which is used for various
4175 purposes including additional configuration.
4177 @itemize @bullet
4178 @item @var{target_name} ... is the name of the debug target.