[openocd.git] / doc / openocd.texi
1 \input texinfo @c -*-texinfo-*-
2 @c %**start of header
3 @setfilename openocd.info
4 @settitle OpenOCD User's Guide
5 @dircategory Development
6 @direntry
7 * OpenOCD: (openocd). OpenOCD User's Guide
8 @end direntry
9 @paragraphindent 0
10 @c %**end of header
12 @include version.texi
14 @copying
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
21 @itemize @bullet
22 @item Copyright @copyright{} 2008 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk}
24 @item Copyright @copyright{} 2008-2010 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
26 @item Copyright @copyright{} 2009-2010 David Brownell
27 @end itemize
29 @quotation
30 Permission is granted to copy, distribute and/or modify this document
31 under the terms of the GNU Free Documentation License, Version 1.2 or
32 any later version published by the Free Software Foundation; with no
33 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
34 Texts. A copy of the license is included in the section entitled ``GNU
35 Free Documentation License''.
36 @end quotation
37 @end copying
39 @titlepage
40 @titlefont{@emph{Open On-Chip Debugger:}}
41 @sp 1
42 @title OpenOCD User's Guide
43 @subtitle for release @value{VERSION}
44 @subtitle @value{UPDATED}
46 @page
47 @vskip 0pt plus 1filll
48 @insertcopying
49 @end titlepage
51 @summarycontents
52 @contents
54 @ifnottex
55 @node Top
56 @top OpenOCD User's Guide
58 @insertcopying
59 @end ifnottex
61 @menu
62 * About:: About OpenOCD
63 * Developers:: OpenOCD Developer Resources
64 * Debug Adapter Hardware:: Debug Adapter Hardware
65 * About Jim-Tcl:: About Jim-Tcl
66 * Running:: Running OpenOCD
67 * OpenOCD Project Setup:: OpenOCD Project Setup
68 * Config File Guidelines:: Config File Guidelines
69 * Daemon Configuration:: Daemon Configuration
70 * Debug Adapter Configuration:: Debug Adapter Configuration
71 * Reset Configuration:: Reset Configuration
72 * TAP Declaration:: TAP Declaration
73 * CPU Configuration:: CPU Configuration
74 * Flash Commands:: Flash Commands
75 * Flash Programming:: Flash Programming
76 * NAND Flash Commands:: NAND Flash Commands
77 * PLD/FPGA Commands:: PLD/FPGA Commands
78 * General Commands:: General Commands
79 * Architecture and Core Commands:: Architecture and Core Commands
80 * JTAG Commands:: JTAG Commands
81 * Boundary Scan Commands:: Boundary Scan Commands
82 * TFTP:: TFTP
83 * GDB and OpenOCD:: Using GDB and OpenOCD
84 * Tcl Scripting API:: Tcl Scripting API
85 * FAQ:: Frequently Asked Questions
86 * Tcl Crash Course:: Tcl Crash Course
87 * License:: GNU Free Documentation License
89 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
90 @comment case issue with ``Index.html'' and ``index.html''
91 @comment Occurs when creating ``--html --no-split'' output
92 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
93 * OpenOCD Concept Index:: Concept Index
94 * Command and Driver Index:: Command and Driver Index
95 @end menu
97 @node About
98 @unnumbered About
99 @cindex about
101 OpenOCD was created by Dominic Rath as part of a diploma thesis written at the
102 University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
103 Since that time, the project has grown into an active open-source project,
104 supported by a diverse community of software and hardware developers from
105 around the world.
107 @section What is OpenOCD?
108 @cindex TAP
109 @cindex JTAG
111 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
112 in-system programming and boundary-scan testing for embedded target
113 devices.
115 It does so with the assistance of a @dfn{debug adapter}, which is
116 a small hardware module which helps provide the right kind of
117 electrical signaling to the target being debugged. These are
118 required since the debug host (on which OpenOCD runs) won't
119 usually have native support for such signaling, or the connector
120 needed to hook up to the target.
122 Such debug adapters support one or more @dfn{transport} protocols,
123 each of which involves different electrical signaling (and uses
124 different messaging protocols on top of that signaling). There
125 are many types of debug adapter, and little uniformity in what
126 they are called. (There are also product naming differences.)
128 These adapters are sometimes packaged as discrete dongles, which
129 may generically be called @dfn{hardware interface dongles}.
130 Some development boards also integrate them directly, which may
131 let the development board can be directly connected to the debug
132 host over USB (and sometimes also to power it over USB).
134 For example, a @dfn{JTAG Adapter} supports JTAG
135 signaling, and is used to communicate
136 with JTAG (IEEE 1149.1) compliant TAPs on your target board.
137 A @dfn{TAP} is a ``Test Access Port'', a module which processes
138 special instructions and data. TAPs are daisy-chained within and
139 between chips and boards. JTAG supports debugging and boundary
140 scan operations.
142 There are also @dfn{SWD Adapters} that support Serial Wire Debug (SWD)
143 signaling to communicate with some newer ARM cores, as well as debug
144 adapters which support both JTAG and SWD transports. SWD only supports
145 debugging, whereas JTAG also supports boundary scan operations.
147 For some chips, there are also @dfn{Programming Adapters} supporting
148 special transports used only to write code to flash memory, without
149 support for on-chip debugging or boundary scan.
150 (At this writing, OpenOCD does not support such non-debug adapters.)
153 @b{Dongles:} OpenOCD currently supports many types of hardware dongles: USB
154 based, parallel port based, and other standalone boxes that run
155 OpenOCD internally. @xref{Debug Adapter Hardware}.
157 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
158 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x) and
159 Cortex-M3 (Stellaris LM3, ST STM32 and Energy Micro EFM32) based cores to be
160 debugged via the GDB protocol.
162 @b{Flash Programing:} Flash writing is supported for external CFI
163 compatible NOR flashes (Intel and AMD/Spansion command set) and several
164 internal flashes (LPC1700, LPC1800, LPC2000, LPC4300, AT91SAM7, AT91SAM3U,
165 STR7x, STR9x, LM3, STM32x and EFM32). Preliminary support for various NAND flash
166 controllers (LPC3180, Orion, S3C24xx, more) controller is included.
168 @section OpenOCD Web Site
170 The OpenOCD web site provides the latest public news from the community:
172 @uref{http://openocd.sourceforge.net/}
174 @section Latest User's Guide:
176 The user's guide you are now reading may not be the latest one
177 available. A version for more recent code may be available.
178 Its HTML form is published regularly at:
180 @uref{http://openocd.sourceforge.net/doc/html/index.html}
182 PDF form is likewise published at:
184 @uref{http://openocd.sourceforge.net/doc/pdf/openocd.pdf}
186 @section OpenOCD User's Forum
188 There is an OpenOCD forum (phpBB) hosted by SparkFun,
189 which might be helpful to you. Note that if you want
190 anything to come to the attention of developers, you
191 should post it to the OpenOCD Developer Mailing List
192 instead of this forum.
194 @uref{http://forum.sparkfun.com/viewforum.php?f=18}
196 @section OpenOCD User's Mailing List
198 The OpenOCD User Mailing List provides the primary means of
199 communication between users:
201 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-user}
203 @section OpenOCD IRC
205 Support can also be found on irc:
206 @uref{irc://irc.freenode.net/openocd}
208 @node Developers
209 @chapter OpenOCD Developer Resources
210 @cindex developers
212 If you are interested in improving the state of OpenOCD's debugging and
213 testing support, new contributions will be welcome. Motivated developers
214 can produce new target, flash or interface drivers, improve the
215 documentation, as well as more conventional bug fixes and enhancements.
217 The resources in this chapter are available for developers wishing to explore
218 or expand the OpenOCD source code.
220 @section OpenOCD GIT Repository
222 During the 0.3.x release cycle, OpenOCD switched from Subversion to
223 a GIT repository hosted at SourceForge. The repository URL is:
225 @uref{git://git.code.sf.net/p/openocd/code}
227 or via http
229 @uref{http://git.code.sf.net/p/openocd/code}
231 You may prefer to use a mirror and the HTTP protocol:
233 @uref{http://repo.or.cz/r/openocd.git}
235 With standard GIT tools, use @command{git clone} to initialize
236 a local repository, and @command{git pull} to update it.
237 There are also gitweb pages letting you browse the repository
238 with a web browser, or download arbitrary snapshots without
239 needing a GIT client:
241 @uref{http://repo.or.cz/w/openocd.git}
243 The @file{README} file contains the instructions for building the project
244 from the repository or a snapshot.
246 Developers that want to contribute patches to the OpenOCD system are
247 @b{strongly} encouraged to work against mainline.
248 Patches created against older versions may require additional
249 work from their submitter in order to be updated for newer releases.
251 @section Doxygen Developer Manual
253 During the 0.2.x release cycle, the OpenOCD project began
254 providing a Doxygen reference manual. This document contains more
255 technical information about the software internals, development
256 processes, and similar documentation:
258 @uref{http://openocd.sourceforge.net/doc/doxygen/html/index.html}
260 This document is a work-in-progress, but contributions would be welcome
261 to fill in the gaps. All of the source files are provided in-tree,
262 listed in the Doxyfile configuration in the top of the source tree.
264 @section OpenOCD Developer Mailing List
266 The OpenOCD Developer Mailing List provides the primary means of
267 communication between developers:
269 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-devel}
271 Discuss and submit patches to this list.
272 The @file{HACKING} file contains basic information about how
273 to prepare patches.
275 @section OpenOCD Bug Database
277 During the 0.4.x release cycle the OpenOCD project team began
278 using Trac for its bug database:
280 @uref{https://sourceforge.net/apps/trac/openocd}
283 @node Debug Adapter Hardware
284 @chapter Debug Adapter Hardware
285 @cindex dongles
286 @cindex FTDI
287 @cindex wiggler
288 @cindex zy1000
289 @cindex printer port
290 @cindex USB Adapter
291 @cindex RTCK
293 Defined: @b{dongle}: A small device that plugins into a computer and serves as
294 an adapter .... [snip]
296 In the OpenOCD case, this generally refers to @b{a small adapter} that
297 attaches to your computer via USB or the Parallel Printer Port. One
298 exception is the Zylin ZY1000, packaged as a small box you attach via
299 an ethernet cable. The Zylin ZY1000 has the advantage that it does not
300 require any drivers to be installed on the developer PC. It also has
301 a built in web interface. It supports RTCK/RCLK or adaptive clocking
302 and has a built in relay to power cycle targets remotely.
305 @section Choosing a Dongle
307 There are several things you should keep in mind when choosing a dongle.
309 @enumerate
310 @item @b{Transport} Does it support the kind of communication that you need?
311 OpenOCD focusses mostly on JTAG. Your version may also support
312 other ways to communicate with target devices.
313 @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
314 Does your dongle support it? You might need a level converter.
315 @item @b{Pinout} What pinout does your target board use?
316 Does your dongle support it? You may be able to use jumper
317 wires, or an "octopus" connector, to convert pinouts.
318 @item @b{Connection} Does your computer have the USB, printer, or
319 Ethernet port needed?
320 @item @b{RTCK} Do you expect to use it with ARM chips and boards with
321 RTCK support? Also known as ``adaptive clocking''
322 @end enumerate
324 @section Stand alone Systems
326 @b{ZY1000} See: @url{http://www.ultsol.com/index.php/component/content/article/8/33-zylin-zy1000-jtag-probe}
327 Technically, not a dongle, but a standalone box. The ZY1000 has the advantage that it does
328 not require any drivers installed on the developer PC. It also has
329 a built in web interface. It supports RTCK/RCLK or adaptive clocking
330 and has a built in relay to power cycle targets remotely.
332 @section USB FT2232 Based
334 There are many USB JTAG dongles on the market, many of them are based
335 on a chip from ``Future Technology Devices International'' (FTDI)
336 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
337 See: @url{http://www.ftdichip.com} for more information.
338 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
339 chips are starting to become available in JTAG adapters. Around 2012 a new
340 variant appeared - FT232H - this is a single-channel version of FT2232H.
341 (Adapters using those high speed FT2232H or FT232H chips may support adaptive
342 clocking.)
344 The FT2232 chips are flexible enough to support some other
345 transport options, such as SWD or the SPI variants used to
346 program some chips. They have two communications channels,
347 and one can be used for a UART adapter at the same time the
348 other one is used to provide a debug adapter.
350 Also, some development boards integrate an FT2232 chip to serve as
351 a built-in low cost debug adapter and usb-to-serial solution.
353 @itemize @bullet
354 @item @b{usbjtag}
355 @* Link @url{http://elk.informatik.fh-augsburg.de/hhweb/doc/openocd/usbjtag/usbjtag.html}
356 @item @b{jtagkey}
357 @* See: @url{http://www.amontec.com/jtagkey.shtml}
358 @item @b{jtagkey2}
359 @* See: @url{http://www.amontec.com/jtagkey2.shtml}
360 @item @b{oocdlink}
361 @* See: @url{http://www.oocdlink.com} By Joern Kaipf
362 @item @b{signalyzer}
363 @* See: @url{http://www.signalyzer.com}
364 @item @b{Stellaris Eval Boards}
365 @* See: @url{http://www.ti.com} - The Stellaris eval boards
366 bundle FT2232-based JTAG and SWD support, which can be used to debug
367 the Stellaris chips. Using separate JTAG adapters is optional.
368 These boards can also be used in a "pass through" mode as JTAG adapters
369 to other target boards, disabling the Stellaris chip.
370 @item @b{TI/Luminary ICDI}
371 @* See: @url{http://www.ti.com} - TI/Luminary In-Circuit Debug
372 Interface (ICDI) Boards are included in Stellaris LM3S9B9x
373 Evaluation Kits. Like the non-detachable FT2232 support on the other
374 Stellaris eval boards, they can be used to debug other target boards.
375 @item @b{olimex-jtag}
376 @* See: @url{http://www.olimex.com}
377 @item @b{Flyswatter/Flyswatter2}
378 @* See: @url{http://www.tincantools.com}
379 @item @b{turtelizer2}
380 @* See:
381 @uref{http://www.ethernut.de/en/hardware/turtelizer/index.html, Turtelizer 2}, or
382 @url{http://www.ethernut.de}
383 @item @b{comstick}
384 @* Link: @url{http://www.hitex.com/index.php?id=383}
385 @item @b{stm32stick}
386 @* Link @url{http://www.hitex.com/stm32-stick}
387 @item @b{axm0432_jtag}
388 @* Axiom AXM-0432 Link @url{http://www.axman.com} - NOTE: This JTAG does not appear
389 to be available anymore as of April 2012.
390 @item @b{cortino}
391 @* Link @url{http://www.hitex.com/index.php?id=cortino}
392 @item @b{dlp-usb1232h}
393 @* Link @url{http://www.dlpdesign.com/usb/usb1232h.shtml}
394 @item @b{digilent-hs1}
395 @* Link @url{http://www.digilentinc.com/Products/Detail.cfm?Prod=JTAG-HS1}
396 @item @b{opendous}
397 @* Link @url{http://code.google.com/p/opendous/wiki/JTAG} FT2232H-based
398 (OpenHardware).
399 @item @b{JTAG-lock-pick Tiny 2}
400 @* Link @url{http://www.distortec.com/jtag-lock-pick-tiny-2} FT232H-based
401 @end itemize
403 @section USB-JTAG / Altera USB-Blaster compatibles
405 These devices also show up as FTDI devices, but are not
406 protocol-compatible with the FT2232 devices. They are, however,
407 protocol-compatible among themselves. USB-JTAG devices typically consist
408 of a FT245 followed by a CPLD that understands a particular protocol,
409 or emulate this protocol using some other hardware.
411 They may appear under different USB VID/PID depending on the particular
412 product. The driver can be configured to search for any VID/PID pair
413 (see the section on driver commands).
415 @itemize
416 @item @b{USB-JTAG} Kolja Waschk's USB Blaster-compatible adapter
417 @* Link: @url{http://ixo-jtag.sourceforge.net/}
418 @item @b{Altera USB-Blaster}
419 @* Link: @url{http://www.altera.com/literature/ug/ug_usb_blstr.pdf}
420 @end itemize
422 @section USB JLINK based
423 There are several OEM versions of the Segger @b{JLINK} adapter. It is
424 an example of a micro controller based JTAG adapter, it uses an
425 AT91SAM764 internally.
427 @itemize @bullet
428 @item @b{ATMEL SAMICE} Only works with ATMEL chips!
429 @* Link: @url{http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3892}
430 @item @b{SEGGER JLINK}
431 @* Link: @url{http://www.segger.com/jlink.html}
432 @item @b{IAR J-Link}
433 @* Link: @url{http://www.iar.com/en/products/hardware-debug-probes/iar-j-link/}
434 @end itemize
436 @section USB RLINK based
437 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer,
438 permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for
439 SWD and not JTAG, thus not supported.
441 @itemize @bullet
442 @item @b{Raisonance RLink}
443 @* Link: @url{http://www.mcu-raisonance.com/~rlink-debugger-programmer__microcontrollers__tool~tool__T018:4cn9ziz4bnx6.html}
444 @item @b{STM32 Primer}
445 @* Link: @url{http://www.stm32circle.com/resources/stm32primer.php}
446 @item @b{STM32 Primer2}
447 @* Link: @url{http://www.stm32circle.com/resources/stm32primer2.php}
448 @end itemize
450 @section USB ST-LINK based
451 ST Micro has an adapter called @b{ST-LINK}.
452 They only work with ST Micro chips, notably STM32 and STM8.
454 @itemize @bullet
455 @item @b{ST-LINK}
456 @* This is available standalone and as part of some kits, eg. STM32VLDISCOVERY.
457 @* Link: @url{http://www.st.com/internet/evalboard/product/219866.jsp}
458 @item @b{ST-LINK/V2}
459 @* This is available standalone and as part of some kits, eg. STM32F4DISCOVERY.
460 @* Link: @url{http://www.st.com/internet/evalboard/product/251168.jsp}
461 @end itemize
463 For info the original ST-LINK enumerates using the mass storage usb class, however
464 it's implementation is completely broken. The result is this causes issues under linux.
465 The simplest solution is to get linux to ignore the ST-LINK using one of the following methods:
466 @itemize @bullet
467 @item modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i
468 @item add "options usb-storage quirks=483:3744:i" to /etc/modprobe.conf
469 @end itemize
471 @section USB TI/Stellaris ICDI based
472 Texas Instruments has an adapter called @b{ICDI}.
473 It is not to be confused with the FTDI based adapters that were originally fitted to their
474 evaluation boards. This is the adapter fitted to the Stellaris LaunchPad.
476 @section USB Other
477 @itemize @bullet
478 @item @b{USBprog}
479 @* Link: @url{http://shop.embedded-projects.net/} - which uses an Atmel MEGA32 and a UBN9604
481 @item @b{USB - Presto}
482 @* Link: @url{http://tools.asix.net/prg_presto.htm}
484 @item @b{Versaloon-Link}
485 @* Link: @url{http://www.versaloon.com}
487 @item @b{ARM-JTAG-EW}
488 @* Link: @url{http://www.olimex.com/dev/arm-jtag-ew.html}
490 @item @b{Buspirate}
491 @* Link: @url{http://dangerousprototypes.com/bus-pirate-manual/}
493 @item @b{opendous}
494 @* Link: @url{http://code.google.com/p/opendous-jtag/} - which uses an AT90USB162
496 @item @b{estick}
497 @* Link: @url{http://code.google.com/p/estick-jtag/}
499 @item @b{Keil ULINK v1}
500 @* Link: @url{http://www.keil.com/ulink1/}
501 @end itemize
503 @section IBM PC Parallel Printer Port Based
505 The two well known ``JTAG Parallel Ports'' cables are the Xilnx DLC5
506 and the Macraigor Wiggler. There are many clones and variations of
507 these on the market.
509 Note that parallel ports are becoming much less common, so if you
510 have the choice you should probably avoid these adapters in favor
511 of USB-based ones.
513 @itemize @bullet
515 @item @b{Wiggler} - There are many clones of this.
516 @* Link: @url{http://www.macraigor.com/wiggler.htm}
518 @item @b{DLC5} - From XILINX - There are many clones of this
519 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
520 produced, PDF schematics are easily found and it is easy to make.
522 @item @b{Amontec - JTAG Accelerator}
523 @* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
525 @item @b{GW16402}
526 @* Link: @url{http://www.gateworks.com/products/avila_accessories/gw16042.php}
528 @item @b{Wiggler2}
529 @* Link: @url{http://www.ccac.rwth-aachen.de/~michaels/index.php/hardware/armjtag}
531 @item @b{Wiggler_ntrst_inverted}
532 @* Yet another variation - See the source code, src/jtag/parport.c
534 @item @b{old_amt_wiggler}
535 @* Unknown - probably not on the market today
537 @item @b{arm-jtag}
538 @* Link: Most likely @url{http://www.olimex.com/dev/arm-jtag.html} [another wiggler clone]
540 @item @b{chameleon}
541 @* Link: @url{http://www.amontec.com/chameleon.shtml}
543 @item @b{Triton}
544 @* Unknown.
546 @item @b{Lattice}
547 @* ispDownload from Lattice Semiconductor
548 @url{http://www.latticesemi.com/lit/docs/@/devtools/dlcable.pdf}
550 @item @b{flashlink}
551 @* From ST Microsystems;
552 @* Link: @url{http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/DATA_BRIEF/DM00039500.pdf}
554 @end itemize
556 @section Other...
557 @itemize @bullet
559 @item @b{ep93xx}
560 @* An EP93xx based Linux machine using the GPIO pins directly.
562 @item @b{at91rm9200}
563 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
565 @end itemize
567 @node About Jim-Tcl
568 @chapter About Jim-Tcl
569 @cindex Jim-Tcl
570 @cindex tcl
572 OpenOCD uses a small ``Tcl Interpreter'' known as Jim-Tcl.
573 This programming language provides a simple and extensible
574 command interpreter.
576 All commands presented in this Guide are extensions to Jim-Tcl.
577 You can use them as simple commands, without needing to learn
578 much of anything about Tcl.
579 Alternatively, can write Tcl programs with them.
581 You can learn more about Jim at its website, @url{http://jim.berlios.de}.
582 There is an active and responsive community, get on the mailing list
583 if you have any questions. Jim-Tcl maintainers also lurk on the
584 OpenOCD mailing list.
586 @itemize @bullet
587 @item @b{Jim vs. Tcl}
588 @* Jim-Tcl is a stripped down version of the well known Tcl language,
589 which can be found here: @url{http://www.tcl.tk}. Jim-Tcl has far
590 fewer features. Jim-Tcl is several dozens of .C files and .H files and
591 implements the basic Tcl command set. In contrast: Tcl 8.6 is a
592 4.2 MB .zip file containing 1540 files.
594 @item @b{Missing Features}
595 @* Our practice has been: Add/clone the real Tcl feature if/when
596 needed. We welcome Jim-Tcl improvements, not bloat. Also there
597 are a large number of optional Jim-Tcl features that are not
598 enabled in OpenOCD.
600 @item @b{Scripts}
601 @* OpenOCD configuration scripts are Jim-Tcl Scripts. OpenOCD's
602 command interpreter today is a mixture of (newer)
603 Jim-Tcl commands, and (older) the orginal command interpreter.
605 @item @b{Commands}
606 @* At the OpenOCD telnet command line (or via the GDB monitor command) one
607 can type a Tcl for() loop, set variables, etc.
608 Some of the commands documented in this guide are implemented
609 as Tcl scripts, from a @file{startup.tcl} file internal to the server.
611 @item @b{Historical Note}
612 @* Jim-Tcl was introduced to OpenOCD in spring 2008. Fall 2010,
613 before OpenOCD 0.5 release OpenOCD switched to using Jim Tcl
614 as a git submodule, which greatly simplified upgrading Jim Tcl
615 to benefit from new features and bugfixes in Jim Tcl.
617 @item @b{Need a crash course in Tcl?}
618 @*@xref{Tcl Crash Course}.
619 @end itemize
621 @node Running
622 @chapter Running
623 @cindex command line options
624 @cindex logfile
625 @cindex directory search
627 Properly installing OpenOCD sets up your operating system to grant it access
628 to the debug adapters. On Linux, this usually involves installing a file
629 in @file{/etc/udev/rules.d,} so OpenOCD has permissions. MS-Windows needs
630 complex and confusing driver configuration for every peripheral. Such issues
631 are unique to each operating system, and are not detailed in this User's Guide.
633 Then later you will invoke the OpenOCD server, with various options to
634 tell it how each debug session should work.
635 The @option{--help} option shows:
636 @verbatim
637 bash$ openocd --help
639 --help | -h display this help
640 --version | -v display OpenOCD version
641 --file | -f use configuration file <name>
642 --search | -s dir to search for config files and scripts
643 --debug | -d set debug level <0-3>
644 --log_output | -l redirect log output to file <name>
645 --command | -c run <command>
646 @end verbatim
648 If you don't give any @option{-f} or @option{-c} options,
649 OpenOCD tries to read the configuration file @file{openocd.cfg}.
650 To specify one or more different
651 configuration files, use @option{-f} options. For example:
653 @example
654 openocd -f config1.cfg -f config2.cfg -f config3.cfg
655 @end example
657 Configuration files and scripts are searched for in
658 @enumerate
659 @item the current directory,
660 @item any search dir specified on the command line using the @option{-s} option,
661 @item any search dir specified using the @command{add_script_search_dir} command,
662 @item @file{$HOME/.openocd} (not on Windows),
663 @item the site wide script library @file{$pkgdatadir/site} and
664 @item the OpenOCD-supplied script library @file{$pkgdatadir/scripts}.
665 @end enumerate
666 The first found file with a matching file name will be used.
668 @quotation Note
669 Don't try to use configuration script names or paths which
670 include the "#" character. That character begins Tcl comments.
671 @end quotation
673 @section Simple setup, no customization
675 In the best case, you can use two scripts from one of the script
676 libraries, hook up your JTAG adapter, and start the server ... and
677 your JTAG setup will just work "out of the box". Always try to
678 start by reusing those scripts, but assume you'll need more
679 customization even if this works. @xref{OpenOCD Project Setup}.
681 If you find a script for your JTAG adapter, and for your board or
682 target, you may be able to hook up your JTAG adapter then start
683 the server like:
685 @example
686 openocd -f interface/ADAPTER.cfg -f board/MYBOARD.cfg
687 @end example
689 You might also need to configure which reset signals are present,
690 using @option{-c 'reset_config trst_and_srst'} or something similar.
691 If all goes well you'll see output something like
693 @example
694 Open On-Chip Debugger 0.4.0 (2010-01-14-15:06)
695 For bug reports, read
696 http://openocd.sourceforge.net/doc/doxygen/bugs.html
697 Info : JTAG tap: lm3s.cpu tap/device found: 0x3ba00477
698 (mfg: 0x23b, part: 0xba00, ver: 0x3)
699 @end example
701 Seeing that "tap/device found" message, and no warnings, means
702 the JTAG communication is working. That's a key milestone, but
703 you'll probably need more project-specific setup.
705 @section What OpenOCD does as it starts
707 OpenOCD starts by processing the configuration commands provided
708 on the command line or, if there were no @option{-c command} or
709 @option{-f file.cfg} options given, in @file{openocd.cfg}.
710 @xref{configurationstage,,Configuration Stage}.
711 At the end of the configuration stage it verifies the JTAG scan
712 chain defined using those commands; your configuration should
713 ensure that this always succeeds.
714 Normally, OpenOCD then starts running as a daemon.
715 Alternatively, commands may be used to terminate the configuration
716 stage early, perform work (such as updating some flash memory),
717 and then shut down without acting as a daemon.
719 Once OpenOCD starts running as a daemon, it waits for connections from
720 clients (Telnet, GDB, Other) and processes the commands issued through
721 those channels.
723 If you are having problems, you can enable internal debug messages via
724 the @option{-d} option.
726 Also it is possible to interleave Jim-Tcl commands w/config scripts using the
727 @option{-c} command line switch.
729 To enable debug output (when reporting problems or working on OpenOCD
730 itself), use the @option{-d} command line switch. This sets the
731 @option{debug_level} to "3", outputting the most information,
732 including debug messages. The default setting is "2", outputting only
733 informational messages, warnings and errors. You can also change this
734 setting from within a telnet or gdb session using @command{debug_level<n>}
735 (@pxref{debuglevel,,debug_level}).
737 You can redirect all output from the daemon to a file using the
738 @option{-l <logfile>} switch.
740 Note! OpenOCD will launch the GDB & telnet server even if it can not
741 establish a connection with the target. In general, it is possible for
742 the JTAG controller to be unresponsive until the target is set up
743 correctly via e.g. GDB monitor commands in a GDB init script.
745 @node OpenOCD Project Setup
746 @chapter OpenOCD Project Setup
748 To use OpenOCD with your development projects, you need to do more than
749 just connecting the JTAG adapter hardware (dongle) to your development board
750 and then starting the OpenOCD server.
751 You also need to configure that server so that it knows
752 about that adapter and board, and helps your work.
753 You may also want to connect OpenOCD to GDB, possibly
754 using Eclipse or some other GUI.
756 @section Hooking up the JTAG Adapter
758 Today's most common case is a dongle with a JTAG cable on one side
759 (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
760 and a USB cable on the other.
761 Instead of USB, some cables use Ethernet;
762 older ones may use a PC parallel port, or even a serial port.
764 @enumerate
765 @item @emph{Start with power to your target board turned off},
766 and nothing connected to your JTAG adapter.
767 If you're particularly paranoid, unplug power to the board.
768 It's important to have the ground signal properly set up,
769 unless you are using a JTAG adapter which provides
770 galvanic isolation between the target board and the
771 debugging host.
773 @item @emph{Be sure it's the right kind of JTAG connector.}
774 If your dongle has a 20-pin ARM connector, you need some kind
775 of adapter (or octopus, see below) to hook it up to
776 boards using 14-pin or 10-pin connectors ... or to 20-pin
777 connectors which don't use ARM's pinout.
779 In the same vein, make sure the voltage levels are compatible.
780 Not all JTAG adapters have the level shifters needed to work
781 with 1.2 Volt boards.
783 @item @emph{Be certain the cable is properly oriented} or you might
784 damage your board. In most cases there are only two possible
785 ways to connect the cable.
786 Connect the JTAG cable from your adapter to the board.
787 Be sure it's firmly connected.
789 In the best case, the connector is keyed to physically
790 prevent you from inserting it wrong.
791 This is most often done using a slot on the board's male connector
792 housing, which must match a key on the JTAG cable's female connector.
793 If there's no housing, then you must look carefully and
794 make sure pin 1 on the cable hooks up to pin 1 on the board.
795 Ribbon cables are frequently all grey except for a wire on one
796 edge, which is red. The red wire is pin 1.
798 Sometimes dongles provide cables where one end is an ``octopus'' of
799 color coded single-wire connectors, instead of a connector block.
800 These are great when converting from one JTAG pinout to another,
801 but are tedious to set up.
802 Use these with connector pinout diagrams to help you match up the
803 adapter signals to the right board pins.
805 @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
806 A USB, parallel, or serial port connector will go to the host which
807 you are using to run OpenOCD.
808 For Ethernet, consult the documentation and your network administrator.
810 For USB based JTAG adapters you have an easy sanity check at this point:
811 does the host operating system see the JTAG adapter? If that host is an
812 MS-Windows host, you'll need to install a driver before OpenOCD works.
814 @item @emph{Connect the adapter's power supply, if needed.}
815 This step is primarily for non-USB adapters,
816 but sometimes USB adapters need extra power.
818 @item @emph{Power up the target board.}
819 Unless you just let the magic smoke escape,
820 you're now ready to set up the OpenOCD server
821 so you can use JTAG to work with that board.
823 @end enumerate
825 Talk with the OpenOCD server using
826 telnet (@code{telnet localhost 4444} on many systems) or GDB.
827 @xref{GDB and OpenOCD}.
829 @section Project Directory
831 There are many ways you can configure OpenOCD and start it up.
833 A simple way to organize them all involves keeping a
834 single directory for your work with a given board.
835 When you start OpenOCD from that directory,
836 it searches there first for configuration files, scripts,
837 files accessed through semihosting,
838 and for code you upload to the target board.
839 It is also the natural place to write files,
840 such as log files and data you download from the board.
842 @section Configuration Basics
844 There are two basic ways of configuring OpenOCD, and
845 a variety of ways you can mix them.
846 Think of the difference as just being how you start the server:
848 @itemize
849 @item Many @option{-f file} or @option{-c command} options on the command line
850 @item No options, but a @dfn{user config file}
851 in the current directory named @file{openocd.cfg}
852 @end itemize
854 Here is an example @file{openocd.cfg} file for a setup
855 using a Signalyzer FT2232-based JTAG adapter to talk to
856 a board with an Atmel AT91SAM7X256 microcontroller:
858 @example
859 source [find interface/signalyzer.cfg]
861 # GDB can also flash my flash!
862 gdb_memory_map enable
863 gdb_flash_program enable
865 source [find target/sam7x256.cfg]
866 @end example
868 Here is the command line equivalent of that configuration:
870 @example
871 openocd -f interface/signalyzer.cfg \
872 -c "gdb_memory_map enable" \
873 -c "gdb_flash_program enable" \
874 -f target/sam7x256.cfg
875 @end example
877 You could wrap such long command lines in shell scripts,
878 each supporting a different development task.
879 One might re-flash the board with a specific firmware version.
880 Another might set up a particular debugging or run-time environment.
882 @quotation Important
883 At this writing (October 2009) the command line method has
884 problems with how it treats variables.
885 For example, after @option{-c "set VAR value"}, or doing the
886 same in a script, the variable @var{VAR} will have no value
887 that can be tested in a later script.
888 @end quotation
890 Here we will focus on the simpler solution: one user config
891 file, including basic configuration plus any TCL procedures
892 to simplify your work.
894 @section User Config Files
895 @cindex config file, user
896 @cindex user config file
897 @cindex config file, overview
899 A user configuration file ties together all the parts of a project
900 in one place.
901 One of the following will match your situation best:
903 @itemize
904 @item Ideally almost everything comes from configuration files
905 provided by someone else.
906 For example, OpenOCD distributes a @file{scripts} directory
907 (probably in @file{/usr/share/openocd/scripts} on Linux).
908 Board and tool vendors can provide these too, as can individual
909 user sites; the @option{-s} command line option lets you say
910 where to find these files. (@xref{Running}.)
911 The AT91SAM7X256 example above works this way.
913 Three main types of non-user configuration file each have their
914 own subdirectory in the @file{scripts} directory:
916 @enumerate
917 @item @b{interface} -- one for each different debug adapter;
918 @item @b{board} -- one for each different board
919 @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
920 @end enumerate
922 Best case: include just two files, and they handle everything else.
923 The first is an interface config file.
924 The second is board-specific, and it sets up the JTAG TAPs and
925 their GDB targets (by deferring to some @file{target.cfg} file),
926 declares all flash memory, and leaves you nothing to do except
927 meet your deadline:
929 @example
930 source [find interface/olimex-jtag-tiny.cfg]
931 source [find board/csb337.cfg]
932 @end example
934 Boards with a single microcontroller often won't need more
935 than the target config file, as in the AT91SAM7X256 example.
936 That's because there is no external memory (flash, DDR RAM), and
937 the board differences are encapsulated by application code.
939 @item Maybe you don't know yet what your board looks like to JTAG.
940 Once you know the @file{interface.cfg} file to use, you may
941 need help from OpenOCD to discover what's on the board.
942 Once you find the JTAG TAPs, you can just search for appropriate
943 target and board
944 configuration files ... or write your own, from the bottom up.
945 @xref{autoprobing,,Autoprobing}.
947 @item You can often reuse some standard config files but
948 need to write a few new ones, probably a @file{board.cfg} file.
949 You will be using commands described later in this User's Guide,
950 and working with the guidelines in the next chapter.
952 For example, there may be configuration files for your JTAG adapter
953 and target chip, but you need a new board-specific config file
954 giving access to your particular flash chips.
955 Or you might need to write another target chip configuration file
956 for a new chip built around the Cortex M3 core.
958 @quotation Note
959 When you write new configuration files, please submit
960 them for inclusion in the next OpenOCD release.
961 For example, a @file{board/newboard.cfg} file will help the
962 next users of that board, and a @file{target/newcpu.cfg}
963 will help support users of any board using that chip.
964 @end quotation
966 @item
967 You may may need to write some C code.
968 It may be as simple as a supporting a new ft2232 or parport
969 based adapter; a bit more involved, like a NAND or NOR flash
970 controller driver; or a big piece of work like supporting
971 a new chip architecture.
972 @end itemize
974 Reuse the existing config files when you can.
975 Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
976 You may find a board configuration that's a good example to follow.
978 When you write config files, separate the reusable parts
979 (things every user of that interface, chip, or board needs)
980 from ones specific to your environment and debugging approach.
981 @itemize
983 @item
984 For example, a @code{gdb-attach} event handler that invokes
985 the @command{reset init} command will interfere with debugging
986 early boot code, which performs some of the same actions
987 that the @code{reset-init} event handler does.
989 @item
990 Likewise, the @command{arm9 vector_catch} command (or
991 @cindex vector_catch
992 its siblings @command{xscale vector_catch}
993 and @command{cortex_m vector_catch}) can be a timesaver
994 during some debug sessions, but don't make everyone use that either.
995 Keep those kinds of debugging aids in your user config file,
996 along with messaging and tracing setup.
997 (@xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.)
999 @item
1000 You might need to override some defaults.
1001 For example, you might need to move, shrink, or back up the target's
1002 work area if your application needs much SRAM.
1004 @item
1005 TCP/IP port configuration is another example of something which
1006 is environment-specific, and should only appear in
1007 a user config file. @xref{tcpipports,,TCP/IP Ports}.
1008 @end itemize
1010 @section Project-Specific Utilities
1012 A few project-specific utility
1013 routines may well speed up your work.
1014 Write them, and keep them in your project's user config file.
1016 For example, if you are making a boot loader work on a
1017 board, it's nice to be able to debug the ``after it's
1018 loaded to RAM'' parts separately from the finicky early
1019 code which sets up the DDR RAM controller and clocks.
1020 A script like this one, or a more GDB-aware sibling,
1021 may help:
1023 @example
1024 proc ramboot @{ @} @{
1025 # Reset, running the target's "reset-init" scripts
1026 # to initialize clocks and the DDR RAM controller.
1027 # Leave the CPU halted.
1028 reset init
1030 # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
1031 load_image u-boot.bin 0x20000000
1033 # Start running.
1034 resume 0x20000000
1035 @}
1036 @end example
1038 Then once that code is working you will need to make it
1039 boot from NOR flash; a different utility would help.
1040 Alternatively, some developers write to flash using GDB.
1041 (You might use a similar script if you're working with a flash
1042 based microcontroller application instead of a boot loader.)
1044 @example
1045 proc newboot @{ @} @{
1046 # Reset, leaving the CPU halted. The "reset-init" event
1047 # proc gives faster access to the CPU and to NOR flash;
1048 # "reset halt" would be slower.
1049 reset init
1051 # Write standard version of U-Boot into the first two
1052 # sectors of NOR flash ... the standard version should
1053 # do the same lowlevel init as "reset-init".
1054 flash protect 0 0 1 off
1055 flash erase_sector 0 0 1
1056 flash write_bank 0 u-boot.bin 0x0
1057 flash protect 0 0 1 on
1059 # Reboot from scratch using that new boot loader.
1060 reset run
1061 @}
1062 @end example
1064 You may need more complicated utility procedures when booting
1065 from NAND.
1066 That often involves an extra bootloader stage,
1067 running from on-chip SRAM to perform DDR RAM setup so it can load
1068 the main bootloader code (which won't fit into that SRAM).
1070 Other helper scripts might be used to write production system images,
1071 involving considerably more than just a three stage bootloader.
1073 @section Target Software Changes
1075 Sometimes you may want to make some small changes to the software
1076 you're developing, to help make JTAG debugging work better.
1077 For example, in C or assembly language code you might
1078 use @code{#ifdef JTAG_DEBUG} (or its converse) around code
1079 handling issues like:
1081 @itemize @bullet
1083 @item @b{Watchdog Timers}...
1084 Watchog timers are typically used to automatically reset systems if
1085 some application task doesn't periodically reset the timer. (The
1086 assumption is that the system has locked up if the task can't run.)
1087 When a JTAG debugger halts the system, that task won't be able to run
1088 and reset the timer ... potentially causing resets in the middle of
1089 your debug sessions.
1091 It's rarely a good idea to disable such watchdogs, since their usage
1092 needs to be debugged just like all other parts of your firmware.
1093 That might however be your only option.
1095 Look instead for chip-specific ways to stop the watchdog from counting
1096 while the system is in a debug halt state. It may be simplest to set
1097 that non-counting mode in your debugger startup scripts. You may however
1098 need a different approach when, for example, a motor could be physically
1099 damaged by firmware remaining inactive in a debug halt state. That might
1100 involve a type of firmware mode where that "non-counting" mode is disabled
1101 at the beginning then re-enabled at the end; a watchdog reset might fire
1102 and complicate the debug session, but hardware (or people) would be
1103 protected.@footnote{Note that many systems support a "monitor mode" debug
1104 that is a somewhat cleaner way to address such issues. You can think of
1105 it as only halting part of the system, maybe just one task,
1106 instead of the whole thing.
1107 At this writing, January 2010, OpenOCD based debugging does not support
1108 monitor mode debug, only "halt mode" debug.}
1110 @item @b{ARM Semihosting}...
1111 @cindex ARM semihosting
1112 When linked with a special runtime library provided with many
1113 toolchains@footnote{See chapter 8 "Semihosting" in
1114 @uref{http://infocenter.arm.com/help/topic/com.arm.doc.dui0203i/DUI0203I_rvct_developer_guide.pdf,
1115 ARM DUI 0203I}, the "RealView Compilation Tools Developer Guide".
1116 The CodeSourcery EABI toolchain also includes a semihosting library.},
1117 your target code can use I/O facilities on the debug host. That library
1118 provides a small set of system calls which are handled by OpenOCD.
1119 It can let the debugger provide your system console and a file system,
1120 helping with early debugging or providing a more capable environment
1121 for sometimes-complex tasks like installing system firmware onto
1122 NAND or SPI flash.
1124 @item @b{ARM Wait-For-Interrupt}...
1125 Many ARM chips synchronize the JTAG clock using the core clock.
1126 Low power states which stop that core clock thus prevent JTAG access.
1127 Idle loops in tasking environments often enter those low power states
1128 via the @code{WFI} instruction (or its coprocessor equivalent, before ARMv7).
1130 You may want to @emph{disable that instruction} in source code,
1131 or otherwise prevent using that state,
1132 to ensure you can get JTAG access at any time.@footnote{As a more
1133 polite alternative, some processors have special debug-oriented
1134 registers which can be used to change various features including
1135 how the low power states are clocked while debugging.
1136 The STM32 DBGMCU_CR register is an example; at the cost of extra
1137 power consumption, JTAG can be used during low power states.}
1138 For example, the OpenOCD @command{halt} command may not
1139 work for an idle processor otherwise.
1141 @item @b{Delay after reset}...
1142 Not all chips have good support for debugger access
1143 right after reset; many LPC2xxx chips have issues here.
1144 Similarly, applications that reconfigure pins used for
1145 JTAG access as they start will also block debugger access.
1147 To work with boards like this, @emph{enable a short delay loop}
1148 the first thing after reset, before "real" startup activities.
1149 For example, one second's delay is usually more than enough
1150 time for a JTAG debugger to attach, so that
1151 early code execution can be debugged
1152 or firmware can be replaced.
1154 @item @b{Debug Communications Channel (DCC)}...
1155 Some processors include mechanisms to send messages over JTAG.
1156 Many ARM cores support these, as do some cores from other vendors.
1157 (OpenOCD may be able to use this DCC internally, speeding up some
1158 operations like writing to memory.)
1160 Your application may want to deliver various debugging messages
1161 over JTAG, by @emph{linking with a small library of code}
1162 provided with OpenOCD and using the utilities there to send
1163 various kinds of message.
1164 @xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.
1166 @end itemize
1168 @section Target Hardware Setup
1170 Chip vendors often provide software development boards which
1171 are highly configurable, so that they can support all options
1172 that product boards may require. @emph{Make sure that any
1173 jumpers or switches match the system configuration you are
1174 working with.}
1176 Common issues include:
1178 @itemize @bullet
1180 @item @b{JTAG setup} ...
1181 Boards may support more than one JTAG configuration.
1182 Examples include jumpers controlling pullups versus pulldowns
1183 on the nTRST and/or nSRST signals, and choice of connectors
1184 (e.g. which of two headers on the base board,
1185 or one from a daughtercard).
1186 For some Texas Instruments boards, you may need to jumper the
1187 EMU0 and EMU1 signals (which OpenOCD won't currently control).
1189 @item @b{Boot Modes} ...
1190 Complex chips often support multiple boot modes, controlled
1191 by external jumpers. Make sure this is set up correctly.
1192 For example many i.MX boards from NXP need to be jumpered
1193 to "ATX mode" to start booting using the on-chip ROM, when
1194 using second stage bootloader code stored in a NAND flash chip.
1196 Such explicit configuration is common, and not limited to
1197 booting from NAND. You might also need to set jumpers to
1198 start booting using code loaded from an MMC/SD card; external
1199 SPI flash; Ethernet, UART, or USB links; NOR flash; OneNAND
1200 flash; some external host; or various other sources.
1203 @item @b{Memory Addressing} ...
1204 Boards which support multiple boot modes may also have jumpers
1205 to configure memory addressing. One board, for example, jumpers
1206 external chipselect 0 (used for booting) to address either
1207 a large SRAM (which must be pre-loaded via JTAG), NOR flash,
1208 or NAND flash. When it's jumpered to address NAND flash, that
1209 board must also be told to start booting from on-chip ROM.
1211 Your @file{board.cfg} file may also need to be told this jumper
1212 configuration, so that it can know whether to declare NOR flash
1213 using @command{flash bank} or instead declare NAND flash with
1214 @command{nand device}; and likewise which probe to perform in
1215 its @code{reset-init} handler.
1217 A closely related issue is bus width. Jumpers might need to
1218 distinguish between 8 bit or 16 bit bus access for the flash
1219 used to start booting.
1221 @item @b{Peripheral Access} ...
1222 Development boards generally provide access to every peripheral
1223 on the chip, sometimes in multiple modes (such as by providing
1224 multiple audio codec chips).
1225 This interacts with software
1226 configuration of pin multiplexing, where for example a
1227 given pin may be routed either to the MMC/SD controller
1228 or the GPIO controller. It also often interacts with
1229 configuration jumpers. One jumper may be used to route
1230 signals to an MMC/SD card slot or an expansion bus (which
1231 might in turn affect booting); others might control which
1232 audio or video codecs are used.
1234 @end itemize
1236 Plus you should of course have @code{reset-init} event handlers
1237 which set up the hardware to match that jumper configuration.
1238 That includes in particular any oscillator or PLL used to clock
1239 the CPU, and any memory controllers needed to access external
1240 memory and peripherals. Without such handlers, you won't be
1241 able to access those resources without working target firmware
1242 which can do that setup ... this can be awkward when you're
1243 trying to debug that target firmware. Even if there's a ROM
1244 bootloader which handles a few issues, it rarely provides full
1245 access to all board-specific capabilities.
1248 @node Config File Guidelines
1249 @chapter Config File Guidelines
1251 This chapter is aimed at any user who needs to write a config file,
1252 including developers and integrators of OpenOCD and any user who
1253 needs to get a new board working smoothly.
1254 It provides guidelines for creating those files.
1256 You should find the following directories under @t{$(INSTALLDIR)/scripts},
1257 with files including the ones listed here.
1258 Use them as-is where you can; or as models for new files.
1259 @itemize @bullet
1260 @item @file{interface} ...
1261 These are for debug adapters.
1262 Files that configure JTAG adapters go here.
1263 @example
1264 $ ls interface -R
1265 interface/:
1266 altera-usb-blaster.cfg hilscher_nxhx50_re.cfg openocd-usb-hs.cfg
1267 arm-jtag-ew.cfg hitex_str9-comstick.cfg openrd.cfg
1268 at91rm9200.cfg icebear.cfg osbdm.cfg
1269 axm0432.cfg jlink.cfg parport.cfg
1270 busblaster.cfg jtagkey2.cfg parport_dlc5.cfg
1271 buspirate.cfg jtagkey2p.cfg redbee-econotag.cfg
1272 calao-usb-a9260-c01.cfg jtagkey.cfg redbee-usb.cfg
1273 calao-usb-a9260-c02.cfg jtagkey-tiny.cfg rlink.cfg
1274 calao-usb-a9260.cfg jtag-lock-pick_tiny_2.cfg sheevaplug.cfg
1275 chameleon.cfg kt-link.cfg signalyzer.cfg
1276 cortino.cfg lisa-l.cfg signalyzer-h2.cfg
1277 digilent-hs1.cfg luminary.cfg signalyzer-h4.cfg
1278 dlp-usb1232h.cfg luminary-icdi.cfg signalyzer-lite.cfg
1279 dummy.cfg luminary-lm3s811.cfg stlink-v1.cfg
1280 estick.cfg minimodule.cfg stlink-v2.cfg
1281 flashlink.cfg neodb.cfg stm32-stick.cfg
1282 flossjtag.cfg ngxtech.cfg sysfsgpio-raspberrypi.cfg
1283 flossjtag-noeeprom.cfg olimex-arm-usb-ocd.cfg ti-icdi.cfg
1284 flyswatter2.cfg olimex-arm-usb-ocd-h.cfg turtelizer2.cfg
1285 flyswatter.cfg olimex-arm-usb-tiny-h.cfg ulink.cfg
1286 ftdi olimex-jtag-tiny.cfg usb-jtag.cfg
1287 hilscher_nxhx10_etm.cfg oocdlink.cfg usbprog.cfg
1288 hilscher_nxhx500_etm.cfg opendous.cfg vpaclink.cfg
1289 hilscher_nxhx500_re.cfg opendous_ftdi.cfg vsllink.cfg
1290 hilscher_nxhx50_etm.cfg openocd-usb.cfg xds100v2.cfg
1292 interface/ftdi:
1293 axm0432.cfg icebear.cfg oocdlink.cfg
1294 calao-usb-a9260-c01.cfg jtagkey2.cfg opendous_ftdi.cfg
1295 calao-usb-a9260-c02.cfg jtagkey2p.cfg openocd-usb.cfg
1296 cortino.cfg jtagkey.cfg openocd-usb-hs.cfg
1297 dlp-usb1232h.cfg jtag-lock-pick_tiny_2.cfg openrd.cfg
1298 dp_busblaster.cfg kt-link.cfg redbee-econotag.cfg
1299 flossjtag.cfg lisa-l.cfg redbee-usb.cfg
1300 flossjtag-noeeprom.cfg luminary.cfg sheevaplug.cfg
1301 flyswatter2.cfg luminary-icdi.cfg signalyzer.cfg
1302 flyswatter.cfg luminary-lm3s811.cfg signalyzer-lite.cfg
1303 hilscher_nxhx10_etm.cfg minimodule.cfg stm32-stick.cfg
1304 hilscher_nxhx500_etm.cfg neodb.cfg turtelizer2-revB.cfg
1305 hilscher_nxhx500_re.cfg ngxtech.cfg turtelizer2-revC.cfg
1306 hilscher_nxhx50_etm.cfg olimex-arm-usb-ocd.cfg vpaclink.cfg
1307 hilscher_nxhx50_re.cfg olimex-arm-usb-ocd-h.cfg xds100v2.cfg
1308 hitex_lpc1768stick.cfg olimex-arm-usb-tiny-h.cfg
1309 hitex_str9-comstick.cfg olimex-jtag-tiny.cfg
1310 $
1311 @end example
1312 @item @file{board} ...
1313 think Circuit Board, PWA, PCB, they go by many names. Board files
1314 contain initialization items that are specific to a board.
1315 They reuse target configuration files, since the same
1316 microprocessor chips are used on many boards,
1317 but support for external parts varies widely. For
1318 example, the SDRAM initialization sequence for the board, or the type
1319 of external flash and what address it uses. Any initialization
1320 sequence to enable that external flash or SDRAM should be found in the
1321 board file. Boards may also contain multiple targets: two CPUs; or
1322 a CPU and an FPGA.
1323 @example
1324 $ ls board
1325 actux3.cfg lpc1850_spifi_generic.cfg
1326 am3517evm.cfg lpc4350_spifi_generic.cfg
1327 arm_evaluator7t.cfg lubbock.cfg
1328 at91cap7a-stk-sdram.cfg mcb1700.cfg
1329 at91eb40a.cfg microchip_explorer16.cfg
1330 at91rm9200-dk.cfg mini2440.cfg
1331 at91rm9200-ek.cfg mini6410.cfg
1332 at91sam9261-ek.cfg netgear-dg834v3.cfg
1333 at91sam9263-ek.cfg olimex_LPC2378STK.cfg
1334 at91sam9g20-ek.cfg olimex_lpc_h2148.cfg
1335 atmel_at91sam7s-ek.cfg olimex_sam7_ex256.cfg
1336 atmel_at91sam9260-ek.cfg olimex_sam9_l9260.cfg
1337 atmel_at91sam9rl-ek.cfg olimex_stm32_h103.cfg
1338 atmel_sam3n_ek.cfg olimex_stm32_h107.cfg
1339 atmel_sam3s_ek.cfg olimex_stm32_p107.cfg
1340 atmel_sam3u_ek.cfg omap2420_h4.cfg
1341 atmel_sam3x_ek.cfg open-bldc.cfg
1342 atmel_sam4s_ek.cfg openrd.cfg
1343 balloon3-cpu.cfg osk5912.cfg
1344 colibri.cfg phone_se_j100i.cfg
1345 crossbow_tech_imote2.cfg phytec_lpc3250.cfg
1346 csb337.cfg pic-p32mx.cfg
1347 csb732.cfg propox_mmnet1001.cfg
1348 da850evm.cfg pxa255_sst.cfg
1349 digi_connectcore_wi-9c.cfg redbee.cfg
1350 diolan_lpc4350-db1.cfg rsc-w910.cfg
1351 dm355evm.cfg sheevaplug.cfg
1352 dm365evm.cfg smdk6410.cfg
1353 dm6446evm.cfg spear300evb.cfg
1354 efikamx.cfg spear300evb_mod.cfg
1355 eir.cfg spear310evb20.cfg
1356 ek-lm3s1968.cfg spear310evb20_mod.cfg
1357 ek-lm3s3748.cfg spear320cpu.cfg
1358 ek-lm3s6965.cfg spear320cpu_mod.cfg
1359 ek-lm3s811.cfg steval_pcc010.cfg
1360 ek-lm3s811-revb.cfg stm320518_eval_stlink.cfg
1361 ek-lm3s8962.cfg stm32100b_eval.cfg
1362 ek-lm3s9b9x.cfg stm3210b_eval.cfg
1363 ek-lm3s9d92.cfg stm3210c_eval.cfg
1364 ek-lm4f120xl.cfg stm3210e_eval.cfg
1365 ek-lm4f232.cfg stm3220g_eval.cfg
1366 embedded-artists_lpc2478-32.cfg stm3220g_eval_stlink.cfg
1367 ethernut3.cfg stm3241g_eval.cfg
1368 glyn_tonga2.cfg stm3241g_eval_stlink.cfg
1369 hammer.cfg stm32f0discovery.cfg
1370 hilscher_nxdb500sys.cfg stm32f3discovery.cfg
1371 hilscher_nxeb500hmi.cfg stm32f4discovery.cfg
1372 hilscher_nxhx10.cfg stm32ldiscovery.cfg
1373 hilscher_nxhx500.cfg stm32vldiscovery.cfg
1374 hilscher_nxhx50.cfg str910-eval.cfg
1375 hilscher_nxsb100.cfg telo.cfg
1376 hitex_lpc1768stick.cfg ti_am335xevm.cfg
1377 hitex_lpc2929.cfg ti_beagleboard.cfg
1378 hitex_stm32-performancestick.cfg ti_beagleboard_xm.cfg
1379 hitex_str9-comstick.cfg ti_beaglebone.cfg
1380 iar_lpc1768.cfg ti_blaze.cfg
1381 iar_str912_sk.cfg ti_pandaboard.cfg
1382 icnova_imx53_sodimm.cfg ti_pandaboard_es.cfg
1383 icnova_sam9g45_sodimm.cfg topas910.cfg
1384 imx27ads.cfg topasa900.cfg
1385 imx27lnst.cfg twr-k60f120m.cfg
1386 imx28evk.cfg twr-k60n512.cfg
1387 imx31pdk.cfg tx25_stk5.cfg
1388 imx35pdk.cfg tx27_stk5.cfg
1389 imx53loco.cfg unknown_at91sam9260.cfg
1390 keil_mcb1700.cfg uptech_2410.cfg
1391 keil_mcb2140.cfg verdex.cfg
1392 kwikstik.cfg voipac.cfg
1393 linksys_nslu2.cfg voltcraft_dso-3062c.cfg
1394 lisa-l.cfg x300t.cfg
1395 logicpd_imx27.cfg zy1000.cfg
1396 $
1397 @end example
1398 @item @file{target} ...
1399 think chip. The ``target'' directory represents the JTAG TAPs
1400 on a chip
1401 which OpenOCD should control, not a board. Two common types of targets
1402 are ARM chips and FPGA or CPLD chips.
1403 When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
1404 the target config file defines all of them.
1405 @example
1406 $ ls target
1407 aduc702x.cfg lpc1763.cfg
1408 am335x.cfg lpc1764.cfg
1409 amdm37x.cfg lpc1765.cfg
1410 ar71xx.cfg lpc1766.cfg
1411 at32ap7000.cfg lpc1767.cfg
1412 at91r40008.cfg lpc1768.cfg
1413 at91rm9200.cfg lpc1769.cfg
1414 at91sam3ax_4x.cfg lpc1788.cfg
1415 at91sam3ax_8x.cfg lpc17xx.cfg
1416 at91sam3ax_xx.cfg lpc1850.cfg
1417 at91sam3nXX.cfg lpc2103.cfg
1418 at91sam3sXX.cfg lpc2124.cfg
1419 at91sam3u1c.cfg lpc2129.cfg
1420 at91sam3u1e.cfg lpc2148.cfg
1421 at91sam3u2c.cfg lpc2294.cfg
1422 at91sam3u2e.cfg lpc2378.cfg
1423 at91sam3u4c.cfg lpc2460.cfg
1424 at91sam3u4e.cfg lpc2478.cfg
1425 at91sam3uxx.cfg lpc2900.cfg
1426 at91sam3XXX.cfg lpc2xxx.cfg
1427 at91sam4sd32x.cfg lpc3131.cfg
1428 at91sam4sXX.cfg lpc3250.cfg
1429 at91sam4XXX.cfg lpc4350.cfg
1430 at91sam7se512.cfg lpc4350.cfg.orig
1431 at91sam7sx.cfg mc13224v.cfg
1432 at91sam7x256.cfg nuc910.cfg
1433 at91sam7x512.cfg omap2420.cfg
1434 at91sam9260.cfg omap3530.cfg
1435 at91sam9260_ext_RAM_ext_flash.cfg omap4430.cfg
1436 at91sam9261.cfg omap4460.cfg
1437 at91sam9263.cfg omap5912.cfg
1438 at91sam9.cfg omapl138.cfg
1439 at91sam9g10.cfg pic32mx.cfg
1440 at91sam9g20.cfg pxa255.cfg
1441 at91sam9g45.cfg pxa270.cfg
1442 at91sam9rl.cfg pxa3xx.cfg
1443 atmega128.cfg readme.txt
1444 avr32.cfg samsung_s3c2410.cfg
1445 c100.cfg samsung_s3c2440.cfg
1446 c100config.tcl samsung_s3c2450.cfg
1447 c100helper.tcl samsung_s3c4510.cfg
1448 c100regs.tcl samsung_s3c6410.cfg
1449 cs351x.cfg sharp_lh79532.cfg
1450 davinci.cfg smp8634.cfg
1451 dragonite.cfg spear3xx.cfg
1452 dsp56321.cfg stellaris.cfg
1453 dsp568013.cfg stellaris_icdi.cfg
1454 dsp568037.cfg stm32f0x_stlink.cfg
1455 efm32_stlink.cfg stm32f1x.cfg
1456 epc9301.cfg stm32f1x_stlink.cfg
1457 faux.cfg stm32f2x.cfg
1458 feroceon.cfg stm32f2x_stlink.cfg
1459 fm3.cfg stm32f3x.cfg
1460 hilscher_netx10.cfg stm32f3x_stlink.cfg
1461 hilscher_netx500.cfg stm32f4x.cfg
1462 hilscher_netx50.cfg stm32f4x_stlink.cfg
1463 icepick.cfg stm32l.cfg
1464 imx21.cfg stm32lx_dual_bank.cfg
1465 imx25.cfg stm32lx_stlink.cfg
1466 imx27.cfg stm32_stlink.cfg
1467 imx28.cfg stm32w108_stlink.cfg
1468 imx31.cfg stm32xl.cfg
1469 imx35.cfg str710.cfg
1470 imx51.cfg str730.cfg
1471 imx53.cfg str750.cfg
1472 imx6.cfg str912.cfg
1473 imx.cfg swj-dp.tcl
1474 is5114.cfg test_reset_syntax_error.cfg
1475 ixp42x.cfg test_syntax_error.cfg
1476 k40.cfg ti-ar7.cfg
1477 k60.cfg ti_calypso.cfg
1478 lpc1751.cfg ti_dm355.cfg
1479 lpc1752.cfg ti_dm365.cfg
1480 lpc1754.cfg ti_dm6446.cfg
1481 lpc1756.cfg tmpa900.cfg
1482 lpc1758.cfg tmpa910.cfg
1483 lpc1759.cfg u8500.cfg
1484 @end example
1485 @item @emph{more} ... browse for other library files which may be useful.
1486 For example, there are various generic and CPU-specific utilities.
1487 @end itemize
1489 The @file{openocd.cfg} user config
1490 file may override features in any of the above files by
1491 setting variables before sourcing the target file, or by adding
1492 commands specific to their situation.
1494 @section Interface Config Files
1496 The user config file
1497 should be able to source one of these files with a command like this:
1499 @example
1500 source [find interface/FOOBAR.cfg]
1501 @end example
1503 A preconfigured interface file should exist for every debug adapter
1504 in use today with OpenOCD.
1505 That said, perhaps some of these config files
1506 have only been used by the developer who created it.
1508 A separate chapter gives information about how to set these up.
1509 @xref{Debug Adapter Configuration}.
1510 Read the OpenOCD source code (and Developer's Guide)
1511 if you have a new kind of hardware interface
1512 and need to provide a driver for it.
1514 @section Board Config Files
1515 @cindex config file, board
1516 @cindex board config file
1518 The user config file
1519 should be able to source one of these files with a command like this:
1521 @example
1522 source [find board/FOOBAR.cfg]
1523 @end example
1525 The point of a board config file is to package everything
1526 about a given board that user config files need to know.
1527 In summary the board files should contain (if present)
1529 @enumerate
1530 @item One or more @command{source [target/...cfg]} statements
1531 @item NOR flash configuration (@pxref{norconfiguration,,NOR Configuration})
1532 @item NAND flash configuration (@pxref{nandconfiguration,,NAND Configuration})
1533 @item Target @code{reset} handlers for SDRAM and I/O configuration
1534 @item JTAG adapter reset configuration (@pxref{Reset Configuration})
1535 @item All things that are not ``inside a chip''
1536 @end enumerate
1538 Generic things inside target chips belong in target config files,
1539 not board config files. So for example a @code{reset-init} event
1540 handler should know board-specific oscillator and PLL parameters,
1541 which it passes to target-specific utility code.
1543 The most complex task of a board config file is creating such a
1544 @code{reset-init} event handler.
1545 Define those handlers last, after you verify the rest of the board
1546 configuration works.
1548 @subsection Communication Between Config files
1550 In addition to target-specific utility code, another way that
1551 board and target config files communicate is by following a
1552 convention on how to use certain variables.
1554 The full Tcl/Tk language supports ``namespaces'', but Jim-Tcl does not.
1555 Thus the rule we follow in OpenOCD is this: Variables that begin with
1556 a leading underscore are temporary in nature, and can be modified and
1557 used at will within a target configuration file.
1559 Complex board config files can do the things like this,
1560 for a board with three chips:
1562 @example
1563 # Chip #1: PXA270 for network side, big endian
1564 set CHIPNAME network
1565 set ENDIAN big
1566 source [find target/pxa270.cfg]
1567 # on return: _TARGETNAME = network.cpu
1568 # other commands can refer to the "network.cpu" target.
1569 $_TARGETNAME configure .... events for this CPU..
1571 # Chip #2: PXA270 for video side, little endian
1572 set CHIPNAME video
1573 set ENDIAN little
1574 source [find target/pxa270.cfg]
1575 # on return: _TARGETNAME = video.cpu
1576 # other commands can refer to the "video.cpu" target.
1577 $_TARGETNAME configure .... events for this CPU..
1579 # Chip #3: Xilinx FPGA for glue logic
1580 set CHIPNAME xilinx
1581 unset ENDIAN
1582 source [find target/spartan3.cfg]
1583 @end example
1585 That example is oversimplified because it doesn't show any flash memory,
1586 or the @code{reset-init} event handlers to initialize external DRAM
1587 or (assuming it needs it) load a configuration into the FPGA.
1588 Such features are usually needed for low-level work with many boards,
1589 where ``low level'' implies that the board initialization software may
1590 not be working. (That's a common reason to need JTAG tools. Another
1591 is to enable working with microcontroller-based systems, which often
1592 have no debugging support except a JTAG connector.)
1594 Target config files may also export utility functions to board and user
1595 config files. Such functions should use name prefixes, to help avoid
1596 naming collisions.
1598 Board files could also accept input variables from user config files.
1599 For example, there might be a @code{J4_JUMPER} setting used to identify
1600 what kind of flash memory a development board is using, or how to set
1601 up other clocks and peripherals.
1603 @subsection Variable Naming Convention
1604 @cindex variable names
1606 Most boards have only one instance of a chip.
1607 However, it should be easy to create a board with more than
1608 one such chip (as shown above).
1609 Accordingly, we encourage these conventions for naming
1610 variables associated with different @file{target.cfg} files,
1611 to promote consistency and
1612 so that board files can override target defaults.
1614 Inputs to target config files include:
1616 @itemize @bullet
1617 @item @code{CHIPNAME} ...
1618 This gives a name to the overall chip, and is used as part of
1619 tap identifier dotted names.
1620 While the default is normally provided by the chip manufacturer,
1621 board files may need to distinguish between instances of a chip.
1622 @item @code{ENDIAN} ...
1623 By default @option{little} - although chips may hard-wire @option{big}.
1624 Chips that can't change endianness don't need to use this variable.
1625 @item @code{CPUTAPID} ...
1626 When OpenOCD examines the JTAG chain, it can be told verify the
1627 chips against the JTAG IDCODE register.
1628 The target file will hold one or more defaults, but sometimes the
1629 chip in a board will use a different ID (perhaps a newer revision).
1630 @end itemize
1632 Outputs from target config files include:
1634 @itemize @bullet
1635 @item @code{_TARGETNAME} ...
1636 By convention, this variable is created by the target configuration
1637 script. The board configuration file may make use of this variable to
1638 configure things like a ``reset init'' script, or other things
1639 specific to that board and that target.
1640 If the chip has 2 targets, the names are @code{_TARGETNAME0},
1641 @code{_TARGETNAME1}, ... etc.
1642 @end itemize
1644 @subsection The reset-init Event Handler
1645 @cindex event, reset-init
1646 @cindex reset-init handler
1648 Board config files run in the OpenOCD configuration stage;
1649 they can't use TAPs or targets, since they haven't been
1650 fully set up yet.
1651 This means you can't write memory or access chip registers;
1652 you can't even verify that a flash chip is present.
1653 That's done later in event handlers, of which the target @code{reset-init}
1654 handler is one of the most important.
1656 Except on microcontrollers, the basic job of @code{reset-init} event
1657 handlers is setting up flash and DRAM, as normally handled by boot loaders.
1658 Microcontrollers rarely use boot loaders; they run right out of their
1659 on-chip flash and SRAM memory. But they may want to use one of these
1660 handlers too, if just for developer convenience.
1662 @quotation Note
1663 Because this is so very board-specific, and chip-specific, no examples
1664 are included here.
1665 Instead, look at the board config files distributed with OpenOCD.
1666 If you have a boot loader, its source code will help; so will
1667 configuration files for other JTAG tools
1668 (@pxref{translatingconfigurationfiles,,Translating Configuration Files}).
1669 @end quotation
1671 Some of this code could probably be shared between different boards.
1672 For example, setting up a DRAM controller often doesn't differ by
1673 much except the bus width (16 bits or 32?) and memory timings, so a
1674 reusable TCL procedure loaded by the @file{target.cfg} file might take
1675 those as parameters.
1676 Similarly with oscillator, PLL, and clock setup;
1677 and disabling the watchdog.
1678 Structure the code cleanly, and provide comments to help
1679 the next developer doing such work.
1680 (@emph{You might be that next person} trying to reuse init code!)
1682 The last thing normally done in a @code{reset-init} handler is probing
1683 whatever flash memory was configured. For most chips that needs to be
1684 done while the associated target is halted, either because JTAG memory
1685 access uses the CPU or to prevent conflicting CPU access.
1687 @subsection JTAG Clock Rate
1689 Before your @code{reset-init} handler has set up
1690 the PLLs and clocking, you may need to run with
1691 a low JTAG clock rate.
1692 @xref{jtagspeed,,JTAG Speed}.
1693 Then you'd increase that rate after your handler has
1694 made it possible to use the faster JTAG clock.
1695 When the initial low speed is board-specific, for example
1696 because it depends on a board-specific oscillator speed, then
1697 you should probably set it up in the board config file;
1698 if it's target-specific, it belongs in the target config file.
1700 For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
1701 @uref{http://www.arm.com/support/faqdev/4170.html} gives details.}
1702 is one sixth of the CPU clock; or one eighth for ARM11 cores.
1703 Consult chip documentation to determine the peak JTAG clock rate,
1704 which might be less than that.
1706 @quotation Warning
1707 On most ARMs, JTAG clock detection is coupled to the core clock, so
1708 software using a @option{wait for interrupt} operation blocks JTAG access.
1709 Adaptive clocking provides a partial workaround, but a more complete
1710 solution just avoids using that instruction with JTAG debuggers.
1711 @end quotation
1713 If both the chip and the board support adaptive clocking,
1714 use the @command{jtag_rclk}
1715 command, in case your board is used with JTAG adapter which
1716 also supports it. Otherwise use @command{adapter_khz}.
1717 Set the slow rate at the beginning of the reset sequence,
1718 and the faster rate as soon as the clocks are at full speed.
1720 @anchor{theinitboardprocedure}
1721 @subsection The init_board procedure
1722 @cindex init_board procedure
1724 The concept of @code{init_board} procedure is very similar to @code{init_targets}
1725 (@xref{theinittargetsprocedure,,The init_targets procedure}.) - it's a replacement of ``linear''
1726 configuration scripts. This procedure is meant to be executed when OpenOCD enters run stage
1727 (@xref{enteringtherunstage,,Entering the Run Stage},) after @code{init_targets}. The idea to have
1728 spearate @code{init_targets} and @code{init_board} procedures is to allow the first one to configure
1729 everything target specific (internal flash, internal RAM, etc.) and the second one to configure
1730 everything board specific (reset signals, chip frequency, reset-init event handler, external memory, etc.).
1731 Additionally ``linear'' board config file will most likely fail when target config file uses
1732 @code{init_targets} scheme (``linear'' script is executed before @code{init} and @code{init_targets} - after),
1733 so separating these two configuration stages is very convenient, as the easiest way to overcome this
1734 problem is to convert board config file to use @code{init_board} procedure. Board config scripts don't
1735 need to override @code{init_targets} defined in target config files when they only need to to add some specifics.
1737 Just as @code{init_targets}, the @code{init_board} procedure can be overriden by ``next level'' script (which sources
1738 the original), allowing greater code reuse.
1740 @example
1741 ### board_file.cfg ###
1743 # source target file that does most of the config in init_targets
1744 source [find target/target.cfg]
1746 proc enable_fast_clock @{@} @{
1747 # enables fast on-board clock source
1748 # configures the chip to use it
1749 @}
1751 # initialize only board specifics - reset, clock, adapter frequency
1752 proc init_board @{@} @{
1753 reset_config trst_and_srst trst_pulls_srst
1755 $_TARGETNAME configure -event reset-init @{
1756 adapter_khz 1
1757 enable_fast_clock
1758 adapter_khz 10000
1759 @}
1760 @}
1761 @end example
1763 @section Target Config Files
1764 @cindex config file, target
1765 @cindex target config file
1767 Board config files communicate with target config files using
1768 naming conventions as described above, and may source one or
1769 more target config files like this:
1771 @example
1772 source [find target/FOOBAR.cfg]
1773 @end example
1775 The point of a target config file is to package everything
1776 about a given chip that board config files need to know.
1777 In summary the target files should contain
1779 @enumerate
1780 @item Set defaults
1781 @item Add TAPs to the scan chain
1782 @item Add CPU targets (includes GDB support)
1783 @item CPU/Chip/CPU-Core specific features
1784 @item On-Chip flash
1785 @end enumerate
1787 As a rule of thumb, a target file sets up only one chip.
1788 For a microcontroller, that will often include a single TAP,
1789 which is a CPU needing a GDB target, and its on-chip flash.
1791 More complex chips may include multiple TAPs, and the target
1792 config file may need to define them all before OpenOCD
1793 can talk to the chip.
1794 For example, some phone chips have JTAG scan chains that include
1795 an ARM core for operating system use, a DSP,
1796 another ARM core embedded in an image processing engine,
1797 and other processing engines.
1799 @subsection Default Value Boiler Plate Code
1801 All target configuration files should start with code like this,
1802 letting board config files express environment-specific
1803 differences in how things should be set up.
1805 @example
1806 # Boards may override chip names, perhaps based on role,
1807 # but the default should match what the vendor uses
1808 if @{ [info exists CHIPNAME] @} @{
1810 @} else @{
1811 set _CHIPNAME sam7x256
1812 @}
1814 # ONLY use ENDIAN with targets that can change it.
1815 if @{ [info exists ENDIAN] @} @{
1816 set _ENDIAN $ENDIAN
1817 @} else @{
1818 set _ENDIAN little
1819 @}
1821 # TAP identifiers may change as chips mature, for example with
1822 # new revision fields (the "3" here). Pick a good default; you
1823 # can pass several such identifiers to the "jtag newtap" command.
1824 if @{ [info exists CPUTAPID ] @} @{
1826 @} else @{
1827 set _CPUTAPID 0x3f0f0f0f
1828 @}
1829 @end example
1830 @c but 0x3f0f0f0f is for an str73x part ...
1832 @emph{Remember:} Board config files may include multiple target
1833 config files, or the same target file multiple times
1834 (changing at least @code{CHIPNAME}).
1836 Likewise, the target configuration file should define
1837 @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
1838 use it later on when defining debug targets:
1840 @example
1842 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1843 @end example
1845 @subsection Adding TAPs to the Scan Chain
1846 After the ``defaults'' are set up,
1847 add the TAPs on each chip to the JTAG scan chain.
1848 @xref{TAP Declaration}, and the naming convention
1849 for taps.
1851 In the simplest case the chip has only one TAP,
1852 probably for a CPU or FPGA.
1853 The config file for the Atmel AT91SAM7X256
1854 looks (in part) like this:
1856 @example
1857 jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
1858 @end example
1860 A board with two such at91sam7 chips would be able
1861 to source such a config file twice, with different
1862 values for @code{CHIPNAME}, so
1863 it adds a different TAP each time.
1865 If there are nonzero @option{-expected-id} values,
1866 OpenOCD attempts to verify the actual tap id against those values.
1867 It will issue error messages if there is mismatch, which
1868 can help to pinpoint problems in OpenOCD configurations.
1870 @example
1871 JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
1872 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
1873 ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
1874 ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
1875 ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
1876 @end example
1878 There are more complex examples too, with chips that have
1879 multiple TAPs. Ones worth looking at include:
1881 @itemize
1882 @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
1883 plus a JRC to enable them
1884 @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
1885 @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
1886 is not currently used)
1887 @end itemize
1889 @subsection Add CPU targets
1891 After adding a TAP for a CPU, you should set it up so that
1892 GDB and other commands can use it.
1893 @xref{CPU Configuration}.
1894 For the at91sam7 example above, the command can look like this;
1895 note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
1896 to little endian, and this chip doesn't support changing that.
1898 @example
1900 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1901 @end example
1903 Work areas are small RAM areas associated with CPU targets.
1904 They are used by OpenOCD to speed up downloads,
1905 and to download small snippets of code to program flash chips.
1906 If the chip includes a form of ``on-chip-ram'' - and many do - define
1907 a work area if you can.
1908 Again using the at91sam7 as an example, this can look like:
1910 @example
1911 $_TARGETNAME configure -work-area-phys 0x00200000 \
1912 -work-area-size 0x4000 -work-area-backup 0
1913 @end example
1915 @anchor{definecputargetsworkinginsmp}
1916 @subsection Define CPU targets working in SMP
1917 @cindex SMP
1918 After setting targets, you can define a list of targets working in SMP.
1920 @example
1921 set _TARGETNAME_1 $_CHIPNAME.cpu1
1922 set _TARGETNAME_2 $_CHIPNAME.cpu2
1923 target create $_TARGETNAME_1 cortex_a -chain-position $_CHIPNAME.dap \
1924 -coreid 0 -dbgbase $_DAP_DBG1
1925 target create $_TARGETNAME_2 cortex_a -chain-position $_CHIPNAME.dap \
1926 -coreid 1 -dbgbase $_DAP_DBG2
1927 #define 2 targets working in smp.
1928 target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
1929 @end example
1930 In the above example on cortex_a, 2 cpus are working in SMP.
1931 In SMP only one GDB instance is created and :
1932 @itemize @bullet
1933 @item a set of hardware breakpoint sets the same breakpoint on all targets in the list.
1934 @item halt command triggers the halt of all targets in the list.
1935 @item resume command triggers the write context and the restart of all targets in the list.
1936 @item following a breakpoint: the target stopped by the breakpoint is displayed to the GDB session.
1937 @item dedicated GDB serial protocol packets are implemented for switching/retrieving the target
1938 displayed by the GDB session @pxref{usingopenocdsmpwithgdb,,Using OpenOCD SMP with GDB}.
1939 @end itemize
1941 The SMP behaviour can be disabled/enabled dynamically. On cortex_a following
1942 command have been implemented.
1943 @itemize @bullet
1944 @item cortex_a smp_on : enable SMP mode, behaviour is as described above.
1945 @item cortex_a smp_off : disable SMP mode, the current target is the one
1946 displayed in the GDB session, only this target is now controlled by GDB
1947 session. This behaviour is useful during system boot up.
1948 @item cortex_a smp_gdb : display/fix the core id displayed in GDB session see
1949 following example.
1950 @end itemize
1952 @example
1953 >cortex_a smp_gdb
1954 gdb coreid 0 -> -1
1955 #0 : coreid 0 is displayed to GDB ,
1956 #-> -1 : next resume triggers a real resume
1957 > cortex_a smp_gdb 1
1958 gdb coreid 0 -> 1
1959 #0 :coreid 0 is displayed to GDB ,
1960 #->1 : next resume displays coreid 1 to GDB
1961 > resume
1962 > cortex_a smp_gdb
1963 gdb coreid 1 -> 1
1964 #1 :coreid 1 is displayed to GDB ,
1965 #->1 : next resume displays coreid 1 to GDB
1966 > cortex_a smp_gdb -1
1967 gdb coreid 1 -> -1
1968 #1 :coreid 1 is displayed to GDB,
1969 #->-1 : next resume triggers a real resume
1970 @end example
1973 @subsection Chip Reset Setup
1975 As a rule, you should put the @command{reset_config} command
1976 into the board file. Most things you think you know about a
1977 chip can be tweaked by the board.
1979 Some chips have specific ways the TRST and SRST signals are
1980 managed. In the unusual case that these are @emph{chip specific}
1981 and can never be changed by board wiring, they could go here.
1982 For example, some chips can't support JTAG debugging without
1983 both signals.
1985 Provide a @code{reset-assert} event handler if you can.
1986 Such a handler uses JTAG operations to reset the target,
1987 letting this target config be used in systems which don't
1988 provide the optional SRST signal, or on systems where you
1989 don't want to reset all targets at once.
1990 Such a handler might write to chip registers to force a reset,
1991 use a JRC to do that (preferable -- the target may be wedged!),
1992 or force a watchdog timer to trigger.
1993 (For Cortex-M targets, this is not necessary. The target
1994 driver knows how to use trigger an NVIC reset when SRST is
1995 not available.)
1997 Some chips need special attention during reset handling if
1998 they're going to be used with JTAG.
1999 An example might be needing to send some commands right
2000 after the target's TAP has been reset, providing a
2001 @code{reset-deassert-post} event handler that writes a chip
2002 register to report that JTAG debugging is being done.
2003 Another would be reconfiguring the watchdog so that it stops
2004 counting while the core is halted in the debugger.
2006 JTAG clocking constraints often change during reset, and in
2007 some cases target config files (rather than board config files)
2008 are the right places to handle some of those issues.
2009 For example, immediately after reset most chips run using a
2010 slower clock than they will use later.
2011 That means that after reset (and potentially, as OpenOCD
2012 first starts up) they must use a slower JTAG clock rate
2013 than they will use later.
2014 @xref{jtagspeed,,JTAG Speed}.
2016 @quotation Important
2017 When you are debugging code that runs right after chip
2018 reset, getting these issues right is critical.
2019 In particular, if you see intermittent failures when
2020 OpenOCD verifies the scan chain after reset,
2021 look at how you are setting up JTAG clocking.
2022 @end quotation
2024 @anchor{theinittargetsprocedure}
2025 @subsection The init_targets procedure
2026 @cindex init_targets procedure
2028 Target config files can either be ``linear'' (script executed line-by-line when parsed in
2029 configuration stage, @xref{configurationstage,,Configuration Stage},) or they can contain a special
2030 procedure called @code{init_targets}, which will be executed when entering run stage
2031 (after parsing all config files or after @code{init} command, @xref{enteringtherunstage,,Entering the Run Stage}.)
2032 Such procedure can be overriden by ``next level'' script (which sources the original).
2033 This concept faciliates code reuse when basic target config files provide generic configuration
2034 procedures and @code{init_targets} procedure, which can then be sourced and enchanced or changed in
2035 a ``more specific'' target config file. This is not possible with ``linear'' config scripts,
2036 because sourcing them executes every initialization commands they provide.
2038 @example
2039 ### generic_file.cfg ###
2041 proc setup_my_chip @{chip_name flash_size ram_size@} @{
2042 # basic initialization procedure ...
2043 @}
2045 proc init_targets @{@} @{
2046 # initializes generic chip with 4kB of flash and 1kB of RAM
2047 setup_my_chip MY_GENERIC_CHIP 4096 1024
2048 @}
2050 ### specific_file.cfg ###
2052 source [find target/generic_file.cfg]
2054 proc init_targets @{@} @{
2055 # initializes specific chip with 128kB of flash and 64kB of RAM
2056 setup_my_chip MY_CHIP_WITH_128K_FLASH_64KB_RAM 131072 65536
2057 @}
2058 @end example
2060 The easiest way to convert ``linear'' config files to @code{init_targets} version is to
2061 enclose every line of ``code'' (i.e. not @code{source} commands, procedures, etc.) in this procedure.
2063 For an example of this scheme see LPC2000 target config files.
2065 The @code{init_boards} procedure is a similar concept concerning board config files
2066 (@xref{theinitboardprocedure,,The init_board procedure}.)
2068 @subsection ARM Core Specific Hacks
2070 If the chip has a DCC, enable it. If the chip is an ARM9 with some
2071 special high speed download features - enable it.
2073 If present, the MMU, the MPU and the CACHE should be disabled.
2075 Some ARM cores are equipped with trace support, which permits
2076 examination of the instruction and data bus activity. Trace
2077 activity is controlled through an ``Embedded Trace Module'' (ETM)
2078 on one of the core's scan chains. The ETM emits voluminous data
2079 through a ``trace port''. (@xref{armhardwaretracing,,ARM Hardware Tracing}.)
2080 If you are using an external trace port,
2081 configure it in your board config file.
2082 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
2083 configure it in your target config file.
2085 @example
2086 etm config $_TARGETNAME 16 normal full etb
2087 etb config $_TARGETNAME $_CHIPNAME.etb
2088 @end example
2090 @subsection Internal Flash Configuration
2092 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
2094 @b{Never ever} in the ``target configuration file'' define any type of
2095 flash that is external to the chip. (For example a BOOT flash on
2096 Chip Select 0.) Such flash information goes in a board file - not
2097 the TARGET (chip) file.
2099 Examples:
2100 @itemize @bullet
2101 @item at91sam7x256 - has 256K flash YES enable it.
2102 @item str912 - has flash internal YES enable it.
2103 @item imx27 - uses boot flash on CS0 - it goes in the board file.
2104 @item pxa270 - again - CS0 flash - it goes in the board file.
2105 @end itemize
2107 @anchor{translatingconfigurationfiles}
2108 @section Translating Configuration Files
2109 @cindex translation
2110 If you have a configuration file for another hardware debugger
2111 or toolset (Abatron, BDI2000, BDI3000, CCS,
2112 Lauterbach, Segger, Macraigor, etc.), translating
2113 it into OpenOCD syntax is often quite straightforward. The most tricky
2114 part of creating a configuration script is oftentimes the reset init
2115 sequence where e.g. PLLs, DRAM and the like is set up.
2117 One trick that you can use when translating is to write small
2118 Tcl procedures to translate the syntax into OpenOCD syntax. This
2119 can avoid manual translation errors and make it easier to
2120 convert other scripts later on.
2122 Example of transforming quirky arguments to a simple search and
2123 replace job:
2125 @example
2126 # Lauterbach syntax(?)
2127 #
2128 # Data.Set c15:0x042f %long 0x40000015
2129 #
2130 # OpenOCD syntax when using procedure below.
2131 #
2132 # setc15 0x01 0x00050078
2134 proc setc15 @{regs value@} @{
2135 global TARGETNAME
2137 echo [format "set p15 0x%04x, 0x%08x" $regs $value]
2139 arm mcr 15 [expr ($regs>>12)&0x7] \
2140 [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] \
2141 [expr ($regs>>8)&0x7] $value
2142 @}
2143 @end example
2147 @node Daemon Configuration
2148 @chapter Daemon Configuration
2149 @cindex initialization
2150 The commands here are commonly found in the openocd.cfg file and are
2151 used to specify what TCP/IP ports are used, and how GDB should be
2152 supported.
2154 @anchor{configurationstage}
2155 @section Configuration Stage
2156 @cindex configuration stage
2157 @cindex config command
2159 When the OpenOCD server process starts up, it enters a
2160 @emph{configuration stage} which is the only time that
2161 certain commands, @emph{configuration commands}, may be issued.
2162 Normally, configuration commands are only available
2163 inside startup scripts.
2165 In this manual, the definition of a configuration command is
2166 presented as a @emph{Config Command}, not as a @emph{Command}
2167 which may be issued interactively.
2168 The runtime @command{help} command also highlights configuration
2169 commands, and those which may be issued at any time.
2171 Those configuration commands include declaration of TAPs,
2172 flash banks,
2173 the interface used for JTAG communication,
2174 and other basic setup.
2175 The server must leave the configuration stage before it
2176 may access or activate TAPs.
2177 After it leaves this stage, configuration commands may no
2178 longer be issued.
2180 @anchor{enteringtherunstage}
2181 @section Entering the Run Stage
2183 The first thing OpenOCD does after leaving the configuration
2184 stage is to verify that it can talk to the scan chain
2185 (list of TAPs) which has been configured.
2186 It will warn if it doesn't find TAPs it expects to find,
2187 or finds TAPs that aren't supposed to be there.
2188 You should see no errors at this point.
2189 If you see errors, resolve them by correcting the
2190 commands you used to configure the server.
2191 Common errors include using an initial JTAG speed that's too
2192 fast, and not providing the right IDCODE values for the TAPs
2193 on the scan chain.
2195 Once OpenOCD has entered the run stage, a number of commands
2196 become available.
2197 A number of these relate to the debug targets you may have declared.
2198 For example, the @command{mww} command will not be available until
2199 a target has been successfuly instantiated.
2200 If you want to use those commands, you may need to force
2201 entry to the run stage.
2203 @deffn {Config Command} init
2204 This command terminates the configuration stage and
2205 enters the run stage. This helps when you need to have
2206 the startup scripts manage tasks such as resetting the target,
2207 programming flash, etc. To reset the CPU upon startup, add "init" and
2208 "reset" at the end of the config script or at the end of the OpenOCD
2209 command line using the @option{-c} command line switch.
2211 If this command does not appear in any startup/configuration file
2212 OpenOCD executes the command for you after processing all
2213 configuration files and/or command line options.
2215 @b{NOTE:} This command normally occurs at or near the end of your
2216 openocd.cfg file to force OpenOCD to ``initialize'' and make the
2217 targets ready. For example: If your openocd.cfg file needs to
2218 read/write memory on your target, @command{init} must occur before
2219 the memory read/write commands. This includes @command{nand probe}.
2220 @end deffn
2222 @deffn {Overridable Procedure} jtag_init
2223 This is invoked at server startup to verify that it can talk
2224 to the scan chain (list of TAPs) which has been configured.
2226 The default implementation first tries @command{jtag arp_init},
2227 which uses only a lightweight JTAG reset before examining the
2228 scan chain.
2229 If that fails, it tries again, using a harder reset
2230 from the overridable procedure @command{init_reset}.
2232 Implementations must have verified the JTAG scan chain before
2233 they return.
2234 This is done by calling @command{jtag arp_init}
2235 (or @command{jtag arp_init-reset}).
2236 @end deffn
2238 @anchor{tcpipports}
2239 @section TCP/IP Ports
2240 @cindex TCP port
2241 @cindex server
2242 @cindex port
2243 @cindex security
2244 The OpenOCD server accepts remote commands in several syntaxes.
2245 Each syntax uses a different TCP/IP port, which you may specify
2246 only during configuration (before those ports are opened).
2248 For reasons including security, you may wish to prevent remote
2249 access using one or more of these ports.
2250 In such cases, just specify the relevant port number as zero.
2251 If you disable all access through TCP/IP, you will need to
2252 use the command line @option{-pipe} option.
2254 @deffn {Command} gdb_port [number]
2255 @cindex GDB server
2256 Normally gdb listens to a TCP/IP port, but GDB can also
2257 communicate via pipes(stdin/out or named pipes). The name
2258 "gdb_port" stuck because it covers probably more than 90% of
2259 the normal use cases.
2261 No arguments reports GDB port. "pipe" means listen to stdin
2262 output to stdout, an integer is base port number, "disable"
2263 disables the gdb server.
2265 When using "pipe", also use log_output to redirect the log
2266 output to a file so as not to flood the stdin/out pipes.
2268 The -p/--pipe option is deprecated and a warning is printed
2269 as it is equivalent to passing in -c "gdb_port pipe; log_output openocd.log".
2271 Any other string is interpreted as named pipe to listen to.
2272 Output pipe is the same name as input pipe, but with 'o' appended,
2273 e.g. /var/gdb, /var/gdbo.
2275 The GDB port for the first target will be the base port, the
2276 second target will listen on gdb_port + 1, and so on.
2277 When not specified during the configuration stage,
2278 the port @var{number} defaults to 3333.
2279 @end deffn
2281 @deffn {Command} tcl_port [number]
2282 Specify or query the port used for a simplified RPC
2283 connection that can be used by clients to issue TCL commands and get the
2284 output from the Tcl engine.
2285 Intended as a machine interface.
2286 When not specified during the configuration stage,
2287 the port @var{number} defaults to 6666.
2289 @end deffn
2291 @deffn {Command} telnet_port [number]
2292 Specify or query the
2293 port on which to listen for incoming telnet connections.
2294 This port is intended for interaction with one human through TCL commands.
2295 When not specified during the configuration stage,
2296 the port @var{number} defaults to 4444.
2297 When specified as zero, this port is not activated.
2298 @end deffn
2300 @anchor{gdbconfiguration}
2301 @section GDB Configuration
2302 @cindex GDB
2303 @cindex GDB configuration
2304 You can reconfigure some GDB behaviors if needed.
2305 The ones listed here are static and global.
2306 @xref{targetconfiguration,,Target Configuration}, about configuring individual targets.
2307 @xref{targetevents,,Target Events}, about configuring target-specific event handling.
2309 @anchor{gdbbreakpointoverride}
2310 @deffn {Command} gdb_breakpoint_override [@option{hard}|@option{soft}|@option{disable}]
2311 Force breakpoint type for gdb @command{break} commands.
2312 This option supports GDB GUIs which don't
2313 distinguish hard versus soft breakpoints, if the default OpenOCD and
2314 GDB behaviour is not sufficient. GDB normally uses hardware
2315 breakpoints if the memory map has been set up for flash regions.
2316 @end deffn
2318 @anchor{gdbflashprogram}
2319 @deffn {Config Command} gdb_flash_program (@option{enable}|@option{disable})
2320 Set to @option{enable} to cause OpenOCD to program the flash memory when a
2321 vFlash packet is received.
2322 The default behaviour is @option{enable}.
2323 @end deffn
2325 @deffn {Config Command} gdb_memory_map (@option{enable}|@option{disable})
2326 Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
2327 requested. GDB will then know when to set hardware breakpoints, and program flash
2328 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
2329 for flash programming to work.
2330 Default behaviour is @option{enable}.
2331 @xref{gdbflashprogram,,gdb_flash_program}.
2332 @end deffn
2334 @deffn {Config Command} gdb_report_data_abort (@option{enable}|@option{disable})
2335 Specifies whether data aborts cause an error to be reported
2336 by GDB memory read packets.
2337 The default behaviour is @option{disable};
2338 use @option{enable} see these errors reported.
2339 @end deffn
2341 @anchor{eventpolling}
2342 @section Event Polling
2344 Hardware debuggers are parts of asynchronous systems,
2345 where significant events can happen at any time.
2346 The OpenOCD server needs to detect some of these events,
2347 so it can report them to through TCL command line
2348 or to GDB.
2350 Examples of such events include:
2352 @itemize
2353 @item One of the targets can stop running ... maybe it triggers
2354 a code breakpoint or data watchpoint, or halts itself.
2355 @item Messages may be sent over ``debug message'' channels ... many
2356 targets support such messages sent over JTAG,
2357 for receipt by the person debugging or tools.
2358 @item Loss of power ... some adapters can detect these events.
2359 @item Resets not issued through JTAG ... such reset sources
2360 can include button presses or other system hardware, sometimes
2361 including the target itself (perhaps through a watchdog).
2362 @item Debug instrumentation sometimes supports event triggering
2363 such as ``trace buffer full'' (so it can quickly be emptied)
2364 or other signals (to correlate with code behavior).
2365 @end itemize
2367 None of those events are signaled through standard JTAG signals.
2368 However, most conventions for JTAG connectors include voltage
2369 level and system reset (SRST) signal detection.
2370 Some connectors also include instrumentation signals, which
2371 can imply events when those signals are inputs.
2373 In general, OpenOCD needs to periodically check for those events,
2374 either by looking at the status of signals on the JTAG connector
2375 or by sending synchronous ``tell me your status'' JTAG requests
2376 to the various active targets.
2377 There is a command to manage and monitor that polling,
2378 which is normally done in the background.
2380 @deffn Command poll [@option{on}|@option{off}]
2381 Poll the current target for its current state.
2382 (Also, @pxref{targetcurstate,,target curstate}.)
2383 If that target is in debug mode, architecture
2384 specific information about the current state is printed.
2385 An optional parameter
2386 allows background polling to be enabled and disabled.
2388 You could use this from the TCL command shell, or
2389 from GDB using @command{monitor poll} command.
2390 Leave background polling enabled while you're using GDB.
2391 @example
2392 > poll
2393 background polling: on
2394 target state: halted
2395 target halted in ARM state due to debug-request, \
2396 current mode: Supervisor
2397 cpsr: 0x800000d3 pc: 0x11081bfc
2398 MMU: disabled, D-Cache: disabled, I-Cache: enabled
2399 >
2400 @end example
2401 @end deffn
2403 @node Debug Adapter Configuration
2404 @chapter Debug Adapter Configuration
2405 @cindex config file, interface
2406 @cindex interface config file
2408 Correctly installing OpenOCD includes making your operating system give
2409 OpenOCD access to debug adapters. Once that has been done, Tcl commands
2410 are used to select which one is used, and to configure how it is used.
2412 @quotation Note
2413 Because OpenOCD started out with a focus purely on JTAG, you may find
2414 places where it wrongly presumes JTAG is the only transport protocol
2415 in use. Be aware that recent versions of OpenOCD are removing that
2416 limitation. JTAG remains more functional than most other transports.
2417 Other transports do not support boundary scan operations, or may be
2418 specific to a given chip vendor. Some might be usable only for
2419 programming flash memory, instead of also for debugging.
2420 @end quotation
2422 Debug Adapters/Interfaces/Dongles are normally configured
2423 through commands in an interface configuration
2424 file which is sourced by your @file{openocd.cfg} file, or
2425 through a command line @option{-f interface/....cfg} option.
2427 @example
2428 source [find interface/olimex-jtag-tiny.cfg]
2429 @end example
2431 These commands tell
2432 OpenOCD what type of JTAG adapter you have, and how to talk to it.
2433 A few cases are so simple that you only need to say what driver to use:
2435 @example
2436 # jlink interface
2437 interface jlink
2438 @end example
2440 Most adapters need a bit more configuration than that.
2443 @section Interface Configuration
2445 The interface command tells OpenOCD what type of debug adapter you are
2446 using. Depending on the type of adapter, you may need to use one or
2447 more additional commands to further identify or configure the adapter.
2449 @deffn {Config Command} {interface} name
2450 Use the interface driver @var{name} to connect to the
2451 target.
2452 @end deffn
2454 @deffn Command {interface_list}
2455 List the debug adapter drivers that have been built into
2456 the running copy of OpenOCD.
2457 @end deffn
2458 @deffn Command {interface transports} transport_name+
2459 Specifies the transports supported by this debug adapter.
2460 The adapter driver builds-in similar knowledge; use this only
2461 when external configuration (such as jumpering) changes what
2462 the hardware can support.
2463 @end deffn
2467 @deffn Command {adapter_name}
2468 Returns the name of the debug adapter driver being used.
2469 @end deffn
2471 @section Interface Drivers
2473 Each of the interface drivers listed here must be explicitly
2474 enabled when OpenOCD is configured, in order to be made
2475 available at run time.
2477 @deffn {Interface Driver} {amt_jtagaccel}
2478 Amontec Chameleon in its JTAG Accelerator configuration,
2479 connected to a PC's EPP mode parallel port.
2480 This defines some driver-specific commands:
2482 @deffn {Config Command} {parport_port} number
2483 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
2484 the number of the @file{/dev/parport} device.
2485 @end deffn
2487 @deffn {Config Command} rtck [@option{enable}|@option{disable}]
2488 Displays status of RTCK option.
2489 Optionally sets that option first.
2490 @end deffn
2491 @end deffn
2493 @deffn {Interface Driver} {arm-jtag-ew}
2494 Olimex ARM-JTAG-EW USB adapter
2495 This has one driver-specific command:
2497 @deffn Command {armjtagew_info}
2498 Logs some status
2499 @end deffn
2500 @end deffn
2502 @deffn {Interface Driver} {at91rm9200}
2503 Supports bitbanged JTAG from the local system,
2504 presuming that system is an Atmel AT91rm9200
2505 and a specific set of GPIOs is used.
2506 @c command: at91rm9200_device NAME
2507 @c chooses among list of bit configs ... only one option
2508 @end deffn
2510 @deffn {Interface Driver} {dummy}
2511 A dummy software-only driver for debugging.
2512 @end deffn
2514 @deffn {Interface Driver} {ep93xx}
2515 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
2516 @end deffn
2518 @deffn {Interface Driver} {ft2232}
2519 FTDI FT2232 (USB) based devices over one of the userspace libraries.
2521 Note that this driver has several flaws and the @command{ftdi} driver is
2522 recommended as its replacement.
2524 These interfaces have several commands, used to configure the driver
2525 before initializing the JTAG scan chain:
2527 @deffn {Config Command} {ft2232_device_desc} description
2528 Provides the USB device description (the @emph{iProduct string})
2529 of the FTDI FT2232 device. If not
2530 specified, the FTDI default value is used. This setting is only valid
2531 if compiled with FTD2XX support.
2532 @end deffn
2534 @deffn {Config Command} {ft2232_serial} serial-number
2535 Specifies the @var{serial-number} of the FTDI FT2232 device to use,
2536 in case the vendor provides unique IDs and more than one FT2232 device
2537 is connected to the host.
2538 If not specified, serial numbers are not considered.
2539 (Note that USB serial numbers can be arbitrary Unicode strings,
2540 and are not restricted to containing only decimal digits.)
2541 @end deffn
2543 @deffn {Config Command} {ft2232_layout} name
2544 Each vendor's FT2232 device can use different GPIO signals
2545 to control output-enables, reset signals, and LEDs.
2546 Currently valid layout @var{name} values include:
2547 @itemize @minus
2548 @item @b{axm0432_jtag} Axiom AXM-0432
2549 @item @b{comstick} Hitex STR9 comstick
2550 @item @b{cortino} Hitex Cortino JTAG interface
2551 @item @b{evb_lm3s811} TI/Luminary Micro EVB_LM3S811 as a JTAG interface,
2552 either for the local Cortex-M3 (SRST only)
2553 or in a passthrough mode (neither SRST nor TRST)
2554 This layout can not support the SWO trace mechanism, and should be
2555 used only for older boards (before rev C).
2556 @item @b{luminary_icdi} This layout should be used with most TI/Luminary
2557 eval boards, including Rev C LM3S811 eval boards and the eponymous
2558 ICDI boards, to debug either the local Cortex-M3 or in passthrough mode
2559 to debug some other target. It can support the SWO trace mechanism.
2560 @item @b{flyswatter} Tin Can Tools Flyswatter
2561 @item @b{icebear} ICEbear JTAG adapter from Section 5
2562 @item @b{jtagkey} Amontec JTAGkey and JTAGkey-Tiny (and compatibles)
2563 @item @b{jtagkey2} Amontec JTAGkey2 (and compatibles)
2564 @item @b{m5960} American Microsystems M5960
2565 @item @b{olimex-jtag} Olimex ARM-USB-OCD and ARM-USB-Tiny
2566 @item @b{oocdlink} OOCDLink
2567 @c oocdlink ~= jtagkey_prototype_v1
2568 @item @b{redbee-econotag} Integrated with a Redbee development board.
2569 @item @b{redbee-usb} Integrated with a Redbee USB-stick development board.
2570 @item @b{sheevaplug} Marvell Sheevaplug development kit
2571 @item @b{signalyzer} Xverve Signalyzer
2572 @item @b{stm32stick} Hitex STM32 Performance Stick
2573 @item @b{turtelizer2} egnite Software turtelizer2
2574 @item @b{usbjtag} "USBJTAG-1" layout described in the OpenOCD diploma thesis
2575 @end itemize
2576 @end deffn
2578 @deffn {Config Command} {ft2232_vid_pid} [vid pid]+
2579 The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
2580 default values are used.
2581 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2582 @example
2583 ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
2584 @end example
2585 @end deffn
2587 @deffn {Config Command} {ft2232_latency} ms
2588 On some systems using FT2232 based JTAG interfaces the FT_Read function call in
2589 ft2232_read() fails to return the expected number of bytes. This can be caused by
2590 USB communication delays and has proved hard to reproduce and debug. Setting the
2591 FT2232 latency timer to a larger value increases delays for short USB packets but it
2592 also reduces the risk of timeouts before receiving the expected number of bytes.
2593 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
2594 @end deffn
2596 @deffn {Config Command} {ft2232_channel} channel
2597 Used to select the channel of the ft2232 chip to use (between 1 and 4).
2598 The default value is 1.
2599 @end deffn
2601 For example, the interface config file for a
2602 Turtelizer JTAG Adapter looks something like this:
2604 @example
2605 interface ft2232
2606 ft2232_device_desc "Turtelizer JTAG/RS232 Adapter"
2607 ft2232_layout turtelizer2
2608 ft2232_vid_pid 0x0403 0xbdc8
2609 @end example
2610 @end deffn
2612 @deffn {Interface Driver} {ftdi}
2613 This driver is for adapters using the MPSSE (Multi-Protocol Synchronous Serial
2614 Engine) mode built into many FTDI chips, such as the FT2232, FT4232 and FT232H.
2615 It is a complete rewrite to address a large number of problems with the ft2232
2616 interface driver.
2618 The driver is using libusb-1.0 in asynchronous mode to talk to the FTDI device,
2619 bypassing intermediate libraries like libftdi of D2XX. Performance-wise it is
2620 consistently faster than the ft2232 driver, sometimes several times faster.
2622 A major improvement of this driver is that support for new FTDI based adapters
2623 can be added competely through configuration files, without the need to patch
2624 and rebuild OpenOCD.
2626 The driver uses a signal abstraction to enable Tcl configuration files to
2627 define outputs for one or several FTDI GPIO. These outputs can then be
2628 controlled using the @command{ftdi_set_signal} command. Special signal names
2629 are reserved for nTRST, nSRST and LED (for blink) so that they, if defined,
2630 will be used for their customary purpose.
2632 Depending on the type of buffer attached to the FTDI GPIO, the outputs have to
2633 be controlled differently. In order to support tristateable signals such as
2634 nSRST, both a data GPIO and an output-enable GPIO can be specified for each
2635 signal. The following output buffer configurations are supported:
2637 @itemize @minus
2638 @item Push-pull with one FTDI output as (non-)inverted data line
2639 @item Open drain with one FTDI output as (non-)inverted output-enable
2640 @item Tristate with one FTDI output as (non-)inverted data line and another
2641 FTDI output as (non-)inverted output-enable
2642 @item Unbuffered, using the FTDI GPIO as a tristate output directly by
2643 switching data and direction as necessary
2644 @end itemize
2646 These interfaces have several commands, used to configure the driver
2647 before initializing the JTAG scan chain:
2649 @deffn {Config Command} {ftdi_vid_pid} [vid pid]+
2650 The vendor ID and product ID of the adapter. If not specified, the FTDI
2651 default values are used.
2652 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2653 @example
2654 ftdi_vid_pid 0x0403 0xcff8 0x15ba 0x0003
2655 @end example
2656 @end deffn
2658 @deffn {Config Command} {ftdi_device_desc} description
2659 Provides the USB device description (the @emph{iProduct string})
2660 of the adapter. If not specified, the device description is ignored
2661 during device selection.
2662 @end deffn
2664 @deffn {Config Command} {ftdi_serial} serial-number
2665 Specifies the @var{serial-number} of the adapter to use,
2666 in case the vendor provides unique IDs and more than one adapter
2667 is connected to the host.
2668 If not specified, serial numbers are not considered.
2669 (Note that USB serial numbers can be arbitrary Unicode strings,
2670 and are not restricted to containing only decimal digits.)
2671 @end deffn
2673 @deffn {Config Command} {ftdi_channel} channel
2674 Selects the channel of the FTDI device to use for MPSSE operations. Most
2675 adapters use the default, channel 0, but there are exceptions.
2676 @end deffn
2678 @deffn {Config Command} {ftdi_layout_init} data direction
2679 Specifies the initial values of the FTDI GPIO data and direction registers.
2680 Each value is a 16-bit number corresponding to the concatenation of the high
2681 and low FTDI GPIO registers. The values should be selected based on the
2682 schematics of the adapter, such that all signals are set to safe levels with
2683 minimal impact on the target system. Avoid floating inputs, conflicting outputs
2684 and initially asserted reset signals.
2685 @end deffn
2687 @deffn {Config Command} {ftdi_layout_signal} name [@option{-data}|@option{-ndata} data_mask] [@option{-oe}|@option{-noe} oe_mask]
2688 Creates a signal with the specified @var{name}, controlled by one or more FTDI
2689 GPIO pins via a range of possible buffer connections. The masks are FTDI GPIO
2690 register bitmasks to tell the driver the connection and type of the output
2691 buffer driving the respective signal. @var{data_mask} is the bitmask for the
2692 pin(s) connected to the data input of the output buffer. @option{-ndata} is
2693 used with inverting data inputs and @option{-data} with non-inverting inputs.
2694 The @option{-oe} (or @option{-noe}) option tells where the output-enable (or
2695 not-output-enable) input to the output buffer is connected.
2697 Both @var{data_mask} and @var{oe_mask} need not be specified. For example, a
2698 simple open-collector transistor driver would be specified with @option{-oe}
2699 only. In that case the signal can only be set to drive low or to Hi-Z and the
2700 driver will complain if the signal is set to drive high. Which means that if
2701 it's a reset signal, @command{reset_config} must be specified as
2702 @option{srst_open_drain}, not @option{srst_push_pull}.
2704 A special case is provided when @option{-data} and @option{-oe} is set to the
2705 same bitmask. Then the FTDI pin is considered being connected straight to the
2706 target without any buffer. The FTDI pin is then switched between output and
2707 input as necessary to provide the full set of low, high and Hi-Z
2708 characteristics. In all other cases, the pins specified in a signal definition
2709 are always driven by the FTDI.
2710 @end deffn
2712 @deffn {Command} {ftdi_set_signal} name @option{0}|@option{1}|@option{z}
2713 Set a previously defined signal to the specified level.
2714 @itemize @minus
2715 @item @option{0}, drive low
2716 @item @option{1}, drive high
2717 @item @option{z}, set to high-impedance
2718 @end itemize
2719 @end deffn
2721 For example adapter definitions, see the configuration files shipped in the
2722 @file{interface/ftdi} directory.
2723 @end deffn
2725 @deffn {Interface Driver} {remote_bitbang}
2726 Drive JTAG from a remote process. This sets up a UNIX or TCP socket connection
2727 with a remote process and sends ASCII encoded bitbang requests to that process
2728 instead of directly driving JTAG.
2730 The remote_bitbang driver is useful for debugging software running on
2731 processors which are being simulated.
2733 @deffn {Config Command} {remote_bitbang_port} number
2734 Specifies the TCP port of the remote process to connect to or 0 to use UNIX
2735 sockets instead of TCP.
2736 @end deffn
2738 @deffn {Config Command} {remote_bitbang_host} hostname
2739 Specifies the hostname of the remote process to connect to using TCP, or the
2740 name of the UNIX socket to use if remote_bitbang_port is 0.
2741 @end deffn
2743 For example, to connect remotely via TCP to the host foobar you might have
2744 something like:
2746 @example
2747 interface remote_bitbang
2748 remote_bitbang_port 3335
2749 remote_bitbang_host foobar
2750 @end example
2752 To connect to another process running locally via UNIX sockets with socket
2753 named mysocket:
2755 @example
2756 interface remote_bitbang
2757 remote_bitbang_port 0
2758 remote_bitbang_host mysocket
2759 @end example
2760 @end deffn
2762 @deffn {Interface Driver} {usb_blaster}
2763 USB JTAG/USB-Blaster compatibles over one of the userspace libraries
2764 for FTDI chips. These interfaces have several commands, used to
2765 configure the driver before initializing the JTAG scan chain:
2767 @deffn {Config Command} {usb_blaster_device_desc} description
2768 Provides the USB device description (the @emph{iProduct string})
2769 of the FTDI FT245 device. If not
2770 specified, the FTDI default value is used. This setting is only valid
2771 if compiled with FTD2XX support.
2772 @end deffn
2774 @deffn {Config Command} {usb_blaster_vid_pid} vid pid
2775 The vendor ID and product ID of the FTDI FT245 device. If not specified,
2776 default values are used.
2777 Currently, only one @var{vid}, @var{pid} pair may be given, e.g. for
2778 Altera USB-Blaster (default):
2779 @example
2780 usb_blaster_vid_pid 0x09FB 0x6001
2781 @end example
2782 The following VID/PID is for Kolja Waschk's USB JTAG:
2783 @example
2784 usb_blaster_vid_pid 0x16C0 0x06AD
2785 @end example
2786 @end deffn
2788 @deffn {Command} {usb_blaster} (@option{pin6}|@option{pin8}) (@option{0}|@option{1})
2789 Sets the state of the unused GPIO pins on USB-Blasters (pins 6 and 8 on the
2790 female JTAG header). These pins can be used as SRST and/or TRST provided the
2791 appropriate connections are made on the target board.
2793 For example, to use pin 6 as SRST (as with an AVR board):
2794 @example
2795 $_TARGETNAME configure -event reset-assert \
2796 "usb_blaster pin6 1; wait 1; usb_blaster pin6 0"
2797 @end example
2798 @end deffn
2800 @end deffn
2802 @deffn {Interface Driver} {gw16012}
2803 Gateworks GW16012 JTAG programmer.
2804 This has one driver-specific command:
2806 @deffn {Config Command} {parport_port} [port_number]
2807 Display either the address of the I/O port
2808 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2809 If a parameter is provided, first switch to use that port.
2810 This is a write-once setting.
2811 @end deffn
2812 @end deffn
2814 @deffn {Interface Driver} {jlink}
2815 Segger J-Link family of USB adapters. It currently supports only the JTAG transport.
2817 @quotation Compatibility Note
2818 Segger released many firmware versions for the many harware versions they
2819 produced. OpenOCD was extensively tested and intended to run on all of them,
2820 but some combinations were reported as incompatible. As a general
2821 recommendation, it is advisable to use the latest firmware version
2822 available for each hardware version. However the current V8 is a moving
2823 target, and Segger firmware versions released after the OpenOCD was
2824 released may not be compatible. In such cases it is recommended to
2825 revert to the last known functional version. For 0.5.0, this is from
2826 "Feb 8 2012 14:30:39", packed with 4.42c. For 0.6.0, the last known
2827 version is from "May 3 2012 18:36:22", packed with 4.46f.
2828 @end quotation
2830 @deffn {Command} {jlink caps}
2831 Display the device firmware capabilities.
2832 @end deffn
2833 @deffn {Command} {jlink info}
2834 Display various device information, like hardware version, firmware version, current bus status.
2835 @end deffn
2836 @deffn {Command} {jlink hw_jtag} [@option{2}|@option{3}]
2837 Set the JTAG protocol version to be used. Without argument, show the actual JTAG protocol version.
2838 @end deffn
2839 @deffn {Command} {jlink config}
2840 Display the J-Link configuration.
2841 @end deffn
2842 @deffn {Command} {jlink config kickstart} [val]
2843 Set the Kickstart power on JTAG-pin 19. Without argument, show the Kickstart configuration.
2844 @end deffn
2845 @deffn {Command} {jlink config mac_address} [@option{ff:ff:ff:ff:ff:ff}]
2846 Set the MAC address of the J-Link Pro. Without argument, show the MAC address.
2847 @end deffn
2848 @deffn {Command} {jlink config ip} [@option{A.B.C.D}(@option{/E}|@option{F.G.H.I})]
2849 Set the IP configuration of the J-Link Pro, where A.B.C.D is the IP address,
2850 E the bit of the subnet mask and
2851 F.G.H.I the subnet mask. Without arguments, show the IP configuration.
2852 @end deffn
2853 @deffn {Command} {jlink config usb_address} [@option{0x00} to @option{0x03} or @option{0xff}]
2854 Set the USB address; this will also change the product id. Without argument, show the USB address.
2855 @end deffn
2856 @deffn {Command} {jlink config reset}
2857 Reset the current configuration.
2858 @end deffn
2859 @deffn {Command} {jlink config save}
2860 Save the current configuration to the internal persistent storage.
2861 @end deffn
2862 @deffn {Config} {jlink pid} val
2863 Set the USB PID of the interface. As a configuration command, it can be used only before 'init'.
2864 @end deffn
2865 @end deffn
2867 @deffn {Interface Driver} {parport}
2868 Supports PC parallel port bit-banging cables:
2869 Wigglers, PLD download cable, and more.
2870 These interfaces have several commands, used to configure the driver
2871 before initializing the JTAG scan chain:
2873 @deffn {Config Command} {parport_cable} name
2874 Set the layout of the parallel port cable used to connect to the target.
2875 This is a write-once setting.
2876 Currently valid cable @var{name} values include:
2878 @itemize @minus
2879 @item @b{altium} Altium Universal JTAG cable.
2880 @item @b{arm-jtag} Same as original wiggler except SRST and
2881 TRST connections reversed and TRST is also inverted.
2882 @item @b{chameleon} The Amontec Chameleon's CPLD when operated
2883 in configuration mode. This is only used to
2884 program the Chameleon itself, not a connected target.
2885 @item @b{dlc5} The Xilinx Parallel cable III.
2886 @item @b{flashlink} The ST Parallel cable.
2887 @item @b{lattice} Lattice ispDOWNLOAD Cable
2888 @item @b{old_amt_wiggler} The Wiggler configuration that comes with
2889 some versions of
2890 Amontec's Chameleon Programmer. The new version available from
2891 the website uses the original Wiggler layout ('@var{wiggler}')
2892 @item @b{triton} The parallel port adapter found on the
2893 ``Karo Triton 1 Development Board''.
2894 This is also the layout used by the HollyGates design
2895 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
2896 @item @b{wiggler} The original Wiggler layout, also supported by
2897 several clones, such as the Olimex ARM-JTAG
2898 @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
2899 @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
2900 @end itemize
2901 @end deffn
2903 @deffn {Config Command} {parport_port} [port_number]
2904 Display either the address of the I/O port
2905 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2906 If a parameter is provided, first switch to use that port.
2907 This is a write-once setting.
2909 When using PPDEV to access the parallel port, use the number of the parallel port:
2910 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
2911 you may encounter a problem.
2912 @end deffn
2914 @deffn Command {parport_toggling_time} [nanoseconds]
2915 Displays how many nanoseconds the hardware needs to toggle TCK;
2916 the parport driver uses this value to obey the
2917 @command{adapter_khz} configuration.
2918 When the optional @var{nanoseconds} parameter is given,
2919 that setting is changed before displaying the current value.
2921 The default setting should work reasonably well on commodity PC hardware.
2922 However, you may want to calibrate for your specific hardware.
2923 @quotation Tip
2924 To measure the toggling time with a logic analyzer or a digital storage
2925 oscilloscope, follow the procedure below:
2926 @example
2927 > parport_toggling_time 1000
2928 > adapter_khz 500
2929 @end example
2930 This sets the maximum JTAG clock speed of the hardware, but
2931 the actual speed probably deviates from the requested 500 kHz.
2932 Now, measure the time between the two closest spaced TCK transitions.
2933 You can use @command{runtest 1000} or something similar to generate a
2934 large set of samples.
2935 Update the setting to match your measurement:
2936 @example
2937 > parport_toggling_time <measured nanoseconds>
2938 @end example
2939 Now the clock speed will be a better match for @command{adapter_khz rate}
2940 commands given in OpenOCD scripts and event handlers.
2942 You can do something similar with many digital multimeters, but note
2943 that you'll probably need to run the clock continuously for several
2944 seconds before it decides what clock rate to show. Adjust the
2945 toggling time up or down until the measured clock rate is a good
2946 match for the adapter_khz rate you specified; be conservative.
2947 @end quotation
2948 @end deffn
2950 @deffn {Config Command} {parport_write_on_exit} (@option{on}|@option{off})
2951 This will configure the parallel driver to write a known
2952 cable-specific value to the parallel interface on exiting OpenOCD.
2953 @end deffn
2955 For example, the interface configuration file for a
2956 classic ``Wiggler'' cable on LPT2 might look something like this:
2958 @example
2959 interface parport
2960 parport_port 0x278
2961 parport_cable wiggler
2962 @end example
2963 @end deffn
2965 @deffn {Interface Driver} {presto}
2966 ASIX PRESTO USB JTAG programmer.
2967 @deffn {Config Command} {presto_serial} serial_string
2968 Configures the USB serial number of the Presto device to use.
2969 @end deffn
2970 @end deffn
2972 @deffn {Interface Driver} {rlink}
2973 Raisonance RLink USB adapter
2974 @end deffn
2976 @deffn {Interface Driver} {usbprog}
2977 usbprog is a freely programmable USB adapter.
2978 @end deffn
2980 @deffn {Interface Driver} {vsllink}
2981 vsllink is part of Versaloon which is a versatile USB programmer.
2983 @quotation Note
2984 This defines quite a few driver-specific commands,
2985 which are not currently documented here.
2986 @end quotation
2987 @end deffn
2989 @deffn {Interface Driver} {hla}
2990 This is a driver that supports multiple High Level Adapters.
2991 This type of adapter does not expose some of the lower level api's
2992 that OpenOCD would normally use to access the target.
2994 Currently supported adapters include the ST STLINK and TI ICDI.
2996 @deffn {Config Command} {hla_device_desc} description
2997 Currently Not Supported.
2998 @end deffn
3000 @deffn {Config Command} {hla_serial} serial
3001 Currently Not Supported.
3002 @end deffn
3004 @deffn {Config Command} {hla_layout} (@option{stlink}|@option{icdi})
3005 Specifies the adapter layout to use.
3006 @end deffn
3008 @deffn {Config Command} {hla_vid_pid} vid pid
3009 The vendor ID and product ID of the device.
3010 @end deffn
3012 @deffn {Config Command} {stlink_api} api_level
3013 Manually sets the stlink api used, valid options are 1 or 2. (@b{STLINK Only}).
3014 @end deffn
3015 @end deffn
3017 @deffn {Interface Driver} {opendous}
3018 opendous-jtag is a freely programmable USB adapter.
3019 @end deffn
3021 @deffn {Interface Driver} {ulink}
3022 This is the Keil ULINK v1 JTAG debugger.
3023 @end deffn
3025 @deffn {Interface Driver} {ZY1000}
3026 This is the Zylin ZY1000 JTAG debugger.
3027 @end deffn
3029 @quotation Note
3030 This defines some driver-specific commands,
3031 which are not currently documented here.
3032 @end quotation
3034 @deffn Command power [@option{on}|@option{off}]
3035 Turn power switch to target on/off.
3036 No arguments: print status.
3037 @end deffn
3039 @section Transport Configuration
3040 @cindex Transport
3041 As noted earlier, depending on the version of OpenOCD you use,
3042 and the debug adapter you are using,
3043 several transports may be available to
3044 communicate with debug targets (or perhaps to program flash memory).
3045 @deffn Command {transport list}
3046 displays the names of the transports supported by this
3047 version of OpenOCD.
3048 @end deffn
3050 @deffn Command {transport select} transport_name
3051 Select which of the supported transports to use in this OpenOCD session.
3052 The transport must be supported by the debug adapter hardware and by the
3053 version of OPenOCD you are using (including the adapter's driver).
3054 No arguments: returns name of session's selected transport.
3055 @end deffn
3057 @subsection JTAG Transport
3058 @cindex JTAG
3059 JTAG is the original transport supported by OpenOCD, and most
3060 of the OpenOCD commands support it.
3061 JTAG transports expose a chain of one or more Test Access Points (TAPs),
3062 each of which must be explicitly declared.
3063 JTAG supports both debugging and boundary scan testing.
3064 Flash programming support is built on top of debug support.
3065 @subsection SWD Transport
3066 @cindex SWD
3067 @cindex Serial Wire Debug
3068 SWD (Serial Wire Debug) is an ARM-specific transport which exposes one
3069 Debug Access Point (DAP, which must be explicitly declared.
3070 (SWD uses fewer signal wires than JTAG.)
3071 SWD is debug-oriented, and does not support boundary scan testing.
3072 Flash programming support is built on top of debug support.
3073 (Some processors support both JTAG and SWD.)
3074 @deffn Command {swd newdap} ...
3075 Declares a single DAP which uses SWD transport.
3076 Parameters are currently the same as "jtag newtap" but this is
3077 expected to change.
3078 @end deffn
3079 @deffn Command {swd wcr trn prescale}
3080 Updates TRN (turnaraound delay) and prescaling.fields of the
3081 Wire Control Register (WCR).
3082 No parameters: displays current settings.
3083 @end deffn
3085 @subsection SPI Transport
3086 @cindex SPI
3087 @cindex Serial Peripheral Interface
3088 The Serial Peripheral Interface (SPI) is a general purpose transport
3089 which uses four wire signaling. Some processors use it as part of a
3090 solution for flash programming.
3092 @anchor{jtagspeed}
3093 @section JTAG Speed
3094 JTAG clock setup is part of system setup.
3095 It @emph{does not belong with interface setup} since any interface
3096 only knows a few of the constraints for the JTAG clock speed.
3097 Sometimes the JTAG speed is
3098 changed during the target initialization process: (1) slow at
3099 reset, (2) program the CPU clocks, (3) run fast.
3100 Both the "slow" and "fast" clock rates are functions of the
3101 oscillators used, the chip, the board design, and sometimes
3102 power management software that may be active.
3104 The speed used during reset, and the scan chain verification which
3105 follows reset, can be adjusted using a @code{reset-start}
3106 target event handler.
3107 It can then be reconfigured to a faster speed by a
3108 @code{reset-init} target event handler after it reprograms those
3109 CPU clocks, or manually (if something else, such as a boot loader,
3110 sets up those clocks).
3111 @xref{targetevents,,Target Events}.
3112 When the initial low JTAG speed is a chip characteristic, perhaps
3113 because of a required oscillator speed, provide such a handler
3114 in the target config file.
3115 When that speed is a function of a board-specific characteristic
3116 such as which speed oscillator is used, it belongs in the board
3117 config file instead.
3118 In both cases it's safest to also set the initial JTAG clock rate
3119 to that same slow speed, so that OpenOCD never starts up using a
3120 clock speed that's faster than the scan chain can support.
3122 @example
3123 jtag_rclk 3000
3124 $_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
3125 @end example
3127 If your system supports adaptive clocking (RTCK), configuring
3128 JTAG to use that is probably the most robust approach.
3129 However, it introduces delays to synchronize clocks; so it
3130 may not be the fastest solution.
3132 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
3133 instead of @command{adapter_khz}, but only for (ARM) cores and boards
3134 which support adaptive clocking.
3136 @deffn {Command} adapter_khz max_speed_kHz
3137 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
3138 JTAG interfaces usually support a limited number of
3139 speeds. The speed actually used won't be faster
3140 than the speed specified.
3142 Chip data sheets generally include a top JTAG clock rate.
3143 The actual rate is often a function of a CPU core clock,
3144 and is normally less than that peak rate.
3145 For example, most ARM cores accept at most one sixth of the CPU clock.
3147 Speed 0 (khz) selects RTCK method.
3148 @xref{faqrtck,,FAQ RTCK}.
3149 If your system uses RTCK, you won't need to change the
3150 JTAG clocking after setup.
3151 Not all interfaces, boards, or targets support ``rtck''.
3152 If the interface device can not
3153 support it, an error is returned when you try to use RTCK.
3154 @end deffn
3156 @defun jtag_rclk fallback_speed_kHz
3157 @cindex adaptive clocking
3158 @cindex RTCK
3159 This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
3160 If that fails (maybe the interface, board, or target doesn't
3161 support it), falls back to the specified frequency.
3162 @example
3163 # Fall back to 3mhz if RTCK is not supported
3164 jtag_rclk 3000
3165 @end example
3166 @end defun
3168 @node Reset Configuration
3169 @chapter Reset Configuration
3170 @cindex Reset Configuration
3172 Every system configuration may require a different reset
3173 configuration. This can also be quite confusing.
3174 Resets also interact with @var{reset-init} event handlers,
3175 which do things like setting up clocks and DRAM, and
3176 JTAG clock rates. (@xref{jtagspeed,,JTAG Speed}.)
3177 They can also interact with JTAG routers.
3178 Please see the various board files for examples.
3180 @quotation Note
3181 To maintainers and integrators:
3182 Reset configuration touches several things at once.
3183 Normally the board configuration file
3184 should define it and assume that the JTAG adapter supports
3185 everything that's wired up to the board's JTAG connector.
3187 However, the target configuration file could also make note
3188 of something the silicon vendor has done inside the chip,
3189 which will be true for most (or all) boards using that chip.
3190 And when the JTAG adapter doesn't support everything, the
3191 user configuration file will need to override parts of
3192 the reset configuration provided by other files.
3193 @end quotation
3195 @section Types of Reset
3197 There are many kinds of reset possible through JTAG, but
3198 they may not all work with a given board and adapter.
3199 That's part of why reset configuration can be error prone.
3201 @itemize @bullet
3202 @item
3203 @emph{System Reset} ... the @emph{SRST} hardware signal
3204 resets all chips connected to the JTAG adapter, such as processors,
3205 power management chips, and I/O controllers. Normally resets triggered
3206 with this signal behave exactly like pressing a RESET button.
3207 @item
3208 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
3209 just the TAP controllers connected to the JTAG adapter.
3210 Such resets should not be visible to the rest of the system; resetting a
3211 device's TAP controller just puts that controller into a known state.
3212 @item
3213 @emph{Emulation Reset} ... many devices can be reset through JTAG
3214 commands. These resets are often distinguishable from system
3215 resets, either explicitly (a "reset reason" register says so)
3216 or implicitly (not all parts of the chip get reset).
3217 @item
3218 @emph{Other Resets} ... system-on-chip devices often support
3219 several other types of reset.
3220 You may need to arrange that a watchdog timer stops
3221 while debugging, preventing a watchdog reset.
3222 There may be individual module resets.
3223 @end itemize
3225 In the best case, OpenOCD can hold SRST, then reset
3226 the TAPs via TRST and send commands through JTAG to halt the
3227 CPU at the reset vector before the 1st instruction is executed.
3228 Then when it finally releases the SRST signal, the system is
3229 halted under debugger control before any code has executed.
3230 This is the behavior required to support the @command{reset halt}
3231 and @command{reset init} commands; after @command{reset init} a
3232 board-specific script might do things like setting up DRAM.
3233 (@xref{resetcommand,,Reset Command}.)
3235 @anchor{srstandtrstissues}
3236 @section SRST and TRST Issues
3238 Because SRST and TRST are hardware signals, they can have a
3239 variety of system-specific constraints. Some of the most
3240 common issues are:
3242 @itemize @bullet
3244 @item @emph{Signal not available} ... Some boards don't wire
3245 SRST or TRST to the JTAG connector. Some JTAG adapters don't
3246 support such signals even if they are wired up.
3247 Use the @command{reset_config} @var{signals} options to say
3248 when either of those signals is not connected.
3249 When SRST is not available, your code might not be able to rely
3250 on controllers having been fully reset during code startup.
3251 Missing TRST is not a problem, since JTAG-level resets can
3252 be triggered using with TMS signaling.
3254 @item @emph{Signals shorted} ... Sometimes a chip, board, or
3255 adapter will connect SRST to TRST, instead of keeping them separate.
3256 Use the @command{reset_config} @var{combination} options to say
3257 when those signals aren't properly independent.
3259 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
3260 delay circuit, reset supervisor, or on-chip features can extend
3261 the effect of a JTAG adapter's reset for some time after the adapter
3262 stops issuing the reset. For example, there may be chip or board
3263 requirements that all reset pulses last for at least a
3264 certain amount of time; and reset buttons commonly have
3265 hardware debouncing.
3266 Use the @command{adapter_nsrst_delay} and @command{jtag_ntrst_delay}
3267 commands to say when extra delays are needed.
3269 @item @emph{Drive type} ... Reset lines often have a pullup
3270 resistor, letting the JTAG interface treat them as open-drain
3271 signals. But that's not a requirement, so the adapter may need
3272 to use push/pull output drivers.
3273 Also, with weak pullups it may be advisable to drive
3274 signals to both levels (push/pull) to minimize rise times.
3275 Use the @command{reset_config} @var{trst_type} and
3276 @var{srst_type} parameters to say how to drive reset signals.
3278 @item @emph{Special initialization} ... Targets sometimes need
3279 special JTAG initialization sequences to handle chip-specific
3280 issues (not limited to errata).
3281 For example, certain JTAG commands might need to be issued while
3282 the system as a whole is in a reset state (SRST active)
3283 but the JTAG scan chain is usable (TRST inactive).
3284 Many systems treat combined assertion of SRST and TRST as a
3285 trigger for a harder reset than SRST alone.
3286 Such custom reset handling is discussed later in this chapter.
3287 @end itemize
3289 There can also be other issues.
3290 Some devices don't fully conform to the JTAG specifications.
3291 Trivial system-specific differences are common, such as
3292 SRST and TRST using slightly different names.
3293 There are also vendors who distribute key JTAG documentation for
3294 their chips only to developers who have signed a Non-Disclosure
3295 Agreement (NDA).
3297 Sometimes there are chip-specific extensions like a requirement to use
3298 the normally-optional TRST signal (precluding use of JTAG adapters which
3299 don't pass TRST through), or needing extra steps to complete a TAP reset.
3301 In short, SRST and especially TRST handling may be very finicky,
3302 needing to cope with both architecture and board specific constraints.
3304 @section Commands for Handling Resets
3306 @deffn {Command} adapter_nsrst_assert_width milliseconds
3307 Minimum amount of time (in milliseconds) OpenOCD should wait
3308 after asserting nSRST (active-low system reset) before
3309 allowing it to be deasserted.
3310 @end deffn
3312 @deffn {Command} adapter_nsrst_delay milliseconds
3313 How long (in milliseconds) OpenOCD should wait after deasserting
3314 nSRST (active-low system reset) before starting new JTAG operations.
3315 When a board has a reset button connected to SRST line it will
3316 probably have hardware debouncing, implying you should use this.
3317 @end deffn
3319 @deffn {Command} jtag_ntrst_assert_width milliseconds
3320 Minimum amount of time (in milliseconds) OpenOCD should wait
3321 after asserting nTRST (active-low JTAG TAP reset) before
3322 allowing it to be deasserted.
3323 @end deffn
3325 @deffn {Command} jtag_ntrst_delay milliseconds
3326 How long (in milliseconds) OpenOCD should wait after deasserting
3327 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
3328 @end deffn
3330 @deffn {Command} reset_config mode_flag ...
3331 This command displays or modifies the reset configuration
3332 of your combination of JTAG board and target in target
3333 configuration scripts.
3335 Information earlier in this section describes the kind of problems
3336 the command is intended to address (@pxref{srstandtrstissues,,SRST and TRST Issues}).
3337 As a rule this command belongs only in board config files,
3338 describing issues like @emph{board doesn't connect TRST};
3339 or in user config files, addressing limitations derived
3340 from a particular combination of interface and board.
3341 (An unlikely example would be using a TRST-only adapter
3342 with a board that only wires up SRST.)
3344 The @var{mode_flag} options can be specified in any order, but only one
3345 of each type -- @var{signals}, @var{combination}, @var{gates},
3346 @var{trst_type}, @var{srst_type} and @var{connect_type}
3347 -- may be specified at a time.
3348 If you don't provide a new value for a given type, its previous
3349 value (perhaps the default) is unchanged.
3350 For example, this means that you don't need to say anything at all about
3351 TRST just to declare that if the JTAG adapter should want to drive SRST,
3352 it must explicitly be driven high (@option{srst_push_pull}).
3354 @itemize
3355 @item
3356 @var{signals} can specify which of the reset signals are connected.
3357 For example, If the JTAG interface provides SRST, but the board doesn't
3358 connect that signal properly, then OpenOCD can't use it.
3359 Possible values are @option{none} (the default), @option{trst_only},
3360 @option{srst_only} and @option{trst_and_srst}.
3362 @quotation Tip
3363 If your board provides SRST and/or TRST through the JTAG connector,
3364 you must declare that so those signals can be used.
3365 @end quotation
3367 @item
3368 The @var{combination} is an optional value specifying broken reset
3369 signal implementations.
3370 The default behaviour if no option given is @option{separate},
3371 indicating everything behaves normally.
3372 @option{srst_pulls_trst} states that the
3373 test logic is reset together with the reset of the system (e.g. NXP
3374 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
3375 the system is reset together with the test logic (only hypothetical, I
3376 haven't seen hardware with such a bug, and can be worked around).
3377 @option{combined} implies both @option{srst_pulls_trst} and
3378 @option{trst_pulls_srst}.
3380 @item
3381 The @var{gates} tokens control flags that describe some cases where
3382 JTAG may be unvailable during reset.
3383 @option{srst_gates_jtag} (default)
3384 indicates that asserting SRST gates the
3385 JTAG clock. This means that no communication can happen on JTAG
3386 while SRST is asserted.
3387 Its converse is @option{srst_nogate}, indicating that JTAG commands
3388 can safely be issued while SRST is active.
3390 @item
3391 The @var{connect_type} tokens control flags that describe some cases where
3392 SRST is asserted while connecting to the target. @option{srst_nogate}
3393 is required to use this option.
3394 @option{connect_deassert_srst} (default)
3395 indicates that SRST will not be asserted while connecting to the target.
3396 Its converse is @option{connect_assert_srst}, indicating that SRST will
3397 be asserted before any target connection.
3398 Only some targets support this feature, STM32 and STR9 are examples.
3399 This feature is useful if you are unable to connect to your target due
3400 to incorrect options byte config or illegal program execution.
3401 @end itemize
3403 The optional @var{trst_type} and @var{srst_type} parameters allow the
3404 driver mode of each reset line to be specified. These values only affect
3405 JTAG interfaces with support for different driver modes, like the Amontec
3406 JTAGkey and JTAG Accelerator. Also, they are necessarily ignored if the
3407 relevant signal (TRST or SRST) is not connected.
3409 @itemize
3410 @item
3411 Possible @var{trst_type} driver modes for the test reset signal (TRST)
3412 are the default @option{trst_push_pull}, and @option{trst_open_drain}.
3413 Most boards connect this signal to a pulldown, so the JTAG TAPs
3414 never leave reset unless they are hooked up to a JTAG adapter.
3416 @item
3417 Possible @var{srst_type} driver modes for the system reset signal (SRST)
3418 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
3419 Most boards connect this signal to a pullup, and allow the
3420 signal to be pulled low by various events including system
3421 powerup and pressing a reset button.
3422 @end itemize
3423 @end deffn
3425 @section Custom Reset Handling
3426 @cindex events
3428 OpenOCD has several ways to help support the various reset
3429 mechanisms provided by chip and board vendors.
3430 The commands shown in the previous section give standard parameters.
3431 There are also @emph{event handlers} associated with TAPs or Targets.
3432 Those handlers are Tcl procedures you can provide, which are invoked
3433 at particular points in the reset sequence.
3435 @emph{When SRST is not an option} you must set
3436 up a @code{reset-assert} event handler for your target.
3437 For example, some JTAG adapters don't include the SRST signal;
3438 and some boards have multiple targets, and you won't always
3439 want to reset everything at once.
3441 After configuring those mechanisms, you might still
3442 find your board doesn't start up or reset correctly.
3443 For example, maybe it needs a slightly different sequence
3444 of SRST and/or TRST manipulations, because of quirks that
3445 the @command{reset_config} mechanism doesn't address;
3446 or asserting both might trigger a stronger reset, which
3447 needs special attention.
3449 Experiment with lower level operations, such as @command{jtag_reset}
3450 and the @command{jtag arp_*} operations shown here,
3451 to find a sequence of operations that works.
3452 @xref{JTAG Commands}.
3453 When you find a working sequence, it can be used to override
3454 @command{jtag_init}, which fires during OpenOCD startup
3455 (@pxref{configurationstage,,Configuration Stage});
3456 or @command{init_reset}, which fires during reset processing.
3458 You might also want to provide some project-specific reset
3459 schemes. For example, on a multi-target board the standard
3460 @command{reset} command would reset all targets, but you
3461 may need the ability to reset only one target at time and
3462 thus want to avoid using the board-wide SRST signal.
3464 @deffn {Overridable Procedure} init_reset mode
3465 This is invoked near the beginning of the @command{reset} command,
3466 usually to provide as much of a cold (power-up) reset as practical.
3467 By default it is also invoked from @command{jtag_init} if
3468 the scan chain does not respond to pure JTAG operations.
3469 The @var{mode} parameter is the parameter given to the
3470 low level reset command (@option{halt},
3471 @option{init}, or @option{run}), @option{setup},
3472 or potentially some other value.
3474 The default implementation just invokes @command{jtag arp_init-reset}.
3475 Replacements will normally build on low level JTAG
3476 operations such as @command{jtag_reset}.
3477 Operations here must not address individual TAPs
3478 (or their associated targets)
3479 until the JTAG scan chain has first been verified to work.
3481 Implementations must have verified the JTAG scan chain before
3482 they return.
3483 This is done by calling @command{jtag arp_init}
3484 (or @command{jtag arp_init-reset}).
3485 @end deffn
3487 @deffn Command {jtag arp_init}
3488 This validates the scan chain using just the four
3489 standard JTAG signals (TMS, TCK, TDI, TDO).
3490 It starts by issuing a JTAG-only reset.
3491 Then it performs checks to verify that the scan chain configuration
3492 matches the TAPs it can observe.
3493 Those checks include checking IDCODE values for each active TAP,
3494 and verifying the length of their instruction registers using
3495 TAP @code{-ircapture} and @code{-irmask} values.
3496 If these tests all pass, TAP @code{setup} events are
3497 issued to all TAPs with handlers for that event.
3498 @end deffn
3500 @deffn Command {jtag arp_init-reset}
3501 This uses TRST and SRST to try resetting
3502 everything on the JTAG scan chain
3503 (and anything else connected to SRST).
3504 It then invokes the logic of @command{jtag arp_init}.
3505 @end deffn
3508 @node TAP Declaration
3509 @chapter TAP Declaration
3510 @cindex TAP declaration
3511 @cindex TAP configuration
3513 @emph{Test Access Ports} (TAPs) are the core of JTAG.
3514 TAPs serve many roles, including:
3516 @itemize @bullet
3517 @item @b{Debug Target} A CPU TAP can be used as a GDB debug target
3518 @item @b{Flash Programing} Some chips program the flash directly via JTAG.
3519 Others do it indirectly, making a CPU do it.
3520 @item @b{Program Download} Using the same CPU support GDB uses,
3521 you can initialize a DRAM controller, download code to DRAM, and then
3522 start running that code.
3523 @item @b{Boundary Scan} Most chips support boundary scan, which
3524 helps test for board assembly problems like solder bridges
3525 and missing connections
3526 @end itemize
3528 OpenOCD must know about the active TAPs on your board(s).
3529 Setting up the TAPs is the core task of your configuration files.
3530 Once those TAPs are set up, you can pass their names to code
3531 which sets up CPUs and exports them as GDB targets,
3532 probes flash memory, performs low-level JTAG operations, and more.
3534 @section Scan Chains
3535 @cindex scan chain
3537 TAPs are part of a hardware @dfn{scan chain},
3538 which is daisy chain of TAPs.
3539 They also need to be added to
3540 OpenOCD's software mirror of that hardware list,
3541 giving each member a name and associating other data with it.
3542 Simple scan chains, with a single TAP, are common in
3543 systems with a single microcontroller or microprocessor.
3544 More complex chips may have several TAPs internally.
3545 Very complex scan chains might have a dozen or more TAPs:
3546 several in one chip, more in the next, and connecting
3547 to other boards with their own chips and TAPs.
3549 You can display the list with the @command{scan_chain} command.
3550 (Don't confuse this with the list displayed by the @command{targets}
3551 command, presented in the next chapter.
3552 That only displays TAPs for CPUs which are configured as
3553 debugging targets.)
3554 Here's what the scan chain might look like for a chip more than one TAP:
3556 @verbatim
3557 TapName Enabled IdCode Expected IrLen IrCap IrMask
3558 -- ------------------ ------- ---------- ---------- ----- ----- ------
3559 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0x01 0x03
3560 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x01 0x0f
3561 2 omap5912.unknown Y 0x00000000 0x00000000 8 0x01 0x03
3562 @end verbatim
3564 OpenOCD can detect some of that information, but not all
3565 of it. @xref{autoprobing,,Autoprobing}.
3566 Unfortunately those TAPs can't always be autoconfigured,
3567 because not all devices provide good support for that.
3568 JTAG doesn't require supporting IDCODE instructions, and
3569 chips with JTAG routers may not link TAPs into the chain
3570 until they are told to do so.
3572 The configuration mechanism currently supported by OpenOCD
3573 requires explicit configuration of all TAP devices using
3574 @command{jtag newtap} commands, as detailed later in this chapter.
3575 A command like this would declare one tap and name it @code{chip1.cpu}:
3577 @example
3578 jtag newtap chip1 cpu -irlen 4 -expected-id 0x3ba00477
3579 @end example
3581 Each target configuration file lists the TAPs provided
3582 by a given chip.
3583 Board configuration files combine all the targets on a board,
3584 and so forth.
3585 Note that @emph{the order in which TAPs are declared is very important.}
3586 It must match the order in the JTAG scan chain, both inside
3587 a single chip and between them.
3588 @xref{faqtaporder,,FAQ TAP Order}.
3590 For example, the ST Microsystems STR912 chip has
3591 three separate TAPs@footnote{See the ST
3592 document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
3593 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
3594 @url{http://eu.st.com/stonline/products/literature/ds/13495.pdf}}.
3595 To configure those taps, @file{target/str912.cfg}
3596 includes commands something like this:
3598 @example
3599 jtag newtap str912 flash ... params ...
3600 jtag newtap str912 cpu ... params ...
3601 jtag newtap str912 bs ... params ...
3602 @end example
3604 Actual config files use a variable instead of literals like
3605 @option{str912}, to support more than one chip of each type.
3606 @xref{Config File Guidelines}.
3608 @deffn Command {jtag names}
3609 Returns the names of all current TAPs in the scan chain.
3610 Use @command{jtag cget} or @command{jtag tapisenabled}
3611 to examine attributes and state of each TAP.
3612 @example
3613 foreach t [jtag names] @{
3614 puts [format "TAP: %s\n" $t]
3615 @}
3616 @end example
3617 @end deffn
3619 @deffn Command {scan_chain}
3620 Displays the TAPs in the scan chain configuration,
3621 and their status.
3622 The set of TAPs listed by this command is fixed by
3623 exiting the OpenOCD configuration stage,
3624 but systems with a JTAG router can
3625 enable or disable TAPs dynamically.
3626 @end deffn
3628 @c FIXME! "jtag cget" should be able to return all TAP
3629 @c attributes, like "$target_name cget" does for targets.
3631 @c Probably want "jtag eventlist", and a "tap-reset" event
3632 @c (on entry to RESET state).
3634 @section TAP Names
3635 @cindex dotted name
3637 When TAP objects are declared with @command{jtag newtap},
3638 a @dfn{dotted.name} is created for the TAP, combining the
3639 name of a module (usually a chip) and a label for the TAP.
3640 For example: @code{xilinx.tap}, @code{str912.flash},
3641 @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
3642 Many other commands use that dotted.name to manipulate or
3643 refer to the TAP. For example, CPU configuration uses the
3644 name, as does declaration of NAND or NOR flash banks.
3646 The components of a dotted name should follow ``C'' symbol
3647 name rules: start with an alphabetic character, then numbers
3648 and underscores are OK; while others (including dots!) are not.
3650 @quotation Tip
3651 In older code, JTAG TAPs were numbered from 0..N.
3652 This feature is still present.
3653 However its use is highly discouraged, and
3654 should not be relied on; it will be removed by mid-2010.
3655 Update all of your scripts to use TAP names rather than numbers,
3656 by paying attention to the runtime warnings they trigger.
3657 Using TAP numbers in target configuration scripts prevents
3658 reusing those scripts on boards with multiple targets.
3659 @end quotation
3661 @section TAP Declaration Commands
3663 @c shouldn't this be(come) a {Config Command}?
3664 @deffn Command {jtag newtap} chipname tapname configparams...
3665 Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
3666 and configured according to the various @var{configparams}.
3668 The @var{chipname} is a symbolic name for the chip.
3669 Conventionally target config files use @code{$_CHIPNAME},
3670 defaulting to the model name given by the chip vendor but
3671 overridable.
3673 @cindex TAP naming convention
3674 The @var{tapname} reflects the role of that TAP,
3675 and should follow this convention:
3677 @itemize @bullet
3678 @item @code{bs} -- For boundary scan if this is a seperate TAP;
3679 @item @code{cpu} -- The main CPU of the chip, alternatively
3680 @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
3681 @code{arm1} and @code{arm2} on chips two ARMs, and so forth;
3682 @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
3683 @item @code{flash} -- If the chip has a flash TAP, like the str912;
3684 @item @code{jrc} -- For JTAG route controller (example: the ICEpick modules
3685 on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
3686 @item @code{tap} -- Should be used only FPGA or CPLD like devices
3687 with a single TAP;
3688 @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
3689 @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
3690 For example, the Freescale IMX31 has a SDMA (Smart DMA) with
3691 a JTAG TAP; that TAP should be named @code{sdma}.
3692 @end itemize
3694 Every TAP requires at least the following @var{configparams}:
3696 @itemize @bullet
3697 @item @code{-irlen} @var{NUMBER}
3698 @*The length in bits of the
3699 instruction register, such as 4 or 5 bits.
3700 @end itemize
3702 A TAP may also provide optional @var{configparams}:
3704 @itemize @bullet
3705 @item @code{-disable} (or @code{-enable})
3706 @*Use the @code{-disable} parameter to flag a TAP which is not
3707 linked in to the scan chain after a reset using either TRST
3708 or the JTAG state machine's @sc{reset} state.
3709 You may use @code{-enable} to highlight the default state
3710 (the TAP is linked in).
3711 @xref{enablinganddisablingtaps,,Enabling and Disabling TAPs}.
3712 @item @code{-expected-id} @var{number}
3713 @*A non-zero @var{number} represents a 32-bit IDCODE
3714 which you expect to find when the scan chain is examined.
3715 These codes are not required by all JTAG devices.
3716 @emph{Repeat the option} as many times as required if more than one
3717 ID code could appear (for example, multiple versions).
3718 Specify @var{number} as zero to suppress warnings about IDCODE
3719 values that were found but not included in the list.
3721 Provide this value if at all possible, since it lets OpenOCD
3722 tell when the scan chain it sees isn't right. These values
3723 are provided in vendors' chip documentation, usually a technical
3724 reference manual. Sometimes you may need to probe the JTAG
3725 hardware to find these values.
3726 @xref{autoprobing,,Autoprobing}.
3727 @item @code{-ignore-version}
3728 @*Specify this to ignore the JTAG version field in the @code{-expected-id}
3729 option. When vendors put out multiple versions of a chip, or use the same
3730 JTAG-level ID for several largely-compatible chips, it may be more practical
3731 to ignore the version field than to update config files to handle all of
3732 the various chip IDs. The version field is defined as bit 28-31 of the IDCODE.
3733 @item @code{-ircapture} @var{NUMBER}
3734 @*The bit pattern loaded by the TAP into the JTAG shift register
3735 on entry to the @sc{ircapture} state, such as 0x01.
3736 JTAG requires the two LSBs of this value to be 01.
3737 By default, @code{-ircapture} and @code{-irmask} are set
3738 up to verify that two-bit value. You may provide
3739 additional bits, if you know them, or indicate that
3740 a TAP doesn't conform to the JTAG specification.
3741 @item @code{-irmask} @var{NUMBER}
3742 @*A mask used with @code{-ircapture}
3743 to verify that instruction scans work correctly.
3744 Such scans are not used by OpenOCD except to verify that
3745 there seems to be no problems with JTAG scan chain operations.
3746 @end itemize
3747 @end deffn
3749 @section Other TAP commands
3751 @deffn Command {jtag cget} dotted.name @option{-event} name
3752 @deffnx Command {jtag configure} dotted.name @option{-event} name string
3753 At this writing this TAP attribute
3754 mechanism is used only for event handling.
3755 (It is not a direct analogue of the @code{cget}/@code{configure}
3756 mechanism for debugger targets.)
3757 See the next section for information about the available events.
3759 The @code{configure} subcommand assigns an event handler,
3760 a TCL string which is evaluated when the event is triggered.
3761 The @code{cget} subcommand returns that handler.
3762 @end deffn
3764 @section TAP Events
3765 @cindex events
3766 @cindex TAP events
3768 OpenOCD includes two event mechanisms.
3769 The one presented here applies to all JTAG TAPs.
3770 The other applies to debugger targets,
3771 which are associated with certain TAPs.
3773 The TAP events currently defined are:
3775 @itemize @bullet
3776 @item @b{post-reset}
3777 @* The TAP has just completed a JTAG reset.
3778 The tap may still be in the JTAG @sc{reset} state.
3779 Handlers for these events might perform initialization sequences
3780 such as issuing TCK cycles, TMS sequences to ensure
3781 exit from the ARM SWD mode, and more.
3783 Because the scan chain has not yet been verified, handlers for these events
3784 @emph{should not issue commands which scan the JTAG IR or DR registers}
3785 of any particular target.
3786 @b{NOTE:} As this is written (September 2009), nothing prevents such access.
3787 @item @b{setup}
3788 @* The scan chain has been reset and verified.
3789 This handler may enable TAPs as needed.
3790 @item @b{tap-disable}
3791 @* The TAP needs to be disabled. This handler should
3792 implement @command{jtag tapdisable}
3793 by issuing the relevant JTAG commands.
3794 @item @b{tap-enable}
3795 @* The TAP needs to be enabled. This handler should
3796 implement @command{jtag tapenable}
3797 by issuing the relevant JTAG commands.
3798 @end itemize
3800 If you need some action after each JTAG reset, which isn't actually
3801 specific to any TAP (since you can't yet trust the scan chain's
3802 contents to be accurate), you might:
3804 @example
3805 jtag configure CHIP.jrc -event post-reset @{
3806 echo "JTAG Reset done"
3807 ... non-scan jtag operations to be done after reset
3808 @}
3809 @end example
3812 @anchor{enablinganddisablingtaps}
3813 @section Enabling and Disabling TAPs
3814 @cindex JTAG Route Controller
3815 @cindex jrc
3817 In some systems, a @dfn{JTAG Route Controller} (JRC)
3818 is used to enable and/or disable specific JTAG TAPs.
3819 Many ARM based chips from Texas Instruments include
3820 an ``ICEpick'' module, which is a JRC.
3821 Such chips include DaVinci and OMAP3 processors.
3823 A given TAP may not be visible until the JRC has been
3824 told to link it into the scan chain; and if the JRC
3825 has been told to unlink that TAP, it will no longer
3826 be visible.
3827 Such routers address problems that JTAG ``bypass mode''
3828 ignores, such as:
3830 @itemize
3831 @item The scan chain can only go as fast as its slowest TAP.
3832 @item Having many TAPs slows instruction scans, since all
3833 TAPs receive new instructions.
3834 @item TAPs in the scan chain must be powered up, which wastes
3835 power and prevents debugging some power management mechanisms.
3836 @end itemize
3838 The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
3839 as implied by the existence of JTAG routers.
3840 However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
3841 does include a kind of JTAG router functionality.
3843 @c (a) currently the event handlers don't seem to be able to
3844 @c fail in a way that could lead to no-change-of-state.
3846 In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
3847 shown below, and is implemented using TAP event handlers.
3848 So for example, when defining a TAP for a CPU connected to
3849 a JTAG router, your @file{target.cfg} file
3850 should define TAP event handlers using
3851 code that looks something like this:
3853 @example
3854 jtag configure CHIP.cpu -event tap-enable @{
3855 ... jtag operations using CHIP.jrc
3856 @}
3857 jtag configure CHIP.cpu -event tap-disable @{
3858 ... jtag operations using CHIP.jrc
3859 @}
3860 @end example
3862 Then you might want that CPU's TAP enabled almost all the time:
3864 @example
3865 jtag configure $CHIP.jrc -event setup "jtag tapenable $CHIP.cpu"
3866 @end example
3868 Note how that particular setup event handler declaration
3869 uses quotes to evaluate @code{$CHIP} when the event is configured.
3870 Using brackets @{ @} would cause it to be evaluated later,
3871 at runtime, when it might have a different value.
3873 @deffn Command {jtag tapdisable} dotted.name
3874 If necessary, disables the tap
3875 by sending it a @option{tap-disable} event.
3876 Returns the string "1" if the tap
3877 specified by @var{dotted.name} is enabled,
3878 and "0" if it is disabled.
3879 @end deffn
3881 @deffn Command {jtag tapenable} dotted.name
3882 If necessary, enables the tap
3883 by sending it a @option{tap-enable} event.
3884 Returns the string "1" if the tap
3885 specified by @var{dotted.name} is enabled,
3886 and "0" if it is disabled.
3887 @end deffn
3889 @deffn Command {jtag tapisenabled} dotted.name
3890 Returns the string "1" if the tap
3891 specified by @var{dotted.name} is enabled,
3892 and "0" if it is disabled.
3894 @quotation Note
3895 Humans will find the @command{scan_chain} command more helpful
3896 for querying the state of the JTAG taps.
3897 @end quotation
3898 @end deffn
3900 @anchor{autoprobing}
3901 @section Autoprobing
3902 @cindex autoprobe
3903 @cindex JTAG autoprobe
3905 TAP configuration is the first thing that needs to be done
3906 after interface and reset configuration. Sometimes it's
3907 hard finding out what TAPs exist, or how they are identified.
3908 Vendor documentation is not always easy to find and use.
3910 To help you get past such problems, OpenOCD has a limited
3911 @emph{autoprobing} ability to look at the scan chain, doing
3912 a @dfn{blind interrogation} and then reporting the TAPs it finds.
3913 To use this mechanism, start the OpenOCD server with only data
3914 that configures your JTAG interface, and arranges to come up
3915 with a slow clock (many devices don't support fast JTAG clocks
3916 right when they come out of reset).
3918 For example, your @file{openocd.cfg} file might have:
3920 @example
3921 source [find interface/olimex-arm-usb-tiny-h.cfg]
3922 reset_config trst_and_srst
3923 jtag_rclk 8
3924 @end example
3926 When you start the server without any TAPs configured, it will
3927 attempt to autoconfigure the TAPs. There are two parts to this:
3929 @enumerate
3930 @item @emph{TAP discovery} ...
3931 After a JTAG reset (sometimes a system reset may be needed too),
3932 each TAP's data registers will hold the contents of either the
3933 IDCODE or BYPASS register.
3934 If JTAG communication is working, OpenOCD will see each TAP,
3935 and report what @option{-expected-id} to use with it.
3936 @item @emph{IR Length discovery} ...
3937 Unfortunately JTAG does not provide a reliable way to find out
3938 the value of the @option{-irlen} parameter to use with a TAP
3939 that is discovered.
3940 If OpenOCD can discover the length of a TAP's instruction
3941 register, it will report it.
3942 Otherwise you may need to consult vendor documentation, such
3943 as chip data sheets or BSDL files.
3944 @end enumerate
3946 In many cases your board will have a simple scan chain with just
3947 a single device. Here's what OpenOCD reported with one board
3948 that's a bit more complex:
3950 @example
3951 clock speed 8 kHz
3952 There are no enabled taps. AUTO PROBING MIGHT NOT WORK!!
3953 AUTO auto0.tap - use "jtag newtap auto0 tap -expected-id 0x2b900f0f ..."
3954 AUTO auto1.tap - use "jtag newtap auto1 tap -expected-id 0x07926001 ..."
3955 AUTO auto2.tap - use "jtag newtap auto2 tap -expected-id 0x0b73b02f ..."
3956 AUTO auto0.tap - use "... -irlen 4"
3957 AUTO auto1.tap - use "... -irlen 4"
3958 AUTO auto2.tap - use "... -irlen 6"
3959 no gdb ports allocated as no target has been specified
3960 @end example
3962 Given that information, you should be able to either find some existing
3963 config files to use, or create your own. If you create your own, you
3964 would configure from the bottom up: first a @file{target.cfg} file
3965 with these TAPs, any targets associated with them, and any on-chip
3966 resources; then a @file{board.cfg} with off-chip resources, clocking,
3967 and so forth.
3969 @node CPU Configuration
3970 @chapter CPU Configuration
3971 @cindex GDB target
3973 This chapter discusses how to set up GDB debug targets for CPUs.
3974 You can also access these targets without GDB
3975 (@pxref{Architecture and Core Commands},
3976 and @ref{targetstatehandling,,Target State handling}) and
3977 through various kinds of NAND and NOR flash commands.
3978 If you have multiple CPUs you can have multiple such targets.
3980 We'll start by looking at how to examine the targets you have,
3981 then look at how to add one more target and how to configure it.
3983 @section Target List
3984 @cindex target, current
3985 @cindex target, list
3987 All targets that have been set up are part of a list,
3988 where each member has a name.
3989 That name should normally be the same as the TAP name.
3990 You can display the list with the @command{targets}
3991 (plural!) command.
3992 This display often has only one CPU; here's what it might
3993 look like with more than one:
3994 @verbatim
3995 TargetName Type Endian TapName State
3996 -- ------------------ ---------- ------ ------------------ ------------
3997 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
3998 1 MyTarget cortex_m little mychip.foo tap-disabled
3999 @end verbatim
4001 One member of that list is the @dfn{current target}, which
4002 is implicitly referenced by many commands.
4003 It's the one marked with a @code{*} near the target name.
4004 In particular, memory addresses often refer to the address
4005 space seen by that current target.
4006 Commands like @command{mdw} (memory display words)
4007 and @command{flash erase_address} (erase NOR flash blocks)
4008 are examples; and there are many more.
4010 Several commands let you examine the list of targets:
4012 @deffn Command {target count}
4013 @emph{Note: target numbers are deprecated; don't use them.
4014 They will be removed shortly after August 2010, including this command.
4015 Iterate target using @command{target names}, not by counting.}
4017 Returns the number of targets, @math{N}.
4018 The highest numbered target is @math{N - 1}.
4019 @example
4020 set c [target count]
4021 for @{ set x 0 @} @{ $x < $c @} @{ incr x @} @{
4022 # Assuming you have created this function
4023 print_target_details $x
4024 @}
4025 @end example
4026 @end deffn
4028 @deffn Command {target current}
4029 Returns the name of the current target.
4030 @end deffn
4032 @deffn Command {target names}
4033 Lists the names of all current targets in the list.
4034 @example
4035 foreach t [target names] @{
4036 puts [format "Target: %s\n" $t]
4037 @}
4038 @end example
4039 @end deffn
4041 @deffn Command {target number} number
4042 @emph{Note: target numbers are deprecated; don't use them.
4043 They will be removed shortly after August 2010, including this command.}
4045 The list of targets is numbered starting at zero.
4046 This command returns the name of the target at index @var{number}.
4047 @example
4048 set thename [target number $x]
4049 puts [format "Target %d is: %s\n" $x $thename]
4050 @end example
4051 @end deffn
4053 @c yep, "target list" would have been better.
4054 @c plus maybe "target setdefault".
4056 @deffn Command targets [name]
4057 @emph{Note: the name of this command is plural. Other target
4058 command names are singular.}
4060 With no parameter, this command displays a table of all known
4061 targets in a user friendly form.
4063 With a parameter, this command sets the current target to
4064 the given target with the given @var{name}; this is
4065 only relevant on boards which have more than one target.
4066 @end deffn
4068 @section Target CPU Types and Variants
4069 @cindex target type
4070 @cindex CPU type
4071 @cindex CPU variant
4073 Each target has a @dfn{CPU type}, as shown in the output of
4074 the @command{targets} command. You need to specify that type
4075 when calling @command{target create}.
4076 The CPU type indicates more than just the instruction set.
4077 It also indicates how that instruction set is implemented,
4078 what kind of debug support it integrates,
4079 whether it has an MMU (and if so, what kind),
4080 what core-specific commands may be available
4081 (@pxref{Architecture and Core Commands}),
4082 and more.
4084 For some CPU types, OpenOCD also defines @dfn{variants} which
4085 indicate differences that affect their handling.
4086 For example, a particular implementation bug might need to be
4087 worked around in some chip versions.
4089 It's easy to see what target types are supported,
4090 since there's a command to list them.
4091 However, there is currently no way to list what target variants
4092 are supported (other than by reading the OpenOCD source code).
4094 @anchor{targettypes}
4095 @deffn Command {target types}
4096 Lists all supported target types.
4097 At this writing, the supported CPU types and variants are:
4099 @itemize @bullet
4100 @item @code{arm11} -- this is a generation of ARMv6 cores
4101 @item @code{arm720t} -- this is an ARMv4 core with an MMU
4102 @item @code{arm7tdmi} -- this is an ARMv4 core
4103 @item @code{arm920t} -- this is an ARMv4 core with an MMU
4104 @item @code{arm926ejs} -- this is an ARMv5 core with an MMU
4105 @item @code{arm966e} -- this is an ARMv5 core
4106 @item @code{arm9tdmi} -- this is an ARMv4 core
4107 @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
4108 (Support for this is preliminary and incomplete.)
4109 @item @code{cortex_a} -- this is an ARMv7 core with an MMU
4110 @item @code{cortex_m} -- this is an ARMv7 core, supporting only the
4111 compact Thumb2 instruction set.
4112 @item @code{dragonite} -- resembles arm966e
4113 @item @code{dsp563xx} -- implements Freescale's 24-bit DSP.
4114 (Support for this is still incomplete.)
4115 @item @code{fa526} -- resembles arm920 (w/o Thumb)
4116 @item @code{feroceon} -- resembles arm926
4117 @item @code{mips_m4k} -- a MIPS core. This supports one variant:
4118 @item @code{xscale} -- this is actually an architecture,
4119 not a CPU type. It is based on the ARMv5 architecture.
4120 There are several variants defined:
4121 @itemize @minus
4122 @item @code{ixp42x}, @code{ixp45x}, @code{ixp46x},
4123 @code{pxa27x} ... instruction register length is 7 bits
4124 @item @code{pxa250}, @code{pxa255},
4125 @code{pxa26x} ... instruction register length is 5 bits
4126 @item @code{pxa3xx} ... instruction register length is 11 bits
4127 @end itemize
4128 @end itemize
4129 @end deffn
4131 To avoid being confused by the variety of ARM based cores, remember
4132 this key point: @emph{ARM is a technology licencing company}.
4133 (See: @url{http://www.arm.com}.)
4134 The CPU name used by OpenOCD will reflect the CPU design that was
4135 licenced, not a vendor brand which incorporates that design.
4136 Name prefixes like arm7, arm9, arm11, and cortex
4137 reflect design generations;
4138 while names like ARMv4, ARMv5, ARMv6, and ARMv7
4139 reflect an architecture version implemented by a CPU design.
4141 @anchor{targetconfiguration}
4142 @section Target Configuration
4144 Before creating a ``target'', you must have added its TAP to the scan chain.
4145 When you've added that TAP, you will have a @code{dotted.name}
4146 which is used to set up the CPU support.
4147 The chip-specific configuration file will normally configure its CPU(s)
4148 right after it adds all of the chip's TAPs to the scan chain.
4150 Although you can set up a target in one step, it's often clearer if you
4151 use shorter commands and do it in two steps: create it, then configure
4152 optional parts.
4153 All operations on the target after it's created will use a new
4154 command, created as part of target creation.
4156 The two main things to configure after target creation are
4157 a work area, which usually has target-specific defaults even
4158 if the board setup code overrides them later;
4159 and event handlers (@pxref{targetevents,,Target Events}), which tend
4160 to be much more board-specific.
4161 The key steps you use might look something like this
4163 @example
4164 target create MyTarget cortex_m -chain-position mychip.cpu
4165 $MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
4166 $MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
4167 $MyTarget configure -event reset-init @{ myboard_reinit @}
4168 @end example
4170 You should specify a working area if you can; typically it uses some
4171 on-chip SRAM.
4172 Such a working area can speed up many things, including bulk
4173 writes to target memory;
4174 flash operations like checking to see if memory needs to be erased;
4175 GDB memory checksumming;
4176 and more.
4178 @quotation Warning