[openocd.git] / doc / openocd.texi
1 \input texinfo @c -*-texinfo-*-
2 @c %**start of header
3 @setfilename openocd.info
4 @settitle OpenOCD User's Guide
5 @dircategory Development
6 @direntry
7 * OpenOCD: (openocd). OpenOCD User's Guide
8 @end direntry
9 @paragraphindent 0
10 @c %**end of header
12 @include version.texi
14 @copying
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
21 @itemize @bullet
22 @item Copyright @copyright{} 2008 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk}
24 @item Copyright @copyright{} 2008-2010 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
26 @item Copyright @copyright{} 2009-2010 David Brownell
27 @end itemize
29 @quotation
30 Permission is granted to copy, distribute and/or modify this document
31 under the terms of the GNU Free Documentation License, Version 1.2 or
32 any later version published by the Free Software Foundation; with no
33 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
34 Texts. A copy of the license is included in the section entitled ``GNU
35 Free Documentation License''.
36 @end quotation
37 @end copying
39 @titlepage
40 @titlefont{@emph{Open On-Chip Debugger:}}
41 @sp 1
42 @title OpenOCD User's Guide
43 @subtitle for release @value{VERSION}
44 @subtitle @value{UPDATED}
46 @page
47 @vskip 0pt plus 1filll
48 @insertcopying
49 @end titlepage
51 @summarycontents
52 @contents
54 @ifnottex
55 @node Top
56 @top OpenOCD User's Guide
58 @insertcopying
59 @end ifnottex
61 @menu
62 * About:: About OpenOCD
63 * Developers:: OpenOCD Developer Resources
64 * Debug Adapter Hardware:: Debug Adapter Hardware
65 * About Jim-Tcl:: About Jim-Tcl
66 * Running:: Running OpenOCD
67 * OpenOCD Project Setup:: OpenOCD Project Setup
68 * Config File Guidelines:: Config File Guidelines
69 * Server Configuration:: Server Configuration
70 * Debug Adapter Configuration:: Debug Adapter Configuration
71 * Reset Configuration:: Reset Configuration
72 * TAP Declaration:: TAP Declaration
73 * CPU Configuration:: CPU Configuration
74 * Flash Commands:: Flash Commands
75 * Flash Programming:: Flash Programming
76 * PLD/FPGA Commands:: PLD/FPGA Commands
77 * General Commands:: General Commands
78 * Architecture and Core Commands:: Architecture and Core Commands
79 * JTAG Commands:: JTAG Commands
80 * Boundary Scan Commands:: Boundary Scan Commands
81 * Utility Commands:: Utility Commands
82 * TFTP:: TFTP
83 * GDB and OpenOCD:: Using GDB and OpenOCD
84 * Tcl Scripting API:: Tcl Scripting API
85 * FAQ:: Frequently Asked Questions
86 * Tcl Crash Course:: Tcl Crash Course
87 * License:: GNU Free Documentation License
89 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
90 @comment case issue with ``Index.html'' and ``index.html''
91 @comment Occurs when creating ``--html --no-split'' output
92 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
93 * OpenOCD Concept Index:: Concept Index
94 * Command and Driver Index:: Command and Driver Index
95 @end menu
97 @node About
98 @unnumbered About
99 @cindex about
101 OpenOCD was created by Dominic Rath as part of a 2005 diploma thesis written
102 at the University of Applied Sciences Augsburg (@uref{http://www.hs-augsburg.de}).
103 Since that time, the project has grown into an active open-source project,
104 supported by a diverse community of software and hardware developers from
105 around the world.
107 @section What is OpenOCD?
108 @cindex TAP
109 @cindex JTAG
111 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
112 in-system programming and boundary-scan testing for embedded target
113 devices.
115 It does so with the assistance of a @dfn{debug adapter}, which is
116 a small hardware module which helps provide the right kind of
117 electrical signaling to the target being debugged. These are
118 required since the debug host (on which OpenOCD runs) won't
119 usually have native support for such signaling, or the connector
120 needed to hook up to the target.
122 Such debug adapters support one or more @dfn{transport} protocols,
123 each of which involves different electrical signaling (and uses
124 different messaging protocols on top of that signaling). There
125 are many types of debug adapter, and little uniformity in what
126 they are called. (There are also product naming differences.)
128 These adapters are sometimes packaged as discrete dongles, which
129 may generically be called @dfn{hardware interface dongles}.
130 Some development boards also integrate them directly, which may
131 let the development board connect directly to the debug
132 host over USB (and sometimes also to power it over USB).
134 For example, a @dfn{JTAG Adapter} supports JTAG
135 signaling, and is used to communicate
136 with JTAG (IEEE 1149.1) compliant TAPs on your target board.
137 A @dfn{TAP} is a ``Test Access Port'', a module which processes
138 special instructions and data. TAPs are daisy-chained within and
139 between chips and boards. JTAG supports debugging and boundary
140 scan operations.
142 There are also @dfn{SWD Adapters} that support Serial Wire Debug (SWD)
143 signaling to communicate with some newer ARM cores, as well as debug
144 adapters which support both JTAG and SWD transports. SWD supports only
145 debugging, whereas JTAG also supports boundary scan operations.
147 For some chips, there are also @dfn{Programming Adapters} supporting
148 special transports used only to write code to flash memory, without
149 support for on-chip debugging or boundary scan.
150 (At this writing, OpenOCD does not support such non-debug adapters.)
153 @b{Dongles:} OpenOCD currently supports many types of hardware dongles:
154 USB-based, parallel port-based, and other standalone boxes that run
155 OpenOCD internally. @xref{Debug Adapter Hardware}.
157 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
158 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x), Cortex-M3
159 (Stellaris LM3, ST STM32 and Energy Micro EFM32) and Intel Quark (x10xx)
160 based cores to be debugged via the GDB protocol.
162 @b{Flash Programming:} Flash writing is supported for external
163 CFI-compatible NOR flashes (Intel and AMD/Spansion command set) and several
164 internal flashes (LPC1700, LPC1800, LPC2000, LPC4300, AT91SAM7, AT91SAM3U,
165 STR7x, STR9x, LM3, STM32x and EFM32). Preliminary support for various NAND flash
166 controllers (LPC3180, Orion, S3C24xx, more) is included.
168 @section OpenOCD Web Site
170 The OpenOCD web site provides the latest public news from the community:
172 @uref{http://openocd.org/}
174 @section Latest User's Guide:
176 The user's guide you are now reading may not be the latest one
177 available. A version for more recent code may be available.
178 Its HTML form is published regularly at:
180 @uref{http://openocd.org/doc/html/index.html}
182 PDF form is likewise published at:
184 @uref{http://openocd.org/doc/pdf/openocd.pdf}
186 @section OpenOCD User's Forum
188 There is an OpenOCD forum (phpBB) hosted by SparkFun,
189 which might be helpful to you. Note that if you want
190 anything to come to the attention of developers, you
191 should post it to the OpenOCD Developer Mailing List
192 instead of this forum.
194 @uref{http://forum.sparkfun.com/viewforum.php?f=18}
196 @section OpenOCD User's Mailing List
198 The OpenOCD User Mailing List provides the primary means of
199 communication between users:
201 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-user}
203 @section OpenOCD IRC
205 Support can also be found on irc:
206 @uref{irc://irc.freenode.net/openocd}
208 @node Developers
209 @chapter OpenOCD Developer Resources
210 @cindex developers
212 If you are interested in improving the state of OpenOCD's debugging and
213 testing support, new contributions will be welcome. Motivated developers
214 can produce new target, flash or interface drivers, improve the
215 documentation, as well as more conventional bug fixes and enhancements.
217 The resources in this chapter are available for developers wishing to explore
218 or expand the OpenOCD source code.
220 @section OpenOCD Git Repository
222 During the 0.3.x release cycle, OpenOCD switched from Subversion to
223 a Git repository hosted at SourceForge. The repository URL is:
225 @uref{git://git.code.sf.net/p/openocd/code}
227 or via http
229 @uref{http://git.code.sf.net/p/openocd/code}
231 You may prefer to use a mirror and the HTTP protocol:
233 @uref{http://repo.or.cz/r/openocd.git}
235 With standard Git tools, use @command{git clone} to initialize
236 a local repository, and @command{git pull} to update it.
237 There are also gitweb pages letting you browse the repository
238 with a web browser, or download arbitrary snapshots without
239 needing a Git client:
241 @uref{http://repo.or.cz/w/openocd.git}
243 The @file{README} file contains the instructions for building the project
244 from the repository or a snapshot.
246 Developers that want to contribute patches to the OpenOCD system are
247 @b{strongly} encouraged to work against mainline.
248 Patches created against older versions may require additional
249 work from their submitter in order to be updated for newer releases.
251 @section Doxygen Developer Manual
253 During the 0.2.x release cycle, the OpenOCD project began
254 providing a Doxygen reference manual. This document contains more
255 technical information about the software internals, development
256 processes, and similar documentation:
258 @uref{http://openocd.org/doc/doxygen/html/index.html}
260 This document is a work-in-progress, but contributions would be welcome
261 to fill in the gaps. All of the source files are provided in-tree,
262 listed in the Doxyfile configuration at the top of the source tree.
264 @section Gerrit Review System
266 All changes in the OpenOCD Git repository go through the web-based Gerrit
267 Code Review System:
269 @uref{http://openocd.zylin.com/}
271 After a one-time registration and repository setup, anyone can push commits
272 from their local Git repository directly into Gerrit.
273 All users and developers are encouraged to review, test, discuss and vote
274 for changes in Gerrit. The feedback provides the basis for a maintainer to
275 eventually submit the change to the main Git repository.
277 The @file{HACKING} file, also available as the Patch Guide in the Doxygen
278 Developer Manual, contains basic information about how to connect a
279 repository to Gerrit, prepare and push patches. Patch authors are expected to
280 maintain their changes while they're in Gerrit, respond to feedback and if
281 necessary rework and push improved versions of the change.
283 @section OpenOCD Developer Mailing List
285 The OpenOCD Developer Mailing List provides the primary means of
286 communication between developers:
288 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-devel}
290 @section OpenOCD Bug Tracker
292 The OpenOCD Bug Tracker is hosted on SourceForge:
294 @uref{http://bugs.openocd.org/}
297 @node Debug Adapter Hardware
298 @chapter Debug Adapter Hardware
299 @cindex dongles
300 @cindex FTDI
301 @cindex wiggler
302 @cindex zy1000
303 @cindex printer port
304 @cindex USB Adapter
305 @cindex RTCK
307 Defined: @b{dongle}: A small device that plugs into a computer and serves as
308 an adapter .... [snip]
310 In the OpenOCD case, this generally refers to @b{a small adapter} that
311 attaches to your computer via USB or the parallel port. One
312 exception is the Ultimate Solutions ZY1000, packaged as a small box you
313 attach via an ethernet cable. The ZY1000 has the advantage that it does not
314 require any drivers to be installed on the developer PC. It also has
315 a built in web interface. It supports RTCK/RCLK or adaptive clocking
316 and has a built-in relay to power cycle targets remotely.
319 @section Choosing a Dongle
321 There are several things you should keep in mind when choosing a dongle.
323 @enumerate
324 @item @b{Transport} Does it support the kind of communication that you need?
325 OpenOCD focusses mostly on JTAG. Your version may also support
326 other ways to communicate with target devices.
327 @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
328 Does your dongle support it? You might need a level converter.
329 @item @b{Pinout} What pinout does your target board use?
330 Does your dongle support it? You may be able to use jumper
331 wires, or an "octopus" connector, to convert pinouts.
332 @item @b{Connection} Does your computer have the USB, parallel, or
333 Ethernet port needed?
334 @item @b{RTCK} Do you expect to use it with ARM chips and boards with
335 RTCK support (also known as ``adaptive clocking'')?
336 @end enumerate
338 @section Stand-alone JTAG Probe
340 The ZY1000 from Ultimate Solutions is technically not a dongle but a
341 stand-alone JTAG probe that, unlike most dongles, doesn't require any drivers
342 running on the developer's host computer.
343 Once installed on a network using DHCP or a static IP assignment, users can
344 access the ZY1000 probe locally or remotely from any host with access to the
345 IP address assigned to the probe.
346 The ZY1000 provides an intuitive web interface with direct access to the
347 OpenOCD debugger.
348 Users may also run a GDBSERVER directly on the ZY1000 to take full advantage
349 of GCC & GDB to debug any distribution of embedded Linux or NetBSD running on
350 the target.
351 The ZY1000 supports RTCK & RCLK or adaptive clocking and has a built-in relay
352 to power cycle the target remotely.
354 For more information, visit:
356 @b{ZY1000} See: @url{http://www.ultsol.com/index.php/component/content/article/8/210-zylin-zy1000-main}
358 @section USB FT2232 Based
360 There are many USB JTAG dongles on the market, many of them based
361 on a chip from ``Future Technology Devices International'' (FTDI)
362 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
363 See: @url{http://www.ftdichip.com} for more information.
364 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
365 chips started to become available in JTAG adapters. Around 2012, a new
366 variant appeared - FT232H - this is a single-channel version of FT2232H.
367 (Adapters using those high speed FT2232H or FT232H chips may support adaptive
368 clocking.)
370 The FT2232 chips are flexible enough to support some other
371 transport options, such as SWD or the SPI variants used to
372 program some chips. They have two communications channels,
373 and one can be used for a UART adapter at the same time the
374 other one is used to provide a debug adapter.
376 Also, some development boards integrate an FT2232 chip to serve as
377 a built-in low-cost debug adapter and USB-to-serial solution.
379 @itemize @bullet
380 @item @b{usbjtag}
381 @* Link @url{http://elk.informatik.fh-augsburg.de/hhweb/doc/openocd/usbjtag/usbjtag.html}
382 @item @b{jtagkey}
383 @* See: @url{http://www.amontec.com/jtagkey.shtml}
384 @item @b{jtagkey2}
385 @* See: @url{http://www.amontec.com/jtagkey2.shtml}
386 @item @b{oocdlink}
387 @* See: @url{http://www.oocdlink.com} By Joern Kaipf
388 @item @b{signalyzer}
389 @* See: @url{http://www.signalyzer.com}
390 @item @b{Stellaris Eval Boards}
391 @* See: @url{http://www.ti.com} - The Stellaris eval boards
392 bundle FT2232-based JTAG and SWD support, which can be used to debug
393 the Stellaris chips. Using separate JTAG adapters is optional.
394 These boards can also be used in a "pass through" mode as JTAG adapters
395 to other target boards, disabling the Stellaris chip.
396 @item @b{TI/Luminary ICDI}
397 @* See: @url{http://www.ti.com} - TI/Luminary In-Circuit Debug
398 Interface (ICDI) Boards are included in Stellaris LM3S9B9x
399 Evaluation Kits. Like the non-detachable FT2232 support on the other
400 Stellaris eval boards, they can be used to debug other target boards.
401 @item @b{olimex-jtag}
402 @* See: @url{http://www.olimex.com}
403 @item @b{Flyswatter/Flyswatter2}
404 @* See: @url{http://www.tincantools.com}
405 @item @b{turtelizer2}
406 @* See:
407 @uref{http://www.ethernut.de/en/hardware/turtelizer/index.html, Turtelizer 2}, or
408 @url{http://www.ethernut.de}
409 @item @b{comstick}
410 @* Link: @url{http://www.hitex.com/index.php?id=383}
411 @item @b{stm32stick}
412 @* Link @url{http://www.hitex.com/stm32-stick}
413 @item @b{axm0432_jtag}
414 @* Axiom AXM-0432 Link @url{http://www.axman.com} - NOTE: This JTAG does not appear
415 to be available anymore as of April 2012.
416 @item @b{cortino}
417 @* Link @url{http://www.hitex.com/index.php?id=cortino}
418 @item @b{dlp-usb1232h}
419 @* Link @url{http://www.dlpdesign.com/usb/usb1232h.shtml}
420 @item @b{digilent-hs1}
421 @* Link @url{http://www.digilentinc.com/Products/Detail.cfm?Prod=JTAG-HS1}
422 @item @b{opendous}
423 @* Link @url{http://code.google.com/p/opendous/wiki/JTAG} FT2232H-based
424 (OpenHardware).
425 @item @b{JTAG-lock-pick Tiny 2}
426 @* Link @url{http://www.distortec.com/jtag-lock-pick-tiny-2} FT232H-based
428 @item @b{GW16042}
429 @* Link: @url{http://shop.gateworks.com/index.php?route=product/product&path=70_80&product_id=64}
430 FT2232H-based
432 @end itemize
433 @section USB-JTAG / Altera USB-Blaster compatibles
435 These devices also show up as FTDI devices, but are not
436 protocol-compatible with the FT2232 devices. They are, however,
437 protocol-compatible among themselves. USB-JTAG devices typically consist
438 of a FT245 followed by a CPLD that understands a particular protocol,
439 or emulates this protocol using some other hardware.
441 They may appear under different USB VID/PID depending on the particular
442 product. The driver can be configured to search for any VID/PID pair
443 (see the section on driver commands).
445 @itemize
446 @item @b{USB-JTAG} Kolja Waschk's USB Blaster-compatible adapter
447 @* Link: @url{http://ixo-jtag.sourceforge.net/}
448 @item @b{Altera USB-Blaster}
449 @* Link: @url{http://www.altera.com/literature/ug/ug_usb_blstr.pdf}
450 @end itemize
452 @section USB J-Link based
453 There are several OEM versions of the SEGGER @b{J-Link} adapter. It is
454 an example of a microcontroller based JTAG adapter, it uses an
455 AT91SAM764 internally.
457 @itemize @bullet
458 @item @b{SEGGER J-Link}
459 @* Link: @url{http://www.segger.com/jlink.html}
460 @item @b{Atmel SAM-ICE} (Only works with Atmel chips!)
461 @* Link: @url{http://www.atmel.com/tools/atmelsam-ice.aspx}
462 @item @b{IAR J-Link}
463 @end itemize
465 @section USB RLINK based
466 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer,
467 permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for
468 SWD and not JTAG, thus not supported.
470 @itemize @bullet
471 @item @b{Raisonance RLink}
472 @* Link: @url{http://www.mcu-raisonance.com/~rlink-debugger-programmer__@/microcontrollers__tool~tool__T018:4cn9ziz4bnx6.html}
473 @item @b{STM32 Primer}
474 @* Link: @url{http://www.stm32circle.com/resources/stm32primer.php}
475 @item @b{STM32 Primer2}
476 @* Link: @url{http://www.stm32circle.com/resources/stm32primer2.php}
477 @end itemize
479 @section USB ST-LINK based
480 ST Micro has an adapter called @b{ST-LINK}.
481 They only work with ST Micro chips, notably STM32 and STM8.
483 @itemize @bullet
484 @item @b{ST-LINK}
485 @* This is available standalone and as part of some kits, eg. STM32VLDISCOVERY.
486 @* Link: @url{http://www.st.com/internet/evalboard/product/219866.jsp}
487 @item @b{ST-LINK/V2}
488 @* This is available standalone and as part of some kits, eg. STM32F4DISCOVERY.
489 @* Link: @url{http://www.st.com/internet/evalboard/product/251168.jsp}
490 @end itemize
492 For info the original ST-LINK enumerates using the mass storage usb class; however,
493 its implementation is completely broken. The result is this causes issues under Linux.
494 The simplest solution is to get Linux to ignore the ST-LINK using one of the following methods:
495 @itemize @bullet
496 @item modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i
497 @item add "options usb-storage quirks=483:3744:i" to /etc/modprobe.conf
498 @end itemize
500 @section USB TI/Stellaris ICDI based
501 Texas Instruments has an adapter called @b{ICDI}.
502 It is not to be confused with the FTDI based adapters that were originally fitted to their
503 evaluation boards. This is the adapter fitted to the Stellaris LaunchPad.
505 @section USB CMSIS-DAP based
506 ARM has released a interface standard called CMSIS-DAP that simplifies connecting
507 debuggers to ARM Cortex based targets @url{http://www.keil.com/support/man/docs/dapdebug/dapdebug_introduction.htm}.
509 @section USB Other
510 @itemize @bullet
511 @item @b{USBprog}
512 @* Link: @url{http://shop.embedded-projects.net/} - which uses an Atmel MEGA32 and a UBN9604
514 @item @b{USB - Presto}
515 @* Link: @url{http://tools.asix.net/prg_presto.htm}
517 @item @b{Versaloon-Link}
518 @* Link: @url{http://www.versaloon.com}
520 @item @b{ARM-JTAG-EW}
521 @* Link: @url{http://www.olimex.com/dev/arm-jtag-ew.html}
523 @item @b{Buspirate}
524 @* Link: @url{http://dangerousprototypes.com/bus-pirate-manual/}
526 @item @b{opendous}
527 @* Link: @url{http://code.google.com/p/opendous-jtag/} - which uses an AT90USB162
529 @item @b{estick}
530 @* Link: @url{http://code.google.com/p/estick-jtag/}
532 @item @b{Keil ULINK v1}
533 @* Link: @url{http://www.keil.com/ulink1/}
535 @item @b{TI XDS110 Debug Probe}
536 @* The XDS110 is included as the embedded debug probe on many Texas Instruments
537 LaunchPad evaluation boards.
538 @* Link: @url{http://processors.wiki.ti.com/index.php/XDS110}
539 @* Link: @url{http://processors.wiki.ti.com/index.php/XDS_Emulation_Software_Package#XDS110_Support_Utilities}
540 @end itemize
542 @section IBM PC Parallel Printer Port Based
544 The two well-known ``JTAG Parallel Ports'' cables are the Xilinx DLC5
545 and the Macraigor Wiggler. There are many clones and variations of
546 these on the market.
548 Note that parallel ports are becoming much less common, so if you
549 have the choice you should probably avoid these adapters in favor
550 of USB-based ones.
552 @itemize @bullet
554 @item @b{Wiggler} - There are many clones of this.
555 @* Link: @url{http://www.macraigor.com/wiggler.htm}
557 @item @b{DLC5} - From XILINX - There are many clones of this
558 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
559 produced, PDF schematics are easily found and it is easy to make.
561 @item @b{Amontec - JTAG Accelerator}
562 @* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
564 @item @b{Wiggler2}
565 @* Link: @url{http://www.ccac.rwth-aachen.de/~michaels/index.php/hardware/armjtag}
567 @item @b{Wiggler_ntrst_inverted}
568 @* Yet another variation - See the source code, src/jtag/parport.c
570 @item @b{old_amt_wiggler}
571 @* Unknown - probably not on the market today
573 @item @b{arm-jtag}
574 @* Link: Most likely @url{http://www.olimex.com/dev/arm-jtag.html} [another wiggler clone]
576 @item @b{chameleon}
577 @* Link: @url{http://www.amontec.com/chameleon.shtml}
579 @item @b{Triton}
580 @* Unknown.
582 @item @b{Lattice}
583 @* ispDownload from Lattice Semiconductor
584 @url{http://www.latticesemi.com/lit/docs/@/devtools/dlcable.pdf}
586 @item @b{flashlink}
587 @* From STMicroelectronics;
588 @* Link: @url{http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/DATA_BRIEF/DM00039500.pdf}
590 @end itemize
592 @section Other...
593 @itemize @bullet
595 @item @b{ep93xx}
596 @* An EP93xx based Linux machine using the GPIO pins directly.
598 @item @b{at91rm9200}
599 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
601 @item @b{bcm2835gpio}
602 @* A BCM2835-based board (e.g. Raspberry Pi) using the GPIO pins of the expansion header.
604 @item @b{imx_gpio}
605 @* A NXP i.MX-based board (e.g. Wandboard) using the GPIO pins (should work on any i.MX processor).
607 @item @b{jtag_vpi}
608 @* A JTAG driver acting as a client for the JTAG VPI server interface.
609 @* Link: @url{http://github.com/fjullien/jtag_vpi}
611 @end itemize
613 @node About Jim-Tcl
614 @chapter About Jim-Tcl
615 @cindex Jim-Tcl
616 @cindex tcl
618 OpenOCD uses a small ``Tcl Interpreter'' known as Jim-Tcl.
619 This programming language provides a simple and extensible
620 command interpreter.
622 All commands presented in this Guide are extensions to Jim-Tcl.
623 You can use them as simple commands, without needing to learn
624 much of anything about Tcl.
625 Alternatively, you can write Tcl programs with them.
627 You can learn more about Jim at its website, @url{http://jim.tcl.tk}.
628 There is an active and responsive community, get on the mailing list
629 if you have any questions. Jim-Tcl maintainers also lurk on the
630 OpenOCD mailing list.
632 @itemize @bullet
633 @item @b{Jim vs. Tcl}
634 @* Jim-Tcl is a stripped down version of the well known Tcl language,
635 which can be found here: @url{http://www.tcl.tk}. Jim-Tcl has far
636 fewer features. Jim-Tcl is several dozens of .C files and .H files and
637 implements the basic Tcl command set. In contrast: Tcl 8.6 is a
638 4.2 MB .zip file containing 1540 files.
640 @item @b{Missing Features}
641 @* Our practice has been: Add/clone the real Tcl feature if/when
642 needed. We welcome Jim-Tcl improvements, not bloat. Also there
643 are a large number of optional Jim-Tcl features that are not
644 enabled in OpenOCD.
646 @item @b{Scripts}
647 @* OpenOCD configuration scripts are Jim-Tcl Scripts. OpenOCD's
648 command interpreter today is a mixture of (newer)
649 Jim-Tcl commands, and the (older) original command interpreter.
651 @item @b{Commands}
652 @* At the OpenOCD telnet command line (or via the GDB monitor command) one
653 can type a Tcl for() loop, set variables, etc.
654 Some of the commands documented in this guide are implemented
655 as Tcl scripts, from a @file{startup.tcl} file internal to the server.
657 @item @b{Historical Note}
658 @* Jim-Tcl was introduced to OpenOCD in spring 2008. Fall 2010,
659 before OpenOCD 0.5 release, OpenOCD switched to using Jim-Tcl
660 as a Git submodule, which greatly simplified upgrading Jim-Tcl
661 to benefit from new features and bugfixes in Jim-Tcl.
663 @item @b{Need a crash course in Tcl?}
664 @*@xref{Tcl Crash Course}.
665 @end itemize
667 @node Running
668 @chapter Running
669 @cindex command line options
670 @cindex logfile
671 @cindex directory search
673 Properly installing OpenOCD sets up your operating system to grant it access
674 to the debug adapters. On Linux, this usually involves installing a file
675 in @file{/etc/udev/rules.d,} so OpenOCD has permissions. An example rules file
676 that works for many common adapters is shipped with OpenOCD in the
677 @file{contrib} directory. MS-Windows needs
678 complex and confusing driver configuration for every peripheral. Such issues
679 are unique to each operating system, and are not detailed in this User's Guide.
681 Then later you will invoke the OpenOCD server, with various options to
682 tell it how each debug session should work.
683 The @option{--help} option shows:
684 @verbatim
685 bash$ openocd --help
687 --help | -h display this help
688 --version | -v display OpenOCD version
689 --file | -f use configuration file <name>
690 --search | -s dir to search for config files and scripts
691 --debug | -d set debug level to 3
692 | -d<n> set debug level to <level>
693 --log_output | -l redirect log output to file <name>
694 --command | -c run <command>
695 @end verbatim
697 If you don't give any @option{-f} or @option{-c} options,
698 OpenOCD tries to read the configuration file @file{openocd.cfg}.
699 To specify one or more different
700 configuration files, use @option{-f} options. For example:
702 @example
703 openocd -f config1.cfg -f config2.cfg -f config3.cfg
704 @end example
706 Configuration files and scripts are searched for in
707 @enumerate
708 @item the current directory,
709 @item any search dir specified on the command line using the @option{-s} option,
710 @item any search dir specified using the @command{add_script_search_dir} command,
711 @item @file{$HOME/.openocd} (not on Windows),
712 @item a directory in the @env{OPENOCD_SCRIPTS} environment variable (if set),
713 @item the site wide script library @file{$pkgdatadir/site} and
714 @item the OpenOCD-supplied script library @file{$pkgdatadir/scripts}.
715 @end enumerate
716 The first found file with a matching file name will be used.
718 @quotation Note
719 Don't try to use configuration script names or paths which
720 include the "#" character. That character begins Tcl comments.
721 @end quotation
723 @section Simple setup, no customization
725 In the best case, you can use two scripts from one of the script
726 libraries, hook up your JTAG adapter, and start the server ... and
727 your JTAG setup will just work "out of the box". Always try to
728 start by reusing those scripts, but assume you'll need more
729 customization even if this works. @xref{OpenOCD Project Setup}.
731 If you find a script for your JTAG adapter, and for your board or
732 target, you may be able to hook up your JTAG adapter then start
733 the server with some variation of one of the following:
735 @example
736 openocd -f interface/ADAPTER.cfg -f board/MYBOARD.cfg
737 openocd -f interface/ftdi/ADAPTER.cfg -f board/MYBOARD.cfg
738 @end example
740 You might also need to configure which reset signals are present,
741 using @option{-c 'reset_config trst_and_srst'} or something similar.
742 If all goes well you'll see output something like
744 @example
745 Open On-Chip Debugger 0.4.0 (2010-01-14-15:06)
746 For bug reports, read
747 http://openocd.org/doc/doxygen/bugs.html
748 Info : JTAG tap: lm3s.cpu tap/device found: 0x3ba00477
749 (mfg: 0x23b, part: 0xba00, ver: 0x3)
750 @end example
752 Seeing that "tap/device found" message, and no warnings, means
753 the JTAG communication is working. That's a key milestone, but
754 you'll probably need more project-specific setup.
756 @section What OpenOCD does as it starts
758 OpenOCD starts by processing the configuration commands provided
759 on the command line or, if there were no @option{-c command} or
760 @option{-f file.cfg} options given, in @file{openocd.cfg}.
761 @xref{configurationstage,,Configuration Stage}.
762 At the end of the configuration stage it verifies the JTAG scan
763 chain defined using those commands; your configuration should
764 ensure that this always succeeds.
765 Normally, OpenOCD then starts running as a server.
766 Alternatively, commands may be used to terminate the configuration
767 stage early, perform work (such as updating some flash memory),
768 and then shut down without acting as a server.
770 Once OpenOCD starts running as a server, it waits for connections from
771 clients (Telnet, GDB, RPC) and processes the commands issued through
772 those channels.
774 If you are having problems, you can enable internal debug messages via
775 the @option{-d} option.
777 Also it is possible to interleave Jim-Tcl commands w/config scripts using the
778 @option{-c} command line switch.
780 To enable debug output (when reporting problems or working on OpenOCD
781 itself), use the @option{-d} command line switch. This sets the
782 @option{debug_level} to "3", outputting the most information,
783 including debug messages. The default setting is "2", outputting only
784 informational messages, warnings and errors. You can also change this
785 setting from within a telnet or gdb session using @command{debug_level<n>}
786 (@pxref{debuglevel,,debug_level}).
788 You can redirect all output from the server to a file using the
789 @option{-l <logfile>} switch.
791 Note! OpenOCD will launch the GDB & telnet server even if it can not
792 establish a connection with the target. In general, it is possible for
793 the JTAG controller to be unresponsive until the target is set up
794 correctly via e.g. GDB monitor commands in a GDB init script.
796 @node OpenOCD Project Setup
797 @chapter OpenOCD Project Setup
799 To use OpenOCD with your development projects, you need to do more than
800 just connect the JTAG adapter hardware (dongle) to your development board
801 and start the OpenOCD server.
802 You also need to configure your OpenOCD server so that it knows
803 about your adapter and board, and helps your work.
804 You may also want to connect OpenOCD to GDB, possibly
805 using Eclipse or some other GUI.
807 @section Hooking up the JTAG Adapter
809 Today's most common case is a dongle with a JTAG cable on one side
810 (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
811 and a USB cable on the other.
812 Instead of USB, some cables use Ethernet;
813 older ones may use a PC parallel port, or even a serial port.
815 @enumerate
816 @item @emph{Start with power to your target board turned off},
817 and nothing connected to your JTAG adapter.
818 If you're particularly paranoid, unplug power to the board.
819 It's important to have the ground signal properly set up,
820 unless you are using a JTAG adapter which provides
821 galvanic isolation between the target board and the
822 debugging host.
824 @item @emph{Be sure it's the right kind of JTAG connector.}
825 If your dongle has a 20-pin ARM connector, you need some kind
826 of adapter (or octopus, see below) to hook it up to
827 boards using 14-pin or 10-pin connectors ... or to 20-pin
828 connectors which don't use ARM's pinout.
830 In the same vein, make sure the voltage levels are compatible.
831 Not all JTAG adapters have the level shifters needed to work
832 with 1.2 Volt boards.
834 @item @emph{Be certain the cable is properly oriented} or you might
835 damage your board. In most cases there are only two possible
836 ways to connect the cable.
837 Connect the JTAG cable from your adapter to the board.
838 Be sure it's firmly connected.
840 In the best case, the connector is keyed to physically
841 prevent you from inserting it wrong.
842 This is most often done using a slot on the board's male connector
843 housing, which must match a key on the JTAG cable's female connector.
844 If there's no housing, then you must look carefully and
845 make sure pin 1 on the cable hooks up to pin 1 on the board.
846 Ribbon cables are frequently all grey except for a wire on one
847 edge, which is red. The red wire is pin 1.
849 Sometimes dongles provide cables where one end is an ``octopus'' of
850 color coded single-wire connectors, instead of a connector block.
851 These are great when converting from one JTAG pinout to another,
852 but are tedious to set up.
853 Use these with connector pinout diagrams to help you match up the
854 adapter signals to the right board pins.
856 @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
857 A USB, parallel, or serial port connector will go to the host which
858 you are using to run OpenOCD.
859 For Ethernet, consult the documentation and your network administrator.
861 For USB-based JTAG adapters you have an easy sanity check at this point:
862 does the host operating system see the JTAG adapter? If you're running
863 Linux, try the @command{lsusb} command. If that host is an
864 MS-Windows host, you'll need to install a driver before OpenOCD works.
866 @item @emph{Connect the adapter's power supply, if needed.}
867 This step is primarily for non-USB adapters,
868 but sometimes USB adapters need extra power.
870 @item @emph{Power up the target board.}
871 Unless you just let the magic smoke escape,
872 you're now ready to set up the OpenOCD server
873 so you can use JTAG to work with that board.
875 @end enumerate
877 Talk with the OpenOCD server using
878 telnet (@code{telnet localhost 4444} on many systems) or GDB.
879 @xref{GDB and OpenOCD}.
881 @section Project Directory
883 There are many ways you can configure OpenOCD and start it up.
885 A simple way to organize them all involves keeping a
886 single directory for your work with a given board.
887 When you start OpenOCD from that directory,
888 it searches there first for configuration files, scripts,
889 files accessed through semihosting,
890 and for code you upload to the target board.
891 It is also the natural place to write files,
892 such as log files and data you download from the board.
894 @section Configuration Basics
896 There are two basic ways of configuring OpenOCD, and
897 a variety of ways you can mix them.
898 Think of the difference as just being how you start the server:
900 @itemize
901 @item Many @option{-f file} or @option{-c command} options on the command line
902 @item No options, but a @dfn{user config file}
903 in the current directory named @file{openocd.cfg}
904 @end itemize
906 Here is an example @file{openocd.cfg} file for a setup
907 using a Signalyzer FT2232-based JTAG adapter to talk to
908 a board with an Atmel AT91SAM7X256 microcontroller:
910 @example
911 source [find interface/ftdi/signalyzer.cfg]
913 # GDB can also flash my flash!
914 gdb_memory_map enable
915 gdb_flash_program enable
917 source [find target/sam7x256.cfg]
918 @end example
920 Here is the command line equivalent of that configuration:
922 @example
923 openocd -f interface/ftdi/signalyzer.cfg \
924 -c "gdb_memory_map enable" \
925 -c "gdb_flash_program enable" \
926 -f target/sam7x256.cfg
927 @end example
929 You could wrap such long command lines in shell scripts,
930 each supporting a different development task.
931 One might re-flash the board with a specific firmware version.
932 Another might set up a particular debugging or run-time environment.
934 @quotation Important
935 At this writing (October 2009) the command line method has
936 problems with how it treats variables.
937 For example, after @option{-c "set VAR value"}, or doing the
938 same in a script, the variable @var{VAR} will have no value
939 that can be tested in a later script.
940 @end quotation
942 Here we will focus on the simpler solution: one user config
943 file, including basic configuration plus any TCL procedures
944 to simplify your work.
946 @section User Config Files
947 @cindex config file, user
948 @cindex user config file
949 @cindex config file, overview
951 A user configuration file ties together all the parts of a project
952 in one place.
953 One of the following will match your situation best:
955 @itemize
956 @item Ideally almost everything comes from configuration files
957 provided by someone else.
958 For example, OpenOCD distributes a @file{scripts} directory
959 (probably in @file{/usr/share/openocd/scripts} on Linux).
960 Board and tool vendors can provide these too, as can individual
961 user sites; the @option{-s} command line option lets you say
962 where to find these files. (@xref{Running}.)
963 The AT91SAM7X256 example above works this way.
965 Three main types of non-user configuration file each have their
966 own subdirectory in the @file{scripts} directory:
968 @enumerate
969 @item @b{interface} -- one for each different debug adapter;
970 @item @b{board} -- one for each different board
971 @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
972 @end enumerate
974 Best case: include just two files, and they handle everything else.
975 The first is an interface config file.
976 The second is board-specific, and it sets up the JTAG TAPs and
977 their GDB targets (by deferring to some @file{target.cfg} file),
978 declares all flash memory, and leaves you nothing to do except
979 meet your deadline:
981 @example
982 source [find interface/olimex-jtag-tiny.cfg]
983 source [find board/csb337.cfg]
984 @end example
986 Boards with a single microcontroller often won't need more
987 than the target config file, as in the AT91SAM7X256 example.
988 That's because there is no external memory (flash, DDR RAM), and
989 the board differences are encapsulated by application code.
991 @item Maybe you don't know yet what your board looks like to JTAG.
992 Once you know the @file{interface.cfg} file to use, you may
993 need help from OpenOCD to discover what's on the board.
994 Once you find the JTAG TAPs, you can just search for appropriate
995 target and board
996 configuration files ... or write your own, from the bottom up.
997 @xref{autoprobing,,Autoprobing}.
999 @item You can often reuse some standard config files but
1000 need to write a few new ones, probably a @file{board.cfg} file.
1001 You will be using commands described later in this User's Guide,
1002 and working with the guidelines in the next chapter.
1004 For example, there may be configuration files for your JTAG adapter
1005 and target chip, but you need a new board-specific config file
1006 giving access to your particular flash chips.
1007 Or you might need to write another target chip configuration file
1008 for a new chip built around the Cortex-M3 core.
1010 @quotation Note
1011 When you write new configuration files, please submit
1012 them for inclusion in the next OpenOCD release.
1013 For example, a @file{board/newboard.cfg} file will help the
1014 next users of that board, and a @file{target/newcpu.cfg}
1015 will help support users of any board using that chip.
1016 @end quotation
1018 @item
1019 You may may need to write some C code.
1020 It may be as simple as supporting a new FT2232 or parport
1021 based adapter; a bit more involved, like a NAND or NOR flash
1022 controller driver; or a big piece of work like supporting
1023 a new chip architecture.
1024 @end itemize
1026 Reuse the existing config files when you can.
1027 Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
1028 You may find a board configuration that's a good example to follow.
1030 When you write config files, separate the reusable parts
1031 (things every user of that interface, chip, or board needs)
1032 from ones specific to your environment and debugging approach.
1033 @itemize
1035 @item
1036 For example, a @code{gdb-attach} event handler that invokes
1037 the @command{reset init} command will interfere with debugging
1038 early boot code, which performs some of the same actions
1039 that the @code{reset-init} event handler does.
1041 @item
1042 Likewise, the @command{arm9 vector_catch} command (or
1043 @cindex vector_catch
1044 its siblings @command{xscale vector_catch}
1045 and @command{cortex_m vector_catch}) can be a time-saver
1046 during some debug sessions, but don't make everyone use that either.
1047 Keep those kinds of debugging aids in your user config file,
1048 along with messaging and tracing setup.
1049 (@xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.)
1051 @item
1052 You might need to override some defaults.
1053 For example, you might need to move, shrink, or back up the target's
1054 work area if your application needs much SRAM.
1056 @item
1057 TCP/IP port configuration is another example of something which
1058 is environment-specific, and should only appear in
1059 a user config file. @xref{tcpipports,,TCP/IP Ports}.
1060 @end itemize
1062 @section Project-Specific Utilities
1064 A few project-specific utility
1065 routines may well speed up your work.
1066 Write them, and keep them in your project's user config file.
1068 For example, if you are making a boot loader work on a
1069 board, it's nice to be able to debug the ``after it's
1070 loaded to RAM'' parts separately from the finicky early
1071 code which sets up the DDR RAM controller and clocks.
1072 A script like this one, or a more GDB-aware sibling,
1073 may help:
1075 @example
1076 proc ramboot @{ @} @{
1077 # Reset, running the target's "reset-init" scripts
1078 # to initialize clocks and the DDR RAM controller.
1079 # Leave the CPU halted.
1080 reset init
1082 # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
1083 load_image u-boot.bin 0x20000000
1085 # Start running.
1086 resume 0x20000000
1087 @}
1088 @end example
1090 Then once that code is working you will need to make it
1091 boot from NOR flash; a different utility would help.
1092 Alternatively, some developers write to flash using GDB.
1093 (You might use a similar script if you're working with a flash
1094 based microcontroller application instead of a boot loader.)
1096 @example
1097 proc newboot @{ @} @{
1098 # Reset, leaving the CPU halted. The "reset-init" event
1099 # proc gives faster access to the CPU and to NOR flash;
1100 # "reset halt" would be slower.
1101 reset init
1103 # Write standard version of U-Boot into the first two
1104 # sectors of NOR flash ... the standard version should
1105 # do the same lowlevel init as "reset-init".
1106 flash protect 0 0 1 off
1107 flash erase_sector 0 0 1
1108 flash write_bank 0 u-boot.bin 0x0
1109 flash protect 0 0 1 on
1111 # Reboot from scratch using that new boot loader.
1112 reset run
1113 @}
1114 @end example
1116 You may need more complicated utility procedures when booting
1117 from NAND.
1118 That often involves an extra bootloader stage,
1119 running from on-chip SRAM to perform DDR RAM setup so it can load
1120 the main bootloader code (which won't fit into that SRAM).
1122 Other helper scripts might be used to write production system images,
1123 involving considerably more than just a three stage bootloader.
1125 @section Target Software Changes
1127 Sometimes you may want to make some small changes to the software
1128 you're developing, to help make JTAG debugging work better.
1129 For example, in C or assembly language code you might
1130 use @code{#ifdef JTAG_DEBUG} (or its converse) around code
1131 handling issues like:
1133 @itemize @bullet
1135 @item @b{Watchdog Timers}...
1136 Watchdog timers are typically used to automatically reset systems if
1137 some application task doesn't periodically reset the timer. (The
1138 assumption is that the system has locked up if the task can't run.)
1139 When a JTAG debugger halts the system, that task won't be able to run
1140 and reset the timer ... potentially causing resets in the middle of
1141 your debug sessions.
1143 It's rarely a good idea to disable such watchdogs, since their usage
1144 needs to be debugged just like all other parts of your firmware.
1145 That might however be your only option.
1147 Look instead for chip-specific ways to stop the watchdog from counting
1148 while the system is in a debug halt state. It may be simplest to set
1149 that non-counting mode in your debugger startup scripts. You may however
1150 need a different approach when, for example, a motor could be physically
1151 damaged by firmware remaining inactive in a debug halt state. That might
1152 involve a type of firmware mode where that "non-counting" mode is disabled
1153 at the beginning then re-enabled at the end; a watchdog reset might fire
1154 and complicate the debug session, but hardware (or people) would be
1155 protected.@footnote{Note that many systems support a "monitor mode" debug
1156 that is a somewhat cleaner way to address such issues. You can think of
1157 it as only halting part of the system, maybe just one task,
1158 instead of the whole thing.
1159 At this writing, January 2010, OpenOCD based debugging does not support
1160 monitor mode debug, only "halt mode" debug.}
1162 @item @b{ARM Semihosting}...
1163 @cindex ARM semihosting
1164 When linked with a special runtime library provided with many
1165 toolchains@footnote{See chapter 8 "Semihosting" in
1166 @uref{http://infocenter.arm.com/help/topic/com.arm.doc.dui0203i/DUI0203I_rvct_developer_guide.pdf,
1167 ARM DUI 0203I}, the "RealView Compilation Tools Developer Guide".
1168 The CodeSourcery EABI toolchain also includes a semihosting library.},
1169 your target code can use I/O facilities on the debug host. That library
1170 provides a small set of system calls which are handled by OpenOCD.
1171 It can let the debugger provide your system console and a file system,
1172 helping with early debugging or providing a more capable environment
1173 for sometimes-complex tasks like installing system firmware onto
1174 NAND or SPI flash.
1176 @item @b{ARM Wait-For-Interrupt}...
1177 Many ARM chips synchronize the JTAG clock using the core clock.
1178 Low power states which stop that core clock thus prevent JTAG access.
1179 Idle loops in tasking environments often enter those low power states
1180 via the @code{WFI} instruction (or its coprocessor equivalent, before ARMv7).
1182 You may want to @emph{disable that instruction} in source code,
1183 or otherwise prevent using that state,
1184 to ensure you can get JTAG access at any time.@footnote{As a more
1185 polite alternative, some processors have special debug-oriented
1186 registers which can be used to change various features including
1187 how the low power states are clocked while debugging.
1188 The STM32 DBGMCU_CR register is an example; at the cost of extra
1189 power consumption, JTAG can be used during low power states.}
1190 For example, the OpenOCD @command{halt} command may not
1191 work for an idle processor otherwise.
1193 @item @b{Delay after reset}...
1194 Not all chips have good support for debugger access
1195 right after reset; many LPC2xxx chips have issues here.
1196 Similarly, applications that reconfigure pins used for
1197 JTAG access as they start will also block debugger access.
1199 To work with boards like this, @emph{enable a short delay loop}
1200 the first thing after reset, before "real" startup activities.
1201 For example, one second's delay is usually more than enough
1202 time for a JTAG debugger to attach, so that
1203 early code execution can be debugged
1204 or firmware can be replaced.
1206 @item @b{Debug Communications Channel (DCC)}...
1207 Some processors include mechanisms to send messages over JTAG.
1208 Many ARM cores support these, as do some cores from other vendors.
1209 (OpenOCD may be able to use this DCC internally, speeding up some
1210 operations like writing to memory.)
1212 Your application may want to deliver various debugging messages
1213 over JTAG, by @emph{linking with a small library of code}
1214 provided with OpenOCD and using the utilities there to send
1215 various kinds of message.
1216 @xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.
1218 @end itemize
1220 @section Target Hardware Setup
1222 Chip vendors often provide software development boards which
1223 are highly configurable, so that they can support all options
1224 that product boards may require. @emph{Make sure that any
1225 jumpers or switches match the system configuration you are
1226 working with.}
1228 Common issues include:
1230 @itemize @bullet
1232 @item @b{JTAG setup} ...
1233 Boards may support more than one JTAG configuration.
1234 Examples include jumpers controlling pullups versus pulldowns
1235 on the nTRST and/or nSRST signals, and choice of connectors
1236 (e.g. which of two headers on the base board,
1237 or one from a daughtercard).
1238 For some Texas Instruments boards, you may need to jumper the
1239 EMU0 and EMU1 signals (which OpenOCD won't currently control).
1241 @item @b{Boot Modes} ...
1242 Complex chips often support multiple boot modes, controlled
1243 by external jumpers. Make sure this is set up correctly.
1244 For example many i.MX boards from NXP need to be jumpered
1245 to "ATX mode" to start booting using the on-chip ROM, when
1246 using second stage bootloader code stored in a NAND flash chip.
1248 Such explicit configuration is common, and not limited to
1249 booting from NAND. You might also need to set jumpers to
1250 start booting using code loaded from an MMC/SD card; external
1251 SPI flash; Ethernet, UART, or USB links; NOR flash; OneNAND
1252 flash; some external host; or various other sources.
1255 @item @b{Memory Addressing} ...
1256 Boards which support multiple boot modes may also have jumpers
1257 to configure memory addressing. One board, for example, jumpers
1258 external chipselect 0 (used for booting) to address either
1259 a large SRAM (which must be pre-loaded via JTAG), NOR flash,
1260 or NAND flash. When it's jumpered to address NAND flash, that
1261 board must also be told to start booting from on-chip ROM.
1263 Your @file{board.cfg} file may also need to be told this jumper
1264 configuration, so that it can know whether to declare NOR flash
1265 using @command{flash bank} or instead declare NAND flash with
1266 @command{nand device}; and likewise which probe to perform in
1267 its @code{reset-init} handler.
1269 A closely related issue is bus width. Jumpers might need to
1270 distinguish between 8 bit or 16 bit bus access for the flash
1271 used to start booting.
1273 @item @b{Peripheral Access} ...
1274 Development boards generally provide access to every peripheral
1275 on the chip, sometimes in multiple modes (such as by providing
1276 multiple audio codec chips).
1277 This interacts with software
1278 configuration of pin multiplexing, where for example a
1279 given pin may be routed either to the MMC/SD controller
1280 or the GPIO controller. It also often interacts with
1281 configuration jumpers. One jumper may be used to route
1282 signals to an MMC/SD card slot or an expansion bus (which
1283 might in turn affect booting); others might control which
1284 audio or video codecs are used.
1286 @end itemize
1288 Plus you should of course have @code{reset-init} event handlers
1289 which set up the hardware to match that jumper configuration.
1290 That includes in particular any oscillator or PLL used to clock
1291 the CPU, and any memory controllers needed to access external
1292 memory and peripherals. Without such handlers, you won't be
1293 able to access those resources without working target firmware
1294 which can do that setup ... this can be awkward when you're
1295 trying to debug that target firmware. Even if there's a ROM
1296 bootloader which handles a few issues, it rarely provides full
1297 access to all board-specific capabilities.
1300 @node Config File Guidelines
1301 @chapter Config File Guidelines
1303 This chapter is aimed at any user who needs to write a config file,
1304 including developers and integrators of OpenOCD and any user who
1305 needs to get a new board working smoothly.
1306 It provides guidelines for creating those files.
1308 You should find the following directories under
1309 @t{$(INSTALLDIR)/scripts}, with config files maintained upstream. Use
1310 them as-is where you can; or as models for new files.
1311 @itemize @bullet
1312 @item @file{interface} ...
1313 These are for debug adapters. Files that specify configuration to use
1314 specific JTAG, SWD and other adapters go here.
1315 @item @file{board} ...
1316 Think Circuit Board, PWA, PCB, they go by many names. Board files
1317 contain initialization items that are specific to a board.
1319 They reuse target configuration files, since the same
1320 microprocessor chips are used on many boards,
1321 but support for external parts varies widely. For
1322 example, the SDRAM initialization sequence for the board, or the type
1323 of external flash and what address it uses. Any initialization
1324 sequence to enable that external flash or SDRAM should be found in the
1325 board file. Boards may also contain multiple targets: two CPUs; or
1326 a CPU and an FPGA.
1327 @item @file{target} ...
1328 Think chip. The ``target'' directory represents the JTAG TAPs
1329 on a chip
1330 which OpenOCD should control, not a board. Two common types of targets
1331 are ARM chips and FPGA or CPLD chips.
1332 When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
1333 the target config file defines all of them.
1334 @item @emph{more} ... browse for other library files which may be useful.
1335 For example, there are various generic and CPU-specific utilities.
1336 @end itemize
1338 The @file{openocd.cfg} user config
1339 file may override features in any of the above files by
1340 setting variables before sourcing the target file, or by adding
1341 commands specific to their situation.
1343 @section Interface Config Files
1345 The user config file
1346 should be able to source one of these files with a command like this:
1348 @example
1349 source [find interface/FOOBAR.cfg]
1350 @end example
1352 A preconfigured interface file should exist for every debug adapter
1353 in use today with OpenOCD.
1354 That said, perhaps some of these config files
1355 have only been used by the developer who created it.
1357 A separate chapter gives information about how to set these up.
1358 @xref{Debug Adapter Configuration}.
1359 Read the OpenOCD source code (and Developer's Guide)
1360 if you have a new kind of hardware interface
1361 and need to provide a driver for it.
1363 @section Board Config Files
1364 @cindex config file, board
1365 @cindex board config file
1367 The user config file
1368 should be able to source one of these files with a command like this:
1370 @example
1371 source [find board/FOOBAR.cfg]
1372 @end example
1374 The point of a board config file is to package everything
1375 about a given board that user config files need to know.
1376 In summary the board files should contain (if present)
1378 @enumerate
1379 @item One or more @command{source [find target/...cfg]} statements
1380 @item NOR flash configuration (@pxref{norconfiguration,,NOR Configuration})
1381 @item NAND flash configuration (@pxref{nandconfiguration,,NAND Configuration})
1382 @item Target @code{reset} handlers for SDRAM and I/O configuration
1383 @item JTAG adapter reset configuration (@pxref{Reset Configuration})
1384 @item All things that are not ``inside a chip''
1385 @end enumerate
1387 Generic things inside target chips belong in target config files,
1388 not board config files. So for example a @code{reset-init} event
1389 handler should know board-specific oscillator and PLL parameters,
1390 which it passes to target-specific utility code.
1392 The most complex task of a board config file is creating such a
1393 @code{reset-init} event handler.
1394 Define those handlers last, after you verify the rest of the board
1395 configuration works.
1397 @subsection Communication Between Config files
1399 In addition to target-specific utility code, another way that
1400 board and target config files communicate is by following a
1401 convention on how to use certain variables.
1403 The full Tcl/Tk language supports ``namespaces'', but Jim-Tcl does not.
1404 Thus the rule we follow in OpenOCD is this: Variables that begin with
1405 a leading underscore are temporary in nature, and can be modified and
1406 used at will within a target configuration file.
1408 Complex board config files can do the things like this,
1409 for a board with three chips:
1411 @example
1412 # Chip #1: PXA270 for network side, big endian
1413 set CHIPNAME network
1414 set ENDIAN big
1415 source [find target/pxa270.cfg]
1416 # on return: _TARGETNAME = network.cpu
1417 # other commands can refer to the "network.cpu" target.
1418 $_TARGETNAME configure .... events for this CPU..
1420 # Chip #2: PXA270 for video side, little endian
1421 set CHIPNAME video
1422 set ENDIAN little
1423 source [find target/pxa270.cfg]
1424 # on return: _TARGETNAME = video.cpu
1425 # other commands can refer to the "video.cpu" target.
1426 $_TARGETNAME configure .... events for this CPU..
1428 # Chip #3: Xilinx FPGA for glue logic
1429 set CHIPNAME xilinx
1430 unset ENDIAN
1431 source [find target/spartan3.cfg]
1432 @end example
1434 That example is oversimplified because it doesn't show any flash memory,
1435 or the @code{reset-init} event handlers to initialize external DRAM
1436 or (assuming it needs it) load a configuration into the FPGA.
1437 Such features are usually needed for low-level work with many boards,
1438 where ``low level'' implies that the board initialization software may
1439 not be working. (That's a common reason to need JTAG tools. Another
1440 is to enable working with microcontroller-based systems, which often
1441 have no debugging support except a JTAG connector.)
1443 Target config files may also export utility functions to board and user
1444 config files. Such functions should use name prefixes, to help avoid
1445 naming collisions.
1447 Board files could also accept input variables from user config files.
1448 For example, there might be a @code{J4_JUMPER} setting used to identify
1449 what kind of flash memory a development board is using, or how to set
1450 up other clocks and peripherals.
1452 @subsection Variable Naming Convention
1453 @cindex variable names
1455 Most boards have only one instance of a chip.
1456 However, it should be easy to create a board with more than
1457 one such chip (as shown above).
1458 Accordingly, we encourage these conventions for naming
1459 variables associated with different @file{target.cfg} files,
1460 to promote consistency and
1461 so that board files can override target defaults.
1463 Inputs to target config files include:
1465 @itemize @bullet
1466 @item @code{CHIPNAME} ...
1467 This gives a name to the overall chip, and is used as part of
1468 tap identifier dotted names.
1469 While the default is normally provided by the chip manufacturer,
1470 board files may need to distinguish between instances of a chip.
1471 @item @code{ENDIAN} ...
1472 By default @option{little} - although chips may hard-wire @option{big}.
1473 Chips that can't change endianess don't need to use this variable.
1474 @item @code{CPUTAPID} ...
1475 When OpenOCD examines the JTAG chain, it can be told verify the
1476 chips against the JTAG IDCODE register.
1477 The target file will hold one or more defaults, but sometimes the
1478 chip in a board will use a different ID (perhaps a newer revision).
1479 @end itemize
1481 Outputs from target config files include:
1483 @itemize @bullet
1484 @item @code{_TARGETNAME} ...
1485 By convention, this variable is created by the target configuration
1486 script. The board configuration file may make use of this variable to
1487 configure things like a ``reset init'' script, or other things
1488 specific to that board and that target.
1489 If the chip has 2 targets, the names are @code{_TARGETNAME0},
1490 @code{_TARGETNAME1}, ... etc.
1491 @end itemize
1493 @subsection The reset-init Event Handler
1494 @cindex event, reset-init
1495 @cindex reset-init handler
1497 Board config files run in the OpenOCD configuration stage;
1498 they can't use TAPs or targets, since they haven't been
1499 fully set up yet.
1500 This means you can't write memory or access chip registers;
1501 you can't even verify that a flash chip is present.
1502 That's done later in event handlers, of which the target @code{reset-init}
1503 handler is one of the most important.
1505 Except on microcontrollers, the basic job of @code{reset-init} event
1506 handlers is setting up flash and DRAM, as normally handled by boot loaders.
1507 Microcontrollers rarely use boot loaders; they run right out of their
1508 on-chip flash and SRAM memory. But they may want to use one of these
1509 handlers too, if just for developer convenience.
1511 @quotation Note
1512 Because this is so very board-specific, and chip-specific, no examples
1513 are included here.
1514 Instead, look at the board config files distributed with OpenOCD.
1515 If you have a boot loader, its source code will help; so will
1516 configuration files for other JTAG tools
1517 (@pxref{translatingconfigurationfiles,,Translating Configuration Files}).
1518 @end quotation
1520 Some of this code could probably be shared between different boards.
1521 For example, setting up a DRAM controller often doesn't differ by
1522 much except the bus width (16 bits or 32?) and memory timings, so a
1523 reusable TCL procedure loaded by the @file{target.cfg} file might take
1524 those as parameters.
1525 Similarly with oscillator, PLL, and clock setup;
1526 and disabling the watchdog.
1527 Structure the code cleanly, and provide comments to help
1528 the next developer doing such work.
1529 (@emph{You might be that next person} trying to reuse init code!)
1531 The last thing normally done in a @code{reset-init} handler is probing
1532 whatever flash memory was configured. For most chips that needs to be
1533 done while the associated target is halted, either because JTAG memory
1534 access uses the CPU or to prevent conflicting CPU access.
1536 @subsection JTAG Clock Rate
1538 Before your @code{reset-init} handler has set up
1539 the PLLs and clocking, you may need to run with
1540 a low JTAG clock rate.
1541 @xref{jtagspeed,,JTAG Speed}.
1542 Then you'd increase that rate after your handler has
1543 made it possible to use the faster JTAG clock.
1544 When the initial low speed is board-specific, for example
1545 because it depends on a board-specific oscillator speed, then
1546 you should probably set it up in the board config file;
1547 if it's target-specific, it belongs in the target config file.
1549 For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
1550 @uref{http://www.arm.com/support/faqdev/4170.html} gives details.}
1551 is one sixth of the CPU clock; or one eighth for ARM11 cores.
1552 Consult chip documentation to determine the peak JTAG clock rate,
1553 which might be less than that.
1555 @quotation Warning
1556 On most ARMs, JTAG clock detection is coupled to the core clock, so
1557 software using a @option{wait for interrupt} operation blocks JTAG access.
1558 Adaptive clocking provides a partial workaround, but a more complete
1559 solution just avoids using that instruction with JTAG debuggers.
1560 @end quotation
1562 If both the chip and the board support adaptive clocking,
1563 use the @command{jtag_rclk}
1564 command, in case your board is used with JTAG adapter which
1565 also supports it. Otherwise use @command{adapter_khz}.
1566 Set the slow rate at the beginning of the reset sequence,
1567 and the faster rate as soon as the clocks are at full speed.
1569 @anchor{theinitboardprocedure}
1570 @subsection The init_board procedure
1571 @cindex init_board procedure
1573 The concept of @code{init_board} procedure is very similar to @code{init_targets}
1574 (@xref{theinittargetsprocedure,,The init_targets procedure}.) - it's a replacement of ``linear''
1575 configuration scripts. This procedure is meant to be executed when OpenOCD enters run stage
1576 (@xref{enteringtherunstage,,Entering the Run Stage},) after @code{init_targets}. The idea to have
1577 separate @code{init_targets} and @code{init_board} procedures is to allow the first one to configure
1578 everything target specific (internal flash, internal RAM, etc.) and the second one to configure
1579 everything board specific (reset signals, chip frequency, reset-init event handler, external memory, etc.).
1580 Additionally ``linear'' board config file will most likely fail when target config file uses
1581 @code{init_targets} scheme (``linear'' script is executed before @code{init} and @code{init_targets} - after),
1582 so separating these two configuration stages is very convenient, as the easiest way to overcome this
1583 problem is to convert board config file to use @code{init_board} procedure. Board config scripts don't
1584 need to override @code{init_targets} defined in target config files when they only need to add some specifics.
1586 Just as @code{init_targets}, the @code{init_board} procedure can be overridden by ``next level'' script (which sources
1587 the original), allowing greater code reuse.
1589 @example
1590 ### board_file.cfg ###
1592 # source target file that does most of the config in init_targets
1593 source [find target/target.cfg]
1595 proc enable_fast_clock @{@} @{
1596 # enables fast on-board clock source
1597 # configures the chip to use it
1598 @}
1600 # initialize only board specifics - reset, clock, adapter frequency
1601 proc init_board @{@} @{
1602 reset_config trst_and_srst trst_pulls_srst
1604 $_TARGETNAME configure -event reset-start @{
1605 adapter_khz 100
1606 @}
1608 $_TARGETNAME configure -event reset-init @{
1609 enable_fast_clock
1610 adapter_khz 10000
1611 @}
1612 @}
1613 @end example
1615 @section Target Config Files
1616 @cindex config file, target
1617 @cindex target config file
1619 Board config files communicate with target config files using
1620 naming conventions as described above, and may source one or
1621 more target config files like this:
1623 @example
1624 source [find target/FOOBAR.cfg]
1625 @end example
1627 The point of a target config file is to package everything
1628 about a given chip that board config files need to know.
1629 In summary the target files should contain
1631 @enumerate
1632 @item Set defaults
1633 @item Add TAPs to the scan chain
1634 @item Add CPU targets (includes GDB support)
1635 @item CPU/Chip/CPU-Core specific features
1636 @item On-Chip flash
1637 @end enumerate
1639 As a rule of thumb, a target file sets up only one chip.
1640 For a microcontroller, that will often include a single TAP,
1641 which is a CPU needing a GDB target, and its on-chip flash.
1643 More complex chips may include multiple TAPs, and the target
1644 config file may need to define them all before OpenOCD
1645 can talk to the chip.
1646 For example, some phone chips have JTAG scan chains that include
1647 an ARM core for operating system use, a DSP,
1648 another ARM core embedded in an image processing engine,
1649 and other processing engines.
1651 @subsection Default Value Boiler Plate Code
1653 All target configuration files should start with code like this,
1654 letting board config files express environment-specific
1655 differences in how things should be set up.
1657 @example
1658 # Boards may override chip names, perhaps based on role,
1659 # but the default should match what the vendor uses
1660 if @{ [info exists CHIPNAME] @} @{
1662 @} else @{
1663 set _CHIPNAME sam7x256
1664 @}
1666 # ONLY use ENDIAN with targets that can change it.
1667 if @{ [info exists ENDIAN] @} @{
1668 set _ENDIAN $ENDIAN
1669 @} else @{
1670 set _ENDIAN little
1671 @}
1673 # TAP identifiers may change as chips mature, for example with
1674 # new revision fields (the "3" here). Pick a good default; you
1675 # can pass several such identifiers to the "jtag newtap" command.
1676 if @{ [info exists CPUTAPID ] @} @{
1678 @} else @{
1679 set _CPUTAPID 0x3f0f0f0f
1680 @}
1681 @end example
1682 @c but 0x3f0f0f0f is for an str73x part ...
1684 @emph{Remember:} Board config files may include multiple target
1685 config files, or the same target file multiple times
1686 (changing at least @code{CHIPNAME}).
1688 Likewise, the target configuration file should define
1689 @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
1690 use it later on when defining debug targets:
1692 @example
1694 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1695 @end example
1697 @subsection Adding TAPs to the Scan Chain
1698 After the ``defaults'' are set up,
1699 add the TAPs on each chip to the JTAG scan chain.
1700 @xref{TAP Declaration}, and the naming convention
1701 for taps.
1703 In the simplest case the chip has only one TAP,
1704 probably for a CPU or FPGA.
1705 The config file for the Atmel AT91SAM7X256
1706 looks (in part) like this:
1708 @example
1709 jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
1710 @end example
1712 A board with two such at91sam7 chips would be able
1713 to source such a config file twice, with different
1714 values for @code{CHIPNAME}, so
1715 it adds a different TAP each time.
1717 If there are nonzero @option{-expected-id} values,
1718 OpenOCD attempts to verify the actual tap id against those values.
1719 It will issue error messages if there is mismatch, which
1720 can help to pinpoint problems in OpenOCD configurations.
1722 @example
1723 JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
1724 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
1725 ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
1726 ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
1727 ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
1728 @end example
1730 There are more complex examples too, with chips that have
1731 multiple TAPs. Ones worth looking at include:
1733 @itemize
1734 @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
1735 plus a JRC to enable them
1736 @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
1737 @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
1738 is not currently used)
1739 @end itemize
1741 @subsection Add CPU targets
1743 After adding a TAP for a CPU, you should set it up so that
1744 GDB and other commands can use it.
1745 @xref{CPU Configuration}.
1746 For the at91sam7 example above, the command can look like this;
1747 note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
1748 to little endian, and this chip doesn't support changing that.
1750 @example
1752 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1753 @end example
1755 Work areas are small RAM areas associated with CPU targets.
1756 They are used by OpenOCD to speed up downloads,
1757 and to download small snippets of code to program flash chips.
1758 If the chip includes a form of ``on-chip-ram'' - and many do - define
1759 a work area if you can.
1760 Again using the at91sam7 as an example, this can look like:
1762 @example
1763 $_TARGETNAME configure -work-area-phys 0x00200000 \
1764 -work-area-size 0x4000 -work-area-backup 0
1765 @end example
1767 @anchor{definecputargetsworkinginsmp}
1768 @subsection Define CPU targets working in SMP
1769 @cindex SMP
1770 After setting targets, you can define a list of targets working in SMP.
1772 @example
1773 set _TARGETNAME_1 $_CHIPNAME.cpu1
1774 set _TARGETNAME_2 $_CHIPNAME.cpu2
1775 target create $_TARGETNAME_1 cortex_a -chain-position $_CHIPNAME.dap \
1776 -coreid 0 -dbgbase $_DAP_DBG1
1777 target create $_TARGETNAME_2 cortex_a -chain-position $_CHIPNAME.dap \
1778 -coreid 1 -dbgbase $_DAP_DBG2
1779 #define 2 targets working in smp.
1780 target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
1781 @end example
1782 In the above example on cortex_a, 2 cpus are working in SMP.
1783 In SMP only one GDB instance is created and :
1784 @itemize @bullet
1785 @item a set of hardware breakpoint sets the same breakpoint on all targets in the list.
1786 @item halt command triggers the halt of all targets in the list.
1787 @item resume command triggers the write context and the restart of all targets in the list.
1788 @item following a breakpoint: the target stopped by the breakpoint is displayed to the GDB session.
1789 @item dedicated GDB serial protocol packets are implemented for switching/retrieving the target
1790 displayed by the GDB session @pxref{usingopenocdsmpwithgdb,,Using OpenOCD SMP with GDB}.
1791 @end itemize
1793 The SMP behaviour can be disabled/enabled dynamically. On cortex_a following
1794 command have been implemented.
1795 @itemize @bullet
1796 @item cortex_a smp_on : enable SMP mode, behaviour is as described above.
1797 @item cortex_a smp_off : disable SMP mode, the current target is the one
1798 displayed in the GDB session, only this target is now controlled by GDB
1799 session. This behaviour is useful during system boot up.
1800 @item cortex_a smp_gdb : display/fix the core id displayed in GDB session see
1801 following example.
1802 @end itemize
1804 @example
1805 >cortex_a smp_gdb
1806 gdb coreid 0 -> -1
1807 #0 : coreid 0 is displayed to GDB ,
1808 #-> -1 : next resume triggers a real resume
1809 > cortex_a smp_gdb 1
1810 gdb coreid 0 -> 1
1811 #0 :coreid 0 is displayed to GDB ,
1812 #->1 : next resume displays coreid 1 to GDB
1813 > resume
1814 > cortex_a smp_gdb
1815 gdb coreid 1 -> 1
1816 #1 :coreid 1 is displayed to GDB ,
1817 #->1 : next resume displays coreid 1 to GDB
1818 > cortex_a smp_gdb -1
1819 gdb coreid 1 -> -1
1820 #1 :coreid 1 is displayed to GDB,
1821 #->-1 : next resume triggers a real resume
1822 @end example
1825 @subsection Chip Reset Setup
1827 As a rule, you should put the @command{reset_config} command
1828 into the board file. Most things you think you know about a
1829 chip can be tweaked by the board.
1831 Some chips have specific ways the TRST and SRST signals are
1832 managed. In the unusual case that these are @emph{chip specific}
1833 and can never be changed by board wiring, they could go here.
1834 For example, some chips can't support JTAG debugging without
1835 both signals.
1837 Provide a @code{reset-assert} event handler if you can.
1838 Such a handler uses JTAG operations to reset the target,
1839 letting this target config be used in systems which don't
1840 provide the optional SRST signal, or on systems where you
1841 don't want to reset all targets at once.
1842 Such a handler might write to chip registers to force a reset,
1843 use a JRC to do that (preferable -- the target may be wedged!),
1844 or force a watchdog timer to trigger.
1845 (For Cortex-M targets, this is not necessary. The target
1846 driver knows how to use trigger an NVIC reset when SRST is
1847 not available.)
1849 Some chips need special attention during reset handling if
1850 they're going to be used with JTAG.
1851 An example might be needing to send some commands right
1852 after the target's TAP has been reset, providing a
1853 @code{reset-deassert-post} event handler that writes a chip
1854 register to report that JTAG debugging is being done.
1855 Another would be reconfiguring the watchdog so that it stops
1856 counting while the core is halted in the debugger.
1858 JTAG clocking constraints often change during reset, and in
1859 some cases target config files (rather than board config files)
1860 are the right places to handle some of those issues.
1861 For example, immediately after reset most chips run using a
1862 slower clock than they will use later.
1863 That means that after reset (and potentially, as OpenOCD
1864 first starts up) they must use a slower JTAG clock rate
1865 than they will use later.
1866 @xref{jtagspeed,,JTAG Speed}.
1868 @quotation Important
1869 When you are debugging code that runs right after chip
1870 reset, getting these issues right is critical.
1871 In particular, if you see intermittent failures when
1872 OpenOCD verifies the scan chain after reset,
1873 look at how you are setting up JTAG clocking.
1874 @end quotation
1876 @anchor{theinittargetsprocedure}
1877 @subsection The init_targets procedure
1878 @cindex init_targets procedure
1880 Target config files can either be ``linear'' (script executed line-by-line when parsed in
1881 configuration stage, @xref{configurationstage,,Configuration Stage},) or they can contain a special
1882 procedure called @code{init_targets}, which will be executed when entering run stage
1883 (after parsing all config files or after @code{init} command, @xref{enteringtherunstage,,Entering the Run Stage}.)
1884 Such procedure can be overridden by ``next level'' script (which sources the original).
1885 This concept facilitates code reuse when basic target config files provide generic configuration
1886 procedures and @code{init_targets} procedure, which can then be sourced and enhanced or changed in
1887 a ``more specific'' target config file. This is not possible with ``linear'' config scripts,
1888 because sourcing them executes every initialization commands they provide.
1890 @example
1891 ### generic_file.cfg ###
1893 proc setup_my_chip @{chip_name flash_size ram_size@} @{
1894 # basic initialization procedure ...
1895 @}
1897 proc init_targets @{@} @{
1898 # initializes generic chip with 4kB of flash and 1kB of RAM
1899 setup_my_chip MY_GENERIC_CHIP 4096 1024
1900 @}
1902 ### specific_file.cfg ###
1904 source [find target/generic_file.cfg]
1906 proc init_targets @{@} @{
1907 # initializes specific chip with 128kB of flash and 64kB of RAM
1908 setup_my_chip MY_CHIP_WITH_128K_FLASH_64KB_RAM 131072 65536
1909 @}
1910 @end example
1912 The easiest way to convert ``linear'' config files to @code{init_targets} version is to
1913 enclose every line of ``code'' (i.e. not @code{source} commands, procedures, etc.) in this procedure.
1915 For an example of this scheme see LPC2000 target config files.
1917 The @code{init_boards} procedure is a similar concept concerning board config files
1918 (@xref{theinitboardprocedure,,The init_board procedure}.)
1920 @anchor{theinittargeteventsprocedure}
1921 @subsection The init_target_events procedure
1922 @cindex init_target_events procedure
1924 A special procedure called @code{init_target_events} is run just after
1925 @code{init_targets} (@xref{theinittargetsprocedure,,The init_targets
1926 procedure}.) and before @code{init_board}
1927 (@xref{theinitboardprocedure,,The init_board procedure}.) It is used
1928 to set up default target events for the targets that do not have those
1929 events already assigned.
1931 @subsection ARM Core Specific Hacks
1933 If the chip has a DCC, enable it. If the chip is an ARM9 with some
1934 special high speed download features - enable it.
1936 If present, the MMU, the MPU and the CACHE should be disabled.
1938 Some ARM cores are equipped with trace support, which permits
1939 examination of the instruction and data bus activity. Trace
1940 activity is controlled through an ``Embedded Trace Module'' (ETM)
1941 on one of the core's scan chains. The ETM emits voluminous data
1942 through a ``trace port''. (@xref{armhardwaretracing,,ARM Hardware Tracing}.)
1943 If you are using an external trace port,
1944 configure it in your board config file.
1945 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
1946 configure it in your target config file.
1948 @example
1949 etm config $_TARGETNAME 16 normal full etb
1950 etb config $_TARGETNAME $_CHIPNAME.etb
1951 @end example
1953 @subsection Internal Flash Configuration
1955 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
1957 @b{Never ever} in the ``target configuration file'' define any type of
1958 flash that is external to the chip. (For example a BOOT flash on
1959 Chip Select 0.) Such flash information goes in a board file - not
1960 the TARGET (chip) file.
1962 Examples:
1963 @itemize @bullet
1964 @item at91sam7x256 - has 256K flash YES enable it.
1965 @item str912 - has flash internal YES enable it.
1966 @item imx27 - uses boot flash on CS0 - it goes in the board file.
1967 @item pxa270 - again - CS0 flash - it goes in the board file.
1968 @end itemize
1970 @anchor{translatingconfigurationfiles}
1971 @section Translating Configuration Files
1972 @cindex translation
1973 If you have a configuration file for another hardware debugger
1974 or toolset (Abatron, BDI2000, BDI3000, CCS,
1975 Lauterbach, SEGGER, Macraigor, etc.), translating
1976 it into OpenOCD syntax is often quite straightforward. The most tricky
1977 part of creating a configuration script is oftentimes the reset init
1978 sequence where e.g. PLLs, DRAM and the like is set up.
1980 One trick that you can use when translating is to write small
1981 Tcl procedures to translate the syntax into OpenOCD syntax. This
1982 can avoid manual translation errors and make it easier to
1983 convert other scripts later on.
1985 Example of transforming quirky arguments to a simple search and
1986 replace job:
1988 @example
1989 # Lauterbach syntax(?)
1990 #
1991 # Data.Set c15:0x042f %long 0x40000015
1992 #
1993 # OpenOCD syntax when using procedure below.
1994 #
1995 # setc15 0x01 0x00050078
1997 proc setc15 @{regs value@} @{
1998 global TARGETNAME
2000 echo [format "set p15 0x%04x, 0x%08x" $regs $value]
2002 arm mcr 15 [expr ($regs>>12)&0x7] \
2003 [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] \
2004 [expr ($regs>>8)&0x7] $value
2005 @}
2006 @end example
2010 @node Server Configuration
2011 @chapter Server Configuration
2012 @cindex initialization
2013 The commands here are commonly found in the openocd.cfg file and are
2014 used to specify what TCP/IP ports are used, and how GDB should be
2015 supported.
2017 @anchor{configurationstage}
2018 @section Configuration Stage
2019 @cindex configuration stage
2020 @cindex config command
2022 When the OpenOCD server process starts up, it enters a
2023 @emph{configuration stage} which is the only time that
2024 certain commands, @emph{configuration commands}, may be issued.
2025 Normally, configuration commands are only available
2026 inside startup scripts.
2028 In this manual, the definition of a configuration command is
2029 presented as a @emph{Config Command}, not as a @emph{Command}
2030 which may be issued interactively.
2031 The runtime @command{help} command also highlights configuration
2032 commands, and those which may be issued at any time.
2034 Those configuration commands include declaration of TAPs,
2035 flash banks,
2036 the interface used for JTAG communication,
2037 and other basic setup.
2038 The server must leave the configuration stage before it
2039 may access or activate TAPs.
2040 After it leaves this stage, configuration commands may no
2041 longer be issued.
2043 @anchor{enteringtherunstage}
2044 @section Entering the Run Stage
2046 The first thing OpenOCD does after leaving the configuration
2047 stage is to verify that it can talk to the scan chain
2048 (list of TAPs) which has been configured.
2049 It will warn if it doesn't find TAPs it expects to find,
2050 or finds TAPs that aren't supposed to be there.
2051 You should see no errors at this point.
2052 If you see errors, resolve them by correcting the
2053 commands you used to configure the server.
2054 Common errors include using an initial JTAG speed that's too
2055 fast, and not providing the right IDCODE values for the TAPs
2056 on the scan chain.
2058 Once OpenOCD has entered the run stage, a number of commands
2059 become available.
2060 A number of these relate to the debug targets you may have declared.
2061 For example, the @command{mww} command will not be available until
2062 a target has been successfully instantiated.
2063 If you want to use those commands, you may need to force
2064 entry to the run stage.
2066 @deffn {Config Command} init
2067 This command terminates the configuration stage and
2068 enters the run stage. This helps when you need to have
2069 the startup scripts manage tasks such as resetting the target,
2070 programming flash, etc. To reset the CPU upon startup, add "init" and
2071 "reset" at the end of the config script or at the end of the OpenOCD
2072 command line using the @option{-c} command line switch.
2074 If this command does not appear in any startup/configuration file
2075 OpenOCD executes the command for you after processing all
2076 configuration files and/or command line options.
2078 @b{NOTE:} This command normally occurs at or near the end of your
2079 openocd.cfg file to force OpenOCD to ``initialize'' and make the
2080 targets ready. For example: If your openocd.cfg file needs to
2081 read/write memory on your target, @command{init} must occur before
2082 the memory read/write commands. This includes @command{nand probe}.
2083 @end deffn
2085 @deffn {Overridable Procedure} jtag_init
2086 This is invoked at server startup to verify that it can talk
2087 to the scan chain (list of TAPs) which has been configured.
2089 The default implementation first tries @command{jtag arp_init},
2090 which uses only a lightweight JTAG reset before examining the
2091 scan chain.
2092 If that fails, it tries again, using a harder reset
2093 from the overridable procedure @command{init_reset}.
2095 Implementations must have verified the JTAG scan chain before
2096 they return.
2097 This is done by calling @command{jtag arp_init}
2098 (or @command{jtag arp_init-reset}).
2099 @end deffn
2101 @anchor{tcpipports}
2102 @section TCP/IP Ports
2103 @cindex TCP port
2104 @cindex server
2105 @cindex port
2106 @cindex security
2107 The OpenOCD server accepts remote commands in several syntaxes.
2108 Each syntax uses a different TCP/IP port, which you may specify
2109 only during configuration (before those ports are opened).
2111 For reasons including security, you may wish to prevent remote
2112 access using one or more of these ports.
2113 In such cases, just specify the relevant port number as "disabled".
2114 If you disable all access through TCP/IP, you will need to
2115 use the command line @option{-pipe} option.
2117 @anchor{gdb_port}
2118 @deffn {Command} gdb_port [number]
2119 @cindex GDB server
2120 Normally gdb listens to a TCP/IP port, but GDB can also
2121 communicate via pipes(stdin/out or named pipes). The name
2122 "gdb_port" stuck because it covers probably more than 90% of
2123 the normal use cases.
2125 No arguments reports GDB port. "pipe" means listen to stdin
2126 output to stdout, an integer is base port number, "disabled"
2127 disables the gdb server.
2129 When using "pipe", also use log_output to redirect the log
2130 output to a file so as not to flood the stdin/out pipes.
2132 The -p/--pipe option is deprecated and a warning is printed
2133 as it is equivalent to passing in -c "gdb_port pipe; log_output openocd.log".
2135 Any other string is interpreted as named pipe to listen to.
2136 Output pipe is the same name as input pipe, but with 'o' appended,
2137 e.g. /var/gdb, /var/gdbo.
2139 The GDB port for the first target will be the base port, the
2140 second target will listen on gdb_port + 1, and so on.
2141 When not specified during the configuration stage,
2142 the port @var{number} defaults to 3333.
2143 When @var{number} is not a numeric value, incrementing it to compute
2144 the next port number does not work. In this case, specify the proper
2145 @var{number} for each target by using the option @code{-gdb-port} of the
2146 commands @command{target create} or @command{$target_name configure}.
2147 @xref{gdbportoverride,,option -gdb-port}.
2149 Note: when using "gdb_port pipe", increasing the default remote timeout in
2150 gdb (with 'set remotetimeout') is recommended. An insufficient timeout may
2151 cause initialization to fail with "Unknown remote qXfer reply: OK".
2152 @end deffn
2154 @deffn {Command} tcl_port [number]
2155 Specify or query the port used for a simplified RPC
2156 connection that can be used by clients to issue TCL commands and get the
2157 output from the Tcl engine.
2158 Intended as a machine interface.
2159 When not specified during the configuration stage,
2160 the port @var{number} defaults to 6666.
2161 When specified as "disabled", this service is not activated.
2162 @end deffn
2164 @deffn {Command} telnet_port [number]
2165 Specify or query the
2166 port on which to listen for incoming telnet connections.
2167 This port is intended for interaction with one human through TCL commands.
2168 When not specified during the configuration stage,
2169 the port @var{number} defaults to 4444.
2170 When specified as "disabled", this service is not activated.
2171 @end deffn
2173 @anchor{gdbconfiguration}
2174 @section GDB Configuration
2175 @cindex GDB
2176 @cindex GDB configuration
2177 You can reconfigure some GDB behaviors if needed.
2178 The ones listed here are static and global.
2179 @xref{targetconfiguration,,Target Configuration}, about configuring individual targets.
2180 @xref{targetevents,,Target Events}, about configuring target-specific event handling.
2182 @anchor{gdbbreakpointoverride}
2183 @deffn {Command} gdb_breakpoint_override [@option{hard}|@option{soft}|@option{disable}]
2184 Force breakpoint type for gdb @command{break} commands.
2185 This option supports GDB GUIs which don't
2186 distinguish hard versus soft breakpoints, if the default OpenOCD and
2187 GDB behaviour is not sufficient. GDB normally uses hardware
2188 breakpoints if the memory map has been set up for flash regions.
2189 @end deffn
2191 @anchor{gdbflashprogram}
2192 @deffn {Config Command} gdb_flash_program (@option{enable}|@option{disable})
2193 Set to @option{enable} to cause OpenOCD to program the flash memory when a
2194 vFlash packet is received.
2195 The default behaviour is @option{enable}.
2196 @end deffn
2198 @deffn {Config Command} gdb_memory_map (@option{enable}|@option{disable})
2199 Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
2200 requested. GDB will then know when to set hardware breakpoints, and program flash
2201 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
2202 for flash programming to work.
2203 Default behaviour is @option{enable}.
2204 @xref{gdbflashprogram,,gdb_flash_program}.
2205 @end deffn
2207 @deffn {Config Command} gdb_report_data_abort (@option{enable}|@option{disable})
2208 Specifies whether data aborts cause an error to be reported
2209 by GDB memory read packets.
2210 The default behaviour is @option{disable};
2211 use @option{enable} see these errors reported.
2212 @end deffn
2214 @deffn {Config Command} gdb_report_register_access_error (@option{enable}|@option{disable})
2215 Specifies whether register accesses requested by GDB register read/write
2216 packets report errors or not.
2217 The default behaviour is @option{disable};
2218 use @option{enable} see these errors reported.
2219 @end deffn
2221 @deffn {Config Command} gdb_target_description (@option{enable}|@option{disable})
2222 Set to @option{enable} to cause OpenOCD to send the target descriptions to gdb via qXfer:features:read packet.
2223 The default behaviour is @option{enable}.
2224 @end deffn
2226 @deffn {Command} gdb_save_tdesc
2227 Saves the target description file to the local file system.
2229 The file name is @i{target_name}.xml.
2230 @end deffn
2232 @anchor{eventpolling}
2233 @section Event Polling
2235 Hardware debuggers are parts of asynchronous systems,
2236 where significant events can happen at any time.
2237 The OpenOCD server needs to detect some of these events,
2238 so it can report them to through TCL command line
2239 or to GDB.
2241 Examples of such events include:
2243 @itemize
2244 @item One of the targets can stop running ... maybe it triggers
2245 a code breakpoint or data watchpoint, or halts itself.
2246 @item Messages may be sent over ``debug message'' channels ... many
2247 targets support such messages sent over JTAG,
2248 for receipt by the person debugging or tools.
2249 @item Loss of power ... some adapters can detect these events.
2250 @item Resets not issued through JTAG ... such reset sources
2251 can include button presses or other system hardware, sometimes
2252 including the target itself (perhaps through a watchdog).
2253 @item Debug instrumentation sometimes supports event triggering
2254 such as ``trace buffer full'' (so it can quickly be emptied)
2255 or other signals (to correlate with code behavior).
2256 @end itemize
2258 None of those events are signaled through standard JTAG signals.
2259 However, most conventions for JTAG connectors include voltage
2260 level and system reset (SRST) signal detection.
2261 Some connectors also include instrumentation signals, which
2262 can imply events when those signals are inputs.
2264 In general, OpenOCD needs to periodically check for those events,
2265 either by looking at the status of signals on the JTAG connector
2266 or by sending synchronous ``tell me your status'' JTAG requests
2267 to the various active targets.
2268 There is a command to manage and monitor that polling,
2269 which is normally done in the background.
2271 @deffn Command poll [@option{on}|@option{off}]
2272 Poll the current target for its current state.
2273 (Also, @pxref{targetcurstate,,target curstate}.)
2274 If that target is in debug mode, architecture
2275 specific information about the current state is printed.
2276 An optional parameter
2277 allows background polling to be enabled and disabled.
2279 You could use this from the TCL command shell, or
2280 from GDB using @command{monitor poll} command.
2281 Leave background polling enabled while you're using GDB.
2282 @example
2283 > poll
2284 background polling: on
2285 target state: halted
2286 target halted in ARM state due to debug-request, \
2287 current mode: Supervisor
2288 cpsr: 0x800000d3 pc: 0x11081bfc
2289 MMU: disabled, D-Cache: disabled, I-Cache: enabled
2290 >
2291 @end example
2292 @end deffn
2294 @node Debug Adapter Configuration
2295 @chapter Debug Adapter Configuration
2296 @cindex config file, interface
2297 @cindex interface config file
2299 Correctly installing OpenOCD includes making your operating system give
2300 OpenOCD access to debug adapters. Once that has been done, Tcl commands
2301 are used to select which one is used, and to configure how it is used.
2303 @quotation Note
2304 Because OpenOCD started out with a focus purely on JTAG, you may find
2305 places where it wrongly presumes JTAG is the only transport protocol
2306 in use. Be aware that recent versions of OpenOCD are removing that
2307 limitation. JTAG remains more functional than most other transports.
2308 Other transports do not support boundary scan operations, or may be
2309 specific to a given chip vendor. Some might be usable only for
2310 programming flash memory, instead of also for debugging.
2311 @end quotation
2313 Debug Adapters/Interfaces/Dongles are normally configured
2314 through commands in an interface configuration
2315 file which is sourced by your @file{openocd.cfg} file, or
2316 through a command line @option{-f interface/....cfg} option.
2318 @example
2319 source [find interface/olimex-jtag-tiny.cfg]
2320 @end example
2322 These commands tell
2323 OpenOCD what type of JTAG adapter you have, and how to talk to it.
2324 A few cases are so simple that you only need to say what driver to use:
2326 @example
2327 # jlink interface
2328 interface jlink
2329 @end example
2331 Most adapters need a bit more configuration than that.
2334 @section Interface Configuration
2336 The interface command tells OpenOCD what type of debug adapter you are
2337 using. Depending on the type of adapter, you may need to use one or
2338 more additional commands to further identify or configure the adapter.
2340 @deffn {Config Command} {interface} name
2341 Use the interface driver @var{name} to connect to the
2342 target.
2343 @end deffn
2345 @deffn Command {interface_list}
2346 List the debug adapter drivers that have been built into
2347 the running copy of OpenOCD.
2348 @end deffn
2349 @deffn Command {interface transports} transport_name+
2350 Specifies the transports supported by this debug adapter.
2351 The adapter driver builds-in similar knowledge; use this only
2352 when external configuration (such as jumpering) changes what
2353 the hardware can support.
2354 @end deffn
2358 @deffn Command {adapter_name}
2359 Returns the name of the debug adapter driver being used.
2360 @end deffn
2362 @section Interface Drivers
2364 Each of the interface drivers listed here must be explicitly
2365 enabled when OpenOCD is configured, in order to be made
2366 available at run time.
2368 @deffn {Interface Driver} {amt_jtagaccel}
2369 Amontec Chameleon in its JTAG Accelerator configuration,
2370 connected to a PC's EPP mode parallel port.
2371 This defines some driver-specific commands:
2373 @deffn {Config Command} {parport_port} number
2374 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
2375 the number of the @file{/dev/parport} device.
2376 @end deffn
2378 @deffn {Config Command} rtck [@option{enable}|@option{disable}]
2379 Displays status of RTCK option.
2380 Optionally sets that option first.
2381 @end deffn
2382 @end deffn
2384 @deffn {Interface Driver} {arm-jtag-ew}
2385 Olimex ARM-JTAG-EW USB adapter
2386 This has one driver-specific command:
2388 @deffn Command {armjtagew_info}
2389 Logs some status
2390 @end deffn
2391 @end deffn
2393 @deffn {Interface Driver} {at91rm9200}
2394 Supports bitbanged JTAG from the local system,
2395 presuming that system is an Atmel AT91rm9200
2396 and a specific set of GPIOs is used.
2397 @c command: at91rm9200_device NAME
2398 @c chooses among list of bit configs ... only one option
2399 @end deffn
2401 @deffn {Interface Driver} {cmsis-dap}
2402 ARM CMSIS-DAP compliant based adapter.
2404 @deffn {Config Command} {cmsis_dap_vid_pid} [vid pid]+
2405 The vendor ID and product ID of the CMSIS-DAP device. If not specified
2406 the driver will attempt to auto detect the CMSIS-DAP device.
2407 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2408 @example
2409 cmsis_dap_vid_pid 0xc251 0xf001 0x0d28 0x0204
2410 @end example
2411 @end deffn
2413 @deffn {Config Command} {cmsis_dap_serial} [serial]
2414 Specifies the @var{serial} of the CMSIS-DAP device to use.
2415 If not specified, serial numbers are not considered.
2416 @end deffn
2418 @deffn {Command} {cmsis-dap info}
2419 Display various device information, like hardware version, firmware version, current bus status.
2420 @end deffn
2421 @end deffn
2423 @deffn {Interface Driver} {dummy}
2424 A dummy software-only driver for debugging.
2425 @end deffn
2427 @deffn {Interface Driver} {ep93xx}
2428 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
2429 @end deffn
2431 @deffn {Interface Driver} {ftdi}
2432 This driver is for adapters using the MPSSE (Multi-Protocol Synchronous Serial
2433 Engine) mode built into many FTDI chips, such as the FT2232, FT4232 and FT232H.
2435 The driver is using libusb-1.0 in asynchronous mode to talk to the FTDI device,
2436 bypassing intermediate libraries like libftdi or D2XX.
2438 Support for new FTDI based adapters can be added completely through
2439 configuration files, without the need to patch and rebuild OpenOCD.
2441 The driver uses a signal abstraction to enable Tcl configuration files to
2442 define outputs for one or several FTDI GPIO. These outputs can then be
2443 controlled using the @command{ftdi_set_signal} command. Special signal names
2444 are reserved for nTRST, nSRST and LED (for blink) so that they, if defined,
2445 will be used for their customary purpose. Inputs can be read using the
2446 @command{ftdi_get_signal} command.
2448 To support SWD, a signal named SWD_EN must be defined. It is set to 1 when the
2449 SWD protocol is selected. When set, the adapter should route the SWDIO pin to
2450 the data input. An SWDIO_OE signal, if defined, will be set to 1 or 0 as
2451 required by the protocol, to tell the adapter to drive the data output onto
2452 the SWDIO pin or keep the SWDIO pin Hi-Z, respectively.
2454 Depending on the type of buffer attached to the FTDI GPIO, the outputs have to
2455 be controlled differently. In order to support tristateable signals such as
2456 nSRST, both a data GPIO and an output-enable GPIO can be specified for each
2457 signal. The following output buffer configurations are supported:
2459 @itemize @minus
2460 @item Push-pull with one FTDI output as (non-)inverted data line
2461 @item Open drain with one FTDI output as (non-)inverted output-enable
2462 @item Tristate with one FTDI output as (non-)inverted data line and another
2463 FTDI output as (non-)inverted output-enable
2464 @item Unbuffered, using the FTDI GPIO as a tristate output directly by
2465 switching data and direction as necessary
2466 @end itemize
2468 These interfaces have several commands, used to configure the driver
2469 before initializing the JTAG scan chain:
2471 @deffn {Config Command} {ftdi_vid_pid} [vid pid]+
2472 The vendor ID and product ID of the adapter. Up to eight
2473 [@var{vid}, @var{pid}] pairs may be given, e.g.
2474 @example
2475 ftdi_vid_pid 0x0403 0xcff8 0x15ba 0x0003
2476 @end example
2477 @end deffn
2479 @deffn {Config Command} {ftdi_device_desc} description
2480 Provides the USB device description (the @emph{iProduct string})
2481 of the adapter. If not specified, the device description is ignored
2482 during device selection.
2483 @end deffn
2485 @deffn {Config Command} {ftdi_serial} serial-number
2486 Specifies the @var{serial-number} of the adapter to use,
2487 in case the vendor provides unique IDs and more than one adapter
2488 is connected to the host.
2489 If not specified, serial numbers are not considered.
2490 (Note that USB serial numbers can be arbitrary Unicode strings,
2491 and are not restricted to containing only decimal digits.)
2492 @end deffn
2494 @deffn {Config Command} {ftdi_location} <bus>:<port>[,<port>]...
2495 Specifies the physical USB port of the adapter to use. The path
2496 roots at @var{bus} and walks down the physical ports, with each
2497 @var{port} option specifying a deeper level in the bus topology, the last
2498 @var{port} denoting where the target adapter is actually plugged.
2499 The USB bus topology can be queried with the command @emph{lsusb -t}.
2501 This command is only available if your libusb1 is at least version 1.0.16.
2502 @end deffn
2504 @deffn {Config Command} {ftdi_channel} channel
2505 Selects the channel of the FTDI device to use for MPSSE operations. Most
2506 adapters use the default, channel 0, but there are exceptions.
2507 @end deffn
2509 @deffn {Config Command} {ftdi_layout_init} data direction
2510 Specifies the initial values of the FTDI GPIO data and direction registers.
2511 Each value is a 16-bit number corresponding to the concatenation of the high
2512 and low FTDI GPIO registers. The values should be selected based on the
2513 schematics of the adapter, such that all signals are set to safe levels with
2514 minimal impact on the target system. Avoid floating inputs, conflicting outputs
2515 and initially asserted reset signals.
2516 @end deffn
2518 @deffn {Config Command} {ftdi_layout_signal} name [@option{-data}|@option{-ndata} data_mask] [@option{-input}|@option{-ninput} input_mask] [@option{-oe}|@option{-noe} oe_mask] [@option{-alias}|@option{-nalias} name]
2519 Creates a signal with the specified @var{name}, controlled by one or more FTDI
2520 GPIO pins via a range of possible buffer connections. The masks are FTDI GPIO
2521 register bitmasks to tell the driver the connection and type of the output
2522 buffer driving the respective signal. @var{data_mask} is the bitmask for the
2523 pin(s) connected to the data input of the output buffer. @option{-ndata} is
2524 used with inverting data inputs and @option{-data} with non-inverting inputs.
2525 The @option{-oe} (or @option{-noe}) option tells where the output-enable (or
2526 not-output-enable) input to the output buffer is connected. The options
2527 @option{-input} and @option{-ninput} specify the bitmask for pins to be read
2528 with the method @command{ftdi_get_signal}.
2530 Both @var{data_mask} and @var{oe_mask} need not be specified. For example, a
2531 simple open-collector transistor driver would be specified with @option{-oe}
2532 only. In that case the signal can only be set to drive low or to Hi-Z and the
2533 driver will complain if the signal is set to drive high. Which means that if
2534 it's a reset signal, @command{reset_config} must be specified as
2535 @option{srst_open_drain}, not @option{srst_push_pull}.
2537 A special case is provided when @option{-data} and @option{-oe} is set to the
2538 same bitmask. Then the FTDI pin is considered being connected straight to the
2539 target without any buffer. The FTDI pin is then switched between output and
2540 input as necessary to provide the full set of low, high and Hi-Z
2541 characteristics. In all other cases, the pins specified in a signal definition
2542 are always driven by the FTDI.
2544 If @option{-alias} or @option{-nalias} is used, the signal is created
2545 identical (or with data inverted) to an already specified signal
2546 @var{name}.
2547 @end deffn
2549 @deffn {Command} {ftdi_set_signal} name @option{0}|@option{1}|@option{z}
2550 Set a previously defined signal to the specified level.
2551 @itemize @minus
2552 @item @option{0}, drive low
2553 @item @option{1}, drive high
2554 @item @option{z}, set to high-impedance
2555 @end itemize
2556 @end deffn
2558 @deffn {Command} {ftdi_get_signal} name
2559 Get the value of a previously defined signal.
2560 @end deffn
2562 @deffn {Command} {ftdi_tdo_sample_edge} @option{rising}|@option{falling}
2563 Configure TCK edge at which the adapter samples the value of the TDO signal
2565 Due to signal propagation delays, sampling TDO on rising TCK can become quite
2566 peculiar at high JTAG clock speeds. However, FTDI chips offer a possibility to sample
2567 TDO on falling edge of TCK. With some board/adapter configurations, this may increase
2568 stability at higher JTAG clocks.
2569 @itemize @minus
2570 @item @option{rising}, sample TDO on rising edge of TCK - this is the default
2571 @item @option{falling}, sample TDO on falling edge of TCK
2572 @end itemize
2573 @end deffn
2575 For example adapter definitions, see the configuration files shipped in the
2576 @file{interface/ftdi} directory.
2578 @end deffn
2580 @deffn {Interface Driver} {ft232r}
2581 This driver is implementing synchronous bitbang mode of an FTDI FT232R
2582 USB UART bridge IC.
2584 List of connections (pin numbers for SSOP):
2585 @itemize @minus
2586 @item RXD(5) - TDI
2587 @item TXD(1) - TCK
2588 @item RTS(3) - TDO
2589 @item CTS(11) - TMS
2590 @item DTR(2) - TRST
2591 @item DCD(10) - SRST
2592 @end itemize
2594 These interfaces have several commands, used to configure the driver
2595 before initializing the JTAG scan chain:
2597 @deffn {Config Command} {ft232r_vid_pid} @var{vid} @var{pid}
2598 The vendor ID and product ID of the adapter. If not specified, default
2599 0x0403:0x6001 is used.
2600 @end deffn
2602 @deffn {Config Command} {ft232r_serial_desc} @var{serial}
2603 Specifies the @var{serial} of the adapter to use, in case the
2604 vendor provides unique IDs and more than one adapter is connected to
2605 the host. If not specified, serial numbers are not considered.
2606 @end deffn
2608 @end deffn
2610 @deffn {Interface Driver} {remote_bitbang}
2611 Drive JTAG from a remote process. This sets up a UNIX or TCP socket connection
2612 with a remote process and sends ASCII encoded bitbang requests to that process
2613 instead of directly driving JTAG.
2615 The remote_bitbang driver is useful for debugging software running on
2616 processors which are being simulated.
2618 @deffn {Config Command} {remote_bitbang_port} number
2619 Specifies the TCP port of the remote process to connect to or 0 to use UNIX
2620 sockets instead of TCP.
2621 @end deffn
2623 @deffn {Config Command} {remote_bitbang_host} hostname
2624 Specifies the hostname of the remote process to connect to using TCP, or the
2625 name of the UNIX socket to use if remote_bitbang_port is 0.
2626 @end deffn
2628 For example, to connect remotely via TCP to the host foobar you might have
2629 something like:
2631 @example
2632 interface remote_bitbang
2633 remote_bitbang_port 3335
2634 remote_bitbang_host foobar
2635 @end example
2637 To connect to another process running locally via UNIX sockets with socket
2638 named mysocket:
2640 @example
2641 interface remote_bitbang
2642 remote_bitbang_port 0
2643 remote_bitbang_host mysocket
2644 @end example
2645 @end deffn
2647 @deffn {Interface Driver} {usb_blaster}
2648 USB JTAG/USB-Blaster compatibles over one of the userspace libraries
2649 for FTDI chips. These interfaces have several commands, used to
2650 configure the driver before initializing the JTAG scan chain:
2652 @deffn {Config Command} {usb_blaster_device_desc} description
2653 Provides the USB device description (the @emph{iProduct string})
2654 of the FTDI FT245 device. If not
2655 specified, the FTDI default value is used. This setting is only valid
2656 if compiled with FTD2XX support.
2657 @end deffn
2659 @deffn {Config Command} {usb_blaster_vid_pid} vid pid
2660 The vendor ID and product ID of the FTDI FT245 device. If not specified,
2661 default values are used.
2662 Currently, only one @var{vid}, @var{pid} pair may be given, e.g. for
2663 Altera USB-Blaster (default):
2664 @example
2665 usb_blaster_vid_pid 0x09FB 0x6001
2666 @end example
2667 The following VID/PID is for Kolja Waschk's USB JTAG:
2668 @example
2669 usb_blaster_vid_pid 0x16C0 0x06AD
2670 @end example
2671 @end deffn
2673 @deffn {Command} {usb_blaster_pin} (@option{pin6}|@option{pin8}) (@option{0}|@option{1}|@option{s}|@option{t})
2674 Sets the state or function of the unused GPIO pins on USB-Blasters
2675 (pins 6 and 8 on the female JTAG header). These pins can be used as
2676 SRST and/or TRST provided the appropriate connections are made on the
2677 target board.
2679 For example, to use pin 6 as SRST:
2680 @example
2681 usb_blaster_pin pin6 s
2682 reset_config srst_only
2683 @end example
2684 @end deffn
2686 @deffn {Command} {usb_blaster_lowlevel_driver} (@option{ftdi}|@option{ublast2})
2687 Chooses the low level access method for the adapter. If not specified,
2688 @option{ftdi} is selected unless it wasn't enabled during the
2689 configure stage. USB-Blaster II needs @option{ublast2}.
2690 @end deffn
2692 @deffn {Command} {usb_blaster_firmware} @var{path}
2693 This command specifies @var{path} to access USB-Blaster II firmware
2694 image. To be used with USB-Blaster II only.
2695 @end deffn
2697 @end deffn
2699 @deffn {Interface Driver} {gw16012}
2700 Gateworks GW16012 JTAG programmer.
2701 This has one driver-specific command:
2703 @deffn {Config Command} {parport_port} [port_number]
2704 Display either the address of the I/O port
2705 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2706 If a parameter is provided, first switch to use that port.
2707 This is a write-once setting.
2708 @end deffn
2709 @end deffn
2711 @deffn {Interface Driver} {jlink}
2712 SEGGER J-Link family of USB adapters. It currently supports JTAG and SWD
2713 transports.
2715 @quotation Compatibility Note
2716 SEGGER released many firmware versions for the many hardware versions they
2717 produced. OpenOCD was extensively tested and intended to run on all of them,
2718 but some combinations were reported as incompatible. As a general
2719 recommendation, it is advisable to use the latest firmware version
2720 available for each hardware version. However the current V8 is a moving
2721 target, and SEGGER firmware versions released after the OpenOCD was
2722 released may not be compatible. In such cases it is recommended to
2723 revert to the last known functional version. For 0.5.0, this is from
2724 "Feb 8 2012 14:30:39", packed with 4.42c. For 0.6.0, the last known
2725 version is from "May 3 2012 18:36:22", packed with 4.46f.
2726 @end quotation
2728 @deffn {Command} {jlink hwstatus}
2729 Display various hardware related information, for example target voltage and pin
2730 states.
2731 @end deffn
2732 @deffn {Command} {jlink freemem}
2733 Display free device internal memory.
2734 @end deffn
2735 @deffn {Command} {jlink jtag} [@option{2}|@option{3}]
2736 Set the JTAG command version to be used. Without argument, show the actual JTAG
2737 command version.
2738 @end deffn
2739 @deffn {Command} {jlink config}
2740 Display the device configuration.
2741 @end deffn
2742 @deffn {Command} {jlink config targetpower} [@option{on}|@option{off}]
2743 Set the target power state on JTAG-pin 19. Without argument, show the target
2744 power state.
2745 @end deffn
2746 @deffn {Command} {jlink config mac} [@option{ff:ff:ff:ff:ff:ff}]
2747 Set the MAC address of the device. Without argument, show the MAC address.
2748 @end deffn
2749 @deffn {Command} {jlink config ip} [@option{A.B.C.D}(@option{/E}|@option{F.G.H.I})]
2750 Set the IP configuration of the device, where A.B.C.D is the IP address, E the
2751 bit of the subnet mask and F.G.H.I the subnet mask. Without arguments, show the
2752 IP configuration.
2753 @end deffn
2754 @deffn {Command} {jlink config usb} [@option{0} to @option{3}]
2755 Set the USB address of the device. This will also change the USB Product ID
2756 (PID) of the device. Without argument, show the USB address.
2757 @end deffn
2758 @deffn {Command} {jlink config reset}
2759 Reset the current configuration.
2760 @end deffn
2761 @deffn {Command} {jlink config write}
2762 Write the current configuration to the internal persistent storage.
2763 @end deffn
2764 @deffn {Command} {jlink emucom write <channel> <data>}
2765 Write data to an EMUCOM channel. The data needs to be encoded as hexadecimal
2766 pairs.
2768 The following example shows how to write the three bytes 0xaa, 0x0b and 0x23 to
2769 the EMUCOM channel 0x10:
2770 @example
2771 > jlink emucom write 0x10 aa0b23
2772 @end example
2773 @end deffn
2774 @deffn {Command} {jlink emucom read <channel> <length>}
2775 Read data from an EMUCOM channel. The read data is encoded as hexadecimal
2776 pairs.
2778 The following example shows how to read 4 bytes from the EMUCOM channel 0x0:
2779 @example
2780 > jlink emucom read 0x0 4
2781 77a90000
2782 @end example
2783 @end deffn
2784 @deffn {Config} {jlink usb} <@option{0} to @option{3}>
2785 Set the USB address of the interface, in case more than one adapter is connected
2786 to the host. If not specified, USB addresses are not considered. Device
2787 selection via USB address is deprecated and the serial number should be used
2788 instead.
2790 As a configuration command, it can be used only before 'init'.
2791 @end deffn
2792 @deffn {Config} {jlink serial} <serial number>
2793 Set the serial number of the interface, in case more than one adapter is
2794 connected to the host. If not specified, serial numbers are not considered.
2796 As a configuration command, it can be used only before 'init'.
2797 @end deffn
2798 @end deffn
2800 @deffn {Interface Driver} {kitprog}
2801 This driver is for Cypress Semiconductor's KitProg adapters. The KitProg is an
2802 SWD-only adapter that is designed to be used with Cypress's PSoC and PRoC device
2803 families, but it is possible to use it with some other devices. If you are using
2804 this adapter with a PSoC or a PRoC, you may need to add
2805 @command{kitprog_init_acquire_psoc} or @command{kitprog acquire_psoc} to your
2806 configuration script.
2808 Note that this driver is for the proprietary KitProg protocol, not the CMSIS-DAP
2809 mode introduced in firmware 2.14. If the KitProg is in CMSIS-DAP mode, it cannot
2810 be used with this driver, and must either be used with the cmsis-dap driver or
2811 switched back to KitProg mode. See the Cypress KitProg User Guide for
2812 instructions on how to switch KitProg modes.
2814 Known limitations:
2815 @itemize @bullet
2816 @item The frequency of SWCLK cannot be configured, and varies between 1.6 MHz
2817 and 2.7 MHz.
2818 @item For firmware versions below 2.14, "JTAG to SWD" sequences are replaced by
2819 "SWD line reset" in the driver. This is for two reasons. First, the KitProg does
2820 not support sending arbitrary SWD sequences, and only firmware 2.14 and later
2821 implement both "JTAG to SWD" and "SWD line reset" in firmware. Earlier firmware
2822 versions only implement "SWD line reset". Second, due to a firmware quirk, an
2823 SWD sequence must be sent after every target reset in order to re-establish
2824 communications with the target.
2825 @item Due in part to the limitation above, KitProg devices with firmware below
2826 version 2.14 will need to use @command{kitprog_init_acquire_psoc} in order to
2827 communicate with PSoC 5LP devices. This is because, assuming debug is not
2828 disabled on the PSoC, the PSoC 5LP needs its JTAG interface switched to SWD
2829 mode before communication can begin, but prior to firmware 2.14, "JTAG to SWD"
2830 could only be sent with an acquisition sequence.
2831 @end itemize
2833 @deffn {Config Command} {kitprog_init_acquire_psoc}
2834 Indicate that a PSoC acquisition sequence needs to be run during adapter init.
2835 Please be aware that the acquisition sequence hard-resets the target.
2836 @end deffn
2838 @deffn {Config Command} {kitprog_serial} serial
2839 Select a KitProg device by its @var{serial}. If left unspecified, the first
2840 device detected by OpenOCD will be used.
2841 @end deffn
2843 @deffn {Command} {kitprog acquire_psoc}
2844 Run a PSoC acquisition sequence immediately. Typically, this should not be used
2845 outside of the target-specific configuration scripts since it hard-resets the
2846 target as a side-effect.
2847 This is necessary for "reset halt" on some PSoC 4 series devices.
2848 @end deffn
2850 @deffn {Command} {kitprog info}
2851 Display various adapter information, such as the hardware version, firmware
2852 version, and target voltage.
2853 @end deffn
2854 @end deffn
2856 @deffn {Interface Driver} {parport}
2857 Supports PC parallel port bit-banging cables:
2858 Wigglers, PLD download cable, and more.
2859 These interfaces have several commands, used to configure the driver
2860 before initializing the JTAG scan chain:
2862 @deffn {Config Command} {parport_cable} name
2863 Set the layout of the parallel port cable used to connect to the target.
2864 This is a write-once setting.
2865 Currently valid cable @var{name} values include:
2867 @itemize @minus
2868 @item @b{altium} Altium Universal JTAG cable.
2869 @item @b{arm-jtag} Same as original wiggler except SRST and
2870 TRST connections reversed and TRST is also inverted.
2871 @item @b{chameleon} The Amontec Chameleon's CPLD when operated
2872 in configuration mode. This is only used to
2873 program the Chameleon itself, not a connected target.
2874 @item @b{dlc5} The Xilinx Parallel cable III.
2875 @item @b{flashlink} The ST Parallel cable.
2876 @item @b{lattice} Lattice ispDOWNLOAD Cable
2877 @item @b{old_amt_wiggler} The Wiggler configuration that comes with
2878 some versions of
2879 Amontec's Chameleon Programmer. The new version available from
2880 the website uses the original Wiggler layout ('@var{wiggler}')
2881 @item @b{triton} The parallel port adapter found on the
2882 ``Karo Triton 1 Development Board''.
2883 This is also the layout used by the HollyGates design
2884 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
2885 @item @b{wiggler} The original Wiggler layout, also supported by
2886 several clones, such as the Olimex ARM-JTAG
2887 @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
2888 @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
2889 @end itemize
2890 @end deffn
2892 @deffn {Config Command} {parport_port} [port_number]
2893 Display either the address of the I/O port
2894 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2895 If a parameter is provided, first switch to use that port.
2896 This is a write-once setting.
2898 When using PPDEV to access the parallel port, use the number of the parallel port:
2899 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
2900 you may encounter a problem.
2901 @end deffn
2903 @deffn Command {parport_toggling_time} [nanoseconds]
2904 Displays how many nanoseconds the hardware needs to toggle TCK;
2905 the parport driver uses this value to obey the
2906 @command{adapter_khz} configuration.
2907 When the optional @var{nanoseconds} parameter is given,
2908 that setting is changed before displaying the current value.
2910 The default setting should work reasonably well on commodity PC hardware.
2911 However, you may want to calibrate for your specific hardware.
2912 @quotation Tip
2913 To measure the toggling time with a logic analyzer or a digital storage
2914 oscilloscope, follow the procedure below:
2915 @example
2916 > parport_toggling_time 1000
2917 > adapter_khz 500
2918 @end example
2919 This sets the maximum JTAG clock speed of the hardware, but
2920 the actual speed probably deviates from the requested 500 kHz.
2921 Now, measure the time between the two closest spaced TCK transitions.
2922 You can use @command{runtest 1000} or something similar to generate a
2923 large set of samples.
2924 Update the setting to match your measurement:
2925 @example
2926 > parport_toggling_time <measured nanoseconds>
2927 @end example
2928 Now the clock speed will be a better match for @command{adapter_khz rate}
2929 commands given in OpenOCD scripts and event handlers.
2931 You can do something similar with many digital multimeters, but note
2932 that you'll probably need to run the clock continuously for several
2933 seconds before it decides what clock rate to show. Adjust the
2934 toggling time up or down until the measured clock rate is a good
2935 match for the adapter_khz rate you specified; be conservative.
2936 @end quotation
2937 @end deffn
2939 @deffn {Config Command} {parport_write_on_exit} (@option{on}|@option{off})
2940 This will configure the parallel driver to write a known
2941 cable-specific value to the parallel interface on exiting OpenOCD.
2942 @end deffn
2944 For example, the interface configuration file for a
2945 classic ``Wiggler'' cable on LPT2 might look something like this:
2947 @example
2948 interface parport
2949 parport_port 0x278
2950 parport_cable wiggler
2951 @end example
2952 @end deffn
2954 @deffn {Interface Driver} {presto}
2955 ASIX PRESTO USB JTAG programmer.
2956 @deffn {Config Command} {presto_serial} serial_string
2957 Configures the USB serial number of the Presto device to use.
2958 @end deffn
2959 @end deffn
2961 @deffn {Interface Driver} {rlink}
2962 Raisonance RLink USB adapter
2963 @end deffn
2965 @deffn {Interface Driver} {usbprog}
2966 usbprog is a freely programmable USB adapter.
2967 @end deffn
2969 @deffn {Interface Driver} {vsllink}
2970 vsllink is part of Versaloon which is a versatile USB programmer.
2972 @quotation Note
2973 This defines quite a few driver-specific commands,
2974 which are not currently documented here.
2975 @end quotation
2976 @end deffn
2978 @anchor{hla_interface}
2979 @deffn {Interface Driver} {hla}
2980 This is a driver that supports multiple High Level Adapters.
2981 This type of adapter does not expose some of the lower level api's
2982 that OpenOCD would normally use to access the target.
2984 Currently supported adapters include the ST ST-LINK and TI ICDI.
2985 ST-LINK firmware version >= V2.J21.S4 recommended due to issues with earlier
2986 versions of firmware where serial number is reset after first use. Suggest
2987 using ST firmware update utility to upgrade ST-LINK firmware even if current
2988 version reported is V2.J21.S4.
2990 @deffn {Config Command} {hla_device_desc} description
2991 Currently Not Supported.
2992 @end deffn
2994 @deffn {Config Command} {hla_serial} serial
2995 Specifies the serial number of the adapter.
2996 @end deffn
2998 @deffn {Config Command} {hla_layout} (@option{stlink}|@option{icdi})
2999 Specifies the adapter layout to use.
3000 @end deffn
3002 @deffn {Config Command} {hla_vid_pid} [vid pid]+
3003 Pairs of vendor IDs and product IDs of the device.
3004 @end deffn
3006 @deffn {Command} {hla_command} command
3007 Execute a custom adapter-specific command. The @var{command} string is
3008 passed as is to the underlying adapter layout handler.
3009 @end deffn
3010 @end deffn
3012 @deffn {Interface Driver} {opendous}
3013 opendous-jtag is a freely programmable USB adapter.
3014 @end deffn
3016 @deffn {Interface Driver} {ulink}
3017 This is the Keil ULINK v1 JTAG debugger.
3018 @end deffn
3020 @deffn {Interface Driver} {ZY1000}
3021 This is the Zylin ZY1000 JTAG debugger.
3022 @end deffn
3024 @quotation Note
3025 This defines some driver-specific commands,
3026 which are not currently documented here.
3027 @end quotation
3029 @deffn Command power [@option{on}|@option{off}]
3030 Turn power switch to target on/off.
3031 No arguments: print status.
3032 @end deffn
3034 @deffn {Interface Driver} {bcm2835gpio}
3035 This SoC is present in Raspberry Pi which is a cheap single-board computer
3036 exposing some GPIOs on its expansion header.
3038 The driver accesses memory-mapped GPIO peripheral registers directly
3039 for maximum performance, but the only possible race condition is for
3040 the pins' modes/muxing (which is highly unlikely), so it should be
3041 able to coexist nicely with both sysfs bitbanging and various
3042 peripherals' kernel drivers. The driver restores the previous
3043 configuration on exit.
3045 See @file{interface/raspberrypi-native.cfg} for a sample config and
3046 pinout.
3048 @end deffn
3050 @deffn {Interface Driver} {imx_gpio}
3051 i.MX SoC is present in many community boards. Wandboard is an example
3052 of the one which is most popular.
3054 This driver is mostly the same as bcm2835gpio.
3056 See @file{interface/imx-native.cfg} for a sample config and
3057 pinout.
3059 @end deffn
3062 @deffn {Interface Driver} {openjtag}
3063 OpenJTAG compatible USB adapter.
3064 This defines some driver-specific commands:
3066 @deffn {Config Command} {openjtag_variant} variant
3067 Specifies the variant of the OpenJTAG adapter (see @uref{http://www.openjtag.org/}).
3068 Currently valid @var{variant} values include:
3070 @itemize @minus
3071 @item @b{standard} Standard variant (default).
3072 @item @b{cy7c65215} Cypress CY7C65215 Dual Channel USB-Serial Bridge Controller
3073 (see @uref{http://www.cypress.com/?rID=82870}).
3074 @end itemize
3075 @end deffn
3077 @deffn {Config Command} {openjtag_device_desc} string
3078 The USB device description string of the adapter.
3079 This value is only used with the standard variant.
3080 @end deffn
3081 @end deffn
3083 @section Transport Configuration
3084 @cindex Transport
3085 As noted earlier, depending on the version of OpenOCD you use,
3086 and the debug adapter you are using,
3087 several transports may be available to
3088 communicate with debug targets (or perhaps to program flash memory).
3089 @deffn Command {transport list}
3090 displays the names of the transports supported by this
3091 version of OpenOCD.
3092 @end deffn
3094 @deffn Command {transport select} @option{transport_name}
3095 Select which of the supported transports to use in this OpenOCD session.
3097 When invoked with @option{transport_name}, attempts to select the named
3098 transport. The transport must be supported by the debug adapter
3099 hardware and by the version of OpenOCD you are using (including the
3100 adapter's driver).
3102 If no transport has been selected and no @option{transport_name} is
3103 provided, @command{transport select} auto-selects the first transport
3104 supported by the debug adapter.
3106 @command{transport select} always returns the name of the session's selected
3107 transport, if any.
3108 @end deffn
3110 @subsection JTAG Transport
3111 @cindex JTAG
3112 JTAG is the original transport supported by OpenOCD, and most
3113 of the OpenOCD commands support it.
3114 JTAG transports expose a chain of one or more Test Access Points (TAPs),
3115 each of which must be explicitly declared.
3116 JTAG supports both debugging and boundary scan testing.
3117 Flash programming support is built on top of debug support.
3119 JTAG transport is selected with the command @command{transport select
3120 jtag}. Unless your adapter uses @ref{hla_interface,the hla interface
3121 driver}, in which case the command is @command{transport select
3122 hla_jtag}.
3124 @subsection SWD Transport
3125 @cindex SWD
3126 @cindex Serial Wire Debug
3127 SWD (Serial Wire Debug) is an ARM-specific transport which exposes one
3128 Debug Access Point (DAP, which must be explicitly declared.
3129 (SWD uses fewer signal wires than JTAG.)
3130 SWD is debug-oriented, and does not support boundary scan testing.
3131 Flash programming support is built on top of debug support.
3132 (Some processors support both JTAG and SWD.)
3134 SWD transport is selected with the command @command{transport select
3135 swd}. Unless your adapter uses @ref{hla_interface,the hla interface
3136 driver}, in which case the command is @command{transport select
3137 hla_swd}.
3139 @deffn Command {swd newdap} ...
3140 Declares a single DAP which uses SWD transport.
3141 Parameters are currently the same as "jtag newtap" but this is
3142 expected to change.
3143 @end deffn
3144 @deffn Command {swd wcr trn prescale}
3145 Updates TRN (turnaround delay) and prescaling.fields of the
3146 Wire Control Register (WCR).
3147 No parameters: displays current settings.
3148 @end deffn
3150 @subsection SPI Transport
3151 @cindex SPI
3152 @cindex Serial Peripheral Interface
3153 The Serial Peripheral Interface (SPI) is a general purpose transport
3154 which uses four wire signaling. Some processors use it as part of a
3155 solution for flash programming.
3157 @anchor{jtagspeed}
3158 @section JTAG Speed
3159 JTAG clock setup is part of system setup.
3160 It @emph{does not belong with interface setup} since any interface
3161 only knows a few of the constraints for the JTAG clock speed.
3162 Sometimes the JTAG speed is
3163 changed during the target initialization process: (1) slow at
3164 reset, (2) program the CPU clocks, (3) run fast.
3165 Both the "slow" and "fast" clock rates are functions of the
3166 oscillators used, the chip, the board design, and sometimes
3167 power management software that may be active.
3169 The speed used during reset, and the scan chain verification which
3170 follows reset, can be adjusted using a @code{reset-start}
3171 target event handler.
3172 It can then be reconfigured to a faster speed by a
3173 @code{reset-init} target event handler after it reprograms those
3174 CPU clocks, or manually (if something else, such as a boot loader,
3175 sets up those clocks).
3176 @xref{targetevents,,Target Events}.
3177 When the initial low JTAG speed is a chip characteristic, perhaps
3178 because of a required oscillator speed, provide such a handler
3179 in the target config file.
3180 When that speed is a function of a board-specific characteristic
3181 such as which speed oscillator is used, it belongs in the board
3182 config file instead.
3183 In both cases it's safest to also set the initial JTAG clock rate
3184 to that same slow speed, so that OpenOCD never starts up using a
3185 clock speed that's faster than the scan chain can support.
3187 @example
3188 jtag_rclk 3000
3189 $_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
3190 @end example
3192 If your system supports adaptive clocking (RTCK), configuring
3193 JTAG to use that is probably the most robust approach.
3194 However, it introduces delays to synchronize clocks; so it
3195 may not be the fastest solution.
3197 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
3198 instead of @command{adapter_khz}, but only for (ARM) cores and boards
3199 which support adaptive clocking.
3201 @deffn {Command} adapter_khz max_speed_kHz
3202 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
3203 JTAG interfaces usually support a limited number of
3204 speeds. The speed actually used won't be faster
3205 than the speed specified.
3207 Chip data sheets generally include a top JTAG clock rate.
3208 The actual rate is often a function of a CPU core clock,
3209 and is normally less than that peak rate.
3210 For example, most ARM cores accept at most one sixth of the CPU clock.
3212 Speed 0 (khz) selects RTCK method.
3213 @xref{faqrtck,,FAQ RTCK}.
3214 If your system uses RTCK, you won't need to change the
3215 JTAG clocking after setup.
3216 Not all interfaces, boards, or targets support ``rtck''.
3217 If the interface device can not
3218 support it, an error is returned when you try to use RTCK.
3219 @end deffn
3221 @defun jtag_rclk fallback_speed_kHz
3222 @cindex adaptive clocking
3223 @cindex RTCK
3224 This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
3225 If that fails (maybe the interface, board, or target doesn't
3226 support it), falls back to the specified frequency.
3227 @example
3228 # Fall back to 3mhz if RTCK is not supported
3229 jtag_rclk 3000
3230 @end example
3231 @end defun
3233 @node Reset Configuration
3234 @chapter Reset Configuration
3235 @cindex Reset Configuration
3237 Every system configuration may require a different reset
3238 configuration. This can also be quite confusing.
3239 Resets also interact with @var{reset-init} event handlers,
3240 which do things like setting up clocks and DRAM, and
3241 JTAG clock rates. (@xref{jtagspeed,,JTAG Speed}.)
3242 They can also interact with JTAG routers.
3243 Please see the various board files for examples.
3245 @quotation Note
3246 To maintainers and integrators:
3247 Reset configuration touches several things at once.
3248 Normally the board configuration file
3249 should define it and assume that the JTAG adapter supports
3250 everything that's wired up to the board's JTAG connector.
3252 However, the target configuration file could also make note
3253 of something the silicon vendor has done inside the chip,
3254 which will be true for most (or all) boards using that chip.
3255 And when the JTAG adapter doesn't support everything, the
3256 user configuration file will need to override parts of
3257 the reset configuration provided by other files.
3258 @end quotation
3260 @section Types of Reset
3262 There are many kinds of reset possible through JTAG, but
3263 they may not all work with a given board and adapter.
3264 That's part of why reset configuration can be error prone.
3266 @itemize @bullet
3267 @item
3268 @emph{System Reset} ... the @emph{SRST} hardware signal
3269 resets all chips connected to the JTAG adapter, such as processors,
3270 power management chips, and I/O controllers. Normally resets triggered
3271 with this signal behave exactly like pressing a RESET button.
3272 @item
3273 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
3274 just the TAP controllers connected to the JTAG adapter.
3275 Such resets should not be visible to the rest of the system; resetting a
3276 device's TAP controller just puts that controller into a known state.
3277 @item
3278 @emph{Emulation Reset} ... many devices can be reset through JTAG
3279 commands. These resets are often distinguishable from system
3280 resets, either explicitly (a "reset reason" register says so)
3281 or implicitly (not all parts of the chip get reset).
3282 @item
3283 @emph{Other Resets} ... system-on-chip devices often support
3284 several other types of reset.
3285 You may need to arrange that a watchdog timer stops
3286 while debugging, preventing a watchdog reset.
3287 There may be individual module resets.
3288 @end itemize
3290 In the best case, OpenOCD can hold SRST, then reset
3291 the TAPs via TRST and send commands through JTAG to halt the
3292 CPU at the reset vector before the 1st instruction is executed.
3293 Then when it finally releases the SRST signal, the system is
3294 halted under debugger control before any code has executed.
3295 This is the behavior required to support the @command{reset halt}
3296 and @command{reset init} commands; after @command{reset init} a
3297 board-specific script might do things like setting up DRAM.
3298 (@xref{resetcommand,,Reset Command}.)
3300 @anchor{srstandtrstissues}
3301 @section SRST and TRST Issues
3303 Because SRST and TRST are hardware signals, they can have a
3304 variety of system-specific constraints. Some of the most
3305 common issues are:
3307 @itemize @bullet
3309 @item @emph{Signal not available} ... Some boards don't wire
3310 SRST or TRST to the JTAG connector. Some JTAG adapters don't
3311 support such signals even if they are wired up.
3312 Use the @command{reset_config} @var{signals} options to say
3313 when either of those signals is not connected.
3314 When SRST is not available, your code might not be able to rely
3315 on controllers having been fully reset during code startup.
3316 Missing TRST is not a problem, since JTAG-level resets can
3317 be triggered using with TMS signaling.
3319 @item @emph{Signals shorted} ... Sometimes a chip, board, or
3320 adapter will connect SRST to TRST, instead of keeping them separate.
3321 Use the @command{reset_config} @var{combination} options to say
3322 when those signals aren't properly independent.
3324 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
3325 delay circuit, reset supervisor, or on-chip features can extend
3326 the effect of a JTAG adapter's reset for some time after the adapter
3327 stops issuing the reset. For example, there may be chip or board
3328 requirements that all reset pulses last for at least a
3329 certain amount of time; and reset buttons commonly have
3330 hardware debouncing.
3331 Use the @command{adapter_nsrst_delay} and @command{jtag_ntrst_delay}
3332 commands to say when extra delays are needed.
3334 @item @emph{Drive type} ... Reset lines often have a pullup
3335 resistor, letting the JTAG interface treat them as open-drain
3336 signals. But that's not a requirement, so the adapter may need
3337 to use push/pull output drivers.
3338 Also, with weak pullups it may be advisable to drive
3339 signals to both levels (push/pull) to minimize rise times.
3340 Use the @command{reset_config} @var{trst_type} and
3341 @var{srst_type} parameters to say how to drive reset signals.
3343 @item @emph{Special initialization} ... Targets sometimes need
3344 special JTAG initialization sequences to handle chip-specific
3345 issues (not limited to errata).
3346 For example, certain JTAG commands might need to be issued while
3347 the system as a whole is in a reset state (SRST active)
3348 but the JTAG scan chain is usable (TRST inactive).
3349 Many systems treat combined assertion of SRST and TRST as a
3350 trigger for a harder reset than SRST alone.
3351 Such custom reset handling is discussed later in this chapter.
3352 @end itemize
3354 There can also be other issues.
3355 Some devices don't fully conform to the JTAG specifications.
3356 Trivial system-specific differences are common, such as
3357 SRST and TRST using slightly different names.
3358 There are also vendors who distribute key JTAG documentation for
3359 their chips only to developers who have signed a Non-Disclosure
3360 Agreement (NDA).
3362 Sometimes there are chip-specific extensions like a requirement to use
3363 the normally-optional TRST signal (precluding use of JTAG adapters which
3364 don't pass TRST through), or needing extra steps to complete a TAP reset.
3366 In short, SRST and especially TRST handling may be very finicky,
3367 needing to cope with both architecture and board specific constraints.
3369 @section Commands for Handling Resets
3371 @deffn {Command} adapter_nsrst_assert_width milliseconds
3372 Minimum amount of time (in milliseconds) OpenOCD should wait
3373 after asserting nSRST (active-low system reset) before
3374 allowing it to be deasserted.
3375 @end deffn
3377 @deffn {Command} adapter_nsrst_delay milliseconds
3378 How long (in milliseconds) OpenOCD should wait after deasserting
3379 nSRST (active-low system reset) before starting new JTAG operations.
3380 When a board has a reset button connected to SRST line it will
3381 probably have hardware debouncing, implying you should use this.
3382 @end deffn
3384 @deffn {Command} jtag_ntrst_assert_width milliseconds
3385 Minimum amount of time (in milliseconds) OpenOCD should wait
3386 after asserting nTRST (active-low JTAG TAP reset) before
3387 allowing it to be deasserted.
3388 @end deffn
3390 @deffn {Command} jtag_ntrst_delay milliseconds
3391 How long (in milliseconds) OpenOCD should wait after deasserting
3392 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
3393 @end deffn
3395 @deffn {Command} reset_config mode_flag ...
3396 This command displays or modifies the reset configuration
3397 of your combination of JTAG board and target in target
3398 configuration scripts.
3400 Information earlier in this section describes the kind of problems
3401 the command is intended to address (@pxref{srstandtrstissues,,SRST and TRST Issues}).
3402 As a rule this command belongs only in board config files,
3403 describing issues like @emph{board doesn't connect TRST};
3404 or in user config files, addressing limitations derived
3405 from a particular combination of interface and board.
3406 (An unlikely example would be using a TRST-only adapter
3407 with a board that only wires up SRST.)
3409 The @var{mode_flag} options can be specified in any order, but only one
3410 of each type -- @var{signals}, @var{combination}, @var{gates},
3411 @var{trst_type}, @var{srst_type} and @var{connect_type}
3412 -- may be specified at a time.
3413 If you don't provide a new value for a given type, its previous
3414 value (perhaps the default) is unchanged.
3415 For example, this means that you don't need to say anything at all about
3416 TRST just to declare that if the JTAG adapter should want to drive SRST,
3417 it must explicitly be driven high (@option{srst_push_pull}).
3419 @itemize
3420 @item
3421 @var{signals} can specify which of the reset signals are connected.
3422 For example, If the JTAG interface provides SRST, but the board doesn't
3423 connect that signal properly, then OpenOCD can't use it.
3424 Possible values are @option{none} (the default), @option{trst_only},
3425 @option{srst_only} and @option{trst_and_srst}.
3427 @quotation Tip
3428 If your board provides SRST and/or TRST through the JTAG connector,
3429 you must declare that so those signals can be used.
3430 @end quotation
3432 @item
3433 The @var{combination} is an optional value specifying broken reset
3434 signal implementations.
3435 The default behaviour if no option given is @option{separate},
3436 indicating everything behaves normally.
3437 @option{srst_pulls_trst} states that the
3438 test logic is reset together with the reset of the system (e.g. NXP
3439 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
3440 the system is reset together with the test logic (only hypothetical, I
3441 haven't seen hardware with such a bug, and can be worked around).
3442 @option{combined} implies both @option{srst_pulls_trst} and
3443 @option{trst_pulls_srst}.
3445 @item
3446 The @var{gates} tokens control flags that describe some cases where
3447 JTAG may be unavailable during reset.
3448 @option{srst_gates_jtag} (default)
3449 indicates that asserting SRST gates the
3450 JTAG clock. This means that no communication can happen on JTAG
3451 while SRST is asserted.
3452 Its converse is @option{srst_nogate}, indicating that JTAG commands
3453 can safely be issued while SRST is active.
3455 @item
3456 The @var{connect_type} tokens control flags that describe some cases where
3457 SRST is asserted while connecting to the target. @option{srst_nogate}
3458 is required to use this option.
3459 @option{connect_deassert_srst} (default)
3460 indicates that SRST will not be asserted while connecting to the target.
3461 Its converse is @option{connect_assert_srst}, indicating that SRST will
3462 be asserted before any target connection.
3463 Only some targets support this feature, STM32 and STR9 are examples.
3464 This feature is useful if you are unable to connect to your target due
3465 to incorrect options byte config or illegal program execution.
3466 @end itemize
3468 The optional @var{trst_type} and @var{srst_type} parameters allow the
3469 driver mode of each reset line to be specified. These values only affect
3470 JTAG interfaces with support for different driver modes, like the Amontec
3471 JTAGkey and JTAG Accelerator. Also, they are necessarily ignored if the
3472 relevant signal (TRST or SRST) is not connected.
3474 @itemize
3475 @item
3476 Possible @var{trst_type} driver modes for the test reset signal (TRST)
3477 are the default @option{trst_push_pull}, and @option{trst_open_drain}.
3478 Most boards connect this signal to a pulldown, so the JTAG TAPs
3479 never leave reset unless they are hooked up to a JTAG adapter.
3481 @item
3482 Possible @var{srst_type} driver modes for the system reset signal (SRST)
3483 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
3484 Most boards connect this signal to a pullup, and allow the
3485 signal to be pulled low by various events including system
3486 power-up and pressing a reset button.
3487 @end itemize
3488 @end deffn
3490 @section Custom Reset Handling
3491 @cindex events
3493 OpenOCD has several ways to help support the various reset
3494 mechanisms provided by chip and board vendors.
3495 The commands shown in the previous section give standard parameters.
3496 There are also @emph{event handlers} associated with TAPs or Targets.
3497 Those handlers are Tcl procedures you can provide, which are invoked
3498 at particular points in the reset sequence.
3500 @emph{When SRST is not an option} you must set
3501 up a @code{reset-assert} event handler for your target.
3502 For example, some JTAG adapters don't include the SRST signal;
3503 and some boards have multiple targets, and you won't always
3504 want to reset everything at once.
3506 After configuring those mechanisms, you might still
3507 find your board doesn't start up or reset correctly.
3508 For example, maybe it needs a slightly different sequence
3509 of SRST and/or TRST manipulations, because of quirks that
3510 the @command{reset_config} mechanism doesn't address;
3511 or asserting both might trigger a stronger reset, which
3512 needs special attention.
3514 Experiment with lower level operations, such as @command{jtag_reset}
3515 and the @command{jtag arp_*} operations shown here,
3516 to find a sequence of operations that works.
3517 @xref{JTAG Commands}.
3518 When you find a working sequence, it can be used to override
3519 @command{jtag_init}, which fires during OpenOCD startup
3520 (@pxref{configurationstage,,Configuration Stage});
3521 or @command{init_reset}, which fires during reset processing.
3523 You might also want to provide some project-specific reset
3524 schemes. For example, on a multi-target board the standard
3525 @command{reset} command would reset all targets, but you
3526 may need the ability to reset only one target at time and
3527 thus want to avoid using the board-wide SRST signal.
3529 @deffn {Overridable Procedure} init_reset mode
3530 This is invoked near the beginning of the @command{reset} command,
3531 usually to provide as much of a cold (power-up) reset as practical.
3532 By default it is also invoked from @command{jtag_init} if
3533 the scan chain does not respond to pure JTAG operations.
3534 The @var{mode} parameter is the parameter given to the
3535 low level reset command (@option{halt},
3536 @option{init}, or @option{run}), @option{setup},
3537 or potentially some other value.
3539 The default implementation just invokes @command{jtag arp_init-reset}.
3540 Replacements will normally build on low level JTAG
3541 operations such as @command{jtag_reset}.
3542 Operations here must not address individual TAPs
3543 (or their associated targets)
3544 until the JTAG scan chain has first been verified to work.
3546 Implementations must have verified the JTAG scan chain before
3547 they return.
3548 This is done by calling @command{jtag arp_init}
3549 (or @command{jtag arp_init-reset}).
3550 @end deffn
3552 @deffn Command {jtag arp_init}
3553 This validates the scan chain using just the four
3554 standard JTAG signals (TMS, TCK, TDI, TDO).
3555 It starts by issuing a JTAG-only reset.
3556 Then it performs checks to verify that the scan chain configuration
3557 matches the TAPs it can observe.
3558 Those checks include checking IDCODE values for each active TAP,
3559 and verifying the length of their instruction registers using
3560 TAP @code{-ircapture} and @code{-irmask} values.
3561 If these tests all pass, TAP @code{setup} events are
3562 issued to all TAPs with handlers for that event.
3563 @end deffn
3565 @deffn Command {jtag arp_init-reset}
3566 This uses TRST and SRST to try resetting
3567 everything on the JTAG scan chain
3568 (and anything else connected to SRST).
3569 It then invokes the logic of @command{jtag arp_init}.
3570 @end deffn
3573 @node TAP Declaration
3574 @chapter TAP Declaration
3575 @cindex TAP declaration
3576 @cindex TAP configuration
3578 @emph{Test Access Ports} (TAPs) are the core of JTAG.
3579 TAPs serve many roles, including:
3581 @itemize @bullet
3582 @item @b{Debug Target} A CPU TAP can be used as a GDB debug target.
3583 @item @b{Flash Programming} Some chips program the flash directly via JTAG.
3584 Others do it indirectly, making a CPU do it.
3585 @item @b{Program Download} Using the same CPU support GDB uses,
3586 you can initialize a DRAM controller, download code to DRAM, and then
3587 start running that code.
3588 @item @b{Boundary Scan} Most chips support boundary scan, which
3589 helps test for board assembly problems like solder bridges
3590 and missing connections.
3591 @end itemize
3593 OpenOCD must know about the active TAPs on your board(s).
3594 Setting up the TAPs is the core task of your configuration files.
3595 Once those TAPs are set up, you can pass their names to code
3596 which sets up CPUs and exports them as GDB targets,
3597 probes flash memory, performs low-level JTAG operations, and more.
3599 @section Scan Chains
3600 @cindex scan chain
3602 TAPs are part of a hardware @dfn{scan chain},
3603 which is a daisy chain of TAPs.
3604 They also need to be added to
3605 OpenOCD's software mirror of that hardware list,
3606 giving each member a name and associating other data with it.
3607 Simple scan chains, with a single TAP, are common in
3608 systems with a single microcontroller or microprocessor.
3609 More complex chips may have several TAPs internally.
3610 Very complex scan chains might have a dozen or more TAPs:
3611 several in one chip, more in the next, and connecting
3612 to other boards with their own chips and TAPs.
3614 You can display the list with the @command{scan_chain} command.
3615 (Don't confuse this with the list displayed by the @command{targets}
3616 command, presented in the next chapter.
3617 That only displays TAPs for CPUs which are configured as
3618 debugging targets.)
3619 Here's what the scan chain might look like for a chip more than one TAP:
3621 @verbatim
3622 TapName Enabled IdCode Expected IrLen IrCap IrMask
3623 -- ------------------ ------- ---------- ---------- ----- ----- ------
3624 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0x01 0x03
3625 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x01 0x0f
3626 2 omap5912.unknown Y 0x00000000 0x00000000 8 0x01 0x03
3627 @end verbatim
3629 OpenOCD can detect some of that information, but not all
3630 of it. @xref{autoprobing,,Autoprobing}.
3631 Unfortunately, those TAPs can't always be autoconfigured,
3632 because not all devices provide good support for that.
3633 JTAG doesn't require supporting IDCODE instructions, and
3634 chips with JTAG routers may not link TAPs into the chain
3635 until they are told to do so.
3637 The configuration mechanism currently supported by OpenOCD
3638 requires explicit configuration of all TAP devices using
3639 @command{jtag newtap} commands, as detailed later in this chapter.
3640 A command like this would declare one tap and name it @code{chip1.cpu}:
3642 @example
3643 jtag newtap chip1 cpu -irlen 4 -expected-id 0x3ba00477
3644 @end example
3646 Each target configuration file lists the TAPs provided
3647 by a given chip.
3648 Board configuration files combine all the targets on a board,
3649 and so forth.
3650 Note that @emph{the order in which TAPs are declared is very important.}
3651 That declaration order must match the order in the JTAG scan chain,
3652 both inside a single chip and between them.
3653 @xref{faqtaporder,,FAQ TAP Order}.
3655 For example, the STMicroelectronics STR912 chip has
3656 three separate TAPs@footnote{See the ST
3657 document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
3658 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
3659 @url{http://eu.st.com/stonline/products/literature/ds/13495.pdf}}.
3660 To configure those taps, @file{target/str912.cfg}
3661 includes commands something like this:
3663 @example
3664 jtag newtap str912 flash ... params ...
3665 jtag newtap str912 cpu ... params ...
3666 jtag newtap str912 bs ... params ...
3667 @end example
3669 Actual config files typically use a variable such as @code{$_CHIPNAME}
3670 instead of literals like @option{str912}, to support more than one chip
3671 of each type. @xref{Config File Guidelines}.
3673 @deffn Command {jtag names}
3674 Returns the names of all current TAPs in the scan chain.
3675 Use @command{jtag cget} or @command{jtag tapisenabled}
3676 to examine attributes and state of each TAP.
3677 @example
3678 foreach t [jtag names] @{
3679 puts [format "TAP: %s\n" $t]
3680 @}
3681 @end example
3682 @end deffn
3684 @deffn Command {scan_chain}
3685 Displays the TAPs in the scan chain configuration,
3686 and their status.
3687 The set of TAPs listed by this command is fixed by
3688 exiting the OpenOCD configuration stage,
3689 but systems with a JTAG router can
3690 enable or disable TAPs dynamically.
3691 @end deffn
3693 @c FIXME! "jtag cget" should be able to return all TAP
3694 @c attributes, like "$target_name cget" does for targets.
3696 @c Probably want "jtag eventlist", and a "tap-reset" event
3697 @c (on entry to RESET state).
3699 @section TAP Names
3700 @cindex dotted name
3702 When TAP objects are declared with @command{jtag newtap},
3703 a @dfn{dotted.name} is created for the TAP, combining the
3704 name of a module (usually a chip) and a label for the TAP.
3705 For example: @code{xilinx.tap}, @code{str912.flash},
3706 @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
3707 Many other commands use that dotted.name to manipulate or
3708 refer to the TAP. For example, CPU configuration uses the
3709 name, as does declaration of NAND or NOR flash banks.
3711 The components of a dotted name should follow ``C'' symbol
3712 name rules: start with an alphabetic character, then numbers
3713 and underscores are OK; while others (including dots!) are not.
3715 @section TAP Declaration Commands
3717 @c shouldn't this be(come) a {Config Command}?
3718 @deffn Command {jtag newtap} chipname tapname configparams...
3719 Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
3720 and configured according to the various @var{configparams}.
3722 The @var{chipname} is a symbolic name for the chip.
3723 Conventionally target config files use @code{$_CHIPNAME},
3724 defaulting to the model name given by the chip vendor but
3725 overridable.
3727 @cindex TAP naming convention
3728 The @var{tapname} reflects the role of that TAP,
3729 and should follow this convention:
3731 @itemize @bullet
3732 @item @code{bs} -- For boundary scan if this is a separate TAP;
3733 @item @code{cpu} -- The main CPU of the chip, alternatively
3734 @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
3735 @code{arm1} and @code{arm2} on chips with two ARMs, and so forth;
3736 @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
3737 @item @code{flash} -- If the chip has a flash TAP, like the str912;
3738 @item @code{jrc} -- For JTAG route controller (example: the ICEPick modules
3739 on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
3740 @item @code{tap} -- Should be used only for FPGA- or CPLD-like devices
3741 with a single TAP;
3742 @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
3743 @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
3744 For example, the Freescale i.MX31 has a SDMA (Smart DMA) with
3745 a JTAG TAP; that TAP should be named @code{sdma}.
3746 @end itemize
3748 Every TAP requires at least the following @var{configparams}:
3750 @itemize @bullet
3751 @item @code{-irlen} @var{NUMBER}
3752 @*The length in bits of the
3753 instruction register, such as 4 or 5 bits.
3754 @end itemize
3756 A TAP may also provide optional @var{configparams}:
3758 @itemize @bullet
3759 @item @code{-disable} (or @code{-enable})
3760 @*Use the @code{-disable} parameter to flag a TAP which is not
3761 linked into the scan chain after a reset using either TRST
3762 or the JTAG state machine's @sc{reset} state.
3763 You may use @code{-enable} to highlight the default state
3764 (the TAP is linked in).
3765 @xref{enablinganddisablingtaps,,Enabling and Disabling TAPs}.
3766 @item @code{-expected-id} @var{NUMBER}
3767 @*A non-zero @var{number} represents a 32-bit IDCODE
3768 which you expect to find when the scan chain is examined.
3769 These codes are not required by all JTAG devices.
3770 @emph{Repeat the option} as many times as required if more than one
3771 ID code could appear (for example, multiple versions).
3772 Specify @var{number} as zero to suppress warnings about IDCODE
3773 values that were found but not included in the list.
3775 Provide this value if at all possible, since it lets OpenOCD
3776 tell when the scan chain it sees isn't right. These values
3777 are provided in vendors' chip documentation, usually a technical
3778 reference manual. Sometimes you may need to probe the JTAG
3779 hardware to find these values.
3780 @xref{autoprobing,,Autoprobing}.
3781 @item @code{-ignore-version}
3782 @*Specify this to ignore the JTAG version field in the @code{-expected-id}
3783 option. When vendors put out multiple versions of a chip, or use the same
3784 JTAG-level ID for several largely-compatible chips, it may be more practical
3785 to ignore the version field than to update config files to handle all of
3786 the various chip IDs. The version field is defined as bit 28-31 of the IDCODE.
3787 @item @code{-ircapture} @var{NUMBER}
3788 @*The bit pattern loaded by the TAP into the JTAG shift register
3789 on entry to the @sc{ircapture} state, such as 0x01.
3790 JTAG requires the two LSBs of this value to be 01.
3791 By default, @code{-ircapture} and @code{-irmask} are set
3792 up to verify that two-bit value. You may provide
3793 additional bits if you know them, or indicate that
3794 a TAP doesn't conform to the JTAG specification.
3795 @item @code{-irmask} @var{NUMBER}
3796 @*A mask used with @code{-ircapture}
3797 to verify that instruction scans work correctly.
3798 Such scans are not used by OpenOCD except to verify that
3799 there seems to be no problems with JTAG scan chain operations.
3800 @item @code{-ignore-syspwrupack}
3801 @*Specify this to ignore the CSYSPWRUPACK bit in the ARM DAP DP CTRL/STAT
3802 register during initial examination and when checking the sticky error bit.
3803 This bit is normally checked after setting the CSYSPWRUPREQ bit, but some
3804 devices do not set the ack bit until sometime later.
3805 @end itemize
3806 @end deffn
3808 @section Other TAP commands
3810 @deffn Command {jtag cget} dotted.name @option{-event} event_name
3811 @deffnx Command {jtag configure} dotted.name @option{-event} event_name handler
3812 At this writing this TAP attribute
3813 mechanism is used only for event handling.
3814 (It is not a direct analogue of the @code{cget}/@code{configure}
3815 mechanism for debugger targets.)
3816 See the next section for information about the available events.
3818 The @code{configure} subcommand assigns an event handler,
3819 a TCL string which is evaluated when the event is triggered.
3820 The @code{cget} subcommand returns that handler.
3821 @end deffn
3823 @section TAP Events
3824 @cindex events
3825 @cindex TAP events
3827 OpenOCD includes two event mechanisms.
3828 The one presented here applies to all JTAG TAPs.
3829 The other applies to debugger targets,
3830 which are associated with certain TAPs.
3832 The TAP events currently defined are:
3834 @itemize @bullet
3835 @item @b{post-reset}
3836 @* The TAP has just completed a JTAG reset.
3837 The tap may still be in the JTAG @sc{reset} state.
3838 Handlers for these events might perform initialization sequences
3839 such as issuing TCK cycles, TMS sequences to ensure
3840 exit from the ARM SWD mode, and more.
3842 Because the scan chain has not yet been verified, handlers for these events
3843 @emph{should not issue commands which scan the JTAG IR or DR registers}
3844 of any particular target.
3845 @b{NOTE:} As this is written (September 2009), nothing prevents such access.
3846 @item @b{setup}
3847 @* The scan chain has been reset and verified.
3848 This handler may enable TAPs as needed.
3849 @item @b{tap-disable}
3850 @* The TAP needs to be disabled. This handler should
3851 implement @command{jtag tapdisable}
3852 by issuing the relevant JTAG commands.
3853 @item @b{tap-enable}
3854 @* The TAP needs to be enabled. This handler should
3855 implement @command{jtag tapenable}
3856 by issuing the relevant JTAG commands.
3857 @end itemize
3859 If you need some action after each JTAG reset which isn't actually
3860 specific to any TAP (since you can't yet trust the scan chain's
3861 contents to be accurate), you might:
3863 @example
3864 jtag configure CHIP.jrc -event post-reset @{
3865 echo "JTAG Reset done"
3866 ... non-scan jtag operations to be done after reset
3867 @}
3868 @end example
3871 @anchor{enablinganddisablingtaps}
3872 @section Enabling and Disabling TAPs
3873 @cindex JTAG Route Controller
3874 @cindex jrc
3876 In some systems, a @dfn{JTAG Route Controller} (JRC)
3877 is used to enable and/or disable specific JTAG TAPs.
3878 Many ARM-based chips from Texas Instruments include
3879 an ``ICEPick'' module, which is a JRC.
3880 Such chips include DaVinci and OMAP3 processors.
3882 A given TAP may not be visible until the JRC has been
3883 told to link it into the scan chain; and if the JRC
3884 has been told to unlink that TAP, it will no longer
3885 be visible.
3886 Such routers address problems that JTAG ``bypass mode''
3887 ignores, such as:
3889 @itemize
3890 @item The scan chain can only go as fast as its slowest TAP.
3891 @item Having many TAPs slows instruction scans, since all
3892 TAPs receive new instructions.
3893 @item TAPs in the scan chain must be powered up, which wastes
3894 power and prevents debugging some power management mechanisms.
3895 @end itemize
3897 The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
3898 as implied by the existence of JTAG routers.
3899 However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
3900 does include a kind of JTAG router functionality.
3902 @c (a) currently the event handlers don't seem to be able to
3903 @c fail in a way that could lead to no-change-of-state.
3905 In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
3906 shown below, and is implemented using TAP event handlers.
3907 So for example, when defining a TAP for a CPU connected to
3908 a JTAG router, your @file{target.cfg} file
3909 should define TAP event handlers using
3910 code that looks something like this:
3912 @example
3913 jtag configure CHIP.cpu -event tap-enable @{
3914 ... jtag operations using CHIP.jrc
3915 @}
3916 jtag configure CHIP.cpu -event tap-disable @{
3917 ... jtag operations using CHIP.jrc
3918 @}
3919 @end example
3921 Then you might want that CPU's TAP enabled almost all the time:
3923 @example
3924 jtag configure $CHIP.jrc -event setup "jtag tapenable $CHIP.cpu"
3925 @end example
3927 Note how that particular setup event handler declaration
3928 uses quotes to evaluate @code{$CHIP} when the event is configured.
3929 Using brackets @{ @} would cause it to be evaluated later,
3930 at runtime, when it might have a different value.
3932 @deffn Command {jtag tapdisable} dotted.name
3933 If necessary, disables the tap
3934 by sending it a @option{tap-disable} event.
3935 Returns the string "1" if the tap
3936 specified by @var{dotted.name} is enabled,
3937 and "0" if it is disabled.
3938 @end deffn
3940 @deffn Command {jtag tapenable} dotted.name
3941 If necessary, enables the tap
3942 by sending it a @option{tap-enable} event.
3943 Returns the string "1" if the tap
3944 specified by @var{dotted.name} is enabled,
3945 and "0" if it is disabled.
3946 @end deffn
3948 @deffn Command {jtag tapisenabled} dotted.name
3949 Returns the string "1" if the tap
3950 specified by @var{dotted.name} is enabled,
3951 and "0" if it is disabled.
3953 @quotation Note
3954 Humans will find the @command{scan_chain} command more helpful
3955 for querying the state of the JTAG taps.
3956 @end quotation
3957 @end deffn
3959 @anchor{autoprobing}
3960 @section Autoprobing
3961 @cindex autoprobe
3962 @cindex JTAG autoprobe
3964 TAP configuration is the first thing that needs to be done
3965 after interface and reset configuration. Sometimes it's
3966 hard finding out what TAPs exist, or how they are identified.
3967 Vendor documentation is not always easy to find and use.
3969 To help you get past such problems, OpenOCD has a limited
3970 @emph{autoprobing} ability to look at the scan chain, doing
3971 a @dfn{blind interrogation} and then reporting the TAPs it finds.
3972 To use this mechanism, start the OpenOCD server with only data
3973 that configures your JTAG interface, and arranges to come up
3974 with a slow clock (many devices don't support fast JTAG clocks
3975 right when they come out of reset).
3977 For example, your @file{openocd.cfg} file might have:
3979 @example
3980 source [find interface/olimex-arm-usb-tiny-h.cfg]
3981 reset_config trst_and_srst
3982 jtag_rclk 8
3983 @end example
3985 When you start the server without any TAPs configured, it will
3986 attempt to autoconfigure the TAPs. There are two parts to this:
3988 @enumerate
3989 @item @emph{TAP discovery} ...
3990 After a JTAG reset (sometimes a system reset may be needed too),
3991 each TAP's data registers will hold the contents of either the
3992 IDCODE or BYPASS register.
3993 If JTAG communication is working, OpenOCD will see each TAP,
3994 and report what @option{-expected-id} to use with it.
3995 @item @emph{IR Length discovery} ...
3996 Unfortunately JTAG does not provide a reliable way to find out
3997 the value of the @option{-irlen} parameter to use with a TAP
3998 that is discovered.
3999 If OpenOCD can discover the length of a TAP's instruction
4000 register, it will report it.
4001 Otherwise you may need to consult vendor documentation, such
4002 as chip data sheets or BSDL files.
4003 @end enumerate
4005 In many cases your board will have a simple scan chain with just
4006 a single device. Here's what OpenOCD reported with one board
4007 that's a bit more complex:
4009 @example
4010 clock speed 8 kHz
4011 There are no enabled taps. AUTO PROBING MIGHT NOT WORK!!
4012 AUTO auto0.tap - use "jtag newtap auto0 tap -expected-id 0x2b900f0f ..."
4013 AUTO auto1.tap - use "jtag newtap auto1 tap -expected-id 0x07926001 ..."
4014 AUTO auto2.tap - use "jtag newtap auto2 tap -expected-id 0x0b73b02f ..."
4015 AUTO auto0.tap - use "... -irlen 4"
4016 AUTO auto1.tap - use "... -irlen 4"
4017 AUTO auto2.tap - use "... -irlen 6"
4018 no gdb ports allocated as no target has been specified
4019 @end example
4021 Given that information, you should be able to either find some existing
4022 config files to use, or create your own. If you create your own, you
4023 would configure from the bottom up: first a @file{target.cfg} file
4024 with these TAPs, any targets associated with them, and any on-chip
4025 resources; then a @file{board.cfg} with off-chip resources, clocking,
4026 and so forth.
4028 @anchor{dapdeclaration}
4029 @section DAP declaration (ARMv7 and ARMv8 targets)
4030 @cindex DAP declaration
4032 Since OpenOCD version 0.11.0, the Debug Access Port (DAP) is
4033 no longer implicitly created together with the target. It must be
4034 explicitly declared using the @command{dap create} command. For all
4035 ARMv7 and ARMv8 targets, the option "@option{-dap} @var{dap_name}" has to be used
4036 instead of "@option{-chain-position} @var{dotted.name}" when the target is created.
4038 The @command{dap} command group supports the following sub-commands:
4040 @deffn Command {dap create} dap_name @option{-chain-position} dotted.name configparams...
4041 Declare a DAP instance named @var{dap_name} linked to the JTAG tap
4042 @var{dotted.name}. This also creates a new command (@command{dap_name})
4043 which is used for various purposes including additional configuration.
4044 There can only be one DAP for each JTAG tap in the system.
4046 A DAP may also provide optional @var{configparams}:
4048 @itemize @bullet
4049 @item @code{-ignore-syspwrupack}
4050 @*Specify this to ignore the CSYSPWRUPACK bit in the ARM DAP DP CTRL/STAT
4051 register during initial examination and when checking the sticky error bit.
4052 This bit is normally checked after setting the CSYSPWRUPREQ bit, but some
4053 devices do not set the ack bit until sometime later.
4054 @end itemize
4055 @end deffn
4057 @deffn Command {dap names}
4058 This command returns a list of all registered DAP objects. It it useful mainly
4059 for TCL scripting.
4060 @end deffn
4062 @deffn Command {dap info} [num]
4063 Displays the ROM table for MEM-AP @var{num},
4064 defaulting to the currently selected AP of the currently selected target.
4065 @end deffn
4067 @deffn Command {dap init}
4068 Initialize all registered DAPs. This command is used internally
4069 during initialization. It can be issued at any time after the
4070 initialization, too.
4071 @end deffn
4073 The following commands exist as subcommands of DAP instances:
4075 @deffn Command {$dap_name info} [num]
4076 Displays the ROM table for MEM-AP @var{num},
4077 defaulting to the currently selected AP.
4078 @end deffn
4080 @deffn Command {$dap_name apid} [num]
4081 Displays ID register from AP @var{num}, defaulting to the currently selected AP.
4082 @end deffn
4084 @anchor{DAP subcommand apreg}
4085 @deffn Command {$dap_name apreg} ap_num reg [value]
4086 Displays content of a register @var{reg} from AP @var{ap_num}
4087 or set a new value @var{value}.
4088 @var{reg} is byte address of a word register, 0, 4, 8 ... 0xfc.
4089 @end deffn
4091 @deffn Command {$dap_name apsel} [num]
4092 Select AP @var{num}, defaulting to 0.
4093 @end deffn
4095 @deffn Command {$dap_name dpreg} reg [value]
4096 Displays the content of DP register at address @var{reg}, or set it to a new
4097 value @var{value}.
4099 In case of SWD, @var{reg} is a value in packed format
4100 @math{dpbanksel << 4 | addr} and assumes values 0, 4, 8 ... 0xfc.
4101 In case of JTAG it only assumes values 0, 4, 8 and 0xc.
4103 @emph{Note:} Consider using @command{poll off} to avoid any disturbing
4104 background activity by OpenOCD while you are operating at such low-level.
4105 @end deffn
4107 @deffn Command {$dap_name baseaddr} [num]
4108 Displays debug base address from MEM-AP @var{num},
4109 defaulting to the currently selected AP.
4110 @end deffn
4112 @deffn Command {$dap_name memaccess} [value]
4113 Displays the number of extra tck cycles in the JTAG idle to use for MEM-AP
4114 memory bus access [0-255], giving additional time to respond to reads.
4115 If @var{value} is defined, first assigns that.
4116 @end deffn
4118 @deffn Command {$dap_name apcsw} [value [mask]]
4119 Displays or changes CSW bit pattern for MEM-AP transfers.
4121 At the begin of each memory access the CSW pattern is extended (bitwise or-ed)
4122 by @dfn{Size} and @dfn{AddrInc} bit-fields according to transfer requirements
4123 and the result is written to the real CSW register. All bits except dynamically
4124 updated fields @dfn{Size} and @dfn{AddrInc} can be changed by changing
4125 the CSW pattern. Refer to ARM ADI v5 manual chapter 7.6.4 and appendix A
4126 for details.
4128 Use @var{value} only syntax if you want to set the new CSW pattern as a whole.
4129 The example sets HPROT1 bit (required by Cortex-M) and clears the rest of
4130 the pattern:
4131 @example
4132 kx.dap apcsw 0x2000000
4133 @end example
4135 If @var{mask} is also used, the CSW pattern is changed only on bit positions
4136 where the mask bit is 1. The following example sets HPROT3 (cacheable)
4137 and leaves the rest of the pattern intact. It configures memory access through
4138 DCache on Cortex-M7.
4139 @example
4140 set CSW_HPROT3_CACHEABLE [expr 1 << 27]
4142 @end example
4144 Another example clears SPROT bit and leaves the rest of pattern intact:
4145 @example
4146 set CSW_SPROT [expr 1 << 30]
4147 samv.dap apcsw 0 $CSW_SPROT
4148 @end example
4150 @emph{Note:} If you want to check the real value of CSW, not CSW pattern, use
4151 @code{xxx.dap apreg 0}. @xref{DAP subcommand apreg,,}.
4153 @emph{Warning:} Some of the CSW bits are vital for working memory transfer.
4154 If you set a wrong CSW pattern and MEM-AP stopped working, use the following
4155 example with a proper dap name:
4156 @example
4157 xxx.dap apcsw default
4158 @end example
4159 @end deffn
4161 @deffn Command {$dap_name ti_be_32_quirks} [@option{enable}]
4162 Set/get quirks mode for TI TMS450/TMS570 processors
4163 Disabled by default
4164 @end deffn
4167 @node CPU Configuration
4168 @chapter CPU Configuration
4169 @cindex GDB target
4171 This chapter discusses how to set up GDB debug targets for CPUs.
4172 You can also access these targets without GDB
4173 (@pxref{Architecture and Core Commands},
4174 and @ref{targetstatehandling,,Target State handling}) and
4175 through various kinds of NAND and NOR flash commands.
4176 If you have multiple CPUs you can have multiple such targets.
4178 We'll start by looking at how to examine the targets you have,
4179 then look at how to add one more target and how to configure it.
4181 @section Target List
4182 @cindex target, current
4183 @cindex target, list
4185 All targets that have been set up are part of a list,
4186 where each member has a name.
4187 That name should normally be the same as the TAP name.
4188 You can display the list with the @command{targets}
4189 (plural!) command.
4190 This display often has only one CPU; here's what it might
4191 look like with more than one:
4192 @verbatim
4193 TargetName Type Endian TapName State
4194 -- ------------------ ---------- ------ ------------------ ------------
4195 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
4196 1 MyTarget cortex_m little mychip.foo tap-disabled
4197 @end verbatim
4199 One member of that list is the @dfn{current target}, which
4200 is implicitly referenced by many commands.
4201 It's the one marked with a @code{*} near the target name.
4202 In particular, memory addresses often refer to the address
4203 space seen by that current target.
4204 Commands like @command{mdw} (memory display words)
4205 and @command{flash erase_address} (erase NOR flash blocks)
4206 are examples; and there are many more.
4208 Several commands let you examine the list of targets:
4210 @deffn Command {target current}
4211 Returns the name of the current target.
4212 @end deffn
4214 @deffn Command {target names}
4215 Lists the names of all current targets in the list.
4216 @example
4217 foreach t [target names] @{
4218 puts [format "Target: %s\n" $t]
4219 @}
4220 @end example
4221 @end deffn
4223 @c yep, "target list" would have been better.
4224 @c plus maybe "target setdefault".
4226 @deffn Command targets [name]
4227 @emph{Note: the name of this command is plural. Other target
4228 command names are singular.}
4230 With no parameter, this command displays a table of all known
4231 targets in a user friendly form.
4233 With a parameter, this command sets the current target to
4234 the given target with the given @var{name}; this is
4235 only relevant on boards which have more than one target.
4236 @end deffn
4238 @section Target CPU Types
4239 @cindex target type
4240 @cindex CPU type
4242 Each target has a @dfn{CPU type}, as shown in the output of
4243 the @command{targets} command. You need to specify that type
4244 when calling @command{target create}.
4245 The CPU type indicates more than just the instruction set.
4246 It also indicates how that instruction set is implemented,
4247 what kind of debug support it integrates,
4248 whether it has an MMU (and if so, what kind),
4249 what core-specific commands may be available
4250 (@pxref{Architecture and Core Commands}),
4251 and more.
4253 It's easy to see what target types are supported,
4254 since there's a command to list them.
4256 @anchor{targettypes}
4257 @deffn Command {target types}
4258 Lists all supported target types.
4259 At this writing, the supported CPU types are:
4261 @itemize @bullet
4262 @item @code{arm11} -- this is a generation of ARMv6 cores
4263 @item @code{arm720t} -- this is an ARMv4 core with an MMU
4264 @item @code{arm7tdmi} -- this is an ARMv4 core
4265 @item @code{arm920t} -- this is an ARMv4 core with an MMU
4266 @item @code{arm926ejs} -- this is an ARMv5 core with an MMU
4267 @item @code{arm966e} -- this is an ARMv5 core
4268 @item @code{arm9tdmi} -- this is an ARMv4 core
4269 @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
4270 (Support for this is preliminary and incomplete.)
4271 @item @code{cortex_a} -- this is an ARMv7 core with an MMU
4272 @item @code{cortex_m} -- this is an ARMv7 core, supporting only the
4273 compact Thumb2 instruction set.
4274 @item @code{aarch64} -- this is an ARMv8-A core with an MMU
4275 @item @code{dragonite} -- resembles arm966e
4276 @item @code{dsp563xx} -- implements Freescale's 24-bit DSP.
4277 (Support for this is still incomplete.)
4278 @item @code{esirisc} -- this is an EnSilica eSi-RISC core.
4279 The current implementation supports eSi-32xx cores.
4280 @item @code{fa526} -- resembles arm920 (w/o Thumb)
4281 @item @code{feroceon} -- resembles arm926
4282 @item @code{mips_m4k} -- a MIPS core
4283 @item @code{xscale} -- this is actually an architecture,
4284 not a CPU type. It is based on the ARMv5 architecture.
4285 @item @code{openrisc} -- this is an OpenRISC 1000 core.
4286 The current implementation supports three JTAG TAP cores:
4287 @item @code{ls1_sap} -- this is the SAP on NXP LS102x CPUs,
4288 allowing access to physical memory addresses independently of CPU cores.
4289 @itemize @minus
4290 @item @code{OpenCores TAP} (See: @url{http://opencores.org/project,jtag})
4291 @item @code{Altera Virtual JTAG TAP} (See: @url{http://www.altera.com/literature/ug/ug_virtualjtag.pdf})
4292 @item @code{Xilinx BSCAN_* virtual JTAG interface} (See: @url{http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_2/spartan6_hdl.pdf})
4293 @end itemize
4294 And two debug interfaces cores:
4295 @itemize @minus
4296 @item @code{Advanced debug interface} (See: @url{http://opencores.org/project,adv_debug_sys})
4297 @item @code{SoC Debug Interface} (See: @url{http://opencores.org/project,dbg_interface})
4298 @end itemize
4299 @end itemize
4300 @end deffn
4302 To avoid being confused by the variety of ARM based cores, remember
4303 this key point: @emph{ARM is a technology licencing company}.
4304 (See: @url{http://www.arm.com}.)
4305 The CPU name used by OpenOCD will reflect the CPU design that was
4306 licensed, not a vendor brand which incorporates that design.
4307 Name prefixes like arm7, arm9, arm11, and cortex
4308 reflect design generations;
4309 while names like ARMv4, ARMv5, ARMv6, ARMv7 and ARMv8
4310 reflect an architecture version implemented by a CPU design.
4312 @anchor{targetconfiguration}
4313 @section Target Configuration
4315 Before creating a ``target'', you must have added its TAP to the scan chain.
4316 When you've added that TAP, you will have a @code{dotted.name}
4317 which is used to set up the CPU support.
4318 The chip-specific configuration file will normally configure its CPU(s)
4319 right after it adds all of the chip's TAPs to the scan chain.
4321 Although you can set up a target in one step, it's often clearer if you
4322 use shorter commands and do it in two steps: create it, then configure
4323 optional parts.
4324 All operations on the target after it's created will use a new
4325 command, created as part of target creation.
4327 The two main things to configure after target creation are
4328 a work area, which usually has target-specific defaults even
4329 if the board setup code overrides them later;
4330 and event handlers (@pxref{targetevents,,Target Events}), which tend
4331 to be much more board-specific.
4332 The key steps you use might look something like this
4334 @example
4335 dap create mychip.dap -chain-position mychip.cpu
4336 target create MyTarget cortex_m -dap mychip.dap
4337 MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
4338 MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
4339 MyTarget configure -event reset-init @{ myboard_reinit @}
4340 @end example
4342 You should specify a working area if you can; typically it uses some
4343 on-chip SRAM.
4344 Such a working area can speed up many things, including bulk
4345 writes to target memory;
4346 flash operations like checking to see if memory needs to be erased;
4347 GDB memory checksumming;
4348 and more.
4350 @quotation Warning
4351 On more complex chips, the work area can become
4352 inaccessible when application code
4353 (such as an operating system)
4354 enables or disables the MMU.
4355 For example, the particular MMU context used to access the virtual
4356 address will probably matter ... and that context might not have
4357 easy access to other addresses needed.
4358 At this writing, OpenOCD doesn't have much MMU intelligence.
4359 @end quotation
4361 It's often very useful to define a @code{reset-init} event handler.
4362 For systems that are normally used with a boot loader,
4363 common tasks include updating clocks and initializing memory
4364 controllers.
4365 That may be needed to let you write the boot loader into flash,
4366 in order to ``de-brick'' your board; or to load programs into
4367 external DDR memory without having run the boot loader.
4369 @deffn Command {target create} target_name type configparams...
4370 This command creates a GDB debug target that refers to a specific JTAG tap.
4371 It enters that target into a list, and creates a new
4372 command (@command{@var{target_name}}) which is used for various
4373 purposes including additional configuration.
4375 @itemize @bullet
4376 @item @var{target_name} ... is the name of the debug target.
4377 By convention this should be the same as the @emph{dotted.name}
4378 of the TAP associated with this target, which must be specified here
4379 using the @code{-chain-position @var{dotted.name}} configparam.
4381 This name is also used to create the target object command,
4382 referred to here as @command{$target_name},
4383 and in other places the target needs to be identified.
4384 @item @var{type} ... specifies the target type. @xref{targettypes,,target types}.
4385 @item @var{configparams} ... all parameters accepted by
4386 @command{$target_name configure} are permitted.
4387 If the target is big-endian, set it here with @code{-endian big}.
4389 You @emph{must} set the @code{-chain-position @var{dotted.name}} or
4390 @code{-dap @var{dap_name}} here.
4391 @end itemize
4392 @end deffn
4394 @deffn Command {$target_name configure} configparams...
4395 The options accepted by this command may also be
4396 specified as parameters to @command{target create}.
4397 Their values can later be queried one at a time by
4398 using the @command{$target_name cget} command.
4400 @emph{Warning:} changing some of these after setup is dangerous.
4401 For example, moving a target from one TAP to another;
4402 and changing its endianness.
4404 @itemize @bullet
4406 @item @code{-chain-position} @var{dotted.name} -- names the TAP
4407 used to access this target.
4409 @item @code{-dap} @var{dap_name} -- names the DAP used to access
4410 this target. @xref{dapdeclaration,,DAP declaration}, on how to
4411 create and manage DAP instances.
4413 @item @code{-endian} (@option{big}|@option{little}) -- specifies
4414 whether the CPU uses big or little endian conventions
4416 @item @code{-event} @var{event_name} @var{event_body} --
4417 @xref{targetevents,,Target Events}.
4418 Note that this updates a list of named event handlers.
4419 Calling this twice with two different event names assigns
4420 two different handlers, but calling it twice with the
4421 same event name assigns only one handler.
4423 Current target is temporarily overridden to the event issuing target
4424 before handler code starts and switched back after handler is done.
4426 @item @code{-work-area-backup} (@option{0}|@option{1}) -- says
4427 whether the work area gets backed up; by default,
4428 @emph{it is not backed up.}
4429 When possible, use a working_area that doesn't need to be backed up,
4430 since performing a backup slows down operations.
4431 For example, the beginning of an SRAM block is likely to
4432 be used by most build systems, but the end is often unused.
4434 @item @code{-work-area-size} @var{size} -- specify work are size,
4435 in bytes. The same size applies regardless of whether its physical
4436 or virtual address is being used.
4438 @item @code{-work-area-phys} @var{address} -- set the work area
4439 base @var{address} to be used when no MMU is active.
4441 @item @code{-work-area-virt} @var{address} -- set the work area
4442 base @var{address} to be used when an MMU is active.
4443 @emph{Do not specify a value for this except on targets with an MMU.}
4444 The value should normally correspond to a static mapping for the
4445 @code{-work-area-phys} address, set up by the current operating system.
4447 @anchor{rtostype}
4448 @item @code{-rtos} @var{rtos_type} -- enable rtos support for target,
4449 @var{rtos_type} can be one of @option{auto}, @option{eCos},
4450 @option{ThreadX}, @option{FreeRTOS}, @option{linux}, @option{ChibiOS},
4451 @option{embKernel}, @option{mqx}, @option{uCOS-III}, @option{nuttx}
4452 @xref{gdbrtossupport,,RTOS Support}.
4454 @item @code{-defer-examine} -- skip target examination at initial JTAG chain
4455 scan and after a reset. A manual call to arp_examine is required to
4456 access the target for debugging.
4458 @item @code{-ap-num} @var{ap_number} -- set DAP access port for target,
4459 @var{ap_number} is the numeric index of the DAP AP the target is connected to.
4460 Use this option with systems where multiple, independent cores are connected
4461 to separate access ports of the same DAP.
4463 @item @code{-cti} @var{cti_name} -- set Cross-Trigger Interface (CTI) connected
4464 to the target. Currently, only the @code{aarch64} target makes use of this option,
4465 where it is a mandatory configuration for the target run control.
4466 @xref{armcrosstrigger,,ARM Cross-Trigger Interface},
4467 for instruction on how to declare and control a CTI instance.
4469 @anchor{gdbportoverride}
4470 @item @code{-gdb-port} @var{number} -- see command @command{gdb_port} for the
4471 possible values of the parameter @var{number}, which are not only numeric values.
4472 Use this option to override, for this target only, the global parameter set with
4473 command @command{gdb_port}.
4474 @xref{gdb_port,,command gdb_port}.
4475 @end itemize
4476 @end deffn
4478 @section Other $target_name Commands
4479 @cindex object command
4481 The Tcl/Tk language has the concept of object commands,
4482 and OpenOCD adopts that same model for targets.
4484 A good Tk example is a on screen button.
4485 Once a button is created a button
4486 has a name (a path in Tk terms) and that name is useable as a first
4487 class command. For example in Tk, one can create a button and later
4488 configure it like this:
4490 @example
4491 # Create
4492 button .foobar -background red -command @{ foo @}
4493 # Modify
4494 .foobar configure -foreground blue
4495 # Query
4496 set x [.foobar cget -background]
4497 # Report
4498 puts [format "The button is %s" $x]
4499 @end example
4501 In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
4502 button, and its object commands are invoked the same way.
4504 @example
4505 str912.cpu mww 0x1234 0x42
4506 omap3530.cpu mww 0x5555 123
4507 @end example
4509 The commands supported by OpenOCD target objects are:
4511 @deffn Command {$target_name arp_examine} @option{allow-defer}
4512 @deffnx Command {$target_name arp_halt}
4513 @deffnx Command {$target_name arp_poll}
4514 @deffnx Command {$target_name arp_reset}
4515 @deffnx Command {$target_name arp_waitstate}
4516 Internal OpenOCD scripts (most notably @file{startup.tcl})
4517 use these to deal with specific reset cases.
4518 They are not otherwise documented here.
4519 @end deffn
4521 @deffn Command {$target_name array2mem} arrayname width address count
4522 @deffnx Command {$target_name mem2array} arrayname width address count
4523 These provide an efficient script-oriented interface to memory.
4524 The @code{array2mem} primitive writes bytes, halfwords, or words;
4525 while @code{mem2array} reads them.
4526 In both cases, the TCL side uses an array, and
4527 the target side uses raw memory.
4529 The efficiency comes from enabling the use of
4530 bulk JTAG data transfer operations.
4531 The script orientation comes from working with data
4532 values that are packaged for use by TCL scripts;
4533 @command{mdw} type primitives only print data they retrieve,
4534 and neither store nor return those values.
4536 @itemize
4537 @item @var{arrayname} ... is the name of an array variable
4538 @item @var{width} ... is 8/16/32 - indicating the memory access size
4539 @item @var{address} ... is the target memory address
4540 @item @var{count} ... is the number of elements to process
4541 @end itemize
4542 @end deffn
4544 @deffn Command {$target_name cget} queryparm
4545 Each configuration parameter accepted by
4546 @command{$target_name configure}
4547 can be individually queried, to return its current value.
4548 The @var{queryparm} is a parameter name
4549 accepted by that command, such as @code{-work-area-phys}.
4550 There are a few special cases:
4552 @itemize @bullet
4553 @item @code{-event} @var{event_name} -- returns the handler for the
4554 event named @var{event_name}.
4555 This is a special case because setting a handler requires
4556 two parameters.
4557 @item @code{-type} -- returns the target type.
4558 This is a special case because this is set using
4559 @command{target create} and can't be changed
4560 using @command{$target_name configure}.
4561 @end itemize
4563 For example, if you wanted to summarize information about
4564 all the targets you might use something like this:
4566 @example
4567 foreach name [target names] @{
4568 set y [$name cget -endian]
4569 set z [$name cget -type]
4570 puts [format "Chip %d is %s, Endian: %s, type: %s" \
4571 $x $name $y $z]
4572 @}
4573 @end example
4574 @end deffn
4576 @anchor{targetcurstate}
4577 @deffn Command {$target_name curstate}
4578 Displays the current target state:
4579 @code{debug-running},
4580 @code{halted},
4581 @code{reset},
4582 @code{running}, or @code{unknown}.
4583 (Also, @pxref{eventpolling,,Event Polling}.)
4584 @end deffn
4586 @deffn Command {$target_name eventlist}
4587 Displays a table listing all event handlers
4588 currently associated with this target.
4589 @xref{targetevents,,Target Events}.
4590 @end deffn
4592 @deffn Command {$target_name invoke-event} event_name
4593 Invokes the handler for the event named @var{event_name}.
4594 (This is primarily intended for use by OpenOCD framework
4595 code, for example by the reset code in @file{startup.tcl}.)
4596 @end deffn
4598 @deffn Command {$target_name mdw} addr [count]
4599 @deffnx Command {$target_name mdh} addr [count]
4600 @deffnx Command {$target_name mdb} addr [count]
4601 Display contents of address @var{addr}, as
4602 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
4603 or 8-bit bytes (@command{mdb}).
4604 If @var{count} is specified, displays that many units.
4605 (If you want to manipulate the data instead of displaying it,
4606 see the @code{mem2array} primitives.)
4607 @end deffn
4609 @deffn Command {$target_name mww} addr word
4610 @deffnx Command {$target_name mwh} addr halfword
4611 @deffnx Command {$target_name mwb} addr byte
4612 Writes the specified @var{word} (32 bits),
4613 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4614 at the specified address @var{addr}.
4615 @end deffn
4617 @anchor{targetevents}
4618 @section Target Events
4619 @cindex target events
4620 @cindex events
4621 At various times, certain things can happen, or you want them to happen.
4622 For example:
4623 @itemize @bullet
4624 @item What should happen when GDB connects? Should your target reset?
4625 @item When GDB tries to flash the target, do you need to enable the flash via a special command?
4626 @item Is using SRST appropriate (and possible) on your system?
4627 Or instead of that, do you need to issue JTAG commands to trigger reset?
4628 SRST usually resets everything on the scan chain, which can be inappropriate.
4629 @item During reset, do you need to write to certain memory locations
4630 to set up system clocks or
4631 to reconfigure the SDRAM?
4632 How about configuring the watchdog timer, or other peripherals,
4633 to stop running while you hold the core stopped for debugging?
4634 @end itemize
4636 All of the above items can be addressed by target event handlers.
4637 These are set up by @command{$target_name configure -event} or
4638 @command{target create ... -event}.
4640 The programmer's model matches the @code{-command} option used in Tcl/Tk
4641 buttons and events. The two examples below act the same, but one creates
4642 and invokes a small procedure while the other inlines it.
4644 @example
4645 proc my_init_proc @{ @} @{
4646 echo "Disabling watchdog..."
4647 mww 0xfffffd44 0x00008000
4648 @}
4649 mychip.cpu configure -event reset-init my_init_proc
4650 mychip.cpu configure -event reset-init @{
4651 echo "Disabling watchdog..."
4652 mww 0xfffffd44 0x00008000
4653 @}
4654 @end example
4656 The following target events are defined:
4658 @itemize @bullet
4659 @item @b{debug-halted}
4660 @* The target has halted for debug reasons (i.e.: breakpoint)
4661 @item @b{debug-resumed}
4662 @* The target has resumed (i.e.: GDB said run)
4663 @item @b{early-halted}
4664 @* Occurs early in the halt process
4665 @item @b{examine-start}
4666 @* Before target examine is called.
4667 @item @b{examine-end}
4668 @* After target examine is called with no errors.
4669 @item @b{gdb-attach}
4670 @* When GDB connects. Issued before any GDB communication with the target
4671 starts. GDB expects the target is halted during attachment.
4672 @xref{gdbmeminspect,,GDB as a non-intrusive memory inspector}, how to
4673 connect GDB to running target.
4674 The event can be also used to set up the target so it is possible to probe flash.
4675 Probing flash is necessary during GDB connect if you want to use
4676 @pxref{programmingusinggdb,,programming using GDB}.
4677 Another use of the flash memory map is for GDB to automatically choose
4678 hardware or software breakpoints depending on whether the breakpoint
4679 is in RAM or read only memory.
4680 Default is @code{halt}
4681 @item @b{gdb-detach}
4682 @* When GDB disconnects
4683 @item @b{gdb-end}
4684 @* When the target has halted and GDB is not doing anything (see early halt)
4685 @item @b{gdb-flash-erase-start}
4686 @* Before the GDB flash process tries to erase the flash (default is
4687 @code{reset init})
4688 @item @b{gdb-flash-erase-end}
4689 @* After the GDB flash process has finished erasing the flash
4690 @item @b{gdb-flash-write-start}
4691 @* Before GDB writes to the flash
4692 @item @b{gdb-flash-write-end}
4693 @* After GDB writes to the flash (default is @code{reset halt})
4694 @item @b{gdb-start}
4695 @* Before the target steps, GDB is trying to start/resume the target
4696 @item @b{halted}
4697 @* The target has halted
4698 @item @b{reset-assert-pre}
4699 @* Issued as part of @command{reset} processing
4700 after @command{reset-start} was triggered
4701 but before either SRST alone is asserted on the scan chain,
4702 or @code{reset-assert} is triggered.
4703 @item @b{reset-assert}
4704 @* Issued as part of @command{reset} processing
4705 after @command{reset-assert-pre} was triggered.
4706 When such a handler is present, cores which support this event will use
4707 it instead of asserting SRST.
4708 This support is essential for debugging with JTAG interfaces which
4709 don't include an SRST line (JTAG doesn't require SRST), and for
4710 selective reset on scan chains that have multiple targets.
4711 @item @b{reset-assert-post}
4712 @* Issued as part of @command{reset} processing
4713 after @code{reset-assert} has been triggered.
4714 or the target asserted SRST on the entire scan chain.
4715 @item @b{reset-deassert-pre}
4716 @* Issued as part of @command{reset} processing
4717 after @code{reset-assert-post} has been triggered.
4718 @item @b{reset-deassert-post}
4719 @* Issued as part of @command{reset} processing
4720 after @code{reset-deassert-pre} has been triggered
4721 and (if the target is using it) after SRST has been
4722 released on the scan chain.
4723 @item @b{reset-end}
4724 @* Issued as the final step in @command{reset} processing.
4725 @item @b{reset-init}
4726 @* Used by @b{reset init} command for board-specific initialization.
4727 This event fires after @emph{reset-deassert-post}.
4729 This is where you would configure PLLs and clocking, set up DRAM so
4730 you can download programs that don't fit in on-chip SRAM, set up pin
4731 multiplexing, and so on.
4732 (You may be able to switch to a fast JTAG clock rate here, after
4733 the target clocks are fully set up.)
4734 @item @b{reset-start}
4735 @* Issued as the first step in @command{reset} processing
4736 before @command{reset-assert-pre} is called.
4738 This is the most robust place to use @command{jtag_rclk}
4739 or @command{adapter_khz} to switch to a low JTAG clock rate,
4740 when reset disables PLLs needed to use a fast clock.
4741 @item @b{resume-start}
4742 @* Before any target is resumed
4743 @item @b{resume-end}
4744 @* After all targets have resumed
4745 @item @b{resumed}
4746 @* Target has resumed
4747 @item @b{trace-config}
4748 @* After target hardware trace configuration was changed
4749 @end itemize
4751 @node Flash Commands
4752 @chapter Flash Commands
4754 OpenOCD has different commands for NOR and NAND flash;
4755 the ``flash'' command works with NOR flash, while
4756 the ``nand'' command works with NAND flash.
4757 This partially reflects different hardware technologies:
4758 NOR flash usually supports direct CPU instruction and data bus access,
4759 while data from a NAND flash must be copied to memory before it can be
4760 used. (SPI flash must also be copied to memory before use.)
4761 However, the documentation also uses ``flash'' as a generic term;
4762 for example, ``Put flash configuration in board-specific files''.
4764 Flash Steps:
4765 @enumerate
4766 @item Configure via the command @command{flash bank}
4767 @* Do this in a board-specific configuration file,
4768 passing parameters as needed by the driver.
4769 @item Operate on the flash via @command{flash subcommand}
4770 @* Often commands to manipulate the flash are typed by a human, or run
4771 via a script in some automated way. Common tasks include writing a
4772 boot loader, operating system, or other data.
4773 @item GDB Flashing
4774 @* Flashing via GDB requires the flash be configured via ``flash
4775 bank'', and the GDB flash features be enabled.
4776 @xref{gdbconfiguration,,GDB Configuration}.
4777 @end enumerate
4779 Many CPUs have the ability to ``boot'' from the first flash bank.
4780 This means that misprogramming that bank can ``brick'' a system,
4781 so that it can't boot.
4782 JTAG tools, like OpenOCD, are often then used to ``de-brick'' the
4783 board by (re)installing working boot firmware.
4785 @anchor{norconfiguration}
4786 @section Flash Configuration Commands
4787 @cindex flash configuration
4789 @deffn {Config Command} {flash bank} name driver base size chip_width bus_width target [driver_options]
4790 Configures a flash bank which provides persistent storage
4791 for addresses from @math{base} to @math{base + size - 1}.
4792 These banks will often be visible to GDB through the target's memory map.
4793 In some cases, configuring a flash bank will activate extra commands;
4794 see the driver-specific documentation.
4796 @itemize @bullet
4797 @item @var{name} ... may be used to reference the flash bank
4798 in other flash commands. A number is also available.
4799 @item @var{driver} ... identifies the controller driver
4800 associated with the flash bank being declared.
4801 This is usually @code{cfi} for external flash, or else
4802 the name of a microcontroller with embedded flash memory.
4803 @xref{flashdriverlist,,Flash Driver List}.
4804 @item @var{base} ... Base address of the flash chip.
4805 @item @var{size} ... Size of the chip, in bytes.
4806 For some drivers, this value is detected from the hardware.
4807 @item @var{chip_width} ... Width of the flash chip, in bytes;
4808 ignored for most microcontroller drivers.
4809 @item @var{bus_width} ... Width of the data bus used to access the
4810 chip, in bytes; ignored for most microcontroller drivers.
4811 @item @var{target} ... Names the target used to issue
4812 commands to the flash controller.
4813 @comment Actually, it's currently a controller-specific parameter...
4814 @item @var{driver_options} ... drivers may support, or require,
4815 additional parameters. See the driver-specific documentation
4816 for more information.
4817 @end itemize
4818 @quotation Note
4819 This command is not available after OpenOCD initialization has completed.
4820 Use it in board specific configuration files, not interactively.
4821 @end quotation
4822 @end deffn
4824 @comment the REAL name for this command is "ocd_flash_banks"
4825 @comment less confusing would be: "flash list" (like "nand list")
4826 @deffn Command {flash banks}
4827 Prints a one-line summary of each device that was
4828 declared using @command{flash bank}, numbered from zero.
4829 Note that this is the @emph{plural} form;
4830 the @emph{singular} form is a very different command.
4831 @end deffn
4833 @deffn Command {flash list}
4834 Retrieves a list of associative arrays for each device that was
4835 declared using @command{flash bank}, numbered from zero.
4836 This returned list can be manipulated easily from within scripts.
4837 @end deffn
4839 @deffn Command {flash probe} num
4840 Identify the flash, or validate the parameters of the configured flash. Operation
4841 depends on the flash type.
4842 The @var{num} parameter is a value shown by @command{flash banks}.
4843 Most flash commands will implicitly @emph{autoprobe} the bank;
4844 flash drivers can distinguish between probing and autoprobing,
4845 but most don't bother.
4846 @end deffn
4848 @section Erasing, Reading, Writing to Flash
4849 @cindex flash erasing
4850 @cindex flash reading
4851 @cindex flash writing
4852 @cindex flash programming
4853 @anchor{flashprogrammingcommands}
4855 One feature distinguishing NOR flash from NAND or serial flash technologies
4856 is that for read access, it acts exactly like any other addressable memory.
4857 This means you can use normal memory read commands like @command{mdw} or
4858 @command{dump_image} with it, with no special @command{flash} subcommands.
4859 @xref{memoryaccess,,Memory access}, and @ref{imageaccess,,Image access}.
4861 Write access works differently. Flash memory normally needs to be erased
4862 before it's written. Erasing a sector turns all of its bits to ones, and
4863 writing can turn ones into zeroes. This is why there are special commands
4864 for interactive erasing and writing, and why GDB needs to know which parts
4865 of the address space hold NOR flash memory.
4867 @quotation Note
4868 Most of these erase and write commands leverage the fact that NOR flash
4869 chips consume target address space. They implicitly refer to the current
4870 JTAG target, and map from an address in that target's address space
4871 back to a flash bank.
4872 @comment In May 2009, those mappings may fail if any bank associated
4873 @comment with that target doesn't successfully autoprobe ... bug worth fixing?
4874 A few commands use abstract addressing based on bank and sector numbers,
4875 and don't depend on searching the current target and its address space.
4876 Avoid confusing the two command models.
4877 @end quotation
4879 Some flash chips implement software protection against accidental writes,
4880 since such buggy writes could in some cases ``brick'' a system.
4881 For such systems, erasing and writing may require sector protection to be
4882 disabled first.
4883 Examples include CFI flash such as ``Intel Advanced Bootblock flash'',
4884 and AT91SAM7 on-chip flash.
4885 @xref{flashprotect,,flash protect}.
4887 @deffn Command {flash erase_sector} num first last
4888 Erase sectors in bank @var{num}, starting at sector @var{first}
4889 up to and including @var{last}.
4890 Sector numbering starts at 0.
4891 Providing a @var{last} sector of @option{last}
4892 specifies "to the end of the flash bank".
4893 The @var{num} parameter is a value shown by @command{flash banks}.
4894 @end deffn
4896 @deffn Command {flash erase_address} [@option{pad}] [@option{unlock}] address length
4897 Erase sectors starting at @var{address} for @var{length} bytes.
4898 Unless @option{pad} is specified, @math{address} must begin a
4899 flash sector, and @math{address + length - 1} must end a sector.
4900 Specifying @option{pad} erases extra data at the beginning and/or
4901 end of the specified region, as needed to erase only full sectors.
4902 The flash bank to use is inferred from the @var{address}, and
4903 the specified length must stay within that bank.
4904 As a special case, when @var{length} is zero and @var{address} is
4905 the start of the bank, the whole flash is erased.
4906 If @option{unlock} is specified, then the flash is unprotected
4907 before erase starts.
4908 @end deffn
4910 @deffn Command {flash fillw} address word length
4911 @deffnx Command {flash fillh} address halfword length
4912 @deffnx Command {flash fillb} address byte length
4913 Fills flash memory with the specified @var{word} (32 bits),
4914 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4915 starting at @var{address} and continuing
4916 for @var{length} units (word/halfword/byte).
4917 No erasure is done before writing; when needed, that must be done
4918 before issuing this command.
4919 Writes are done in blocks of up to 1024 bytes, and each write is
4920 verified by reading back the data and comparing it to what was written.
4921 The flash bank to use is inferred from the @var{address} of
4922 each block, and the specified length must stay within that bank.
4923 @end deffn
4924 @comment no current checks for errors if fill blocks touch multiple banks!
4926 @deffn Command {flash write_bank} num filename [offset]
4927 Write the binary @file{filename} to flash bank @var{num},
4928 starting at @var{offset} bytes from the beginning of the bank. If @var{offset}
4929 is omitted, start at the beginning of the flash bank.
4930 The @var{num} parameter is a value shown by @command{flash banks}.
4931 @end deffn
4933 @deffn Command {flash read_bank} num filename [offset [length]]
4934 Read @var{length} bytes from the flash bank @var{num} starting at @var{offset}
4935 and write the contents to the binary @file{filename}. If @var{offset} is
4936 omitted, start at the beginning of the flash bank. If @var{length} is omitted,
4937 read the remaining bytes from the flash bank.
4938 The @var{num} parameter is a value shown by @command{flash banks}.
4939 @end deffn
4941 @deffn Command {flash verify_bank} num filename [offset]
4942 Compare the contents of the binary file @var{filename} with the contents of the
4943 flash bank @var{num} starting at @var{offset}. If @var{offset} is omitted,
4944 start at the beginning of the flash bank. Fail if the contents do not match.
4945 The @var{num} parameter is a value shown by @command{flash banks}.
4946 @end deffn
4948 @deffn Command {flash write_image} [erase] [unlock] filename [offset] [type]
4949 Write the image @file{filename} to the current target's flash bank(s).
4950 Only loadable sections from the image are written.
4951 A relocation @var{offset} may be specified, in which case it is added
4952 to the base address for each section in the image.
4953 The file [@var{type}] can be specified
4954 explicitly as @option{bin} (binary), @option{ihex} (Intel hex),
4955 @option{elf} (ELF file), @option{s19} (Motorola s19).
4956 @option{mem}, or @option{builder}.
4957 The relevant flash sectors will be erased prior to programming
4958 if the @option{erase} parameter is given. If @option{unlock} is
4959 provided, then the flash banks are unlocked before erase and
4960 program. The flash bank to use is inferred from the address of
4961 each image section.
4963 @quotation Warning
4964 Be careful using the @option{erase} flag when the flash is holding
4965 data you want to preserve.
4966 Portions of the flash outside those described in the image's
4967 sections might be erased with no notice.
4968 @itemize
4969 @item
4970 When a section of the image being written does not fill out all the
4971 sectors it uses, the unwritten parts of those sectors are necessarily
4972 also erased, because sectors can't be partially erased.
4973 @item
4974 Data stored in sector "holes" between image sections are also affected.
4975 For example, "@command{flash write_image erase ...}" of an image with
4976 one byte at the beginning of a flash bank and one byte at the end
4977 erases the entire bank -- not just the two sectors being written.
4978 @end itemize
4979 Also, when flash protection is important, you must re-apply it after
4980 it has been removed by the @option{unlock} flag.
4981 @end quotation
4983 @end deffn
4985 @section Other Flash commands
4986 @cindex flash protection
4988 @deffn Command {flash erase_check} num
4989 Check erase state of sectors in flash bank @var{num},
4990 and display that status.
4991 The @var{num} parameter is a value shown by @command{flash banks}.
4992 @end deffn
4994 @deffn Command {flash info} num [sectors]
4995 Print info about flash bank @var{num}, a list of protection blocks
4996 and their status. Use @option{sectors} to show a list of sectors instead.
4998 The @var{num} parameter is a value shown by @command{flash banks}.
4999 This command will first query the hardware, it does not print cached
5000 and possibly stale information.
5001 @end deffn
5003 @anchor{flashprotect}
5004 @deffn Command {flash protect} num first last (@option{on}|@option{off})
5005 Enable (@option{on}) or disable (@option{off}) protection of flash blocks
5006 in flash bank @var{num}, starting at protection block @var{first}
5007 and continuing up to and including @var{last}.
5008 Providing a @var{last} block of @option{last}
5009 specifies "to the end of the flash bank".
5010 The @var{num} parameter is a value shown by @command{flash banks}.
5011 The protection block is usually identical to a flash sector.
5012 Some devices may utilize a protection block distinct from flash sector.
5013 See @command{flash info} for a list of protection blocks.
5014 @end deffn
5016 @deffn Command {flash padded_value} num value
5017 Sets the default value used for padding any image sections, This should
5018 normally match the flash bank erased value. If not specified by this
5019 command or the flash driver then it defaults to 0xff.
5020 @end deffn
5022 @anchor{program}
5023 @deffn Command {program} filename [verify] [reset] [exit] [offset]
5024 This is a helper script that simplifies using OpenOCD as a standalone
5025 programmer. The only required parameter is @option{filename}, the others are optional.
5026 @xref{Flash Programming}.
5027 @end deffn
5029 @anchor{flashdriverlist}
5030 @section Flash Driver List
5031 As noted above, the @command{flash bank} command requires a driver name,
5032 and allows driver-specific options and behaviors.
5033 Some drivers also activate driver-specific commands.
5035 @deffn {Flash Driver} virtual
5036 This is a special driver that maps a previously defined bank to another
5037 address. All bank settings will be copied from the master physical bank.
5039 The @var{virtual} driver defines one mandatory parameters,
5041 @itemize
5042 @item @var{master_bank} The bank that this virtual address refers to.
5043 @end itemize
5045 So in the following example addresses 0xbfc00000 and 0x9fc00000 refer to
5046 the flash bank defined at address 0x1fc00000. Any command executed on
5047 the virtual banks is actually performed on the physical banks.
5048 @example
5049 flash bank $_FLASHNAME pic32mx 0x1fc00000 0 0 0 $_TARGETNAME
5050 flash bank vbank0 virtual 0xbfc00000 0 0 0 \
5052 flash bank vbank1 virtual 0x9fc00000 0 0 0 \
5054 @end example
5055 @end deffn
5057 @subsection External Flash
5059 @deffn {Flash Driver} cfi
5060 @cindex Common Flash Interface
5061 @cindex CFI
5062 The ``Common Flash Interface'' (CFI) is the main standard for
5063 external NOR flash chips, each of which connects to a
5064 specific external chip select on the CPU.
5065 Frequently the first such chip is used to boot the system.
5066 Your board's @code{reset-init} handler might need to