flash/startup: extend "program" command to accept "exit"
[openocd.git] / doc / openocd.texi
1 \input texinfo @c -*-texinfo-*-
2 @c %**start of header
3 @setfilename openocd.info
4 @settitle OpenOCD User's Guide
5 @dircategory Development
6 @direntry
7 * OpenOCD: (openocd). OpenOCD User's Guide
8 @end direntry
9 @paragraphindent 0
10 @c %**end of header
12 @include version.texi
14 @copying
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
21 @itemize @bullet
22 @item Copyright @copyright{} 2008 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk}
24 @item Copyright @copyright{} 2008-2010 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
26 @item Copyright @copyright{} 2009-2010 David Brownell
27 @end itemize
29 @quotation
30 Permission is granted to copy, distribute and/or modify this document
31 under the terms of the GNU Free Documentation License, Version 1.2 or
32 any later version published by the Free Software Foundation; with no
33 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
34 Texts. A copy of the license is included in the section entitled ``GNU
35 Free Documentation License''.
36 @end quotation
37 @end copying
39 @titlepage
40 @titlefont{@emph{Open On-Chip Debugger:}}
41 @sp 1
42 @title OpenOCD User's Guide
43 @subtitle for release @value{VERSION}
44 @subtitle @value{UPDATED}
46 @page
47 @vskip 0pt plus 1filll
48 @insertcopying
49 @end titlepage
51 @summarycontents
52 @contents
54 @ifnottex
55 @node Top
56 @top OpenOCD User's Guide
58 @insertcopying
59 @end ifnottex
61 @menu
62 * About:: About OpenOCD
63 * Developers:: OpenOCD Developer Resources
64 * Debug Adapter Hardware:: Debug Adapter Hardware
65 * About Jim-Tcl:: About Jim-Tcl
66 * Running:: Running OpenOCD
67 * OpenOCD Project Setup:: OpenOCD Project Setup
68 * Config File Guidelines:: Config File Guidelines
69 * Daemon Configuration:: Daemon Configuration
70 * Debug Adapter Configuration:: Debug Adapter Configuration
71 * Reset Configuration:: Reset Configuration
72 * TAP Declaration:: TAP Declaration
73 * CPU Configuration:: CPU Configuration
74 * Flash Commands:: Flash Commands
75 * Flash Programming:: Flash Programming
76 * NAND Flash Commands:: NAND Flash Commands
77 * PLD/FPGA Commands:: PLD/FPGA Commands
78 * General Commands:: General Commands
79 * Architecture and Core Commands:: Architecture and Core Commands
80 * JTAG Commands:: JTAG Commands
81 * Boundary Scan Commands:: Boundary Scan Commands
82 * Utility Commands:: Utility Commands
83 * TFTP:: TFTP
84 * GDB and OpenOCD:: Using GDB and OpenOCD
85 * Tcl Scripting API:: Tcl Scripting API
86 * FAQ:: Frequently Asked Questions
87 * Tcl Crash Course:: Tcl Crash Course
88 * License:: GNU Free Documentation License
90 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
91 @comment case issue with ``Index.html'' and ``index.html''
92 @comment Occurs when creating ``--html --no-split'' output
93 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
94 * OpenOCD Concept Index:: Concept Index
95 * Command and Driver Index:: Command and Driver Index
96 @end menu
98 @node About
99 @unnumbered About
100 @cindex about
102 OpenOCD was created by Dominic Rath as part of a 2005 diploma thesis written
103 at the University of Applied Sciences Augsburg (@uref{http://www.hs-augsburg.de}).
104 Since that time, the project has grown into an active open-source project,
105 supported by a diverse community of software and hardware developers from
106 around the world.
108 @section What is OpenOCD?
109 @cindex TAP
110 @cindex JTAG
112 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
113 in-system programming and boundary-scan testing for embedded target
114 devices.
116 It does so with the assistance of a @dfn{debug adapter}, which is
117 a small hardware module which helps provide the right kind of
118 electrical signaling to the target being debugged. These are
119 required since the debug host (on which OpenOCD runs) won't
120 usually have native support for such signaling, or the connector
121 needed to hook up to the target.
123 Such debug adapters support one or more @dfn{transport} protocols,
124 each of which involves different electrical signaling (and uses
125 different messaging protocols on top of that signaling). There
126 are many types of debug adapter, and little uniformity in what
127 they are called. (There are also product naming differences.)
129 These adapters are sometimes packaged as discrete dongles, which
130 may generically be called @dfn{hardware interface dongles}.
131 Some development boards also integrate them directly, which may
132 let the development board connect directly to the debug
133 host over USB (and sometimes also to power it over USB).
135 For example, a @dfn{JTAG Adapter} supports JTAG
136 signaling, and is used to communicate
137 with JTAG (IEEE 1149.1) compliant TAPs on your target board.
138 A @dfn{TAP} is a ``Test Access Port'', a module which processes
139 special instructions and data. TAPs are daisy-chained within and
140 between chips and boards. JTAG supports debugging and boundary
141 scan operations.
143 There are also @dfn{SWD Adapters} that support Serial Wire Debug (SWD)
144 signaling to communicate with some newer ARM cores, as well as debug
145 adapters which support both JTAG and SWD transports. SWD supports only
146 debugging, whereas JTAG also supports boundary scan operations.
148 For some chips, there are also @dfn{Programming Adapters} supporting
149 special transports used only to write code to flash memory, without
150 support for on-chip debugging or boundary scan.
151 (At this writing, OpenOCD does not support such non-debug adapters.)
154 @b{Dongles:} OpenOCD currently supports many types of hardware dongles:
155 USB-based, parallel port-based, and other standalone boxes that run
156 OpenOCD internally. @xref{Debug Adapter Hardware}.
158 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
159 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x), Cortex-M3
160 (Stellaris LM3, ST STM32 and Energy Micro EFM32) and Intel Quark (x10xx)
161 based cores to be debugged via the GDB protocol.
163 @b{Flash Programming:} Flash writing is supported for external
164 CFI-compatible NOR flashes (Intel and AMD/Spansion command set) and several
165 internal flashes (LPC1700, LPC1800, LPC2000, LPC4300, AT91SAM7, AT91SAM3U,
166 STR7x, STR9x, LM3, STM32x and EFM32). Preliminary support for various NAND flash
167 controllers (LPC3180, Orion, S3C24xx, more) is included.
169 @section OpenOCD Web Site
171 The OpenOCD web site provides the latest public news from the community:
173 @uref{http://openocd.sourceforge.net/}
175 @section Latest User's Guide:
177 The user's guide you are now reading may not be the latest one
178 available. A version for more recent code may be available.
179 Its HTML form is published regularly at:
181 @uref{http://openocd.sourceforge.net/doc/html/index.html}
183 PDF form is likewise published at:
185 @uref{http://openocd.sourceforge.net/doc/pdf/openocd.pdf}
187 @section OpenOCD User's Forum
189 There is an OpenOCD forum (phpBB) hosted by SparkFun,
190 which might be helpful to you. Note that if you want
191 anything to come to the attention of developers, you
192 should post it to the OpenOCD Developer Mailing List
193 instead of this forum.
195 @uref{http://forum.sparkfun.com/viewforum.php?f=18}
197 @section OpenOCD User's Mailing List
199 The OpenOCD User Mailing List provides the primary means of
200 communication between users:
202 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-user}
204 @section OpenOCD IRC
206 Support can also be found on irc:
207 @uref{irc://irc.freenode.net/openocd}
209 @node Developers
210 @chapter OpenOCD Developer Resources
211 @cindex developers
213 If you are interested in improving the state of OpenOCD's debugging and
214 testing support, new contributions will be welcome. Motivated developers
215 can produce new target, flash or interface drivers, improve the
216 documentation, as well as more conventional bug fixes and enhancements.
218 The resources in this chapter are available for developers wishing to explore
219 or expand the OpenOCD source code.
221 @section OpenOCD Git Repository
223 During the 0.3.x release cycle, OpenOCD switched from Subversion to
224 a Git repository hosted at SourceForge. The repository URL is:
226 @uref{git://git.code.sf.net/p/openocd/code}
228 or via http
230 @uref{http://git.code.sf.net/p/openocd/code}
232 You may prefer to use a mirror and the HTTP protocol:
234 @uref{http://repo.or.cz/r/openocd.git}
236 With standard Git tools, use @command{git clone} to initialize
237 a local repository, and @command{git pull} to update it.
238 There are also gitweb pages letting you browse the repository
239 with a web browser, or download arbitrary snapshots without
240 needing a Git client:
242 @uref{http://repo.or.cz/w/openocd.git}
244 The @file{README} file contains the instructions for building the project
245 from the repository or a snapshot.
247 Developers that want to contribute patches to the OpenOCD system are
248 @b{strongly} encouraged to work against mainline.
249 Patches created against older versions may require additional
250 work from their submitter in order to be updated for newer releases.
252 @section Doxygen Developer Manual
254 During the 0.2.x release cycle, the OpenOCD project began
255 providing a Doxygen reference manual. This document contains more
256 technical information about the software internals, development
257 processes, and similar documentation:
259 @uref{http://openocd.sourceforge.net/doc/doxygen/html/index.html}
261 This document is a work-in-progress, but contributions would be welcome
262 to fill in the gaps. All of the source files are provided in-tree,
263 listed in the Doxyfile configuration at the top of the source tree.
265 @section Gerrit Review System
267 All changes in the OpenOCD Git repository go through the web-based Gerrit
268 Code Review System:
270 @uref{http://openocd.zylin.com/}
272 After a one-time registration and repository setup, anyone can push commits
273 from their local Git repository directly into Gerrit.
274 All users and developers are encouraged to review, test, discuss and vote
275 for changes in Gerrit. The feedback provides the basis for a maintainer to
276 eventually submit the change to the main Git repository.
278 The @file{HACKING} file, also available as the Patch Guide in the Doxygen
279 Developer Manual, contains basic information about how to connect a
280 repository to Gerrit, prepare and push patches. Patch authors are expected to
281 maintain their changes while they're in Gerrit, respond to feedback and if
282 necessary rework and push improved versions of the change.
284 @section OpenOCD Developer Mailing List
286 The OpenOCD Developer Mailing List provides the primary means of
287 communication between developers:
289 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-devel}
291 @section OpenOCD Bug Tracker
293 The OpenOCD Bug Tracker is hosted on SourceForge:
295 @uref{https://sourceforge.net/p/openocd/tickets/}
298 @node Debug Adapter Hardware
299 @chapter Debug Adapter Hardware
300 @cindex dongles
301 @cindex FTDI
302 @cindex wiggler
303 @cindex zy1000
304 @cindex printer port
305 @cindex USB Adapter
306 @cindex RTCK
308 Defined: @b{dongle}: A small device that plugs into a computer and serves as
309 an adapter .... [snip]
311 In the OpenOCD case, this generally refers to @b{a small adapter} that
312 attaches to your computer via USB or the parallel port. One
313 exception is the Ultimate Solutions ZY1000, packaged as a small box you
314 attach via an ethernet cable. The ZY1000 has the advantage that it does not
315 require any drivers to be installed on the developer PC. It also has
316 a built in web interface. It supports RTCK/RCLK or adaptive clocking
317 and has a built-in relay to power cycle targets remotely.
320 @section Choosing a Dongle
322 There are several things you should keep in mind when choosing a dongle.
324 @enumerate
325 @item @b{Transport} Does it support the kind of communication that you need?
326 OpenOCD focusses mostly on JTAG. Your version may also support
327 other ways to communicate with target devices.
328 @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
329 Does your dongle support it? You might need a level converter.
330 @item @b{Pinout} What pinout does your target board use?
331 Does your dongle support it? You may be able to use jumper
332 wires, or an "octopus" connector, to convert pinouts.
333 @item @b{Connection} Does your computer have the USB, parallel, or
334 Ethernet port needed?
335 @item @b{RTCK} Do you expect to use it with ARM chips and boards with
336 RTCK support (also known as ``adaptive clocking'')?
337 @end enumerate
339 @section Stand-alone JTAG Probe
341 The ZY1000 from Ultimate Solutions is technically not a dongle but a
342 stand-alone JTAG probe that, unlike most dongles, doesn't require any drivers
343 running on the developer's host computer.
344 Once installed on a network using DHCP or a static IP assignment, users can
345 access the ZY1000 probe locally or remotely from any host with access to the
346 IP address assigned to the probe.
347 The ZY1000 provides an intuitive web interface with direct access to the
348 OpenOCD debugger.
349 Users may also run a GDBSERVER directly on the ZY1000 to take full advantage
350 of GCC & GDB to debug any distribution of embedded Linux or NetBSD running on
351 the target.
352 The ZY1000 supports RTCK & RCLK or adaptive clocking and has a built-in relay
353 to power cycle the target remotely.
355 For more information, visit:
357 @b{ZY1000} See: @url{http://www.ultsol.com/index.php/component/content/article/8/210-zylin-zy1000-main}
359 @section USB FT2232 Based
361 There are many USB JTAG dongles on the market, many of them based
362 on a chip from ``Future Technology Devices International'' (FTDI)
363 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
364 See: @url{http://www.ftdichip.com} for more information.
365 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
366 chips started to become available in JTAG adapters. Around 2012, a new
367 variant appeared - FT232H - this is a single-channel version of FT2232H.
368 (Adapters using those high speed FT2232H or FT232H chips may support adaptive
369 clocking.)
371 The FT2232 chips are flexible enough to support some other
372 transport options, such as SWD or the SPI variants used to
373 program some chips. They have two communications channels,
374 and one can be used for a UART adapter at the same time the
375 other one is used to provide a debug adapter.
377 Also, some development boards integrate an FT2232 chip to serve as
378 a built-in low-cost debug adapter and USB-to-serial solution.
380 @itemize @bullet
381 @item @b{usbjtag}
382 @* Link @url{http://elk.informatik.fh-augsburg.de/hhweb/doc/openocd/usbjtag/usbjtag.html}
383 @item @b{jtagkey}
384 @* See: @url{http://www.amontec.com/jtagkey.shtml}
385 @item @b{jtagkey2}
386 @* See: @url{http://www.amontec.com/jtagkey2.shtml}
387 @item @b{oocdlink}
388 @* See: @url{http://www.oocdlink.com} By Joern Kaipf
389 @item @b{signalyzer}
390 @* See: @url{http://www.signalyzer.com}
391 @item @b{Stellaris Eval Boards}
392 @* See: @url{http://www.ti.com} - The Stellaris eval boards
393 bundle FT2232-based JTAG and SWD support, which can be used to debug
394 the Stellaris chips. Using separate JTAG adapters is optional.
395 These boards can also be used in a "pass through" mode as JTAG adapters
396 to other target boards, disabling the Stellaris chip.
397 @item @b{TI/Luminary ICDI}
398 @* See: @url{http://www.ti.com} - TI/Luminary In-Circuit Debug
399 Interface (ICDI) Boards are included in Stellaris LM3S9B9x
400 Evaluation Kits. Like the non-detachable FT2232 support on the other
401 Stellaris eval boards, they can be used to debug other target boards.
402 @item @b{olimex-jtag}
403 @* See: @url{http://www.olimex.com}
404 @item @b{Flyswatter/Flyswatter2}
405 @* See: @url{http://www.tincantools.com}
406 @item @b{turtelizer2}
407 @* See:
408 @uref{http://www.ethernut.de/en/hardware/turtelizer/index.html, Turtelizer 2}, or
409 @url{http://www.ethernut.de}
410 @item @b{comstick}
411 @* Link: @url{http://www.hitex.com/index.php?id=383}
412 @item @b{stm32stick}
413 @* Link @url{http://www.hitex.com/stm32-stick}
414 @item @b{axm0432_jtag}
415 @* Axiom AXM-0432 Link @url{http://www.axman.com} - NOTE: This JTAG does not appear
416 to be available anymore as of April 2012.
417 @item @b{cortino}
418 @* Link @url{http://www.hitex.com/index.php?id=cortino}
419 @item @b{dlp-usb1232h}
420 @* Link @url{http://www.dlpdesign.com/usb/usb1232h.shtml}
421 @item @b{digilent-hs1}
422 @* Link @url{http://www.digilentinc.com/Products/Detail.cfm?Prod=JTAG-HS1}
423 @item @b{opendous}
424 @* Link @url{http://code.google.com/p/opendous/wiki/JTAG} FT2232H-based
425 (OpenHardware).
426 @item @b{JTAG-lock-pick Tiny 2}
427 @* Link @url{http://www.distortec.com/jtag-lock-pick-tiny-2} FT232H-based
429 @item @b{GW16042}
430 @* Link: @url{http://shop.gateworks.com/index.php?route=product/product&path=70_80&product_id=64}
431 FT2232H-based
433 @end itemize
434 @section USB-JTAG / Altera USB-Blaster compatibles
436 These devices also show up as FTDI devices, but are not
437 protocol-compatible with the FT2232 devices. They are, however,
438 protocol-compatible among themselves. USB-JTAG devices typically consist
439 of a FT245 followed by a CPLD that understands a particular protocol,
440 or emulates this protocol using some other hardware.
442 They may appear under different USB VID/PID depending on the particular
443 product. The driver can be configured to search for any VID/PID pair
444 (see the section on driver commands).
446 @itemize
447 @item @b{USB-JTAG} Kolja Waschk's USB Blaster-compatible adapter
448 @* Link: @url{http://ixo-jtag.sourceforge.net/}
449 @item @b{Altera USB-Blaster}
450 @* Link: @url{http://www.altera.com/literature/ug/ug_usb_blstr.pdf}
451 @end itemize
453 @section USB JLINK based
454 There are several OEM versions of the Segger @b{JLINK} adapter. It is
455 an example of a micro controller based JTAG adapter, it uses an
456 AT91SAM764 internally.
458 @itemize @bullet
459 @item @b{ATMEL SAMICE} Only works with ATMEL chips!
460 @* Link: @url{http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3892}
461 @item @b{SEGGER JLINK}
462 @* Link: @url{http://www.segger.com/jlink.html}
463 @item @b{IAR J-Link}
464 @* Link: @url{http://www.iar.com/en/products/hardware-debug-probes/iar-j-link/}
465 @end itemize
467 @section USB RLINK based
468 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer,
469 permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for
470 SWD and not JTAG, thus not supported.
472 @itemize @bullet
473 @item @b{Raisonance RLink}
474 @* Link: @url{http://www.mcu-raisonance.com/~rlink-debugger-programmer__microcontrollers__tool~tool__T018:4cn9ziz4bnx6.html}
475 @item @b{STM32 Primer}
476 @* Link: @url{http://www.stm32circle.com/resources/stm32primer.php}
477 @item @b{STM32 Primer2}
478 @* Link: @url{http://www.stm32circle.com/resources/stm32primer2.php}
479 @end itemize
481 @section USB ST-LINK based
482 ST Micro has an adapter called @b{ST-LINK}.
483 They only work with ST Micro chips, notably STM32 and STM8.
485 @itemize @bullet
486 @item @b{ST-LINK}
487 @* This is available standalone and as part of some kits, eg. STM32VLDISCOVERY.
488 @* Link: @url{http://www.st.com/internet/evalboard/product/219866.jsp}
489 @item @b{ST-LINK/V2}
490 @* This is available standalone and as part of some kits, eg. STM32F4DISCOVERY.
491 @* Link: @url{http://www.st.com/internet/evalboard/product/251168.jsp}
492 @end itemize
494 For info the original ST-LINK enumerates using the mass storage usb class; however,
495 its implementation is completely broken. The result is this causes issues under Linux.
496 The simplest solution is to get Linux to ignore the ST-LINK using one of the following methods:
497 @itemize @bullet
498 @item modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i
499 @item add "options usb-storage quirks=483:3744:i" to /etc/modprobe.conf
500 @end itemize
502 @section USB TI/Stellaris ICDI based
503 Texas Instruments has an adapter called @b{ICDI}.
504 It is not to be confused with the FTDI based adapters that were originally fitted to their
505 evaluation boards. This is the adapter fitted to the Stellaris LaunchPad.
507 @section USB CMSIS-DAP based
508 ARM has released a interface standard called CMSIS-DAP that simplifies connecting
509 debuggers to ARM Cortex based targets @url{http://www.keil.com/support/man/docs/dapdebug/dapdebug_introduction.htm}.
511 @section USB Other
512 @itemize @bullet
513 @item @b{USBprog}
514 @* Link: @url{http://shop.embedded-projects.net/} - which uses an Atmel MEGA32 and a UBN9604
516 @item @b{USB - Presto}
517 @* Link: @url{http://tools.asix.net/prg_presto.htm}
519 @item @b{Versaloon-Link}
520 @* Link: @url{http://www.versaloon.com}
522 @item @b{ARM-JTAG-EW}
523 @* Link: @url{http://www.olimex.com/dev/arm-jtag-ew.html}
525 @item @b{Buspirate}
526 @* Link: @url{http://dangerousprototypes.com/bus-pirate-manual/}
528 @item @b{opendous}
529 @* Link: @url{http://code.google.com/p/opendous-jtag/} - which uses an AT90USB162
531 @item @b{estick}
532 @* Link: @url{http://code.google.com/p/estick-jtag/}
534 @item @b{Keil ULINK v1}
535 @* Link: @url{http://www.keil.com/ulink1/}
536 @end itemize
538 @section IBM PC Parallel Printer Port Based
540 The two well-known ``JTAG Parallel Ports'' cables are the Xilinx DLC5
541 and the Macraigor Wiggler. There are many clones and variations of
542 these on the market.
544 Note that parallel ports are becoming much less common, so if you
545 have the choice you should probably avoid these adapters in favor
546 of USB-based ones.
548 @itemize @bullet
550 @item @b{Wiggler} - There are many clones of this.
551 @* Link: @url{http://www.macraigor.com/wiggler.htm}
553 @item @b{DLC5} - From XILINX - There are many clones of this
554 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
555 produced, PDF schematics are easily found and it is easy to make.
557 @item @b{Amontec - JTAG Accelerator}
558 @* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
560 @item @b{Wiggler2}
561 @* Link: @url{http://www.ccac.rwth-aachen.de/~michaels/index.php/hardware/armjtag}
563 @item @b{Wiggler_ntrst_inverted}
564 @* Yet another variation - See the source code, src/jtag/parport.c
566 @item @b{old_amt_wiggler}
567 @* Unknown - probably not on the market today
569 @item @b{arm-jtag}
570 @* Link: Most likely @url{http://www.olimex.com/dev/arm-jtag.html} [another wiggler clone]
572 @item @b{chameleon}
573 @* Link: @url{http://www.amontec.com/chameleon.shtml}
575 @item @b{Triton}
576 @* Unknown.
578 @item @b{Lattice}
579 @* ispDownload from Lattice Semiconductor
580 @url{http://www.latticesemi.com/lit/docs/@/devtools/dlcable.pdf}
582 @item @b{flashlink}
583 @* From ST Microsystems;
584 @* Link: @url{http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/DATA_BRIEF/DM00039500.pdf}
586 @end itemize
588 @section Other...
589 @itemize @bullet
591 @item @b{ep93xx}
592 @* An EP93xx based Linux machine using the GPIO pins directly.
594 @item @b{at91rm9200}
595 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
597 @item @b{bcm2835gpio}
598 @* A BCM2835-based board (e.g. Raspberry Pi) using the GPIO pins of the expansion header.
600 @item @b{jtag_vpi}
601 @* A JTAG driver acting as a client for the JTAG VPI server interface.
602 @* Link: @url{http://github.com/fjullien/jtag_vpi}
604 @end itemize
606 @node About Jim-Tcl
607 @chapter About Jim-Tcl
608 @cindex Jim-Tcl
609 @cindex tcl
611 OpenOCD uses a small ``Tcl Interpreter'' known as Jim-Tcl.
612 This programming language provides a simple and extensible
613 command interpreter.
615 All commands presented in this Guide are extensions to Jim-Tcl.
616 You can use them as simple commands, without needing to learn
617 much of anything about Tcl.
618 Alternatively, you can write Tcl programs with them.
620 You can learn more about Jim at its website, @url{http://jim.tcl.tk}.
621 There is an active and responsive community, get on the mailing list
622 if you have any questions. Jim-Tcl maintainers also lurk on the
623 OpenOCD mailing list.
625 @itemize @bullet
626 @item @b{Jim vs. Tcl}
627 @* Jim-Tcl is a stripped down version of the well known Tcl language,
628 which can be found here: @url{http://www.tcl.tk}. Jim-Tcl has far
629 fewer features. Jim-Tcl is several dozens of .C files and .H files and
630 implements the basic Tcl command set. In contrast: Tcl 8.6 is a
631 4.2 MB .zip file containing 1540 files.
633 @item @b{Missing Features}
634 @* Our practice has been: Add/clone the real Tcl feature if/when
635 needed. We welcome Jim-Tcl improvements, not bloat. Also there
636 are a large number of optional Jim-Tcl features that are not
637 enabled in OpenOCD.
639 @item @b{Scripts}
640 @* OpenOCD configuration scripts are Jim-Tcl Scripts. OpenOCD's
641 command interpreter today is a mixture of (newer)
642 Jim-Tcl commands, and the (older) original command interpreter.
644 @item @b{Commands}
645 @* At the OpenOCD telnet command line (or via the GDB monitor command) one
646 can type a Tcl for() loop, set variables, etc.
647 Some of the commands documented in this guide are implemented
648 as Tcl scripts, from a @file{startup.tcl} file internal to the server.
650 @item @b{Historical Note}
651 @* Jim-Tcl was introduced to OpenOCD in spring 2008. Fall 2010,
652 before OpenOCD 0.5 release, OpenOCD switched to using Jim-Tcl
653 as a Git submodule, which greatly simplified upgrading Jim-Tcl
654 to benefit from new features and bugfixes in Jim-Tcl.
656 @item @b{Need a crash course in Tcl?}
657 @*@xref{Tcl Crash Course}.
658 @end itemize
660 @node Running
661 @chapter Running
662 @cindex command line options
663 @cindex logfile
664 @cindex directory search
666 Properly installing OpenOCD sets up your operating system to grant it access
667 to the debug adapters. On Linux, this usually involves installing a file
668 in @file{/etc/udev/rules.d,} so OpenOCD has permissions. An example rules file
669 that works for many common adapters is shipped with OpenOCD in the
670 @file{contrib} directory. MS-Windows needs
671 complex and confusing driver configuration for every peripheral. Such issues
672 are unique to each operating system, and are not detailed in this User's Guide.
674 Then later you will invoke the OpenOCD server, with various options to
675 tell it how each debug session should work.
676 The @option{--help} option shows:
677 @verbatim
678 bash$ openocd --help
680 --help | -h display this help
681 --version | -v display OpenOCD version
682 --file | -f use configuration file <name>
683 --search | -s dir to search for config files and scripts
684 --debug | -d set debug level <0-3>
685 --log_output | -l redirect log output to file <name>
686 --command | -c run <command>
687 @end verbatim
689 If you don't give any @option{-f} or @option{-c} options,
690 OpenOCD tries to read the configuration file @file{openocd.cfg}.
691 To specify one or more different
692 configuration files, use @option{-f} options. For example:
694 @example
695 openocd -f config1.cfg -f config2.cfg -f config3.cfg
696 @end example
698 Configuration files and scripts are searched for in
699 @enumerate
700 @item the current directory,
701 @item any search dir specified on the command line using the @option{-s} option,
702 @item any search dir specified using the @command{add_script_search_dir} command,
703 @item @file{$HOME/.openocd} (not on Windows),
704 @item the site wide script library @file{$pkgdatadir/site} and
705 @item the OpenOCD-supplied script library @file{$pkgdatadir/scripts}.
706 @end enumerate
707 The first found file with a matching file name will be used.
709 @quotation Note
710 Don't try to use configuration script names or paths which
711 include the "#" character. That character begins Tcl comments.
712 @end quotation
714 @section Simple setup, no customization
716 In the best case, you can use two scripts from one of the script
717 libraries, hook up your JTAG adapter, and start the server ... and
718 your JTAG setup will just work "out of the box". Always try to
719 start by reusing those scripts, but assume you'll need more
720 customization even if this works. @xref{OpenOCD Project Setup}.
722 If you find a script for your JTAG adapter, and for your board or
723 target, you may be able to hook up your JTAG adapter then start
724 the server with some variation of one of the following:
726 @example
727 openocd -f interface/ADAPTER.cfg -f board/MYBOARD.cfg
728 openocd -f interface/ftdi/ADAPTER.cfg -f board/MYBOARD.cfg
729 @end example
731 You might also need to configure which reset signals are present,
732 using @option{-c 'reset_config trst_and_srst'} or something similar.
733 If all goes well you'll see output something like
735 @example
736 Open On-Chip Debugger 0.4.0 (2010-01-14-15:06)
737 For bug reports, read
738 http://openocd.sourceforge.net/doc/doxygen/bugs.html
739 Info : JTAG tap: lm3s.cpu tap/device found: 0x3ba00477
740 (mfg: 0x23b, part: 0xba00, ver: 0x3)
741 @end example
743 Seeing that "tap/device found" message, and no warnings, means
744 the JTAG communication is working. That's a key milestone, but
745 you'll probably need more project-specific setup.
747 @section What OpenOCD does as it starts
749 OpenOCD starts by processing the configuration commands provided
750 on the command line or, if there were no @option{-c command} or
751 @option{-f file.cfg} options given, in @file{openocd.cfg}.
752 @xref{configurationstage,,Configuration Stage}.
753 At the end of the configuration stage it verifies the JTAG scan
754 chain defined using those commands; your configuration should
755 ensure that this always succeeds.
756 Normally, OpenOCD then starts running as a daemon.
757 Alternatively, commands may be used to terminate the configuration
758 stage early, perform work (such as updating some flash memory),
759 and then shut down without acting as a daemon.
761 Once OpenOCD starts running as a daemon, it waits for connections from
762 clients (Telnet, GDB, Other) and processes the commands issued through
763 those channels.
765 If you are having problems, you can enable internal debug messages via
766 the @option{-d} option.
768 Also it is possible to interleave Jim-Tcl commands w/config scripts using the
769 @option{-c} command line switch.
771 To enable debug output (when reporting problems or working on OpenOCD
772 itself), use the @option{-d} command line switch. This sets the
773 @option{debug_level} to "3", outputting the most information,
774 including debug messages. The default setting is "2", outputting only
775 informational messages, warnings and errors. You can also change this
776 setting from within a telnet or gdb session using @command{debug_level<n>}
777 (@pxref{debuglevel,,debug_level}).
779 You can redirect all output from the daemon to a file using the
780 @option{-l <logfile>} switch.
782 Note! OpenOCD will launch the GDB & telnet server even if it can not
783 establish a connection with the target. In general, it is possible for
784 the JTAG controller to be unresponsive until the target is set up
785 correctly via e.g. GDB monitor commands in a GDB init script.
787 @node OpenOCD Project Setup
788 @chapter OpenOCD Project Setup
790 To use OpenOCD with your development projects, you need to do more than
791 just connect the JTAG adapter hardware (dongle) to your development board
792 and start the OpenOCD server.
793 You also need to configure your OpenOCD server so that it knows
794 about your adapter and board, and helps your work.
795 You may also want to connect OpenOCD to GDB, possibly
796 using Eclipse or some other GUI.
798 @section Hooking up the JTAG Adapter
800 Today's most common case is a dongle with a JTAG cable on one side
801 (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
802 and a USB cable on the other.
803 Instead of USB, some cables use Ethernet;
804 older ones may use a PC parallel port, or even a serial port.
806 @enumerate
807 @item @emph{Start with power to your target board turned off},
808 and nothing connected to your JTAG adapter.
809 If you're particularly paranoid, unplug power to the board.
810 It's important to have the ground signal properly set up,
811 unless you are using a JTAG adapter which provides
812 galvanic isolation between the target board and the
813 debugging host.
815 @item @emph{Be sure it's the right kind of JTAG connector.}
816 If your dongle has a 20-pin ARM connector, you need some kind
817 of adapter (or octopus, see below) to hook it up to
818 boards using 14-pin or 10-pin connectors ... or to 20-pin
819 connectors which don't use ARM's pinout.
821 In the same vein, make sure the voltage levels are compatible.
822 Not all JTAG adapters have the level shifters needed to work
823 with 1.2 Volt boards.
825 @item @emph{Be certain the cable is properly oriented} or you might
826 damage your board. In most cases there are only two possible
827 ways to connect the cable.
828 Connect the JTAG cable from your adapter to the board.
829 Be sure it's firmly connected.
831 In the best case, the connector is keyed to physically
832 prevent you from inserting it wrong.
833 This is most often done using a slot on the board's male connector
834 housing, which must match a key on the JTAG cable's female connector.
835 If there's no housing, then you must look carefully and
836 make sure pin 1 on the cable hooks up to pin 1 on the board.
837 Ribbon cables are frequently all grey except for a wire on one
838 edge, which is red. The red wire is pin 1.
840 Sometimes dongles provide cables where one end is an ``octopus'' of
841 color coded single-wire connectors, instead of a connector block.
842 These are great when converting from one JTAG pinout to another,
843 but are tedious to set up.
844 Use these with connector pinout diagrams to help you match up the
845 adapter signals to the right board pins.
847 @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
848 A USB, parallel, or serial port connector will go to the host which
849 you are using to run OpenOCD.
850 For Ethernet, consult the documentation and your network administrator.
852 For USB-based JTAG adapters you have an easy sanity check at this point:
853 does the host operating system see the JTAG adapter? If you're running
854 Linux, try the @command{lsusb} command. If that host is an
855 MS-Windows host, you'll need to install a driver before OpenOCD works.
857 @item @emph{Connect the adapter's power supply, if needed.}
858 This step is primarily for non-USB adapters,
859 but sometimes USB adapters need extra power.
861 @item @emph{Power up the target board.}
862 Unless you just let the magic smoke escape,
863 you're now ready to set up the OpenOCD server
864 so you can use JTAG to work with that board.
866 @end enumerate
868 Talk with the OpenOCD server using
869 telnet (@code{telnet localhost 4444} on many systems) or GDB.
870 @xref{GDB and OpenOCD}.
872 @section Project Directory
874 There are many ways you can configure OpenOCD and start it up.
876 A simple way to organize them all involves keeping a
877 single directory for your work with a given board.
878 When you start OpenOCD from that directory,
879 it searches there first for configuration files, scripts,
880 files accessed through semihosting,
881 and for code you upload to the target board.
882 It is also the natural place to write files,
883 such as log files and data you download from the board.
885 @section Configuration Basics
887 There are two basic ways of configuring OpenOCD, and
888 a variety of ways you can mix them.
889 Think of the difference as just being how you start the server:
891 @itemize
892 @item Many @option{-f file} or @option{-c command} options on the command line
893 @item No options, but a @dfn{user config file}
894 in the current directory named @file{openocd.cfg}
895 @end itemize
897 Here is an example @file{openocd.cfg} file for a setup
898 using a Signalyzer FT2232-based JTAG adapter to talk to
899 a board with an Atmel AT91SAM7X256 microcontroller:
901 @example
902 source [find interface/signalyzer.cfg]
904 # GDB can also flash my flash!
905 gdb_memory_map enable
906 gdb_flash_program enable
908 source [find target/sam7x256.cfg]
909 @end example
911 Here is the command line equivalent of that configuration:
913 @example
914 openocd -f interface/signalyzer.cfg \
915 -c "gdb_memory_map enable" \
916 -c "gdb_flash_program enable" \
917 -f target/sam7x256.cfg
918 @end example
920 You could wrap such long command lines in shell scripts,
921 each supporting a different development task.
922 One might re-flash the board with a specific firmware version.
923 Another might set up a particular debugging or run-time environment.
925 @quotation Important
926 At this writing (October 2009) the command line method has
927 problems with how it treats variables.
928 For example, after @option{-c "set VAR value"}, or doing the
929 same in a script, the variable @var{VAR} will have no value
930 that can be tested in a later script.
931 @end quotation
933 Here we will focus on the simpler solution: one user config
934 file, including basic configuration plus any TCL procedures
935 to simplify your work.
937 @section User Config Files
938 @cindex config file, user
939 @cindex user config file
940 @cindex config file, overview
942 A user configuration file ties together all the parts of a project
943 in one place.
944 One of the following will match your situation best:
946 @itemize
947 @item Ideally almost everything comes from configuration files
948 provided by someone else.
949 For example, OpenOCD distributes a @file{scripts} directory
950 (probably in @file{/usr/share/openocd/scripts} on Linux).
951 Board and tool vendors can provide these too, as can individual
952 user sites; the @option{-s} command line option lets you say
953 where to find these files. (@xref{Running}.)
954 The AT91SAM7X256 example above works this way.
956 Three main types of non-user configuration file each have their
957 own subdirectory in the @file{scripts} directory:
959 @enumerate
960 @item @b{interface} -- one for each different debug adapter;
961 @item @b{board} -- one for each different board
962 @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
963 @end enumerate
965 Best case: include just two files, and they handle everything else.
966 The first is an interface config file.
967 The second is board-specific, and it sets up the JTAG TAPs and
968 their GDB targets (by deferring to some @file{target.cfg} file),
969 declares all flash memory, and leaves you nothing to do except
970 meet your deadline:
972 @example
973 source [find interface/olimex-jtag-tiny.cfg]
974 source [find board/csb337.cfg]
975 @end example
977 Boards with a single microcontroller often won't need more
978 than the target config file, as in the AT91SAM7X256 example.
979 That's because there is no external memory (flash, DDR RAM), and
980 the board differences are encapsulated by application code.
982 @item Maybe you don't know yet what your board looks like to JTAG.
983 Once you know the @file{interface.cfg} file to use, you may
984 need help from OpenOCD to discover what's on the board.
985 Once you find the JTAG TAPs, you can just search for appropriate
986 target and board
987 configuration files ... or write your own, from the bottom up.
988 @xref{autoprobing,,Autoprobing}.
990 @item You can often reuse some standard config files but
991 need to write a few new ones, probably a @file{board.cfg} file.
992 You will be using commands described later in this User's Guide,
993 and working with the guidelines in the next chapter.
995 For example, there may be configuration files for your JTAG adapter
996 and target chip, but you need a new board-specific config file
997 giving access to your particular flash chips.
998 Or you might need to write another target chip configuration file
999 for a new chip built around the Cortex M3 core.
1001 @quotation Note
1002 When you write new configuration files, please submit
1003 them for inclusion in the next OpenOCD release.
1004 For example, a @file{board/newboard.cfg} file will help the
1005 next users of that board, and a @file{target/newcpu.cfg}
1006 will help support users of any board using that chip.
1007 @end quotation
1009 @item
1010 You may may need to write some C code.
1011 It may be as simple as supporting a new FT2232 or parport
1012 based adapter; a bit more involved, like a NAND or NOR flash
1013 controller driver; or a big piece of work like supporting
1014 a new chip architecture.
1015 @end itemize
1017 Reuse the existing config files when you can.
1018 Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
1019 You may find a board configuration that's a good example to follow.
1021 When you write config files, separate the reusable parts
1022 (things every user of that interface, chip, or board needs)
1023 from ones specific to your environment and debugging approach.
1024 @itemize
1026 @item
1027 For example, a @code{gdb-attach} event handler that invokes
1028 the @command{reset init} command will interfere with debugging
1029 early boot code, which performs some of the same actions
1030 that the @code{reset-init} event handler does.
1032 @item
1033 Likewise, the @command{arm9 vector_catch} command (or
1034 @cindex vector_catch
1035 its siblings @command{xscale vector_catch}
1036 and @command{cortex_m vector_catch}) can be a timesaver
1037 during some debug sessions, but don't make everyone use that either.
1038 Keep those kinds of debugging aids in your user config file,
1039 along with messaging and tracing setup.
1040 (@xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.)
1042 @item
1043 You might need to override some defaults.
1044 For example, you might need to move, shrink, or back up the target's
1045 work area if your application needs much SRAM.
1047 @item
1048 TCP/IP port configuration is another example of something which
1049 is environment-specific, and should only appear in
1050 a user config file. @xref{tcpipports,,TCP/IP Ports}.
1051 @end itemize
1053 @section Project-Specific Utilities
1055 A few project-specific utility
1056 routines may well speed up your work.
1057 Write them, and keep them in your project's user config file.
1059 For example, if you are making a boot loader work on a
1060 board, it's nice to be able to debug the ``after it's
1061 loaded to RAM'' parts separately from the finicky early
1062 code which sets up the DDR RAM controller and clocks.
1063 A script like this one, or a more GDB-aware sibling,
1064 may help:
1066 @example
1067 proc ramboot @{ @} @{
1068 # Reset, running the target's "reset-init" scripts
1069 # to initialize clocks and the DDR RAM controller.
1070 # Leave the CPU halted.
1071 reset init
1073 # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
1074 load_image u-boot.bin 0x20000000
1076 # Start running.
1077 resume 0x20000000
1078 @}
1079 @end example
1081 Then once that code is working you will need to make it
1082 boot from NOR flash; a different utility would help.
1083 Alternatively, some developers write to flash using GDB.
1084 (You might use a similar script if you're working with a flash
1085 based microcontroller application instead of a boot loader.)
1087 @example
1088 proc newboot @{ @} @{
1089 # Reset, leaving the CPU halted. The "reset-init" event
1090 # proc gives faster access to the CPU and to NOR flash;
1091 # "reset halt" would be slower.
1092 reset init
1094 # Write standard version of U-Boot into the first two
1095 # sectors of NOR flash ... the standard version should
1096 # do the same lowlevel init as "reset-init".
1097 flash protect 0 0 1 off
1098 flash erase_sector 0 0 1
1099 flash write_bank 0 u-boot.bin 0x0
1100 flash protect 0 0 1 on
1102 # Reboot from scratch using that new boot loader.
1103 reset run
1104 @}
1105 @end example
1107 You may need more complicated utility procedures when booting
1108 from NAND.
1109 That often involves an extra bootloader stage,
1110 running from on-chip SRAM to perform DDR RAM setup so it can load
1111 the main bootloader code (which won't fit into that SRAM).
1113 Other helper scripts might be used to write production system images,
1114 involving considerably more than just a three stage bootloader.
1116 @section Target Software Changes
1118 Sometimes you may want to make some small changes to the software
1119 you're developing, to help make JTAG debugging work better.
1120 For example, in C or assembly language code you might
1121 use @code{#ifdef JTAG_DEBUG} (or its converse) around code
1122 handling issues like:
1124 @itemize @bullet
1126 @item @b{Watchdog Timers}...
1127 Watchog timers are typically used to automatically reset systems if
1128 some application task doesn't periodically reset the timer. (The
1129 assumption is that the system has locked up if the task can't run.)
1130 When a JTAG debugger halts the system, that task won't be able to run
1131 and reset the timer ... potentially causing resets in the middle of
1132 your debug sessions.
1134 It's rarely a good idea to disable such watchdogs, since their usage
1135 needs to be debugged just like all other parts of your firmware.
1136 That might however be your only option.
1138 Look instead for chip-specific ways to stop the watchdog from counting
1139 while the system is in a debug halt state. It may be simplest to set
1140 that non-counting mode in your debugger startup scripts. You may however
1141 need a different approach when, for example, a motor could be physically
1142 damaged by firmware remaining inactive in a debug halt state. That might
1143 involve a type of firmware mode where that "non-counting" mode is disabled
1144 at the beginning then re-enabled at the end; a watchdog reset might fire
1145 and complicate the debug session, but hardware (or people) would be
1146 protected.@footnote{Note that many systems support a "monitor mode" debug
1147 that is a somewhat cleaner way to address such issues. You can think of
1148 it as only halting part of the system, maybe just one task,
1149 instead of the whole thing.
1150 At this writing, January 2010, OpenOCD based debugging does not support
1151 monitor mode debug, only "halt mode" debug.}
1153 @item @b{ARM Semihosting}...
1154 @cindex ARM semihosting
1155 When linked with a special runtime library provided with many
1156 toolchains@footnote{See chapter 8 "Semihosting" in
1157 @uref{http://infocenter.arm.com/help/topic/com.arm.doc.dui0203i/DUI0203I_rvct_developer_guide.pdf,
1158 ARM DUI 0203I}, the "RealView Compilation Tools Developer Guide".
1159 The CodeSourcery EABI toolchain also includes a semihosting library.},
1160 your target code can use I/O facilities on the debug host. That library
1161 provides a small set of system calls which are handled by OpenOCD.
1162 It can let the debugger provide your system console and a file system,
1163 helping with early debugging or providing a more capable environment
1164 for sometimes-complex tasks like installing system firmware onto
1165 NAND or SPI flash.
1167 @item @b{ARM Wait-For-Interrupt}...
1168 Many ARM chips synchronize the JTAG clock using the core clock.
1169 Low power states which stop that core clock thus prevent JTAG access.
1170 Idle loops in tasking environments often enter those low power states
1171 via the @code{WFI} instruction (or its coprocessor equivalent, before ARMv7).
1173 You may want to @emph{disable that instruction} in source code,
1174 or otherwise prevent using that state,
1175 to ensure you can get JTAG access at any time.@footnote{As a more
1176 polite alternative, some processors have special debug-oriented
1177 registers which can be used to change various features including
1178 how the low power states are clocked while debugging.
1179 The STM32 DBGMCU_CR register is an example; at the cost of extra
1180 power consumption, JTAG can be used during low power states.}
1181 For example, the OpenOCD @command{halt} command may not
1182 work for an idle processor otherwise.
1184 @item @b{Delay after reset}...
1185 Not all chips have good support for debugger access
1186 right after reset; many LPC2xxx chips have issues here.
1187 Similarly, applications that reconfigure pins used for
1188 JTAG access as they start will also block debugger access.
1190 To work with boards like this, @emph{enable a short delay loop}
1191 the first thing after reset, before "real" startup activities.
1192 For example, one second's delay is usually more than enough
1193 time for a JTAG debugger to attach, so that
1194 early code execution can be debugged
1195 or firmware can be replaced.
1197 @item @b{Debug Communications Channel (DCC)}...
1198 Some processors include mechanisms to send messages over JTAG.
1199 Many ARM cores support these, as do some cores from other vendors.
1200 (OpenOCD may be able to use this DCC internally, speeding up some
1201 operations like writing to memory.)
1203 Your application may want to deliver various debugging messages
1204 over JTAG, by @emph{linking with a small library of code}
1205 provided with OpenOCD and using the utilities there to send
1206 various kinds of message.
1207 @xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.
1209 @end itemize
1211 @section Target Hardware Setup
1213 Chip vendors often provide software development boards which
1214 are highly configurable, so that they can support all options
1215 that product boards may require. @emph{Make sure that any
1216 jumpers or switches match the system configuration you are
1217 working with.}
1219 Common issues include:
1221 @itemize @bullet
1223 @item @b{JTAG setup} ...
1224 Boards may support more than one JTAG configuration.
1225 Examples include jumpers controlling pullups versus pulldowns
1226 on the nTRST and/or nSRST signals, and choice of connectors
1227 (e.g. which of two headers on the base board,
1228 or one from a daughtercard).
1229 For some Texas Instruments boards, you may need to jumper the
1230 EMU0 and EMU1 signals (which OpenOCD won't currently control).
1232 @item @b{Boot Modes} ...
1233 Complex chips often support multiple boot modes, controlled
1234 by external jumpers. Make sure this is set up correctly.
1235 For example many i.MX boards from NXP need to be jumpered
1236 to "ATX mode" to start booting using the on-chip ROM, when
1237 using second stage bootloader code stored in a NAND flash chip.
1239 Such explicit configuration is common, and not limited to
1240 booting from NAND. You might also need to set jumpers to
1241 start booting using code loaded from an MMC/SD card; external
1242 SPI flash; Ethernet, UART, or USB links; NOR flash; OneNAND
1243 flash; some external host; or various other sources.
1246 @item @b{Memory Addressing} ...
1247 Boards which support multiple boot modes may also have jumpers
1248 to configure memory addressing. One board, for example, jumpers
1249 external chipselect 0 (used for booting) to address either
1250 a large SRAM (which must be pre-loaded via JTAG), NOR flash,
1251 or NAND flash. When it's jumpered to address NAND flash, that
1252 board must also be told to start booting from on-chip ROM.
1254 Your @file{board.cfg} file may also need to be told this jumper
1255 configuration, so that it can know whether to declare NOR flash
1256 using @command{flash bank} or instead declare NAND flash with
1257 @command{nand device}; and likewise which probe to perform in
1258 its @code{reset-init} handler.
1260 A closely related issue is bus width. Jumpers might need to
1261 distinguish between 8 bit or 16 bit bus access for the flash
1262 used to start booting.
1264 @item @b{Peripheral Access} ...
1265 Development boards generally provide access to every peripheral
1266 on the chip, sometimes in multiple modes (such as by providing
1267 multiple audio codec chips).
1268 This interacts with software
1269 configuration of pin multiplexing, where for example a
1270 given pin may be routed either to the MMC/SD controller
1271 or the GPIO controller. It also often interacts with
1272 configuration jumpers. One jumper may be used to route
1273 signals to an MMC/SD card slot or an expansion bus (which
1274 might in turn affect booting); others might control which
1275 audio or video codecs are used.
1277 @end itemize
1279 Plus you should of course have @code{reset-init} event handlers
1280 which set up the hardware to match that jumper configuration.
1281 That includes in particular any oscillator or PLL used to clock
1282 the CPU, and any memory controllers needed to access external
1283 memory and peripherals. Without such handlers, you won't be
1284 able to access those resources without working target firmware
1285 which can do that setup ... this can be awkward when you're
1286 trying to debug that target firmware. Even if there's a ROM
1287 bootloader which handles a few issues, it rarely provides full
1288 access to all board-specific capabilities.
1291 @node Config File Guidelines
1292 @chapter Config File Guidelines
1294 This chapter is aimed at any user who needs to write a config file,
1295 including developers and integrators of OpenOCD and any user who
1296 needs to get a new board working smoothly.
1297 It provides guidelines for creating those files.
1299 You should find the following directories under @t{$(INSTALLDIR)/scripts},
1300 with files including the ones listed here.
1301 Use them as-is where you can; or as models for new files.
1302 @itemize @bullet
1303 @item @file{interface} ...
1304 These are for debug adapters.
1305 Files that configure JTAG adapters go here.
1306 @example
1307 $ ls interface -R
1308 interface/:
1309 altera-usb-blaster.cfg hilscher_nxhx50_re.cfg openocd-usb-hs.cfg
1310 arm-jtag-ew.cfg hitex_str9-comstick.cfg openrd.cfg
1311 at91rm9200.cfg icebear.cfg osbdm.cfg
1312 axm0432.cfg jlink.cfg parport.cfg
1313 busblaster.cfg jtagkey2.cfg parport_dlc5.cfg
1314 buspirate.cfg jtagkey2p.cfg redbee-econotag.cfg
1315 calao-usb-a9260-c01.cfg jtagkey.cfg redbee-usb.cfg
1316 calao-usb-a9260-c02.cfg jtagkey-tiny.cfg rlink.cfg
1317 calao-usb-a9260.cfg jtag-lock-pick_tiny_2.cfg sheevaplug.cfg
1318 chameleon.cfg kt-link.cfg signalyzer.cfg
1319 cortino.cfg lisa-l.cfg signalyzer-h2.cfg
1320 digilent-hs1.cfg luminary.cfg signalyzer-h4.cfg
1321 dlp-usb1232h.cfg luminary-icdi.cfg signalyzer-lite.cfg
1322 dummy.cfg luminary-lm3s811.cfg stlink-v1.cfg
1323 estick.cfg minimodule.cfg stlink-v2.cfg
1324 flashlink.cfg neodb.cfg stm32-stick.cfg
1325 flossjtag.cfg ngxtech.cfg sysfsgpio-raspberrypi.cfg
1326 flossjtag-noeeprom.cfg olimex-arm-usb-ocd.cfg ti-icdi.cfg
1327 flyswatter2.cfg olimex-arm-usb-ocd-h.cfg turtelizer2.cfg
1328 flyswatter.cfg olimex-arm-usb-tiny-h.cfg ulink.cfg
1329 ftdi olimex-jtag-tiny.cfg usb-jtag.cfg
1330 hilscher_nxhx10_etm.cfg oocdlink.cfg usbprog.cfg
1331 hilscher_nxhx500_etm.cfg opendous.cfg vpaclink.cfg
1332 hilscher_nxhx500_re.cfg opendous_ftdi.cfg vsllink.cfg
1333 hilscher_nxhx50_etm.cfg openocd-usb.cfg xds100v2.cfg
1335 interface/ftdi:
1336 axm0432.cfg hitex_str9-comstick.cfg olimex-jtag-tiny.cfg
1337 calao-usb-a9260-c01.cfg icebear.cfg oocdlink.cfg
1338 calao-usb-a9260-c02.cfg jtagkey2.cfg opendous_ftdi.cfg
1339 cortino.cfg jtagkey2p.cfg openocd-usb.cfg
1340 dlp-usb1232h.cfg jtagkey.cfg openocd-usb-hs.cfg
1341 dp_busblaster.cfg jtag-lock-pick_tiny_2.cfg openrd.cfg
1342 flossjtag.cfg kt-link.cfg redbee-econotag.cfg
1343 flossjtag-noeeprom.cfg lisa-l.cfg redbee-usb.cfg
1344 flyswatter2.cfg luminary.cfg sheevaplug.cfg
1345 flyswatter.cfg luminary-icdi.cfg signalyzer.cfg
1346 gw16042.cfg luminary-lm3s811.cfg signalyzer-lite.cfg
1347 hilscher_nxhx10_etm.cfg minimodule.cfg stm32-stick.cfg
1348 hilscher_nxhx500_etm.cfg neodb.cfg turtelizer2-revB.cfg
1349 hilscher_nxhx500_re.cfg ngxtech.cfg turtelizer2-revC.cfg
1350 hilscher_nxhx50_etm.cfg olimex-arm-usb-ocd.cfg vpaclink.cfg
1351 hilscher_nxhx50_re.cfg olimex-arm-usb-ocd-h.cfg xds100v2.cfg
1352 hitex_lpc1768stick.cfg olimex-arm-usb-tiny-h.cfg
1353 $
1354 @end example
1355 @item @file{board} ...
1356 think Circuit Board, PWA, PCB, they go by many names. Board files
1357 contain initialization items that are specific to a board.
1358 They reuse target configuration files, since the same
1359 microprocessor chips are used on many boards,
1360 but support for external parts varies widely. For
1361 example, the SDRAM initialization sequence for the board, or the type
1362 of external flash and what address it uses. Any initialization
1363 sequence to enable that external flash or SDRAM should be found in the
1364 board file. Boards may also contain multiple targets: two CPUs; or
1365 a CPU and an FPGA.
1366 @example
1367 $ ls board
1368 actux3.cfg lpc1850_spifi_generic.cfg
1369 am3517evm.cfg lpc4350_spifi_generic.cfg
1370 arm_evaluator7t.cfg lubbock.cfg
1371 at91cap7a-stk-sdram.cfg mcb1700.cfg
1372 at91eb40a.cfg microchip_explorer16.cfg
1373 at91rm9200-dk.cfg mini2440.cfg
1374 at91rm9200-ek.cfg mini6410.cfg
1375 at91sam9261-ek.cfg netgear-dg834v3.cfg
1376 at91sam9263-ek.cfg olimex_LPC2378STK.cfg
1377 at91sam9g20-ek.cfg olimex_lpc_h2148.cfg
1378 atmel_at91sam7s-ek.cfg olimex_sam7_ex256.cfg
1379 atmel_at91sam9260-ek.cfg olimex_sam9_l9260.cfg
1380 atmel_at91sam9rl-ek.cfg olimex_stm32_h103.cfg
1381 atmel_sam3n_ek.cfg olimex_stm32_h107.cfg
1382 atmel_sam3s_ek.cfg olimex_stm32_p107.cfg
1383 atmel_sam3u_ek.cfg omap2420_h4.cfg
1384 atmel_sam3x_ek.cfg open-bldc.cfg
1385 atmel_sam4s_ek.cfg openrd.cfg
1386 balloon3-cpu.cfg osk5912.cfg
1387 colibri.cfg phone_se_j100i.cfg
1388 crossbow_tech_imote2.cfg phytec_lpc3250.cfg
1389 csb337.cfg pic-p32mx.cfg
1390 csb732.cfg propox_mmnet1001.cfg
1391 da850evm.cfg pxa255_sst.cfg
1392 digi_connectcore_wi-9c.cfg redbee.cfg
1393 diolan_lpc4350-db1.cfg rsc-w910.cfg
1394 dm355evm.cfg sheevaplug.cfg
1395 dm365evm.cfg smdk6410.cfg
1396 dm6446evm.cfg spear300evb.cfg
1397 efikamx.cfg spear300evb_mod.cfg
1398 eir.cfg spear310evb20.cfg
1399 ek-lm3s1968.cfg spear310evb20_mod.cfg
1400 ek-lm3s3748.cfg spear320cpu.cfg
1401 ek-lm3s6965.cfg spear320cpu_mod.cfg
1402 ek-lm3s811.cfg steval_pcc010.cfg
1403 ek-lm3s811-revb.cfg stm320518_eval_stlink.cfg
1404 ek-lm3s8962.cfg stm32100b_eval.cfg
1405 ek-lm3s9b9x.cfg stm3210b_eval.cfg
1406 ek-lm3s9d92.cfg stm3210c_eval.cfg
1407 ek-lm4f120xl.cfg stm3210e_eval.cfg
1408 ek-lm4f232.cfg stm3220g_eval.cfg
1409 embedded-artists_lpc2478-32.cfg stm3220g_eval_stlink.cfg
1410 ethernut3.cfg stm3241g_eval.cfg
1411 glyn_tonga2.cfg stm3241g_eval_stlink.cfg
1412 hammer.cfg stm32f0discovery.cfg
1413 hilscher_nxdb500sys.cfg stm32f3discovery.cfg
1414 hilscher_nxeb500hmi.cfg stm32f4discovery.cfg
1415 hilscher_nxhx10.cfg stm32ldiscovery.cfg
1416 hilscher_nxhx500.cfg stm32vldiscovery.cfg
1417 hilscher_nxhx50.cfg str910-eval.cfg
1418 hilscher_nxsb100.cfg telo.cfg
1419 hitex_lpc1768stick.cfg ti_am335xevm.cfg
1420 hitex_lpc2929.cfg ti_beagleboard.cfg
1421 hitex_stm32-performancestick.cfg ti_beagleboard_xm.cfg
1422 hitex_str9-comstick.cfg ti_beaglebone.cfg
1423 iar_lpc1768.cfg ti_blaze.cfg
1424 iar_str912_sk.cfg ti_pandaboard.cfg
1425 icnova_imx53_sodimm.cfg ti_pandaboard_es.cfg
1426 icnova_sam9g45_sodimm.cfg topas910.cfg
1427 imx27ads.cfg topasa900.cfg
1428 imx27lnst.cfg twr-k60f120m.cfg
1429 imx28evk.cfg twr-k60n512.cfg
1430 imx31pdk.cfg tx25_stk5.cfg
1431 imx35pdk.cfg tx27_stk5.cfg
1432 imx53loco.cfg unknown_at91sam9260.cfg
1433 keil_mcb1700.cfg uptech_2410.cfg
1434 keil_mcb2140.cfg verdex.cfg
1435 kwikstik.cfg voipac.cfg
1436 linksys_nslu2.cfg voltcraft_dso-3062c.cfg
1437 lisa-l.cfg x300t.cfg
1438 logicpd_imx27.cfg zy1000.cfg
1439 $
1440 @end example
1441 @item @file{target} ...
1442 think chip. The ``target'' directory represents the JTAG TAPs
1443 on a chip
1444 which OpenOCD should control, not a board. Two common types of targets
1445 are ARM chips and FPGA or CPLD chips.
1446 When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
1447 the target config file defines all of them.
1448 @example
1449 $ ls target
1450 aduc702x.cfg lpc1764.cfg
1451 am335x.cfg lpc1765.cfg
1452 amdm37x.cfg lpc1766.cfg
1453 ar71xx.cfg lpc1767.cfg
1454 at32ap7000.cfg lpc1768.cfg
1455 at91r40008.cfg lpc1769.cfg
1456 at91rm9200.cfg lpc1788.cfg
1457 at91sam3ax_4x.cfg lpc17xx.cfg
1458 at91sam3ax_8x.cfg lpc1850.cfg
1459 at91sam3ax_xx.cfg lpc2103.cfg
1460 at91sam3nXX.cfg lpc2124.cfg
1461 at91sam3sXX.cfg lpc2129.cfg
1462 at91sam3u1c.cfg lpc2148.cfg
1463 at91sam3u1e.cfg lpc2294.cfg
1464 at91sam3u2c.cfg lpc2378.cfg
1465 at91sam3u2e.cfg lpc2460.cfg
1466 at91sam3u4c.cfg lpc2478.cfg
1467 at91sam3u4e.cfg lpc2900.cfg
1468 at91sam3uxx.cfg lpc2xxx.cfg
1469 at91sam3XXX.cfg lpc3131.cfg
1470 at91sam4sd32x.cfg lpc3250.cfg
1471 at91sam4sXX.cfg lpc4350.cfg
1472 at91sam4XXX.cfg lpc4350.cfg.orig
1473 at91sam7se512.cfg mc13224v.cfg
1474 at91sam7sx.cfg nuc910.cfg
1475 at91sam7x256.cfg omap2420.cfg
1476 at91sam7x512.cfg omap3530.cfg
1477 at91sam9260.cfg omap4430.cfg
1478 at91sam9260_ext_RAM_ext_flash.cfg omap4460.cfg
1479 at91sam9261.cfg omap5912.cfg
1480 at91sam9263.cfg omapl138.cfg
1481 at91sam9.cfg pic32mx.cfg
1482 at91sam9g10.cfg pxa255.cfg
1483 at91sam9g20.cfg pxa270.cfg
1484 at91sam9g45.cfg pxa3xx.cfg
1485 at91sam9rl.cfg readme.txt
1486 atmega128.cfg samsung_s3c2410.cfg
1487 avr32.cfg samsung_s3c2440.cfg
1488 c100.cfg samsung_s3c2450.cfg
1489 c100config.tcl samsung_s3c4510.cfg
1490 c100helper.tcl samsung_s3c6410.cfg
1491 c100regs.tcl sharp_lh79532.cfg
1492 cs351x.cfg sim3x.cfg
1493 davinci.cfg smp8634.cfg
1494 dragonite.cfg spear3xx.cfg
1495 dsp56321.cfg stellaris.cfg
1496 dsp568013.cfg stellaris_icdi.cfg
1497 dsp568037.cfg stm32f0x_stlink.cfg
1498 efm32_stlink.cfg stm32f1x.cfg
1499 epc9301.cfg stm32f1x_stlink.cfg
1500 faux.cfg stm32f2x.cfg
1501 feroceon.cfg stm32f2x_stlink.cfg
1502 fm3.cfg stm32f3x.cfg
1503 hilscher_netx10.cfg stm32f3x_stlink.cfg
1504 hilscher_netx500.cfg stm32f4x.cfg
1505 hilscher_netx50.cfg stm32f4x_stlink.cfg
1506 icepick.cfg stm32l.cfg
1507 imx21.cfg stm32lx_dual_bank.cfg
1508 imx25.cfg stm32lx_stlink.cfg
1509 imx27.cfg stm32_stlink.cfg
1510 imx28.cfg stm32w108_stlink.cfg
1511 imx31.cfg stm32xl.cfg
1512 imx35.cfg str710.cfg
1513 imx51.cfg str730.cfg
1514 imx53.cfg str750.cfg
1515 imx6.cfg str912.cfg
1516 imx.cfg swj-dp.tcl
1517 is5114.cfg test_reset_syntax_error.cfg
1518 ixp42x.cfg test_syntax_error.cfg
1519 k40.cfg ti-ar7.cfg
1520 k60.cfg ti_calypso.cfg
1521 lpc1751.cfg ti_dm355.cfg
1522 lpc1752.cfg ti_dm365.cfg
1523 lpc1754.cfg ti_dm6446.cfg
1524 lpc1756.cfg tmpa900.cfg
1525 lpc1758.cfg tmpa910.cfg
1526 lpc1759.cfg u8500.cfg
1527 lpc1763.cfg
1528 @end example
1529 @item @emph{more} ... browse for other library files which may be useful.
1530 For example, there are various generic and CPU-specific utilities.
1531 @end itemize
1533 The @file{openocd.cfg} user config
1534 file may override features in any of the above files by
1535 setting variables before sourcing the target file, or by adding
1536 commands specific to their situation.
1538 @section Interface Config Files
1540 The user config file
1541 should be able to source one of these files with a command like this:
1543 @example
1544 source [find interface/FOOBAR.cfg]
1545 @end example
1547 A preconfigured interface file should exist for every debug adapter
1548 in use today with OpenOCD.
1549 That said, perhaps some of these config files
1550 have only been used by the developer who created it.
1552 A separate chapter gives information about how to set these up.
1553 @xref{Debug Adapter Configuration}.
1554 Read the OpenOCD source code (and Developer's Guide)
1555 if you have a new kind of hardware interface
1556 and need to provide a driver for it.
1558 @section Board Config Files
1559 @cindex config file, board
1560 @cindex board config file
1562 The user config file
1563 should be able to source one of these files with a command like this:
1565 @example
1566 source [find board/FOOBAR.cfg]
1567 @end example
1569 The point of a board config file is to package everything
1570 about a given board that user config files need to know.
1571 In summary the board files should contain (if present)
1573 @enumerate
1574 @item One or more @command{source [find target/...cfg]} statements
1575 @item NOR flash configuration (@pxref{norconfiguration,,NOR Configuration})
1576 @item NAND flash configuration (@pxref{nandconfiguration,,NAND Configuration})
1577 @item Target @code{reset} handlers for SDRAM and I/O configuration
1578 @item JTAG adapter reset configuration (@pxref{Reset Configuration})
1579 @item All things that are not ``inside a chip''
1580 @end enumerate
1582 Generic things inside target chips belong in target config files,
1583 not board config files. So for example a @code{reset-init} event
1584 handler should know board-specific oscillator and PLL parameters,
1585 which it passes to target-specific utility code.
1587 The most complex task of a board config file is creating such a
1588 @code{reset-init} event handler.
1589 Define those handlers last, after you verify the rest of the board
1590 configuration works.
1592 @subsection Communication Between Config files
1594 In addition to target-specific utility code, another way that
1595 board and target config files communicate is by following a
1596 convention on how to use certain variables.
1598 The full Tcl/Tk language supports ``namespaces'', but Jim-Tcl does not.
1599 Thus the rule we follow in OpenOCD is this: Variables that begin with
1600 a leading underscore are temporary in nature, and can be modified and
1601 used at will within a target configuration file.
1603 Complex board config files can do the things like this,
1604 for a board with three chips:
1606 @example
1607 # Chip #1: PXA270 for network side, big endian
1608 set CHIPNAME network
1609 set ENDIAN big
1610 source [find target/pxa270.cfg]
1611 # on return: _TARGETNAME = network.cpu
1612 # other commands can refer to the "network.cpu" target.
1613 $_TARGETNAME configure .... events for this CPU..
1615 # Chip #2: PXA270 for video side, little endian
1616 set CHIPNAME video
1617 set ENDIAN little
1618 source [find target/pxa270.cfg]
1619 # on return: _TARGETNAME = video.cpu
1620 # other commands can refer to the "video.cpu" target.
1621 $_TARGETNAME configure .... events for this CPU..
1623 # Chip #3: Xilinx FPGA for glue logic
1624 set CHIPNAME xilinx
1625 unset ENDIAN
1626 source [find target/spartan3.cfg]
1627 @end example
1629 That example is oversimplified because it doesn't show any flash memory,
1630 or the @code{reset-init} event handlers to initialize external DRAM
1631 or (assuming it needs it) load a configuration into the FPGA.
1632 Such features are usually needed for low-level work with many boards,
1633 where ``low level'' implies that the board initialization software may
1634 not be working. (That's a common reason to need JTAG tools. Another
1635 is to enable working with microcontroller-based systems, which often
1636 have no debugging support except a JTAG connector.)
1638 Target config files may also export utility functions to board and user
1639 config files. Such functions should use name prefixes, to help avoid
1640 naming collisions.
1642 Board files could also accept input variables from user config files.
1643 For example, there might be a @code{J4_JUMPER} setting used to identify
1644 what kind of flash memory a development board is using, or how to set
1645 up other clocks and peripherals.
1647 @subsection Variable Naming Convention
1648 @cindex variable names
1650 Most boards have only one instance of a chip.
1651 However, it should be easy to create a board with more than
1652 one such chip (as shown above).
1653 Accordingly, we encourage these conventions for naming
1654 variables associated with different @file{target.cfg} files,
1655 to promote consistency and
1656 so that board files can override target defaults.
1658 Inputs to target config files include:
1660 @itemize @bullet
1661 @item @code{CHIPNAME} ...
1662 This gives a name to the overall chip, and is used as part of
1663 tap identifier dotted names.
1664 While the default is normally provided by the chip manufacturer,
1665 board files may need to distinguish between instances of a chip.
1666 @item @code{ENDIAN} ...
1667 By default @option{little} - although chips may hard-wire @option{big}.
1668 Chips that can't change endianness don't need to use this variable.
1669 @item @code{CPUTAPID} ...
1670 When OpenOCD examines the JTAG chain, it can be told verify the
1671 chips against the JTAG IDCODE register.
1672 The target file will hold one or more defaults, but sometimes the
1673 chip in a board will use a different ID (perhaps a newer revision).
1674 @end itemize
1676 Outputs from target config files include:
1678 @itemize @bullet
1679 @item @code{_TARGETNAME} ...
1680 By convention, this variable is created by the target configuration
1681 script. The board configuration file may make use of this variable to
1682 configure things like a ``reset init'' script, or other things
1683 specific to that board and that target.
1684 If the chip has 2 targets, the names are @code{_TARGETNAME0},
1685 @code{_TARGETNAME1}, ... etc.
1686 @end itemize
1688 @subsection The reset-init Event Handler
1689 @cindex event, reset-init
1690 @cindex reset-init handler
1692 Board config files run in the OpenOCD configuration stage;
1693 they can't use TAPs or targets, since they haven't been
1694 fully set up yet.
1695 This means you can't write memory or access chip registers;
1696 you can't even verify that a flash chip is present.
1697 That's done later in event handlers, of which the target @code{reset-init}
1698 handler is one of the most important.
1700 Except on microcontrollers, the basic job of @code{reset-init} event
1701 handlers is setting up flash and DRAM, as normally handled by boot loaders.
1702 Microcontrollers rarely use boot loaders; they run right out of their
1703 on-chip flash and SRAM memory. But they may want to use one of these
1704 handlers too, if just for developer convenience.
1706 @quotation Note
1707 Because this is so very board-specific, and chip-specific, no examples
1708 are included here.
1709 Instead, look at the board config files distributed with OpenOCD.
1710 If you have a boot loader, its source code will help; so will
1711 configuration files for other JTAG tools
1712 (@pxref{translatingconfigurationfiles,,Translating Configuration Files}).
1713 @end quotation
1715 Some of this code could probably be shared between different boards.
1716 For example, setting up a DRAM controller often doesn't differ by
1717 much except the bus width (16 bits or 32?) and memory timings, so a
1718 reusable TCL procedure loaded by the @file{target.cfg} file might take
1719 those as parameters.
1720 Similarly with oscillator, PLL, and clock setup;
1721 and disabling the watchdog.
1722 Structure the code cleanly, and provide comments to help
1723 the next developer doing such work.
1724 (@emph{You might be that next person} trying to reuse init code!)
1726 The last thing normally done in a @code{reset-init} handler is probing
1727 whatever flash memory was configured. For most chips that needs to be
1728 done while the associated target is halted, either because JTAG memory
1729 access uses the CPU or to prevent conflicting CPU access.
1731 @subsection JTAG Clock Rate
1733 Before your @code{reset-init} handler has set up
1734 the PLLs and clocking, you may need to run with
1735 a low JTAG clock rate.
1736 @xref{jtagspeed,,JTAG Speed}.
1737 Then you'd increase that rate after your handler has
1738 made it possible to use the faster JTAG clock.
1739 When the initial low speed is board-specific, for example
1740 because it depends on a board-specific oscillator speed, then
1741 you should probably set it up in the board config file;
1742 if it's target-specific, it belongs in the target config file.
1744 For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
1745 @uref{http://www.arm.com/support/faqdev/4170.html} gives details.}
1746 is one sixth of the CPU clock; or one eighth for ARM11 cores.
1747 Consult chip documentation to determine the peak JTAG clock rate,
1748 which might be less than that.
1750 @quotation Warning
1751 On most ARMs, JTAG clock detection is coupled to the core clock, so
1752 software using a @option{wait for interrupt} operation blocks JTAG access.
1753 Adaptive clocking provides a partial workaround, but a more complete
1754 solution just avoids using that instruction with JTAG debuggers.
1755 @end quotation
1757 If both the chip and the board support adaptive clocking,
1758 use the @command{jtag_rclk}
1759 command, in case your board is used with JTAG adapter which
1760 also supports it. Otherwise use @command{adapter_khz}.
1761 Set the slow rate at the beginning of the reset sequence,
1762 and the faster rate as soon as the clocks are at full speed.
1764 @anchor{theinitboardprocedure}
1765 @subsection The init_board procedure
1766 @cindex init_board procedure
1768 The concept of @code{init_board} procedure is very similar to @code{init_targets}
1769 (@xref{theinittargetsprocedure,,The init_targets procedure}.) - it's a replacement of ``linear''
1770 configuration scripts. This procedure is meant to be executed when OpenOCD enters run stage
1771 (@xref{enteringtherunstage,,Entering the Run Stage},) after @code{init_targets}. The idea to have
1772 separate @code{init_targets} and @code{init_board} procedures is to allow the first one to configure
1773 everything target specific (internal flash, internal RAM, etc.) and the second one to configure
1774 everything board specific (reset signals, chip frequency, reset-init event handler, external memory, etc.).
1775 Additionally ``linear'' board config file will most likely fail when target config file uses
1776 @code{init_targets} scheme (``linear'' script is executed before @code{init} and @code{init_targets} - after),
1777 so separating these two configuration stages is very convenient, as the easiest way to overcome this
1778 problem is to convert board config file to use @code{init_board} procedure. Board config scripts don't
1779 need to override @code{init_targets} defined in target config files when they only need to add some specifics.
1781 Just as @code{init_targets}, the @code{init_board} procedure can be overridden by ``next level'' script (which sources
1782 the original), allowing greater code reuse.
1784 @example
1785 ### board_file.cfg ###
1787 # source target file that does most of the config in init_targets
1788 source [find target/target.cfg]
1790 proc enable_fast_clock @{@} @{
1791 # enables fast on-board clock source
1792 # configures the chip to use it
1793 @}
1795 # initialize only board specifics - reset, clock, adapter frequency
1796 proc init_board @{@} @{
1797 reset_config trst_and_srst trst_pulls_srst
1799 $_TARGETNAME configure -event reset-init @{
1800 adapter_khz 1
1801 enable_fast_clock
1802 adapter_khz 10000
1803 @}
1804 @}
1805 @end example
1807 @section Target Config Files
1808 @cindex config file, target
1809 @cindex target config file
1811 Board config files communicate with target config files using
1812 naming conventions as described above, and may source one or
1813 more target config files like this:
1815 @example
1816 source [find target/FOOBAR.cfg]
1817 @end example
1819 The point of a target config file is to package everything
1820 about a given chip that board config files need to know.
1821 In summary the target files should contain
1823 @enumerate
1824 @item Set defaults
1825 @item Add TAPs to the scan chain
1826 @item Add CPU targets (includes GDB support)
1827 @item CPU/Chip/CPU-Core specific features
1828 @item On-Chip flash
1829 @end enumerate
1831 As a rule of thumb, a target file sets up only one chip.
1832 For a microcontroller, that will often include a single TAP,
1833 which is a CPU needing a GDB target, and its on-chip flash.
1835 More complex chips may include multiple TAPs, and the target
1836 config file may need to define them all before OpenOCD
1837 can talk to the chip.
1838 For example, some phone chips have JTAG scan chains that include
1839 an ARM core for operating system use, a DSP,
1840 another ARM core embedded in an image processing engine,
1841 and other processing engines.
1843 @subsection Default Value Boiler Plate Code
1845 All target configuration files should start with code like this,
1846 letting board config files express environment-specific
1847 differences in how things should be set up.
1849 @example
1850 # Boards may override chip names, perhaps based on role,
1851 # but the default should match what the vendor uses
1852 if @{ [info exists CHIPNAME] @} @{
1854 @} else @{
1855 set _CHIPNAME sam7x256
1856 @}
1858 # ONLY use ENDIAN with targets that can change it.
1859 if @{ [info exists ENDIAN] @} @{
1860 set _ENDIAN $ENDIAN
1861 @} else @{
1862 set _ENDIAN little
1863 @}
1865 # TAP identifiers may change as chips mature, for example with
1866 # new revision fields (the "3" here). Pick a good default; you
1867 # can pass several such identifiers to the "jtag newtap" command.
1868 if @{ [info exists CPUTAPID ] @} @{
1870 @} else @{
1871 set _CPUTAPID 0x3f0f0f0f
1872 @}
1873 @end example
1874 @c but 0x3f0f0f0f is for an str73x part ...
1876 @emph{Remember:} Board config files may include multiple target
1877 config files, or the same target file multiple times
1878 (changing at least @code{CHIPNAME}).
1880 Likewise, the target configuration file should define
1881 @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
1882 use it later on when defining debug targets:
1884 @example
1886 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1887 @end example
1889 @subsection Adding TAPs to the Scan Chain
1890 After the ``defaults'' are set up,
1891 add the TAPs on each chip to the JTAG scan chain.
1892 @xref{TAP Declaration}, and the naming convention
1893 for taps.
1895 In the simplest case the chip has only one TAP,
1896 probably for a CPU or FPGA.
1897 The config file for the Atmel AT91SAM7X256
1898 looks (in part) like this:
1900 @example
1901 jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
1902 @end example
1904 A board with two such at91sam7 chips would be able
1905 to source such a config file twice, with different
1906 values for @code{CHIPNAME}, so
1907 it adds a different TAP each time.
1909 If there are nonzero @option{-expected-id} values,
1910 OpenOCD attempts to verify the actual tap id against those values.
1911 It will issue error messages if there is mismatch, which
1912 can help to pinpoint problems in OpenOCD configurations.
1914 @example
1915 JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
1916 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
1917 ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
1918 ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
1919 ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
1920 @end example
1922 There are more complex examples too, with chips that have
1923 multiple TAPs. Ones worth looking at include:
1925 @itemize
1926 @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
1927 plus a JRC to enable them
1928 @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
1929 @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
1930 is not currently used)
1931 @end itemize
1933 @subsection Add CPU targets
1935 After adding a TAP for a CPU, you should set it up so that
1936 GDB and other commands can use it.
1937 @xref{CPU Configuration}.
1938 For the at91sam7 example above, the command can look like this;
1939 note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
1940 to little endian, and this chip doesn't support changing that.
1942 @example
1944 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1945 @end example
1947 Work areas are small RAM areas associated with CPU targets.
1948 They are used by OpenOCD to speed up downloads,
1949 and to download small snippets of code to program flash chips.
1950 If the chip includes a form of ``on-chip-ram'' - and many do - define
1951 a work area if you can.
1952 Again using the at91sam7 as an example, this can look like:
1954 @example
1955 $_TARGETNAME configure -work-area-phys 0x00200000 \
1956 -work-area-size 0x4000 -work-area-backup 0
1957 @end example
1959 @anchor{definecputargetsworkinginsmp}
1960 @subsection Define CPU targets working in SMP
1961 @cindex SMP
1962 After setting targets, you can define a list of targets working in SMP.
1964 @example
1965 set _TARGETNAME_1 $_CHIPNAME.cpu1
1966 set _TARGETNAME_2 $_CHIPNAME.cpu2
1967 target create $_TARGETNAME_1 cortex_a -chain-position $_CHIPNAME.dap \
1968 -coreid 0 -dbgbase $_DAP_DBG1
1969 target create $_TARGETNAME_2 cortex_a -chain-position $_CHIPNAME.dap \
1970 -coreid 1 -dbgbase $_DAP_DBG2
1971 #define 2 targets working in smp.
1972 target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
1973 @end example
1974 In the above example on cortex_a, 2 cpus are working in SMP.
1975 In SMP only one GDB instance is created and :
1976 @itemize @bullet
1977 @item a set of hardware breakpoint sets the same breakpoint on all targets in the list.
1978 @item halt command triggers the halt of all targets in the list.
1979 @item resume command triggers the write context and the restart of all targets in the list.
1980 @item following a breakpoint: the target stopped by the breakpoint is displayed to the GDB session.
1981 @item dedicated GDB serial protocol packets are implemented for switching/retrieving the target
1982 displayed by the GDB session @pxref{usingopenocdsmpwithgdb,,Using OpenOCD SMP with GDB}.
1983 @end itemize
1985 The SMP behaviour can be disabled/enabled dynamically. On cortex_a following
1986 command have been implemented.
1987 @itemize @bullet
1988 @item cortex_a smp_on : enable SMP mode, behaviour is as described above.
1989 @item cortex_a smp_off : disable SMP mode, the current target is the one
1990 displayed in the GDB session, only this target is now controlled by GDB
1991 session. This behaviour is useful during system boot up.
1992 @item cortex_a smp_gdb : display/fix the core id displayed in GDB session see
1993 following example.
1994 @end itemize
1996 @example
1997 >cortex_a smp_gdb
1998 gdb coreid 0 -> -1
1999 #0 : coreid 0 is displayed to GDB ,
2000 #-> -1 : next resume triggers a real resume
2001 > cortex_a smp_gdb 1
2002 gdb coreid 0 -> 1
2003 #0 :coreid 0 is displayed to GDB ,
2004 #->1 : next resume displays coreid 1 to GDB
2005 > resume
2006 > cortex_a smp_gdb
2007 gdb coreid 1 -> 1
2008 #1 :coreid 1 is displayed to GDB ,
2009 #->1 : next resume displays coreid 1 to GDB
2010 > cortex_a smp_gdb -1
2011 gdb coreid 1 -> -1
2012 #1 :coreid 1 is displayed to GDB,
2013 #->-1 : next resume triggers a real resume
2014 @end example
2017 @subsection Chip Reset Setup
2019 As a rule, you should put the @command{reset_config} command
2020 into the board file. Most things you think you know about a
2021 chip can be tweaked by the board.
2023 Some chips have specific ways the TRST and SRST signals are
2024 managed. In the unusual case that these are @emph{chip specific}
2025 and can never be changed by board wiring, they could go here.
2026 For example, some chips can't support JTAG debugging without
2027 both signals.
2029 Provide a @code{reset-assert} event handler if you can.
2030 Such a handler uses JTAG operations to reset the target,
2031 letting this target config be used in systems which don't
2032 provide the optional SRST signal, or on systems where you
2033 don't want to reset all targets at once.
2034 Such a handler might write to chip registers to force a reset,
2035 use a JRC to do that (preferable -- the target may be wedged!),
2036 or force a watchdog timer to trigger.
2037 (For Cortex-M targets, this is not necessary. The target
2038 driver knows how to use trigger an NVIC reset when SRST is
2039 not available.)
2041 Some chips need special attention during reset handling if
2042 they're going to be used with JTAG.
2043 An example might be needing to send some commands right
2044 after the target's TAP has been reset, providing a
2045 @code{reset-deassert-post} event handler that writes a chip
2046 register to report that JTAG debugging is being done.
2047 Another would be reconfiguring the watchdog so that it stops
2048 counting while the core is halted in the debugger.
2050 JTAG clocking constraints often change during reset, and in
2051 some cases target config files (rather than board config files)
2052 are the right places to handle some of those issues.
2053 For example, immediately after reset most chips run using a
2054 slower clock than they will use later.
2055 That means that after reset (and potentially, as OpenOCD
2056 first starts up) they must use a slower JTAG clock rate
2057 than they will use later.
2058 @xref{jtagspeed,,JTAG Speed}.
2060 @quotation Important
2061 When you are debugging code that runs right after chip
2062 reset, getting these issues right is critical.
2063 In particular, if you see intermittent failures when
2064 OpenOCD verifies the scan chain after reset,
2065 look at how you are setting up JTAG clocking.
2066 @end quotation
2068 @anchor{theinittargetsprocedure}
2069 @subsection The init_targets procedure
2070 @cindex init_targets procedure
2072 Target config files can either be ``linear'' (script executed line-by-line when parsed in
2073 configuration stage, @xref{configurationstage,,Configuration Stage},) or they can contain a special
2074 procedure called @code{init_targets}, which will be executed when entering run stage
2075 (after parsing all config files or after @code{init} command, @xref{enteringtherunstage,,Entering the Run Stage}.)
2076 Such procedure can be overriden by ``next level'' script (which sources the original).
2077 This concept faciliates code reuse when basic target config files provide generic configuration
2078 procedures and @code{init_targets} procedure, which can then be sourced and enchanced or changed in
2079 a ``more specific'' target config file. This is not possible with ``linear'' config scripts,
2080 because sourcing them executes every initialization commands they provide.
2082 @example
2083 ### generic_file.cfg ###
2085 proc setup_my_chip @{chip_name flash_size ram_size@} @{
2086 # basic initialization procedure ...
2087 @}
2089 proc init_targets @{@} @{
2090 # initializes generic chip with 4kB of flash and 1kB of RAM
2091 setup_my_chip MY_GENERIC_CHIP 4096 1024
2092 @}
2094 ### specific_file.cfg ###
2096 source [find target/generic_file.cfg]
2098 proc init_targets @{@} @{
2099 # initializes specific chip with 128kB of flash and 64kB of RAM
2100 setup_my_chip MY_CHIP_WITH_128K_FLASH_64KB_RAM 131072 65536
2101 @}
2102 @end example
2104 The easiest way to convert ``linear'' config files to @code{init_targets} version is to
2105 enclose every line of ``code'' (i.e. not @code{source} commands, procedures, etc.) in this procedure.
2107 For an example of this scheme see LPC2000 target config files.
2109 The @code{init_boards} procedure is a similar concept concerning board config files
2110 (@xref{theinitboardprocedure,,The init_board procedure}.)
2112 @anchor{theinittargeteventsprocedure}
2113 @subsection The init_target_events procedure
2114 @cindex init_target_events procedure
2116 A special procedure called @code{init_target_events} is run just after
2117 @code{init_targets} (@xref{theinittargetsprocedure,,The init_targets
2118 procedure}.) and before @code{init_board}
2119 (@xref{theinitboardprocedure,,The init_board procedure}.) It is used
2120 to set up default target events for the targets that do not have those
2121 events already assigned.
2123 @subsection ARM Core Specific Hacks
2125 If the chip has a DCC, enable it. If the chip is an ARM9 with some
2126 special high speed download features - enable it.
2128 If present, the MMU, the MPU and the CACHE should be disabled.
2130 Some ARM cores are equipped with trace support, which permits
2131 examination of the instruction and data bus activity. Trace
2132 activity is controlled through an ``Embedded Trace Module'' (ETM)
2133 on one of the core's scan chains. The ETM emits voluminous data
2134 through a ``trace port''. (@xref{armhardwaretracing,,ARM Hardware Tracing}.)
2135 If you are using an external trace port,
2136 configure it in your board config file.
2137 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
2138 configure it in your target config file.
2140 @example
2141 etm config $_TARGETNAME 16 normal full etb
2142 etb config $_TARGETNAME $_CHIPNAME.etb
2143 @end example
2145 @subsection Internal Flash Configuration
2147 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
2149 @b{Never ever} in the ``target configuration file'' define any type of
2150 flash that is external to the chip. (For example a BOOT flash on
2151 Chip Select 0.) Such flash information goes in a board file - not
2152 the TARGET (chip) file.
2154 Examples:
2155 @itemize @bullet
2156 @item at91sam7x256 - has 256K flash YES enable it.
2157 @item str912 - has flash internal YES enable it.
2158 @item imx27 - uses boot flash on CS0 - it goes in the board file.
2159 @item pxa270 - again - CS0 flash - it goes in the board file.
2160 @end itemize
2162 @anchor{translatingconfigurationfiles}
2163 @section Translating Configuration Files
2164 @cindex translation
2165 If you have a configuration file for another hardware debugger
2166 or toolset (Abatron, BDI2000, BDI3000, CCS,
2167 Lauterbach, Segger, Macraigor, etc.), translating
2168 it into OpenOCD syntax is often quite straightforward. The most tricky
2169 part of creating a configuration script is oftentimes the reset init
2170 sequence where e.g. PLLs, DRAM and the like is set up.
2172 One trick that you can use when translating is to write small
2173 Tcl procedures to translate the syntax into OpenOCD syntax. This
2174 can avoid manual translation errors and make it easier to
2175 convert other scripts later on.
2177 Example of transforming quirky arguments to a simple search and
2178 replace job:
2180 @example
2181 # Lauterbach syntax(?)
2182 #
2183 # Data.Set c15:0x042f %long 0x40000015
2184 #
2185 # OpenOCD syntax when using procedure below.
2186 #
2187 # setc15 0x01 0x00050078
2189 proc setc15 @{regs value@} @{
2190 global TARGETNAME
2192 echo [format "set p15 0x%04x, 0x%08x" $regs $value]
2194 arm mcr 15 [expr ($regs>>12)&0x7] \
2195 [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] \
2196 [expr ($regs>>8)&0x7] $value
2197 @}
2198 @end example
2202 @node Daemon Configuration
2203 @chapter Daemon Configuration
2204 @cindex initialization
2205 The commands here are commonly found in the openocd.cfg file and are
2206 used to specify what TCP/IP ports are used, and how GDB should be
2207 supported.
2209 @anchor{configurationstage}
2210 @section Configuration Stage
2211 @cindex configuration stage
2212 @cindex config command
2214 When the OpenOCD server process starts up, it enters a
2215 @emph{configuration stage} which is the only time that
2216 certain commands, @emph{configuration commands}, may be issued.
2217 Normally, configuration commands are only available
2218 inside startup scripts.
2220 In this manual, the definition of a configuration command is
2221 presented as a @emph{Config Command}, not as a @emph{Command}
2222 which may be issued interactively.
2223 The runtime @command{help} command also highlights configuration
2224 commands, and those which may be issued at any time.
2226 Those configuration commands include declaration of TAPs,
2227 flash banks,
2228 the interface used for JTAG communication,
2229 and other basic setup.
2230 The server must leave the configuration stage before it
2231 may access or activate TAPs.
2232 After it leaves this stage, configuration commands may no
2233 longer be issued.
2235 @anchor{enteringtherunstage}
2236 @section Entering the Run Stage
2238 The first thing OpenOCD does after leaving the configuration
2239 stage is to verify that it can talk to the scan chain
2240 (list of TAPs) which has been configured.
2241 It will warn if it doesn't find TAPs it expects to find,
2242 or finds TAPs that aren't supposed to be there.
2243 You should see no errors at this point.
2244 If you see errors, resolve them by correcting the
2245 commands you used to configure the server.
2246 Common errors include using an initial JTAG speed that's too
2247 fast, and not providing the right IDCODE values for the TAPs
2248 on the scan chain.
2250 Once OpenOCD has entered the run stage, a number of commands
2251 become available.
2252 A number of these relate to the debug targets you may have declared.
2253 For example, the @command{mww} command will not be available until
2254 a target has been successfuly instantiated.
2255 If you want to use those commands, you may need to force
2256 entry to the run stage.
2258 @deffn {Config Command} init
2259 This command terminates the configuration stage and
2260 enters the run stage. This helps when you need to have
2261 the startup scripts manage tasks such as resetting the target,
2262 programming flash, etc. To reset the CPU upon startup, add "init" and
2263 "reset" at the end of the config script or at the end of the OpenOCD
2264 command line using the @option{-c} command line switch.
2266 If this command does not appear in any startup/configuration file
2267 OpenOCD executes the command for you after processing all
2268 configuration files and/or command line options.
2270 @b{NOTE:} This command normally occurs at or near the end of your
2271 openocd.cfg file to force OpenOCD to ``initialize'' and make the
2272 targets ready. For example: If your openocd.cfg file needs to
2273 read/write memory on your target, @command{init} must occur before
2274 the memory read/write commands. This includes @command{nand probe}.
2275 @end deffn
2277 @deffn {Overridable Procedure} jtag_init
2278 This is invoked at server startup to verify that it can talk
2279 to the scan chain (list of TAPs) which has been configured.
2281 The default implementation first tries @command{jtag arp_init},
2282 which uses only a lightweight JTAG reset before examining the
2283 scan chain.
2284 If that fails, it tries again, using a harder reset
2285 from the overridable procedure @command{init_reset}.
2287 Implementations must have verified the JTAG scan chain before
2288 they return.
2289 This is done by calling @command{jtag arp_init}
2290 (or @command{jtag arp_init-reset}).
2291 @end deffn
2293 @anchor{tcpipports}
2294 @section TCP/IP Ports
2295 @cindex TCP port
2296 @cindex server
2297 @cindex port
2298 @cindex security
2299 The OpenOCD server accepts remote commands in several syntaxes.
2300 Each syntax uses a different TCP/IP port, which you may specify
2301 only during configuration (before those ports are opened).
2303 For reasons including security, you may wish to prevent remote
2304 access using one or more of these ports.
2305 In such cases, just specify the relevant port number as zero.
2306 If you disable all access through TCP/IP, you will need to
2307 use the command line @option{-pipe} option.
2309 @deffn {Command} gdb_port [number]
2310 @cindex GDB server
2311 Normally gdb listens to a TCP/IP port, but GDB can also
2312 communicate via pipes(stdin/out or named pipes). The name
2313 "gdb_port" stuck because it covers probably more than 90% of
2314 the normal use cases.
2316 No arguments reports GDB port. "pipe" means listen to stdin
2317 output to stdout, an integer is base port number, "disable"
2318 disables the gdb server.
2320 When using "pipe", also use log_output to redirect the log
2321 output to a file so as not to flood the stdin/out pipes.
2323 The -p/--pipe option is deprecated and a warning is printed
2324 as it is equivalent to passing in -c "gdb_port pipe; log_output openocd.log".
2326 Any other string is interpreted as named pipe to listen to.
2327 Output pipe is the same name as input pipe, but with 'o' appended,
2328 e.g. /var/gdb, /var/gdbo.
2330 The GDB port for the first target will be the base port, the
2331 second target will listen on gdb_port + 1, and so on.
2332 When not specified during the configuration stage,
2333 the port @var{number} defaults to 3333.
2334 @end deffn
2336 @deffn {Command} tcl_port [number]
2337 Specify or query the port used for a simplified RPC
2338 connection that can be used by clients to issue TCL commands and get the
2339 output from the Tcl engine.
2340 Intended as a machine interface.
2341 When not specified during the configuration stage,
2342 the port @var{number} defaults to 6666.
2344 @end deffn
2346 @deffn {Command} telnet_port [number]
2347 Specify or query the
2348 port on which to listen for incoming telnet connections.
2349 This port is intended for interaction with one human through TCL commands.
2350 When not specified during the configuration stage,
2351 the port @var{number} defaults to 4444.
2352 When specified as zero, this port is not activated.
2353 @end deffn
2355 @anchor{gdbconfiguration}
2356 @section GDB Configuration
2357 @cindex GDB
2358 @cindex GDB configuration
2359 You can reconfigure some GDB behaviors if needed.
2360 The ones listed here are static and global.
2361 @xref{targetconfiguration,,Target Configuration}, about configuring individual targets.
2362 @xref{targetevents,,Target Events}, about configuring target-specific event handling.
2364 @anchor{gdbbreakpointoverride}
2365 @deffn {Command} gdb_breakpoint_override [@option{hard}|@option{soft}|@option{disable}]
2366 Force breakpoint type for gdb @command{break} commands.
2367 This option supports GDB GUIs which don't
2368 distinguish hard versus soft breakpoints, if the default OpenOCD and
2369 GDB behaviour is not sufficient. GDB normally uses hardware
2370 breakpoints if the memory map has been set up for flash regions.
2371 @end deffn
2373 @anchor{gdbflashprogram}
2374 @deffn {Config Command} gdb_flash_program (@option{enable}|@option{disable})
2375 Set to @option{enable} to cause OpenOCD to program the flash memory when a
2376 vFlash packet is received.
2377 The default behaviour is @option{enable}.
2378 @end deffn
2380 @deffn {Config Command} gdb_memory_map (@option{enable}|@option{disable})
2381 Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
2382 requested. GDB will then know when to set hardware breakpoints, and program flash
2383 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
2384 for flash programming to work.
2385 Default behaviour is @option{enable}.
2386 @xref{gdbflashprogram,,gdb_flash_program}.
2387 @end deffn
2389 @deffn {Config Command} gdb_report_data_abort (@option{enable}|@option{disable})
2390 Specifies whether data aborts cause an error to be reported
2391 by GDB memory read packets.
2392 The default behaviour is @option{disable};
2393 use @option{enable} see these errors reported.
2394 @end deffn
2396 @deffn {Config Command} gdb_target_description (@option{enable}|@option{disable})
2397 Set to @option{enable} to cause OpenOCD to send the target descriptions to gdb via qXfer:features:read packet.
2398 The default behaviour is @option{disable}.
2399 @end deffn
2401 @deffn {Command} gdb_save_tdesc
2402 Saves the target descripton file to the local file system.
2404 The file name is @i{target_name}.xml.
2405 @end deffn
2407 @anchor{eventpolling}
2408 @section Event Polling
2410 Hardware debuggers are parts of asynchronous systems,
2411 where significant events can happen at any time.
2412 The OpenOCD server needs to detect some of these events,
2413 so it can report them to through TCL command line
2414 or to GDB.
2416 Examples of such events include:
2418 @itemize
2419 @item One of the targets can stop running ... maybe it triggers
2420 a code breakpoint or data watchpoint, or halts itself.
2421 @item Messages may be sent over ``debug message'' channels ... many
2422 targets support such messages sent over JTAG,
2423 for receipt by the person debugging or tools.
2424 @item Loss of power ... some adapters can detect these events.
2425 @item Resets not issued through JTAG ... such reset sources
2426 can include button presses or other system hardware, sometimes
2427 including the target itself (perhaps through a watchdog).
2428 @item Debug instrumentation sometimes supports event triggering
2429 such as ``trace buffer full'' (so it can quickly be emptied)
2430 or other signals (to correlate with code behavior).
2431 @end itemize
2433 None of those events are signaled through standard JTAG signals.
2434 However, most conventions for JTAG connectors include voltage
2435 level and system reset (SRST) signal detection.
2436 Some connectors also include instrumentation signals, which
2437 can imply events when those signals are inputs.
2439 In general, OpenOCD needs to periodically check for those events,
2440 either by looking at the status of signals on the JTAG connector
2441 or by sending synchronous ``tell me your status'' JTAG requests
2442 to the various active targets.
2443 There is a command to manage and monitor that polling,
2444 which is normally done in the background.
2446 @deffn Command poll [@option{on}|@option{off}]
2447 Poll the current target for its current state.
2448 (Also, @pxref{targetcurstate,,target curstate}.)
2449 If that target is in debug mode, architecture
2450 specific information about the current state is printed.
2451 An optional parameter
2452 allows background polling to be enabled and disabled.
2454 You could use this from the TCL command shell, or
2455 from GDB using @command{monitor poll} command.
2456 Leave background polling enabled while you're using GDB.
2457 @example
2458 > poll
2459 background polling: on
2460 target state: halted
2461 target halted in ARM state due to debug-request, \
2462 current mode: Supervisor
2463 cpsr: 0x800000d3 pc: 0x11081bfc
2464 MMU: disabled, D-Cache: disabled, I-Cache: enabled
2465 >
2466 @end example
2467 @end deffn
2469 @node Debug Adapter Configuration
2470 @chapter Debug Adapter Configuration
2471 @cindex config file, interface
2472 @cindex interface config file
2474 Correctly installing OpenOCD includes making your operating system give
2475 OpenOCD access to debug adapters. Once that has been done, Tcl commands
2476 are used to select which one is used, and to configure how it is used.
2478 @quotation Note
2479 Because OpenOCD started out with a focus purely on JTAG, you may find
2480 places where it wrongly presumes JTAG is the only transport protocol
2481 in use. Be aware that recent versions of OpenOCD are removing that
2482 limitation. JTAG remains more functional than most other transports.
2483 Other transports do not support boundary scan operations, or may be
2484 specific to a given chip vendor. Some might be usable only for
2485 programming flash memory, instead of also for debugging.
2486 @end quotation
2488 Debug Adapters/Interfaces/Dongles are normally configured
2489 through commands in an interface configuration
2490 file which is sourced by your @file{openocd.cfg} file, or
2491 through a command line @option{-f interface/....cfg} option.
2493 @example
2494 source [find interface/olimex-jtag-tiny.cfg]
2495 @end example
2497 These commands tell
2498 OpenOCD what type of JTAG adapter you have, and how to talk to it.
2499 A few cases are so simple that you only need to say what driver to use:
2501 @example
2502 # jlink interface
2503 interface jlink
2504 @end example
2506 Most adapters need a bit more configuration than that.
2509 @section Interface Configuration
2511 The interface command tells OpenOCD what type of debug adapter you are
2512 using. Depending on the type of adapter, you may need to use one or
2513 more additional commands to further identify or configure the adapter.
2515 @deffn {Config Command} {interface} name
2516 Use the interface driver @var{name} to connect to the
2517 target.
2518 @end deffn
2520 @deffn Command {interface_list}
2521 List the debug adapter drivers that have been built into
2522 the running copy of OpenOCD.
2523 @end deffn
2524 @deffn Command {interface transports} transport_name+
2525 Specifies the transports supported by this debug adapter.
2526 The adapter driver builds-in similar knowledge; use this only
2527 when external configuration (such as jumpering) changes what
2528 the hardware can support.
2529 @end deffn
2533 @deffn Command {adapter_name}
2534 Returns the name of the debug adapter driver being used.
2535 @end deffn
2537 @section Interface Drivers
2539 Each of the interface drivers listed here must be explicitly
2540 enabled when OpenOCD is configured, in order to be made
2541 available at run time.
2543 @deffn {Interface Driver} {amt_jtagaccel}
2544 Amontec Chameleon in its JTAG Accelerator configuration,
2545 connected to a PC's EPP mode parallel port.
2546 This defines some driver-specific commands:
2548 @deffn {Config Command} {parport_port} number
2549 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
2550 the number of the @file{/dev/parport} device.
2551 @end deffn
2553 @deffn {Config Command} rtck [@option{enable}|@option{disable}]
2554 Displays status of RTCK option.
2555 Optionally sets that option first.
2556 @end deffn
2557 @end deffn
2559 @deffn {Interface Driver} {arm-jtag-ew}
2560 Olimex ARM-JTAG-EW USB adapter
2561 This has one driver-specific command:
2563 @deffn Command {armjtagew_info}
2564 Logs some status
2565 @end deffn
2566 @end deffn
2568 @deffn {Interface Driver} {at91rm9200}
2569 Supports bitbanged JTAG from the local system,
2570 presuming that system is an Atmel AT91rm9200
2571 and a specific set of GPIOs is used.
2572 @c command: at91rm9200_device NAME
2573 @c chooses among list of bit configs ... only one option
2574 @end deffn
2576 @deffn {Interface Driver} {cmsis-dap}
2577 ARM CMSIS-DAP compliant based adapter.
2579 @deffn {Config Command} {cmsis_dap_vid_pid} [vid pid]+
2580 The vendor ID and product ID of the CMSIS-DAP device. If not specified
2581 the driver will attempt to auto detect the CMSIS-DAP device.
2582 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2583 @example
2584 cmsis_dap_vid_pid 0xc251 0xf001 0x0d28 0x0204
2585 @end example
2586 @end deffn
2588 @deffn {Config Command} {cmsis_dap_serial} [serial]
2589 Specifies the @var{serial} of the CMSIS-DAP device to use.
2590 If not specified, serial numbers are not considered.
2591 @end deffn
2593 @deffn {Command} {cmsis-dap info}
2594 Display various device information, like hardware version, firmware version, current bus status.
2595 @end deffn
2596 @end deffn
2598 @deffn {Interface Driver} {dummy}
2599 A dummy software-only driver for debugging.
2600 @end deffn
2602 @deffn {Interface Driver} {ep93xx}
2603 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
2604 @end deffn
2606 @deffn {Interface Driver} {ft2232}
2607 FTDI FT2232 (USB) based devices over one of the userspace libraries.
2609 Note that this driver has several flaws and the @command{ftdi} driver is
2610 recommended as its replacement.
2612 These interfaces have several commands, used to configure the driver
2613 before initializing the JTAG scan chain:
2615 @deffn {Config Command} {ft2232_device_desc} description
2616 Provides the USB device description (the @emph{iProduct string})
2617 of the FTDI FT2232 device. If not
2618 specified, the FTDI default value is used. This setting is only valid
2619 if compiled with FTD2XX support.
2620 @end deffn
2622 @deffn {Config Command} {ft2232_serial} serial-number
2623 Specifies the @var{serial-number} of the FTDI FT2232 device to use,
2624 in case the vendor provides unique IDs and more than one FT2232 device
2625 is connected to the host.
2626 If not specified, serial numbers are not considered.
2627 (Note that USB serial numbers can be arbitrary Unicode strings,
2628 and are not restricted to containing only decimal digits.)
2629 @end deffn
2631 @deffn {Config Command} {ft2232_layout} name
2632 Each vendor's FT2232 device can use different GPIO signals
2633 to control output-enables, reset signals, and LEDs.
2634 Currently valid layout @var{name} values include:
2635 @itemize @minus
2636 @item @b{axm0432_jtag} Axiom AXM-0432
2637 @item @b{comstick} Hitex STR9 comstick
2638 @item @b{cortino} Hitex Cortino JTAG interface
2639 @item @b{evb_lm3s811} TI/Luminary Micro EVB_LM3S811 as a JTAG interface,
2640 either for the local Cortex-M3 (SRST only)
2641 or in a passthrough mode (neither SRST nor TRST)
2642 This layout can not support the SWO trace mechanism, and should be
2643 used only for older boards (before rev C).
2644 @item @b{luminary_icdi} This layout should be used with most TI/Luminary
2645 eval boards, including Rev C LM3S811 eval boards and the eponymous
2646 ICDI boards, to debug either the local Cortex-M3 or in passthrough mode
2647 to debug some other target. It can support the SWO trace mechanism.
2648 @item @b{flyswatter} Tin Can Tools Flyswatter
2649 @item @b{icebear} ICEbear JTAG adapter from Section 5
2650 @item @b{jtagkey} Amontec JTAGkey and JTAGkey-Tiny (and compatibles)
2651 @item @b{jtagkey2} Amontec JTAGkey2 (and compatibles)
2652 @item @b{m5960} American Microsystems M5960
2653 @item @b{olimex-jtag} Olimex ARM-USB-OCD and ARM-USB-Tiny
2654 @item @b{oocdlink} OOCDLink
2655 @c oocdlink ~= jtagkey_prototype_v1
2656 @item @b{redbee-econotag} Integrated with a Redbee development board.
2657 @item @b{redbee-usb} Integrated with a Redbee USB-stick development board.
2658 @item @b{sheevaplug} Marvell Sheevaplug development kit
2659 @item @b{signalyzer} Xverve Signalyzer
2660 @item @b{stm32stick} Hitex STM32 Performance Stick
2661 @item @b{turtelizer2} egnite Software turtelizer2
2662 @item @b{usbjtag} "USBJTAG-1" layout described in the OpenOCD diploma thesis
2663 @end itemize
2664 @end deffn
2666 @deffn {Config Command} {ft2232_vid_pid} [vid pid]+
2667 The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
2668 default values are used.
2669 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2670 @example
2671 ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
2672 @end example
2673 @end deffn
2675 @deffn {Config Command} {ft2232_latency} ms
2676 On some systems using FT2232 based JTAG interfaces the FT_Read function call in
2677 ft2232_read() fails to return the expected number of bytes. This can be caused by
2678 USB communication delays and has proved hard to reproduce and debug. Setting the
2679 FT2232 latency timer to a larger value increases delays for short USB packets but it
2680 also reduces the risk of timeouts before receiving the expected number of bytes.
2681 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
2682 @end deffn
2684 @deffn {Config Command} {ft2232_channel} channel
2685 Used to select the channel of the ft2232 chip to use (between 1 and 4).
2686 The default value is 1.
2687 @end deffn
2689 For example, the interface config file for a
2690 Turtelizer JTAG Adapter looks something like this:
2692 @example
2693 interface ft2232
2694 ft2232_device_desc "Turtelizer JTAG/RS232 Adapter"
2695 ft2232_layout turtelizer2
2696 ft2232_vid_pid 0x0403 0xbdc8
2697 @end example
2698 @end deffn
2700 @deffn {Interface Driver} {ftdi}
2701 This driver is for adapters using the MPSSE (Multi-Protocol Synchronous Serial
2702 Engine) mode built into many FTDI chips, such as the FT2232, FT4232 and FT232H.
2703 It is a complete rewrite to address a large number of problems with the ft2232
2704 interface driver.
2706 The driver is using libusb-1.0 in asynchronous mode to talk to the FTDI device,
2707 bypassing intermediate libraries like libftdi of D2XX. Performance-wise it is
2708 consistently faster than the ft2232 driver, sometimes several times faster.
2710 A major improvement of this driver is that support for new FTDI based adapters
2711 can be added competely through configuration files, without the need to patch
2712 and rebuild OpenOCD.
2714 The driver uses a signal abstraction to enable Tcl configuration files to
2715 define outputs for one or several FTDI GPIO. These outputs can then be
2716 controlled using the @command{ftdi_set_signal} command. Special signal names
2717 are reserved for nTRST, nSRST and LED (for blink) so that they, if defined,
2718 will be used for their customary purpose.
2720 Depending on the type of buffer attached to the FTDI GPIO, the outputs have to
2721 be controlled differently. In order to support tristateable signals such as
2722 nSRST, both a data GPIO and an output-enable GPIO can be specified for each
2723 signal. The following output buffer configurations are supported:
2725 @itemize @minus
2726 @item Push-pull with one FTDI output as (non-)inverted data line
2727 @item Open drain with one FTDI output as (non-)inverted output-enable
2728 @item Tristate with one FTDI output as (non-)inverted data line and another
2729 FTDI output as (non-)inverted output-enable
2730 @item Unbuffered, using the FTDI GPIO as a tristate output directly by
2731 switching data and direction as necessary
2732 @end itemize
2734 These interfaces have several commands, used to configure the driver
2735 before initializing the JTAG scan chain:
2737 @deffn {Config Command} {ftdi_vid_pid} [vid pid]+
2738 The vendor ID and product ID of the adapter. If not specified, the FTDI
2739 default values are used.
2740 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2741 @example
2742 ftdi_vid_pid 0x0403 0xcff8 0x15ba 0x0003
2743 @end example
2744 @end deffn
2746 @deffn {Config Command} {ftdi_device_desc} description
2747 Provides the USB device description (the @emph{iProduct string})
2748 of the adapter. If not specified, the device description is ignored
2749 during device selection.
2750 @end deffn
2752 @deffn {Config Command} {ftdi_serial} serial-number
2753 Specifies the @var{serial-number} of the adapter to use,
2754 in case the vendor provides unique IDs and more than one adapter
2755 is connected to the host.
2756 If not specified, serial numbers are not considered.
2757 (Note that USB serial numbers can be arbitrary Unicode strings,
2758 and are not restricted to containing only decimal digits.)
2759 @end deffn
2761 @deffn {Config Command} {ftdi_channel} channel
2762 Selects the channel of the FTDI device to use for MPSSE operations. Most
2763 adapters use the default, channel 0, but there are exceptions.
2764 @end deffn
2766 @deffn {Config Command} {ftdi_layout_init} data direction
2767 Specifies the initial values of the FTDI GPIO data and direction registers.
2768 Each value is a 16-bit number corresponding to the concatenation of the high
2769 and low FTDI GPIO registers. The values should be selected based on the
2770 schematics of the adapter, such that all signals are set to safe levels with
2771 minimal impact on the target system. Avoid floating inputs, conflicting outputs
2772 and initially asserted reset signals.
2773 @end deffn
2775 @deffn {Config Command} {ftdi_layout_signal} name [@option{-data}|@option{-ndata} data_mask] [@option{-oe}|@option{-noe} oe_mask] [@option{-alias}|@option{-nalias} name]
2776 Creates a signal with the specified @var{name}, controlled by one or more FTDI
2777 GPIO pins via a range of possible buffer connections. The masks are FTDI GPIO
2778 register bitmasks to tell the driver the connection and type of the output
2779 buffer driving the respective signal. @var{data_mask} is the bitmask for the
2780 pin(s) connected to the data input of the output buffer. @option{-ndata} is
2781 used with inverting data inputs and @option{-data} with non-inverting inputs.
2782 The @option{-oe} (or @option{-noe}) option tells where the output-enable (or
2783 not-output-enable) input to the output buffer is connected.
2785 Both @var{data_mask} and @var{oe_mask} need not be specified. For example, a
2786 simple open-collector transistor driver would be specified with @option{-oe}
2787 only. In that case the signal can only be set to drive low or to Hi-Z and the
2788 driver will complain if the signal is set to drive high. Which means that if
2789 it's a reset signal, @command{reset_config} must be specified as
2790 @option{srst_open_drain}, not @option{srst_push_pull}.
2792 A special case is provided when @option{-data} and @option{-oe} is set to the
2793 same bitmask. Then the FTDI pin is considered being connected straight to the
2794 target without any buffer. The FTDI pin is then switched between output and
2795 input as necessary to provide the full set of low, high and Hi-Z
2796 characteristics. In all other cases, the pins specified in a signal definition
2797 are always driven by the FTDI.
2799 If @option{-alias} or @option{-nalias} is used, the signal is created
2800 identical (or with data inverted) to an already specified signal
2801 @var{name}.
2802 @end deffn
2804 @deffn {Command} {ftdi_set_signal} name @option{0}|@option{1}|@option{z}
2805 Set a previously defined signal to the specified level.
2806 @itemize @minus
2807 @item @option{0}, drive low
2808 @item @option{1}, drive high
2809 @item @option{z}, set to high-impedance
2810 @end itemize
2811 @end deffn
2813 For example adapter definitions, see the configuration files shipped in the
2814 @file{interface/ftdi} directory.
2815 @end deffn
2817 @deffn {Interface Driver} {remote_bitbang}
2818 Drive JTAG from a remote process. This sets up a UNIX or TCP socket connection
2819 with a remote process and sends ASCII encoded bitbang requests to that process
2820 instead of directly driving JTAG.
2822 The remote_bitbang driver is useful for debugging software running on
2823 processors which are being simulated.
2825 @deffn {Config Command} {remote_bitbang_port} number
2826 Specifies the TCP port of the remote process to connect to or 0 to use UNIX
2827 sockets instead of TCP.
2828 @end deffn
2830 @deffn {Config Command} {remote_bitbang_host} hostname
2831 Specifies the hostname of the remote process to connect to using TCP, or the
2832 name of the UNIX socket to use if remote_bitbang_port is 0.
2833 @end deffn
2835 For example, to connect remotely via TCP to the host foobar you might have
2836 something like:
2838 @example
2839 interface remote_bitbang
2840 remote_bitbang_port 3335
2841 remote_bitbang_host foobar
2842 @end example
2844 To connect to another process running locally via UNIX sockets with socket
2845 named mysocket:
2847 @example
2848 interface remote_bitbang
2849 remote_bitbang_port 0
2850 remote_bitbang_host mysocket
2851 @end example
2852 @end deffn
2854 @deffn {Interface Driver} {usb_blaster}
2855 USB JTAG/USB-Blaster compatibles over one of the userspace libraries
2856 for FTDI chips. These interfaces have several commands, used to
2857 configure the driver before initializing the JTAG scan chain:
2859 @deffn {Config Command} {usb_blaster_device_desc} description
2860 Provides the USB device description (the @emph{iProduct string})
2861 of the FTDI FT245 device. If not
2862 specified, the FTDI default value is used. This setting is only valid
2863 if compiled with FTD2XX support.
2864 @end deffn
2866 @deffn {Config Command} {usb_blaster_vid_pid} vid pid
2867 The vendor ID and product ID of the FTDI FT245 device. If not specified,
2868 default values are used.
2869 Currently, only one @var{vid}, @var{pid} pair may be given, e.g. for
2870 Altera USB-Blaster (default):
2871 @example
2872 usb_blaster_vid_pid 0x09FB 0x6001
2873 @end example
2874 The following VID/PID is for Kolja Waschk's USB JTAG:
2875 @example
2876 usb_blaster_vid_pid 0x16C0 0x06AD
2877 @end example
2878 @end deffn
2880 @deffn {Command} {usb_blaster} (@option{pin6}|@option{pin8}) (@option{0}|@option{1})
2881 Sets the state of the unused GPIO pins on USB-Blasters (pins 6 and 8 on the
2882 female JTAG header). These pins can be used as SRST and/or TRST provided the
2883 appropriate connections are made on the target board.
2885 For example, to use pin 6 as SRST (as with an AVR board):
2886 @example
2887 $_TARGETNAME configure -event reset-assert \
2888 "usb_blaster pin6 1; wait 1; usb_blaster pin6 0"
2889 @end example
2890 @end deffn
2892 @end deffn
2894 @deffn {Interface Driver} {gw16012}
2895 Gateworks GW16012 JTAG programmer.
2896 This has one driver-specific command:
2898 @deffn {Config Command} {parport_port} [port_number]
2899 Display either the address of the I/O port
2900 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2901 If a parameter is provided, first switch to use that port.
2902 This is a write-once setting.
2903 @end deffn
2904 @end deffn
2906 @deffn {Interface Driver} {jlink}
2907 Segger J-Link family of USB adapters. It currently supports JTAG and SWD transports.
2909 @quotation Compatibility Note
2910 Segger released many firmware versions for the many harware versions they
2911 produced. OpenOCD was extensively tested and intended to run on all of them,
2912 but some combinations were reported as incompatible. As a general
2913 recommendation, it is advisable to use the latest firmware version
2914 available for each hardware version. However the current V8 is a moving
2915 target, and Segger firmware versions released after the OpenOCD was
2916 released may not be compatible. In such cases it is recommended to
2917 revert to the last known functional version. For 0.5.0, this is from
2918 "Feb 8 2012 14:30:39", packed with 4.42c. For 0.6.0, the last known
2919 version is from "May 3 2012 18:36:22", packed with 4.46f.
2920 @end quotation
2922 @deffn {Command} {jlink caps}
2923 Display the device firmware capabilities.
2924 @end deffn
2925 @deffn {Command} {jlink info}
2926 Display various device information, like hardware version, firmware version, current bus status.
2927 @end deffn
2928 @deffn {Command} {jlink hw_jtag} [@option{2}|@option{3}]
2929 Set the JTAG protocol version to be used. Without argument, show the actual JTAG protocol version.
2930 @end deffn
2931 @deffn {Command} {jlink config}
2932 Display the J-Link configuration.
2933 @end deffn
2934 @deffn {Command} {jlink config kickstart} [val]
2935 Set the Kickstart power on JTAG-pin 19. Without argument, show the Kickstart configuration.
2936 @end deffn
2937 @deffn {Command} {jlink config mac_address} [@option{ff:ff:ff:ff:ff:ff}]
2938 Set the MAC address of the J-Link Pro. Without argument, show the MAC address.
2939 @end deffn
2940 @deffn {Command} {jlink config ip} [@option{A.B.C.D}(@option{/E}|@option{F.G.H.I})]
2941 Set the IP configuration of the J-Link Pro, where A.B.C.D is the IP address,
2942 E the bit of the subnet mask and
2943 F.G.H.I the subnet mask. Without arguments, show the IP configuration.
2944 @end deffn
2945 @deffn {Command} {jlink config usb_address} [@option{0x00} to @option{0x03} or @option{0xff}]
2946 Set the USB address; this will also change the product id. Without argument, show the USB address.
2947 @end deffn
2948 @deffn {Command} {jlink config reset}
2949 Reset the current configuration.
2950 @end deffn
2951 @deffn {Command} {jlink config save}
2952 Save the current configuration to the internal persistent storage.
2953 @end deffn
2954 @deffn {Config} {jlink pid} val
2955 Set the USB PID of the interface. As a configuration command, it can be used only before 'init'.
2956 @end deffn
2957 @deffn {Config} {jlink serial} serial-number
2958 Set the @var{serial-number} of the interface, in case more than one adapter is connected to the host.
2959 If not specified, serial numbers are not considered.
2961 Note that there may be leading zeros in the @var{serial-number} string
2962 that will not show in the Segger software, but must be specified here.
2963 Debug level 3 output contains serial numbers if there is a mismatch.
2965 As a configuration command, it can be used only before 'init'.
2966 @end deffn
2967 @end deffn
2969 @deffn {Interface Driver} {parport}
2970 Supports PC parallel port bit-banging cables:
2971 Wigglers, PLD download cable, and more.
2972 These interfaces have several commands, used to configure the driver
2973 before initializing the JTAG scan chain:
2975 @deffn {Config Command} {parport_cable} name
2976 Set the layout of the parallel port cable used to connect to the target.
2977 This is a write-once setting.
2978 Currently valid cable @var{name} values include:
2980 @itemize @minus
2981 @item @b{altium} Altium Universal JTAG cable.
2982 @item @b{arm-jtag} Same as original wiggler except SRST and
2983 TRST connections reversed and TRST is also inverted.
2984 @item @b{chameleon} The Amontec Chameleon's CPLD when operated
2985 in configuration mode. This is only used to
2986 program the Chameleon itself, not a connected target.
2987 @item @b{dlc5} The Xilinx Parallel cable III.
2988 @item @b{flashlink} The ST Parallel cable.
2989 @item @b{lattice} Lattice ispDOWNLOAD Cable
2990 @item @b{old_amt_wiggler} The Wiggler configuration that comes with
2991 some versions of
2992 Amontec's Chameleon Programmer. The new version available from
2993 the website uses the original Wiggler layout ('@var{wiggler}')
2994 @item @b{triton} The parallel port adapter found on the
2995 ``Karo Triton 1 Development Board''.
2996 This is also the layout used by the HollyGates design
2997 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
2998 @item @b{wiggler} The original Wiggler layout, also supported by
2999 several clones, such as the Olimex ARM-JTAG
3000 @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
3001 @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
3002 @end itemize
3003 @end deffn
3005 @deffn {Config Command} {parport_port} [port_number]
3006 Display either the address of the I/O port
3007 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
3008 If a parameter is provided, first switch to use that port.
3009 This is a write-once setting.
3011 When using PPDEV to access the parallel port, use the number of the parallel port:
3012 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
3013 you may encounter a problem.
3014 @end deffn
3016 @deffn Command {parport_toggling_time} [nanoseconds]
3017 Displays how many nanoseconds the hardware needs to toggle TCK;
3018 the parport driver uses this value to obey the
3019 @command{adapter_khz} configuration.
3020 When the optional @var{nanoseconds} parameter is given,
3021 that setting is changed before displaying the current value.
3023 The default setting should work reasonably well on commodity PC hardware.
3024 However, you may want to calibrate for your specific hardware.
3025 @quotation Tip
3026 To measure the toggling time with a logic analyzer or a digital storage
3027 oscilloscope, follow the procedure below:
3028 @example
3029 > parport_toggling_time 1000
3030 > adapter_khz 500
3031 @end example
3032 This sets the maximum JTAG clock speed of the hardware, but
3033 the actual speed probably deviates from the requested 500 kHz.
3034 Now, measure the time between the two closest spaced TCK transitions.
3035 You can use @command{runtest 1000} or something similar to generate a
3036 large set of samples.
3037 Update the setting to match your measurement:
3038 @example
3039 > parport_toggling_time <measured nanoseconds>
3040 @end example
3041 Now the clock speed will be a better match for @command{adapter_khz rate}
3042 commands given in OpenOCD scripts and event handlers.
3044 You can do something similar with many digital multimeters, but note
3045 that you'll probably need to run the clock continuously for several
3046 seconds before it decides what clock rate to show. Adjust the
3047 toggling time up or down until the measured clock rate is a good
3048 match for the adapter_khz rate you specified; be conservative.
3049 @end quotation
3050 @end deffn
3052 @deffn {Config Command} {parport_write_on_exit} (@option{on}|@option{off})
3053 This will configure the parallel driver to write a known
3054 cable-specific value to the parallel interface on exiting OpenOCD.
3055 @end deffn
3057 For example, the interface configuration file for a
3058 classic ``Wiggler'' cable on LPT2 might look something like this:
3060 @example
3061 interface parport
3062 parport_port 0x278
3063 parport_cable wiggler
3064 @end example
3065 @end deffn
3067 @deffn {Interface Driver} {presto}
3068 ASIX PRESTO USB JTAG programmer.
3069 @deffn {Config Command} {presto_serial} serial_string
3070 Configures the USB serial number of the Presto device to use.
3071 @end deffn
3072 @end deffn
3074 @deffn {Interface Driver} {rlink}
3075 Raisonance RLink USB adapter
3076 @end deffn
3078 @deffn {Interface Driver} {usbprog}
3079 usbprog is a freely programmable USB adapter.
3080 @end deffn
3082 @deffn {Interface Driver} {vsllink}
3083 vsllink is part of Versaloon which is a versatile USB programmer.
3085 @quotation Note
3086 This defines quite a few driver-specific commands,
3087 which are not currently documented here.
3088 @end quotation
3089 @end deffn
3091 @deffn {Interface Driver} {hla}
3092 This is a driver that supports multiple High Level Adapters.
3093 This type of adapter does not expose some of the lower level api's
3094 that OpenOCD would normally use to access the target.
3096 Currently supported adapters include the ST STLINK and TI ICDI.
3097 STLINK firmware version >= V2.J21.S4 recommended due to issues with earlier
3098 versions of firmware where serial number is reset after first use. Suggest
3099 using ST firmware update utility to upgrade STLINK firmware even if current
3100 version reported is V2.J21.S4.
3102 @deffn {Config Command} {hla_device_desc} description
3103 Currently Not Supported.
3104 @end deffn
3106 @deffn {Config Command} {hla_serial} serial
3107 Specifies the serial number of the adapter.
3108 @end deffn
3110 @deffn {Config Command} {hla_layout} (@option{stlink}|@option{icdi})
3111 Specifies the adapter layout to use.
3112 @end deffn
3114 @deffn {Config Command} {hla_vid_pid} vid pid
3115 The vendor ID and product ID of the device.
3116 @end deffn
3118 @deffn {Command} {hla_command} command
3119 Execute a custom adapter-specific command. The @var{command} string is
3120 passed as is to the underlying adapter layout handler.
3121 @end deffn
3123 @deffn {Config Command} {trace} source_clock_hz [output_file_path]
3124 Enable SWO tracing (if supported). The source clock rate for the
3125 trace port must be specified, this is typically the CPU clock rate. If
3126 the optional output file is specified then raw trace data is appended
3127 to the file, and the file is created if it does not exist.
3128 @end deffn
3129 @end deffn
3131 @deffn {Interface Driver} {opendous}
3132 opendous-jtag is a freely programmable USB adapter.
3133 @end deffn
3135 @deffn {Interface Driver} {ulink}
3136 This is the Keil ULINK v1 JTAG debugger.
3137 @end deffn
3139 @deffn {Interface Driver} {ZY1000}
3140 This is the Zylin ZY1000 JTAG debugger.
3141 @end deffn
3143 @quotation Note
3144 This defines some driver-specific commands,
3145 which are not currently documented here.
3146 @end quotation
3148 @deffn Command power [@option{on}|@option{off}]
3149 Turn power switch to target on/off.
3150 No arguments: print status.
3151 @end deffn
3153 @deffn {Interface Driver} {bcm2835gpio}
3154 This SoC is present in Raspberry Pi which is a cheap single-board computer
3155 exposing some GPIOs on its expansion header.
3157 The driver accesses memory-mapped GPIO peripheral registers directly
3158 for maximum performance, but the only possible race condition is for
3159 the pins' modes/muxing (which is highly unlikely), so it should be
3160 able to coexist nicely with both sysfs bitbanging and various
3161 peripherals' kernel drivers. The driver restores the previous
3162 configuration on exit.
3164 See @file{interface/raspberrypi-native.cfg} for a sample config and
3165 pinout.
3167 @end deffn
3169 @section Transport Configuration
3170 @cindex Transport
3171 As noted earlier, depending on the version of OpenOCD you use,
3172 and the debug adapter you are using,
3173 several transports may be available to
3174 communicate with debug targets (or perhaps to program flash memory).
3175 @deffn Command {transport list}
3176 displays the names of the transports supported by this
3177 version of OpenOCD.
3178 @end deffn
3180 @deffn Command {transport select} transport_name
3181 Select which of the supported transports to use in this OpenOCD session.
3182 The transport must be supported by the debug adapter hardware and by the
3183 version of OpenOCD you are using (including the adapter's driver).
3184 No arguments: returns name of session's selected transport.
3185 @end deffn
3187 @subsection JTAG Transport
3188 @cindex JTAG
3189 JTAG is the original transport supported by OpenOCD, and most
3190 of the OpenOCD commands support it.
3191 JTAG transports expose a chain of one or more Test Access Points (TAPs),
3192 each of which must be explicitly declared.
3193 JTAG supports both debugging and boundary scan testing.
3194 Flash programming support is built on top of debug support.
3195 @subsection SWD Transport
3196 @cindex SWD
3197 @cindex Serial Wire Debug
3198 SWD (Serial Wire Debug) is an ARM-specific transport which exposes one
3199 Debug Access Point (DAP, which must be explicitly declared.
3200 (SWD uses fewer signal wires than JTAG.)
3201 SWD is debug-oriented, and does not support boundary scan testing.
3202 Flash programming support is built on top of debug support.
3203 (Some processors support both JTAG and SWD.)
3204 @deffn Command {swd newdap} ...
3205 Declares a single DAP which uses SWD transport.
3206 Parameters are currently the same as "jtag newtap" but this is
3207 expected to change.
3208 @end deffn
3209 @deffn Command {swd wcr trn prescale}
3210 Updates TRN (turnaraound delay) and prescaling.fields of the
3211 Wire Control Register (WCR).
3212 No parameters: displays current settings.
3213 @end deffn
3215 @subsection CMSIS-DAP Transport
3216 @cindex CMSIS-DAP
3217 CMSIS-DAP is an ARM-specific transport that is used to connect to
3218 compilant debuggers.
3220 @subsection SPI Transport
3221 @cindex SPI
3222 @cindex Serial Peripheral Interface
3223 The Serial Peripheral Interface (SPI) is a general purpose transport
3224 which uses four wire signaling. Some processors use it as part of a
3225 solution for flash programming.
3227 @anchor{jtagspeed}
3228 @section JTAG Speed
3229 JTAG clock setup is part of system setup.
3230 It @emph{does not belong with interface setup} since any interface
3231 only knows a few of the constraints for the JTAG clock speed.
3232 Sometimes the JTAG speed is
3233 changed during the target initialization process: (1) slow at
3234 reset, (2) program the CPU clocks, (3) run fast.
3235 Both the "slow" and "fast" clock rates are functions of the
3236 oscillators used, the chip, the board design, and sometimes
3237 power management software that may be active.
3239 The speed used during reset, and the scan chain verification which
3240 follows reset, can be adjusted using a @code{reset-start}
3241 target event handler.
3242 It can then be reconfigured to a faster speed by a
3243 @code{reset-init} target event handler after it reprograms those
3244 CPU clocks, or manually (if something else, such as a boot loader,
3245 sets up those clocks).
3246 @xref{targetevents,,Target Events}.
3247 When the initial low JTAG speed is a chip characteristic, perhaps
3248 because of a required oscillator speed, provide such a handler
3249 in the target config file.
3250 When that speed is a function of a board-specific characteristic
3251 such as which speed oscillator is used, it belongs in the board
3252 config file instead.
3253 In both cases it's safest to also set the initial JTAG clock rate
3254 to that same slow speed, so that OpenOCD never starts up using a
3255 clock speed that's faster than the scan chain can support.
3257 @example
3258 jtag_rclk 3000
3259 $_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
3260 @end example
3262 If your system supports adaptive clocking (RTCK), configuring
3263 JTAG to use that is probably the most robust approach.
3264 However, it introduces delays to synchronize clocks; so it
3265 may not be the fastest solution.
3267 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
3268 instead of @command{adapter_khz}, but only for (ARM) cores and boards
3269 which support adaptive clocking.
3271 @deffn {Command} adapter_khz max_speed_kHz
3272 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
3273 JTAG interfaces usually support a limited number of
3274 speeds. The speed actually used won't be faster
3275 than the speed specified.
3277 Chip data sheets generally include a top JTAG clock rate.
3278 The actual rate is often a function of a CPU core clock,
3279 and is normally less than that peak rate.
3280 For example, most ARM cores accept at most one sixth of the CPU clock.
3282 Speed 0 (khz) selects RTCK method.
3283 @xref{faqrtck,,FAQ RTCK}.
3284 If your system uses RTCK, you won't need to change the
3285 JTAG clocking after setup.
3286 Not all interfaces, boards, or targets support ``rtck''.
3287 If the interface device can not
3288 support it, an error is returned when you try to use RTCK.
3289 @end deffn
3291 @defun jtag_rclk fallback_speed_kHz
3292 @cindex adaptive clocking
3293 @cindex RTCK
3294 This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
3295 If that fails (maybe the interface, board, or target doesn't
3296 support it), falls back to the specified frequency.
3297 @example
3298 # Fall back to 3mhz if RTCK is not supported
3299 jtag_rclk 3000
3300 @end example
3301 @end defun
3303 @node Reset Configuration
3304 @chapter Reset Configuration
3305 @cindex Reset Configuration
3307 Every system configuration may require a different reset
3308 configuration. This can also be quite confusing.
3309 Resets also interact with @var{reset-init} event handlers,
3310 which do things like setting up clocks and DRAM, and
3311 JTAG clock rates. (@xref{jtagspeed,,JTAG Speed}.)
3312 They can also interact with JTAG routers.
3313 Please see the various board files for examples.
3315 @quotation Note
3316 To maintainers and integrators:
3317 Reset configuration touches several things at once.
3318 Normally the board configuration file
3319 should define it and assume that the JTAG adapter supports
3320 everything that's wired up to the board's JTAG connector.
3322 However, the target configuration file could also make note
3323 of something the silicon vendor has done inside the chip,
3324 which will be true for most (or all) boards using that chip.
3325 And when the JTAG adapter doesn't support everything, the
3326 user configuration file will need to override parts of
3327 the reset configuration provided by other files.
3328 @end quotation
3330 @section Types of Reset
3332 There are many kinds of reset possible through JTAG, but
3333 they may not all work with a given board and adapter.
3334 That's part of why reset configuration can be error prone.
3336 @itemize @bullet
3337 @item
3338 @emph{System Reset} ... the @emph{SRST} hardware signal
3339 resets all chips connected to the JTAG adapter, such as processors,
3340 power management chips, and I/O controllers. Normally resets triggered
3341 with this signal behave exactly like pressing a RESET button.
3342 @item
3343 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
3344 just the TAP controllers connected to the JTAG adapter.
3345 Such resets should not be visible to the rest of the system; resetting a
3346 device's TAP controller just puts that controller into a known state.
3347 @item
3348 @emph{Emulation Reset} ... many devices can be reset through JTAG
3349 commands. These resets are often distinguishable from system
3350 resets, either explicitly (a "reset reason" register says so)
3351 or implicitly (not all parts of the chip get reset).
3352 @item
3353 @emph{Other Resets} ... system-on-chip devices often support
3354 several other types of reset.
3355 You may need to arrange that a watchdog timer stops
3356 while debugging, preventing a watchdog reset.
3357 There may be individual module resets.
3358 @end itemize
3360 In the best case, OpenOCD can hold SRST, then reset
3361 the TAPs via TRST and send commands through JTAG to halt the
3362 CPU at the reset vector before the 1st instruction is executed.
3363 Then when it finally releases the SRST signal, the system is
3364 halted under debugger control before any code has executed.
3365 This is the behavior required to support the @command{reset halt}
3366 and @command{reset init} commands; after @command{reset init} a
3367 board-specific script might do things like setting up DRAM.
3368 (@xref{resetcommand,,Reset Command}.)
3370 @anchor{srstandtrstissues}
3371 @section SRST and TRST Issues
3373 Because SRST and TRST are hardware signals, they can have a
3374 variety of system-specific constraints. Some of the most
3375 common issues are:
3377 @itemize @bullet
3379 @item @emph{Signal not available} ... Some boards don't wire
3380 SRST or TRST to the JTAG connector. Some JTAG adapters don't
3381 support such signals even if they are wired up.
3382 Use the @command{reset_config} @var{signals} options to say
3383 when either of those signals is not connected.
3384 When SRST is not available, your code might not be able to rely
3385 on controllers having been fully reset during code startup.
3386 Missing TRST is not a problem, since JTAG-level resets can
3387 be triggered using with TMS signaling.
3389 @item @emph{Signals shorted} ... Sometimes a chip, board, or
3390 adapter will connect SRST to TRST, instead of keeping them separate.
3391 Use the @command{reset_config} @var{combination} options to say
3392 when those signals aren't properly independent.
3394 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
3395 delay circuit, reset supervisor, or on-chip features can extend
3396 the effect of a JTAG adapter's reset for some time after the adapter
3397 stops issuing the reset. For example, there may be chip or board
3398 requirements that all reset pulses last for at least a
3399 certain amount of time; and reset buttons commonly have
3400 hardware debouncing.
3401 Use the @command{adapter_nsrst_delay} and @command{jtag_ntrst_delay}
3402 commands to say when extra delays are needed.
3404 @item @emph{Drive type} ... Reset lines often have a pullup
3405 resistor, letting the JTAG interface treat them as open-drain
3406 signals. But that's not a requirement, so the adapter may need
3407 to use push/pull output drivers.
3408 Also, with weak pullups it may be advisable to drive
3409 signals to both levels (push/pull) to minimize rise times.
3410 Use the @command{reset_config} @var{trst_type} and
3411 @var{srst_type} parameters to say how to drive reset signals.
3413 @item @emph{Special initialization} ... Targets sometimes need
3414 special JTAG initialization sequences to handle chip-specific
3415 issues (not limited to errata).
3416 For example, certain JTAG commands might need to be issued while
3417 the system as a whole is in a reset state (SRST active)
3418 but the JTAG scan chain is usable (TRST inactive).
3419 Many systems treat combined assertion of SRST and TRST as a
3420 trigger for a harder reset than SRST alone.
3421 Such custom reset handling is discussed later in this chapter.
3422 @end itemize
3424 There can also be other issues.
3425 Some devices don't fully conform to the JTAG specifications.
3426 Trivial system-specific differences are common, such as
3427 SRST and TRST using slightly different names.
3428 There are also vendors who distribute key JTAG documentation for
3429 their chips only to developers who have signed a Non-Disclosure
3430 Agreement (NDA).
3432 Sometimes there are chip-specific extensions like a requirement to use
3433 the normally-optional TRST signal (precluding use of JTAG adapters which
3434 don't pass TRST through), or needing extra steps to complete a TAP reset.
3436 In short, SRST and especially TRST handling may be very finicky,
3437 needing to cope with both architecture and board specific constraints.
3439 @section Commands for Handling Resets
3441 @deffn {Command} adapter_nsrst_assert_width milliseconds
3442 Minimum amount of time (in milliseconds) OpenOCD should wait
3443 after asserting nSRST (active-low system reset) before
3444 allowing it to be deasserted.
3445 @end deffn
3447 @deffn {Command} adapter_nsrst_delay milliseconds
3448 How long (in milliseconds) OpenOCD should wait after deasserting
3449 nSRST (active-low system reset) before starting new JTAG operations.
3450 When a board has a reset button connected to SRST line it will
3451 probably have hardware debouncing, implying you should use this.
3452 @end deffn
3454 @deffn {Command} jtag_ntrst_assert_width milliseconds
3455 Minimum amount of time (in milliseconds) OpenOCD should wait
3456 after asserting nTRST (active-low JTAG TAP reset) before
3457 allowing it to be deasserted.
3458 @end deffn
3460 @deffn {Command} jtag_ntrst_delay milliseconds
3461 How long (in milliseconds) OpenOCD should wait after deasserting
3462 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
3463 @end deffn
3465 @deffn {Command} reset_config mode_flag ...
3466 This command displays or modifies the reset configuration
3467 of your combination of JTAG board and target in target
3468 configuration scripts.
3470 Information earlier in this section describes the kind of problems
3471 the command is intended to address (@pxref{srstandtrstissues,,SRST and TRST Issues}).
3472 As a rule this command belongs only in board config files,
3473 describing issues like @emph{board doesn't connect TRST};
3474 or in user config files, addressing limitations derived
3475 from a particular combination of interface and board.
3476 (An unlikely example would be using a TRST-only adapter
3477 with a board that only wires up SRST.)
3479 The @var{mode_flag} options can be specified in any order, but only one
3480 of each type -- @var{signals}, @var{combination}, @var{gates},
3481 @var{trst_type}, @var{srst_type} and @var{connect_type}
3482 -- may be specified at a time.
3483 If you don't provide a new value for a given type, its previous
3484 value (perhaps the default) is unchanged.
3485 For example, this means that you don't need to say anything at all about
3486 TRST just to declare that if the JTAG adapter should want to drive SRST,
3487 it must explicitly be driven high (@option{srst_push_pull}).
3489 @itemize
3490 @item
3491 @var{signals} can specify which of the reset signals are connected.
3492 For example, If the JTAG interface provides SRST, but the board doesn't
3493 connect that signal properly, then OpenOCD can't use it.
3494 Possible values are @option{none} (the default), @option{trst_only},
3495 @option{srst_only} and @option{trst_and_srst}.
3497 @quotation Tip
3498 If your board provides SRST and/or TRST through the JTAG connector,
3499 you must declare that so those signals can be used.
3500 @end quotation
3502 @item
3503 The @var{combination} is an optional value specifying broken reset
3504 signal implementations.
3505 The default behaviour if no option given is @option{separate},
3506 indicating everything behaves normally.
3507 @option{srst_pulls_trst} states that the
3508 test logic is reset together with the reset of the system (e.g. NXP
3509 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
3510 the system is reset together with the test logic (only hypothetical, I
3511 haven't seen hardware with such a bug, and can be worked around).
3512 @option{combined} implies both @option{srst_pulls_trst} and
3513 @option{trst_pulls_srst}.
3515 @item
3516 The @var{gates} tokens control flags that describe some cases where
3517 JTAG may be unvailable during reset.
3518 @option{srst_gates_jtag} (default)
3519 indicates that asserting SRST gates the
3520 JTAG clock. This means that no communication can happen on JTAG
3521 while SRST is asserted.
3522 Its converse is @option{srst_nogate}, indicating that JTAG commands
3523 can safely be issued while SRST is active.
3525 @item
3526 The @var{connect_type} tokens control flags that describe some cases where
3527 SRST is asserted while connecting to the target. @option{srst_nogate}
3528 is required to use this option.
3529 @option{connect_deassert_srst} (default)
3530 indicates that SRST will not be asserted while connecting to the target.
3531 Its converse is @option{connect_assert_srst}, indicating that SRST will
3532 be asserted before any target connection.
3533 Only some targets support this feature, STM32 and STR9 are examples.
3534 This feature is useful if you are unable to connect to your target due
3535 to incorrect options byte config or illegal program execution.
3536 @end itemize
3538 The optional @var{trst_type} and @var{srst_type} parameters allow the
3539 driver mode of each reset line to be specified. These values only affect
3540 JTAG interfaces with support for different driver modes, like the Amontec
3541 JTAGkey and JTAG Accelerator. Also, they are necessarily ignored if the
3542 relevant signal (TRST or SRST) is not connected.
3544 @itemize
3545 @item
3546 Possible @var{trst_type} driver modes for the test reset signal (TRST)
3547 are the default @option{trst_push_pull}, and @option{trst_open_drain}.
3548 Most boards connect this signal to a pulldown, so the JTAG TAPs
3549 never leave reset unless they are hooked up to a JTAG adapter.
3551 @item
3552 Possible @var{srst_type} driver modes for the system reset signal (SRST)
3553 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
3554 Most boards connect this signal to a pullup, and allow the
3555 signal to be pulled low by various events including system
3556 powerup and pressing a reset button.
3557 @end itemize
3558 @end deffn
3560 @section Custom Reset Handling
3561 @cindex events
3563 OpenOCD has several ways to help support the various reset
3564 mechanisms provided by chip and board vendors.
3565 The commands shown in the previous section give standard parameters.
3566 There are also @emph{event handlers} associated with TAPs or Targets.
3567 Those handlers are Tcl procedures you can provide, which are invoked
3568 at particular points in the reset sequence.
3570 @emph{When SRST is not an option} you must set
3571 up a @code{reset-assert} event handler for your target.
3572 For example, some JTAG adapters don't include the SRST signal;
3573 and some boards have multiple targets, and you won't always
3574 want to reset everything at once.
3576 After configuring those mechanisms, you might still
3577 find your board doesn't start up or reset correctly.
3578 For example, maybe it needs a slightly different sequence
3579 of SRST and/or TRST manipulations, because of quirks that
3580 the @command{reset_config} mechanism doesn't address;
3581 or asserting both might trigger a stronger reset, which
3582 needs special attention.
3584 Experiment with lower level operations, such as @command{jtag_reset}
3585 and the @command{jtag arp_*} operations shown here,
3586 to find a sequence of operations that works.
3587 @xref{JTAG Commands}.
3588 When you find a working sequence, it can be used to override
3589 @command{jtag_init}, which fires during OpenOCD startup
3590 (@pxref{configurationstage,,Configuration Stage});
3591 or @command{init_reset}, which fires during reset processing.
3593 You might also want to provide some project-specific reset
3594 schemes. For example, on a multi-target board the standard
3595 @command{reset} command would reset all targets, but you
3596 may need the ability to reset only one target at time and
3597 thus want to avoid using the board-wide SRST signal.
3599 @deffn {Overridable Procedure} init_reset mode
3600 This is invoked near the beginning of the @command{reset} command,
3601 usually to provide as much of a cold (power-up) reset as practical.
3602 By default it is also invoked from @command{jtag_init} if
3603 the scan chain does not respond to pure JTAG operations.
3604 The @var{mode} parameter is the parameter given to the
3605 low level reset command (@option{halt},
3606 @option{init}, or @option{run}), @option{setup},
3607 or potentially some other value.
3609 The default implementation just invokes @command{jtag arp_init-reset}.
3610 Replacements will normally build on low level JTAG
3611 operations such as @command{jtag_reset}.
3612 Operations here must not address individual TAPs
3613 (or their associated targets)
3614 until the JTAG scan chain has first been verified to work.
3616 Implementations must have verified the JTAG scan chain before
3617 they return.
3618 This is done by calling @command{jtag arp_init}
3619 (or @command{jtag arp_init-reset}).
3620 @end deffn
3622 @deffn Command {jtag arp_init}
3623 This validates the scan chain using just the four
3624 standard JTAG signals (TMS, TCK, TDI, TDO).
3625 It starts by issuing a JTAG-only reset.
3626 Then it performs checks to verify that the scan chain configuration
3627 matches the TAPs it can observe.
3628 Those checks include checking IDCODE values for each active TAP,
3629 and verifying the length of their instruction registers using
3630 TAP @code{-ircapture} and @code{-irmask} values.
3631 If these tests all pass, TAP @code{setup} events are
3632 issued to all TAPs with handlers for that event.
3633 @end deffn
3635 @deffn Command {jtag arp_init-reset}
3636 This uses TRST and SRST to try resetting
3637 everything on the JTAG scan chain
3638 (and anything else connected to SRST).
3639 It then invokes the logic of @command{jtag arp_init}.
3640 @end deffn
3643 @node TAP Declaration
3644 @chapter TAP Declaration
3645 @cindex TAP declaration
3646 @cindex TAP configuration
3648 @emph{Test Access Ports} (TAPs) are the core of JTAG.
3649 TAPs serve many roles, including:
3651 @itemize @bullet
3652 @item @b{Debug Target} A CPU TAP can be used as a GDB debug target.
3653 @item @b{Flash Programming} Some chips program the flash directly via JTAG.
3654 Others do it indirectly, making a CPU do it.
3655 @item @b{Program Download} Using the same CPU support GDB uses,
3656 you can initialize a DRAM controller, download code to DRAM, and then
3657 start running that code.
3658 @item @b{Boundary Scan} Most chips support boundary scan, which
3659 helps test for board assembly problems like solder bridges
3660 and missing connections.
3661 @end itemize
3663 OpenOCD must know about the active TAPs on your board(s).
3664 Setting up the TAPs is the core task of your configuration files.
3665 Once those TAPs are set up, you can pass their names to code
3666 which sets up CPUs and exports them as GDB targets,
3667 probes flash memory, performs low-level JTAG operations, and more.
3669 @section Scan Chains
3670 @cindex scan chain
3672 TAPs are part of a hardware @dfn{scan chain},
3673 which is a daisy chain of TAPs.
3674 They also need to be added to
3675 OpenOCD's software mirror of that hardware list,
3676 giving each member a name and associating other data with it.
3677 Simple scan chains, with a single TAP, are common in
3678 systems with a single microcontroller or microprocessor.
3679 More complex chips may have several TAPs internally.
3680 Very complex scan chains might have a dozen or more TAPs:
3681 several in one chip, more in the next, and connecting
3682 to other boards with their own chips and TAPs.
3684 You can display the list with the @command{scan_chain} command.
3685 (Don't confuse this with the list displayed by the @command{targets}
3686 command, presented in the next chapter.
3687 That only displays TAPs for CPUs which are configured as
3688 debugging targets.)
3689 Here's what the scan chain might look like for a chip more than one TAP:
3691 @verbatim
3692 TapName Enabled IdCode Expected IrLen IrCap IrMask
3693 -- ------------------ ------- ---------- ---------- ----- ----- ------
3694 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0x01 0x03
3695 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x01 0x0f
3696 2 omap5912.unknown Y 0x00000000 0x00000000 8 0x01 0x03
3697 @end verbatim
3699 OpenOCD can detect some of that information, but not all
3700 of it. @xref{autoprobing,,Autoprobing}.
3701 Unfortunately, those TAPs can't always be autoconfigured,
3702 because not all devices provide good support for that.
3703 JTAG doesn't require supporting IDCODE instructions, and
3704 chips with JTAG routers may not link TAPs into the chain
3705 until they are told to do so.
3707 The configuration mechanism currently supported by OpenOCD
3708 requires explicit configuration of all TAP devices using
3709 @command{jtag newtap} commands, as detailed later in this chapter.
3710 A command like this would declare one tap and name it @code{chip1.cpu}:
3712 @example
3713 jtag newtap chip1 cpu -irlen 4 -expected-id 0x3ba00477
3714 @end example
3716 Each target configuration file lists the TAPs provided
3717 by a given chip.
3718 Board configuration files combine all the targets on a board,
3719 and so forth.
3720 Note that @emph{the order in which TAPs are declared is very important.}
3721 That declaration order must match the order in the JTAG scan chain,
3722 both inside a single chip and between them.
3723 @xref{faqtaporder,,FAQ TAP Order}.
3725 For example, the ST Microsystems STR912 chip has
3726 three separate TAPs@footnote{See the ST
3727 document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
3728 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
3729 @url{http://eu.st.com/stonline/products/literature/ds/13495.pdf}}.
3730 To configure those taps, @file{target/str912.cfg}
3731 includes commands something like this:
3733 @example
3734 jtag newtap str912 flash ... params ...
3735 jtag newtap str912 cpu ... params ...
3736 jtag newtap str912 bs ... params ...
3737 @end example
3739 Actual config files typically use a variable such as @code{$_CHIPNAME}
3740 instead of literals like @option{str912}, to support more than one chip
3741 of each type. @xref{Config File Guidelines}.
3743 @deffn Command {jtag names}
3744 Returns the names of all current TAPs in the scan chain.
3745 Use @command{jtag cget} or @command{jtag tapisenabled}
3746 to examine attributes and state of each TAP.
3747 @example
3748 foreach t [jtag names] @{
3749 puts [format "TAP: %s\n" $t]
3750 @}
3751 @end example
3752 @end deffn
3754 @deffn Command {scan_chain}
3755 Displays the TAPs in the scan chain configuration,
3756 and their status.
3757 The set of TAPs listed by this command is fixed by
3758 exiting the OpenOCD configuration stage,
3759 but systems with a JTAG router can
3760 enable or disable TAPs dynamically.
3761 @end deffn
3763 @c FIXME! "jtag cget" should be able to return all TAP
3764 @c attributes, like "$target_name cget" does for targets.
3766 @c Probably want "jtag eventlist", and a "tap-reset" event
3767 @c (on entry to RESET state).
3769 @section TAP Names
3770 @cindex dotted name
3772 When TAP objects are declared with @command{jtag newtap},
3773 a @dfn{dotted.name} is created for the TAP, combining the
3774 name of a module (usually a chip) and a label for the TAP.
3775 For example: @code{xilinx.tap}, @code{str912.flash},
3776 @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
3777 Many other commands use that dotted.name to manipulate or
3778 refer to the TAP. For example, CPU configuration uses the
3779 name, as does declaration of NAND or NOR flash banks.
3781 The components of a dotted name should follow ``C'' symbol
3782 name rules: start with an alphabetic character, then numbers
3783 and underscores are OK; while others (including dots!) are not.
3785 @section TAP Declaration Commands
3787 @c shouldn't this be(come) a {Config Command}?
3788 @deffn Command {jtag newtap} chipname tapname configparams...
3789 Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
3790 and configured according to the various @var{configparams}.
3792 The @var{chipname} is a symbolic name for the chip.
3793 Conventionally target config files use @code{$_CHIPNAME},
3794 defaulting to the model name given by the chip vendor but
3795 overridable.
3797 @cindex TAP naming convention
3798 The @var{tapname} reflects the role of that TAP,
3799 and should follow this convention:
3801 @itemize @bullet
3802 @item @code{bs} -- For boundary scan if this is a separate TAP;
3803 @item @code{cpu} -- The main CPU of the chip, alternatively
3804 @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
3805 @code{arm1} and @code{arm2} on chips with two ARMs, and so forth;
3806 @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
3807 @item @code{flash} -- If the chip has a flash TAP, like the str912;
3808 @item @code{jrc} -- For JTAG route controller (example: the ICEPick modules
3809 on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
3810 @item @code{tap} -- Should be used only for FPGA- or CPLD-like devices
3811 with a single TAP;
3812 @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
3813 @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
3814 For example, the Freescale i.MX31 has a SDMA (Smart DMA) with
3815 a JTAG TAP; that TAP should be named @code{sdma}.
3816 @end itemize
3818 Every TAP requires at least the following @var{configparams}:
3820 @itemize @bullet
3821 @item @code{-irlen} @var{NUMBER}
3822 @*The length in bits of the
3823 instruction register, such as 4 or 5 bits.
3824 @end itemize
3826 A TAP may also provide optional @var{configparams}:
3828 @itemize @bullet
3829 @item @code{-disable} (or @code{-enable})
3830 @*Use the @code{-disable} parameter to flag a TAP which is not
3831 linked into the scan chain after a reset using either TRST
3832 or the JTAG state machine's @sc{reset} state.
3833 You may use @code{-enable} to highlight the default state
3834 (the TAP is linked in).
3835 @xref{enablinganddisablingtaps,,Enabling and Disabling TAPs}.
3836 @item @code{-expected-id} @var{NUMBER}
3837 @*A non-zero @var{number} represents a 32-bit IDCODE
3838 which you expect to find when the scan chain is examined.
3839 These codes are not required by all JTAG devices.
3840 @emph{Repeat the option} as many times as required if more than one
3841 ID code could appear (for example, multiple versions).
3842 Specify @var{number} as zero to suppress warnings about IDCODE
3843 values that were found but not included in the list.
3845 Provide this value if at all possible, since it lets OpenOCD
3846 tell when the scan chain it sees isn't right. These values
3847 are provided in vendors' chip documentation, usually a technical
3848 reference manual. Sometimes you may need to probe the JTAG
3849 hardware to find these values.
3850 @xref{autoprobing,,Autoprobing}.
3851 @item @code{-ignore-version}
3852 @*Specify this to ignore the JTAG version field in the @code{-expected-id}
3853 option. When vendors put out multiple versions of a chip, or use the same
3854 JTAG-level ID for several largely-compatible chips, it may be more practical
3855 to ignore the version field than to update config files to handle all of
3856 the various chip IDs. The version field is defined as bit 28-31 of the IDCODE.
3857 @item @code{-ircapture} @var{NUMBER}
3858 @*The bit pattern loaded by the TAP into the JTAG shift register
3859 on entry to the @sc{ircapture} state, such as 0x01.
3860 JTAG requires the two LSBs of this value to be 01.
3861 By default, @code{-ircapture} and @code{-irmask} are set
3862 up to verify that two-bit value. You may provide
3863 additional bits if you know them, or indicate that
3864 a TAP doesn't conform to the JTAG specification.
3865 @item @code{-irmask} @var{NUMBER}
3866 @*A mask used with @code{-ircapture}
3867 to verify that instruction scans work correctly.
3868 Such scans are not used by OpenOCD except to verify that
3869 there seems to be no problems with JTAG scan chain operations.
3870 @end itemize
3871 @end deffn
3873 @section Other TAP commands
3875 @deffn Command {jtag cget} dotted.name @option{-event} event_name
3876 @deffnx Command {jtag configure} dotted.name @option{-event} event_name handler
3877 At this writing this TAP attribute
3878 mechanism is used only for event handling.
3879 (It is not a direct analogue of the @code{cget}/@code{configure}
3880 mechanism for debugger targets.)
3881 See the next section for information about the available events.
3883 The @code{configure} subcommand assigns an event handler,
3884 a TCL string which is evaluated when the event is triggered.
3885 The @code{cget} subcommand returns that handler.
3886 @end deffn
3888 @section TAP Events
3889 @cindex events
3890 @cindex TAP events
3892 OpenOCD includes two event mechanisms.
3893 The one presented here applies to all JTAG TAPs.
3894 The other applies to debugger targets,
3895 which are associated with certain TAPs.
3897 The TAP events currently defined are:
3899 @itemize @bullet
3900 @item @b{post-reset}
3901 @* The TAP has just completed a JTAG reset.
3902 The tap may still be in the JTAG @sc{reset} state.
3903 Handlers for these events might perform initialization sequences
3904 such as issuing TCK cycles, TMS sequences to ensure
3905 exit from the ARM SWD mode, and more.
3907 Because the scan chain has not yet been verified, handlers for these events
3908 @emph{should not issue commands which scan the JTAG IR or DR registers}
3909 of any particular target.
3910 @b{NOTE:} As this is written (September 2009), nothing prevents such access.
3911 @item @b{setup}
3912 @* The scan chain has been reset and verified.
3913 This handler may enable TAPs as needed.
3914 @item @b{tap-disable}
3915 @* The TAP needs to be disabled. This handler should
3916 implement @command{jtag tapdisable}
3917 by issuing the relevant JTAG commands.
3918 @item @b{tap-enable}
3919 @* The TAP needs to be enabled. This handler should
3920 implement @command{jtag tapenable}
3921 by issuing the relevant JTAG commands.
3922 @end itemize
3924 If you need some action after each JTAG reset which isn't actually
3925 specific to any TAP (since you can't yet trust the scan chain's
3926 contents to be accurate), you might:
3928 @example
3929 jtag configure CHIP.jrc -event post-reset @{
3930 echo "JTAG Reset done"
3931 ... non-scan jtag operations to be done after reset
3932 @}
3933 @end example
3936 @anchor{enablinganddisablingtaps}
3937 @section Enabling and Disabling TAPs
3938 @cindex JTAG Route Controller
3939 @cindex jrc
3941 In some systems, a @dfn{JTAG Route Controller} (JRC)
3942 is used to enable and/or disable specific JTAG TAPs.
3943 Many ARM-based chips from Texas Instruments include
3944 an ``ICEPick'' module, which is a JRC.
3945 Such chips include DaVinci and OMAP3 processors.
3947 A given TAP may not be visible until the JRC has been
3948 told to link it into the scan chain; and if the JRC
3949 has been told to unlink that TAP, it will no longer
3950 be visible.
3951 Such routers address problems that JTAG ``bypass mode''
3952 ignores, such as:
3954 @itemize
3955 @item The scan chain can only go as fast as its slowest TAP.
3956 @item Having many TAPs slows instruction scans, since all
3957 TAPs receive new instructions.
3958 @item TAPs in the scan chain must be powered up, which wastes
3959 power and prevents debugging some power management mechanisms.
3960 @end itemize
3962 The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
3963 as implied by the existence of JTAG routers.
3964 However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
3965 does include a kind of JTAG router functionality.
3967 @c (a) currently the event handlers don't seem to be able to
3968 @c fail in a way that could lead to no-change-of-state.
3970 In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
3971 shown below, and is implemented using TAP event handlers.
3972 So for example, when defining a TAP for a CPU connected to
3973 a JTAG router, your @file{target.cfg} file
3974 should define TAP event handlers using
3975 code that looks something like this:
3977 @example
3978 jtag configure CHIP.cpu -event tap-enable @{
3979 ... jtag operations using CHIP.jrc
3980 @}
3981 jtag configure CHIP.cpu -event tap-disable @{
3982 ... jtag operations using CHIP.jrc
3983 @}
3984 @end example
3986 Then you might want that CPU's TAP enabled almost all the time:
3988 @example
3989 jtag configure $CHIP.jrc -event setup "jtag tapenable $CHIP.cpu"
3990 @end example
3992 Note how that particular setup event handler declaration
3993 uses quotes to evaluate @code{$CHIP} when the event is configured.
3994 Using brackets @{ @} would cause it to be evaluated later,
3995 at runtime, when it might have a different value.
3997 @deffn Command {jtag tapdisable} dotted.name
3998 If necessary, disables the tap
3999 by sending it a @option{tap-disable} event.
4000 Returns the string "1" if the tap
4001 specified by @var{dotted.name} is enabled,
4002 and "0" if it is disabled.
4003 @end deffn
4005 @deffn Command {jtag tapenable} dotted.name
4006 If necessary, enables the tap
4007 by sending it a @option{tap-enable} event.
4008 Returns the string "1" if the tap
4009 specified by @var{dotted.name} is enabled,
4010 and "0" if it is disabled.
4011 @end deffn
4013 @deffn Command {jtag tapisenabled} dotted.name
4014 Returns the string "1" if the tap
4015 specified by @var{dotted.name} is enabled,
4016 and "0" if it is disabled.
4018 @quotation Note
4019 Humans will find the @command{scan_chain} command more helpful
4020 for querying the state of the JTAG taps.
4021 @end quotation
4022 @end deffn
4024 @anchor{autoprobing}
4025 @section Autoprobing
4026 @cindex autoprobe
4027 @cindex JTAG autoprobe
4029 TAP configuration is the first thing that needs to be done
4030 after interface and reset configuration. Sometimes it's
4031 hard finding out what TAPs exist, or how they are identified.
4032 Vendor documentation is not always easy to find and use.
4034 To help you get past such problems, OpenOCD has a limited
4035 @emph{autoprobing} ability to look at the scan chain, doing
4036 a @dfn{blind interrogation} and then reporting the TAPs it finds.
4037 To use this mechanism, start the OpenOCD server with only data
4038 that configures your JTAG interface, and arranges to come up
4039 with a slow clock (many devices don't support fast JTAG clocks
4040 right when they come out of reset).
4042 For example, your @file{openocd.cfg} file might have:
4044 @example
4045 source [find interface/olimex-arm-usb-tiny-h.cfg]
4046 reset_config trst_and_srst
4047 jtag_rclk 8
4048 @end example
4050 When you start the server without any TAPs configured, it will
4051 attempt to autoconfigure the TAPs. There are two parts to this:
4053 @enumerate
4054 @item @emph{TAP discovery} ...
4055 After a JTAG reset (sometimes a system reset may be needed too),
4056 each TAP's data registers will hold the contents of either the
4057 IDCODE or BYPASS register.
4058 If JTAG communication is working, OpenOCD will see each TAP,
4059 and report what @option{-expected-id} to use with it.
4060 @item @emph{IR Length discovery} ...
4061 Unfortunately JTAG does not provide a reliable way to find out
4062 the value of the @option{-irlen} parameter to use with a TAP
4063 that is discovered.
4064 If OpenOCD can discover the length of a TAP's instruction
4065 register, it will report it.
4066 Otherwise you may need to consult vendor documentation, such
4067 as chip data sheets or BSDL files.
4068 @end enumerate
4070 In many cases your board will have a simple scan chain with just
4071 a single device. Here's what OpenOCD reported with one board
4072 that's a bit more complex:
4074 @example
4075 clock speed 8 kHz
4076 There are no enabled taps. AUTO PROBING MIGHT NOT WORK!!
4077 AUTO auto0.tap - use "jtag newtap auto0 tap -expected-id 0x2b900f0f ..."
4078 AUTO auto1.tap - use "jtag newtap auto1 tap -expected-id 0x07926001 ..."
4079 AUTO auto2.tap - use "jtag newtap auto2 tap -expected-id 0x0b73b02f ..."
4080 AUTO auto0.tap - use "... -irlen 4"
4081 AUTO auto1.tap - use "... -irlen 4"
4082 AUTO auto2.tap - use "... -irlen 6"
4083 no gdb ports allocated as no target has been specified
4084 @end example
4086 Given that information, you should be able to either find some existing
4087 config files to use, or create your own. If you create your own, you
4088 would configure from the bottom up: first a @file{target.cfg} file
4089 with these TAPs, any targets associated with them, and any on-chip
4090 resources; then a @file{board.cfg} with off-chip resources, clocking,
4091 and so forth.
4093 @node CPU Configuration
4094 @chapter CPU Configuration
4095 @cindex GDB target
4097 This chapter discusses how to set up GDB debug targets for CPUs.
4098 You can also access these targets without GDB
4099 (@pxref{Architecture and Core Commands},
4100 and @ref{targetstatehandling,,Target State handling}) and
4101 through various kinds of NAND and NOR flash commands.
4102 If you have multiple CPUs you can have multiple such targets.
4104 We'll start by looking at how to examine the targets you have,
4105 then look at how to add one more target and how to configure it.
4107 @section Target List
4108 @cindex target, current
4109 @cindex target, list
4111 All targets that have been set up are part of a list,
4112 where each member has a name.
4113 That name should normally be the same as the TAP name.
4114 You can display the list with the @command{targets}
4115 (plural!) command.
4116 This display often has only one CPU; here's what it might
4117 look like with more than one:
4118 @verbatim
4119 TargetName Type Endian TapName State
4120 -- ------------------ ---------- ------ ------------------ ------------
4121 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
4122 1 MyTarget cortex_m little mychip.foo tap-disabled
4123 @end verbatim
4125 One member of that list is the @dfn{current target}, which
4126 is implicitly referenced by many commands.
4127 It's the one marked with a @code{*} near the target name.
4128 In particular, memory addresses often refer to the address
4129 space seen by that current target.
4130 Commands like @command{mdw} (memory display words)
4131 and @command{flash erase_address} (erase NOR flash blocks)
4132 are examples; and there are many more.
4134 Several commands let you examine the list of targets:
4136 @deffn Command {target count}
4137 @emph{Note: target numbers are deprecated; don't use them.
4138 They will be removed shortly after August 2010, including this command.
4139 Iterate target using @command{target names}, not by counting.}
4141 Returns the number of targets, @math{N}.
4142 The highest numbered target is @math{N - 1}.
4143 @example
4144 set c [target count]
4145 for @{ set x 0 @} @{ $x < $c @} @{ incr x @} @{
4146 # Assuming you have created this function
4147 print_target_details $x
4148 @}
4149 @end example
4150 @end deffn
4152 @deffn Command {target current}
4153 Returns the name of the current target.
4154 @end deffn
4156 @deffn Command {target names}
4157 Lists the names of all current targets in the list.
4158 @example
4159 foreach t [target names] @{
4160 puts [format "Target: %s\n" $t]
4161 @}
4162 @end example
4163 @end deffn
4165 @deffn Command {target number} number
4166 @emph{Note: target numbers are deprecated; don't use them.
4167 They will be removed shortly after August 2010, including this command.}
4169 The list of targets is numbered starting at zero.
4170 This command returns the name of the target at index @var{number}.
4171 @example
4172 set thename [target number $x]