ebb3a4f88697f1b286706c95f915e22b0c4cf330
[openocd.git] / doc / openocd.texi
1 \input texinfo @c -*-texinfo-*-
2 @c %**start of header
3 @setfilename openocd.info
4 @settitle Open On-Chip Debugger (OpenOCD)
5 @dircategory Development
6 @direntry
7 @paragraphindent 0
8 * OpenOCD: (openocd). Open On-Chip Debugger.
9 @end direntry
10 @c %**end of header
11
12 @include version.texi
13
14 @copying
15
16 @itemize @bullet
17 @item Copyright @copyright{} 2008 The OpenOCD Project
18 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk}
19 @item Copyright @copyright{} 2008 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
20 @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
21 @end itemize
22
23 @quotation
24 Permission is granted to copy, distribute and/or modify this document
25 under the terms of the GNU Free Documentation License, Version 1.2 or
26 any later version published by the Free Software Foundation; with no
27 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
28 Texts. A copy of the license is included in the section entitled ``GNU
29 Free Documentation License''.
30 @end quotation
31 @end copying
32
33 @titlepage
34 @title Open On-Chip Debugger (OpenOCD)
35 @subtitle Edition @value{EDITION} for OpenOCD version @value{VERSION}
36 @subtitle @value{UPDATED}
37 @page
38 @vskip 0pt plus 1filll
39 @insertcopying
40 @end titlepage
41
42 @summarycontents
43 @contents
44
45 @node Top, About, , (dir)
46 @top OpenOCD
47
48 This manual documents edition @value{EDITION} of the Open On-Chip Debugger
49 (OpenOCD) version @value{VERSION}, @value{UPDATED}.
50
51 @insertcopying
52
53 @menu
54 * About:: About OpenOCD
55 * Developers:: OpenOCD Developers
56 * Building OpenOCD:: Building OpenOCD From SVN
57 * JTAG Hardware Dongles:: JTAG Hardware Dongles
58 * Running:: Running OpenOCD
59 * Simple Configuration Files:: Simple Configuration Files
60 * Config File Guidelines:: Config File Guidelines
61 * About JIM-Tcl:: About JIM-Tcl
62 * Daemon Configuration:: Daemon Configuration
63 * Interface - Dongle Configuration:: Interface - Dongle Configuration
64 * Reset Configuration:: Reset Configuration
65 * Tap Creation:: Tap Creation
66 * Target Configuration:: Target Configuration
67 * Flash Configuration:: Flash Configuration
68 * NAND Flash Commands:: NAND Flash Commands
69 * General Commands:: General Commands
70 * JTAG Commands:: JTAG Commands
71 * Sample Scripts:: Sample Target Scripts
72 * TFTP:: TFTP
73 * GDB and OpenOCD:: Using GDB and OpenOCD
74 * Tcl Scripting API:: Tcl Scripting API
75 * Upgrading:: Deprecated/Removed Commands
76 * Target Library:: Target Library
77 * FAQ:: Frequently Asked Questions
78 * Tcl Crash Course:: Tcl Crash Course
79 * License:: GNU Free Documentation License
80 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
81 @comment case issue with ``Index.html'' and ``index.html''
82 @comment Occurs when creating ``--html --no-split'' output
83 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
84 * OpenOCD Concept Index:: Concept Index
85 * OpenOCD Command Index:: Command Index
86 @end menu
87
88 @node About
89 @unnumbered About
90 @cindex about
91
92 OpenOCD was created by Dominic Rath as part of a diploma thesis written at the
93 University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
94 Since that time, the project has grown into an active open-source project,
95 supported by a diverse community of software and hardware developers from
96 around the world.
97
98 @section What is OpenOCD?
99
100 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
101 in-system programming and boundary-scan testing for embedded target
102 devices.
103
104 @b{JTAG:} OpenOCD uses a ``hardware interface dongle'' to communicate
105 with the JTAG (IEEE 1149.1) compliant taps on your target board.
106
107 @b{Dongles:} OpenOCD currently supports many types of hardware dongles: USB
108 based, parallel port based, and other standalone boxes that run
109 OpenOCD internally. @xref{JTAG Hardware Dongles}.
110
111 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
112 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x) and
113 Cortex-M3 (Luminary Stellaris LM3 and ST STM32) based cores to be
114 debugged via the GDB protocol.
115
116 @b{Flash Programing:} Flash writing is supported for external CFI
117 compatible NOR flashes (Intel and AMD/Spansion command set) and several
118 internal flashes (LPC2000, AT91SAM7, STR7x, STR9x, LM3, and
119 STM32x). Preliminary support for various NAND flash controllers
120 (LPC3180, Orion, S3C24xx, more) controller is included.
121
122 @section OpenOCD Web Site
123
124 The OpenOCD web site provides the latest public news from the community:
125
126 @uref{http://openocd.berlios.de/web/}
127
128
129 @node Developers
130 @chapter OpenOCD Developer Resources
131 @cindex developers
132
133 If you are interested in improving the state of OpenOCD's debugging and
134 testing support, new contributions will be welcome. Motivated developers
135 can produce new target, flash or interface drivers, improve the
136 documentation, as well as more conventional bug fixes and enhancements.
137
138 The resources in this chapter are available for developers wishing to explore
139 or expand the OpenOCD source code.
140
141 @section OpenOCD Subversion Repository
142
143 The ``Building From Source'' section provides instructions to retrieve
144 and and build the latest version of the OpenOCD source code.
145 @xref{Building OpenOCD}.
146
147 Developers that want to contribute patches to the OpenOCD system are
148 @b{strongly} encouraged to base their work off of the most recent trunk
149 revision. Patches created against older versions may require additional
150 work from their submitter in order to be updated for newer releases.
151
152 @section Doxygen Developer Manual
153
154 During the development of the 0.2.0 release, the OpenOCD project began
155 providing a Doxygen reference manual. This document contains more
156 technical information about the software internals, development
157 processes, and similar documentation:
158
159 @uref{http://openocd.berlios.de/doc/doxygen/index.html}
160
161 This document is a work-in-progress, but contributions would be welcome
162 to fill in the gaps. All of the source files are provided in-tree,
163 listed in the Doxyfile configuration in the top of the repository trunk.
164
165 @section OpenOCD Developer Mailing List
166
167 The OpenOCD Developer Mailing List provides the primary means of
168 communication between developers:
169
170 @uref{https://lists.berlios.de/mailman/listinfo/openocd-development}
171
172 All drivers developers are enouraged to also subscribe to the list of
173 SVN commits to keep pace with the ongoing changes:
174
175 @uref{https://lists.berlios.de/mailman/listinfo/openocd-svn}
176
177 @node Building OpenOCD
178 @chapter Building OpenOCD
179 @cindex building
180
181 @section Pre-Built Tools
182 If you are interested in getting actual work done rather than building
183 OpenOCD, then check if your interface supplier provides binaries for
184 you. Chances are that that binary is from some SVN version that is more
185 stable than SVN trunk where bleeding edge development takes place.
186
187 @section Packagers Please Read!
188
189 You are a @b{PACKAGER} of OpenOCD if you
190
191 @enumerate
192 @item @b{Sell dongles} and include pre-built binaries
193 @item @b{Supply tools} i.e.: A complete development solution
194 @item @b{Supply IDEs} like Eclipse, or RHIDE, etc.
195 @item @b{Build packages} i.e.: RPM files, or DEB files for a Linux Distro
196 @end enumerate
197
198 As a @b{PACKAGER}, you will experience first reports of most issues.
199 When you fix those problems for your users, your solution may help
200 prevent hundreds (if not thousands) of other questions from other users.
201
202 If something does not work for you, please work to inform the OpenOCD
203 developers know how to improve the system or documentation to avoid
204 future problems, and follow-up to help us ensure the issue will be fully
205 resolved in our future releases.
206
207 That said, the OpenOCD developers would also like you to follow a few
208 suggestions:
209
210 @enumerate
211 @item @b{Always build with printer ports enabled.}
212 @item @b{Try to use LIBFTDI + LIBUSB where possible. You cover more bases.}
213 @end enumerate
214
215 @itemize @bullet
216 @item @b{Why YES to LIBFTDI + LIBUSB?}
217 @itemize @bullet
218 @item @b{LESS} work - libusb perhaps already there
219 @item @b{LESS} work - identical code, multiple platforms
220 @item @b{MORE} dongles are supported
221 @item @b{MORE} platforms are supported
222 @item @b{MORE} complete solution
223 @end itemize
224 @item @b{Why not LIBFTDI + LIBUSB} (i.e.: ftd2xx instead)?
225 @itemize @bullet
226 @item @b{LESS} speed - some say it is slower
227 @item @b{LESS} complex to distribute (external dependencies)
228 @end itemize
229 @end itemize
230
231 @section Building From Source
232
233 You can download the current SVN version with an SVN client of your choice from the
234 following repositories:
235
236 @uref{svn://svn.berlios.de/openocd/trunk}
237
238 or
239
240 @uref{http://svn.berlios.de/svnroot/repos/openocd/trunk}
241
242 Using the SVN command line client, you can use the following command to fetch the
243 latest version (make sure there is no (non-svn) directory called "openocd" in the
244 current directory):
245
246 @example
247 svn checkout svn://svn.berlios.de/openocd/trunk openocd
248 @end example
249
250 Building OpenOCD requires a recent version of the GNU autotools (autoconf >= 2.59 and automake >= 1.9).
251 For building on Windows,
252 you have to use Cygwin. Make sure that your @env{PATH} environment variable contains no
253 other locations with Unix utils (like UnxUtils) - these can't handle the Cygwin
254 paths, resulting in obscure dependency errors (This is an observation I've gathered
255 from the logs of one user - correct me if I'm wrong).
256
257 You further need the appropriate driver files, if you want to build support for
258 a FTDI FT2232 based interface:
259
260 @itemize @bullet
261 @item @b{ftdi2232} libftdi (@uref{http://www.intra2net.com/opensource/ftdi/})
262 @item @b{ftd2xx} libftd2xx (@uref{http://www.ftdichip.com/Drivers/D2XX.htm})
263 @item When using the Amontec JTAGkey, you have to get the drivers from the Amontec
264 homepage (@uref{http://www.amontec.com}), as the JTAGkey uses a non-standard VID/PID.
265 @end itemize
266
267 libftdi is supported under Windows. Do not use versions earlier than 0.14.
268
269 In general, the D2XX driver provides superior performance (several times as fast),
270 but has the draw-back of being binary-only - though that isn't that bad, as it isn't
271 a kernel module, only a user space library.
272
273 To build OpenOCD (on both Linux and Cygwin), use the following commands:
274
275 @example
276 ./bootstrap
277 @end example
278
279 Bootstrap generates the configure script, and prepares building on your system.
280
281 @example
282 ./configure [options, see below]
283 @end example
284
285 Configure generates the Makefiles used to build OpenOCD.
286
287 @example
288 make
289 make install
290 @end example
291
292 Make builds OpenOCD, and places the final executable in ./src/, the last step, ``make install'' is optional.
293
294 The configure script takes several options, specifying which JTAG interfaces
295 should be included (among other things):
296
297 @itemize @bullet
298 @item
299 @option{--enable-parport} - Enable building the PC parallel port driver.
300 @item
301 @option{--enable-parport_ppdev} - Enable use of ppdev (/dev/parportN) for parport.
302 @item
303 @option{--enable-parport_giveio} - Enable use of giveio for parport instead of ioperm.
304 @item
305 @option{--enable-amtjtagaccel} - Enable building the Amontec JTAG-Accelerator driver.
306 @item
307 @option{--enable-ecosboard} - Enable building support for eCosBoard based JTAG debugger.
308 @item
309 @option{--enable-ioutil} - Enable ioutil functions - useful for standalone OpenOCD implementations.
310 @item
311 @option{--enable-httpd} - Enable builtin httpd server - useful for standalone OpenOCD implementations.
312 @item
313 @option{--enable-ep93xx} - Enable building support for EP93xx based SBCs.
314 @item
315 @option{--enable-at91rm9200} - Enable building support for AT91RM9200 based SBCs.
316 @item
317 @option{--enable-gw16012} - Enable building support for the Gateworks GW16012 JTAG programmer.
318 @item
319 @option{--enable-ft2232_ftd2xx} - Numerous USB type ARM JTAG dongles use the FT2232C chip from this FTDICHIP.COM chip (closed source).
320 @item
321 @option{--enable-ft2232_libftdi} - An open source (free) alternative to FTDICHIP.COM ftd2xx solution (Linux, MacOS, Cygwin).
322 @item
323 @option{--with-ftd2xx-win32-zipdir=PATH} - If using FTDICHIP.COM ft2232c, point at the directory where the Win32 FTDICHIP.COM 'CDM' driver zip file was unpacked.
324 @item
325 @option{--with-ftd2xx-linux-tardir=PATH} - Linux only. Equivalent of @option{--with-ftd2xx-win32-zipdir}, where you unpacked the TAR.GZ file.
326 @item
327 @option{--with-ftd2xx-lib=shared|static} - Linux only. Default: static. Specifies how the FTDICHIP.COM libftd2xx driver should be linked. Note: 'static' only works in conjunction with @option{--with-ftd2xx-linux-tardir}. The 'shared' value is supported (12/26/2008), however you must manually install the required header files and shared libraries in an appropriate place. This uses ``libusb'' internally.
328 @item
329 @option{--enable-presto_libftdi} - Enable building support for ASIX Presto programmer using the libftdi driver.
330 @item
331 @option{--enable-presto_ftd2xx} - Enable building support for ASIX Presto programmer using the FTD2XX driver.
332 @item
333 @option{--enable-usbprog} - Enable building support for the USBprog JTAG programmer.
334 @item
335 @option{--enable-oocd_trace} - Enable building support for the OpenOCD+trace ETM capture device.
336 @item
337 @option{--enable-jlink} - Enable building support for the Segger J-Link JTAG programmer.
338 @item
339 @option{--enable-vsllink} - Enable building support for the Versaloon-Link JTAG programmer.
340 @item
341 @option{--enable-rlink} - Enable building support for the Raisonance RLink JTAG programmer.
342 @item
343 @option{--enable-arm-jtag-ew} - Enable building support for the Olimex ARM-JTAG-EW programmer.
344 @item
345 @option{--enable-dummy} - Enable building the dummy port driver.
346 @end itemize
347
348 @section Parallel Port Dongles
349
350 If you want to access the parallel port using the PPDEV interface you have to specify
351 both the @option{--enable-parport} AND the @option{--enable-parport_ppdev} option since
352 the @option{--enable-parport_ppdev} option actually is an option to the parport driver
353 (see @uref{http://forum.sparkfun.com/viewtopic.php?t=3795} for more info).
354
355 The same is true for the @option{--enable-parport_giveio} option, you have to
356 use both the @option{--enable-parport} AND the @option{--enable-parport_giveio} option if you want to use giveio instead of ioperm parallel port access method.
357
358 @section FT2232C Based USB Dongles
359
360 There are 2 methods of using the FTD2232, either (1) using the
361 FTDICHIP.COM closed source driver, or (2) the open (and free) driver
362 libftdi. Some claim the (closed) FTDICHIP.COM solution is faster.
363
364 The FTDICHIP drivers come as either a (win32) ZIP file, or a (Linux)
365 TAR.GZ file. You must unpack them ``some where'' convient. As of this
366 writing (12/26/2008) FTDICHIP does not supply means to install these
367 files ``in an appropriate place'' As a result, there are two
368 ``./configure'' options that help.
369
370 Below is an example build process:
371
372 1) Check out the latest version of ``openocd'' from SVN.
373
374 2) Download & unpack either the Windows or Linux FTD2xx drivers
375 (@uref{http://www.ftdichip.com/Drivers/D2XX.htm}).
376
377 @example
378 /home/duane/ftd2xx.win32 => the Cygwin/Win32 ZIP file contents.
379 /home/duane/libftd2xx0.4.16 => the Linux TAR.GZ file contents.
380 @end example
381
382 3) Configure with these options:
383
384 @example
385 Cygwin FTDICHIP solution:
386 ./configure --prefix=/home/duane/mytools \
387 --enable-ft2232_ftd2xx \
388 --with-ftd2xx-win32-zipdir=/home/duane/ftd2xx.win32
389
390 Linux FTDICHIP solution:
391 ./configure --prefix=/home/duane/mytools \
392 --enable-ft2232_ftd2xx \
393 --with-ft2xx-linux-tardir=/home/duane/libftd2xx0.4.16
394
395 Cygwin/Linux LIBFTDI solution:
396 Assumes:
397 1a) For Windows: The Windows port of LIBUSB is in place.
398 1b) For Linux: libusb has been built/installed and is in place.
399
400 2) And libftdi has been built and installed
401 Note: libftdi - relies upon libusb.
402
403 ./configure --prefix=/home/duane/mytools \
404 --enable-ft2232_libftdi
405
406 @end example
407
408 4) Then just type ``make'', and perhaps ``make install''.
409
410
411 @section Miscellaneous Configure Options
412
413 @itemize @bullet
414 @item
415 @option{--disable-option-checking} - Ignore unrecognized @option{--enable} and @option{--with} options.
416 @item
417 @option{--enable-gccwarnings} - Enable extra gcc warnings during build.
418 Default is enabled.
419 @item
420 @option{--enable-release} - Enable building of an OpenOCD release, generally
421 this is for developers. It simply omits the svn version string when the
422 openocd @option{-v} is executed.
423 @end itemize
424
425 @node JTAG Hardware Dongles
426 @chapter JTAG Hardware Dongles
427 @cindex dongles
428 @cindex FTDI
429 @cindex wiggler
430 @cindex zy1000
431 @cindex printer port
432 @cindex USB Adapter
433 @cindex rtck
434
435 Defined: @b{dongle}: A small device that plugins into a computer and serves as
436 an adapter .... [snip]
437
438 In the OpenOCD case, this generally refers to @b{a small adapater} one
439 attaches to your computer via USB or the Parallel Printer Port. The
440 execption being the Zylin ZY1000 which is a small box you attach via
441 an ethernet cable. The Zylin ZY1000 has the advantage that it does not
442 require any drivers to be installed on the developer PC. It also has
443 a built in web interface. It supports RTCK/RCLK or adaptive clocking
444 and has a built in relay to power cycle targets remotely.
445
446
447 @section Choosing a Dongle
448
449 There are three things you should keep in mind when choosing a dongle.
450
451 @enumerate
452 @item @b{Voltage} What voltage is your target? 1.8, 2.8, 3.3, or 5V? Does your dongle support it?
453 @item @b{Connection} Printer Ports - Does your computer have one?
454 @item @b{Connection} Is that long printer bit-bang cable practical?
455 @item @b{RTCK} Do you require RTCK? Also known as ``adaptive clocking''
456 @end enumerate
457
458 @section Stand alone Systems
459
460 @b{ZY1000} See: @url{http://www.zylin.com/zy1000.html} Technically, not a
461 dongle, but a standalone box. The ZY1000 has the advantage that it does
462 not require any drivers installed on the developer PC. It also has
463 a built in web interface. It supports RTCK/RCLK or adaptive clocking
464 and has a built in relay to power cycle targets remotely.
465
466 @section USB FT2232 Based
467
468 There are many USB JTAG dongles on the market, many of them are based
469 on a chip from ``Future Technology Devices International'' (FTDI)
470 known as the FTDI FT2232.
471
472 See: @url{http://www.ftdichip.com} or @url{http://www.ftdichip.com/Products/FT2232H.htm}
473
474 As of 28/Nov/2008, the following are supported:
475
476 @itemize @bullet
477 @item @b{usbjtag}
478 @* Link @url{http://www.hs-augsburg.de/~hhoegl/proj/usbjtag/usbjtag.html}
479 @item @b{jtagkey}
480 @* See: @url{http://www.amontec.com/jtagkey.shtml}
481 @item @b{oocdlink}
482 @* See: @url{http://www.oocdlink.com} By Joern Kaipf
483 @item @b{signalyzer}
484 @* See: @url{http://www.signalyzer.com}
485 @item @b{evb_lm3s811}
486 @* See: @url{http://www.luminarymicro.com} - The Luminary Micro Stellaris LM3S811 eval board has an FTD2232C chip built in.
487 @item @b{olimex-jtag}
488 @* See: @url{http://www.olimex.com}
489 @item @b{flyswatter}
490 @* See: @url{http://www.tincantools.com}
491 @item @b{turtelizer2}
492 @* See: @url{http://www.ethernut.de}, or @url{http://www.ethernut.de/en/hardware/turtelizer/index.html}
493 @item @b{comstick}
494 @* Link: @url{http://www.hitex.com/index.php?id=383}
495 @item @b{stm32stick}
496 @* Link @url{http://www.hitex.com/stm32-stick}
497 @item @b{axm0432_jtag}
498 @* Axiom AXM-0432 Link @url{http://www.axman.com}
499 @end itemize
500
501 @section USB JLINK based
502 There are several OEM versions of the Segger @b{JLINK} adapter. It is
503 an example of a micro controller based JTAG adapter, it uses an
504 AT91SAM764 internally.
505
506 @itemize @bullet
507 @item @b{ATMEL SAMICE} Only works with ATMEL chips!
508 @* Link: @url{http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3892}
509 @item @b{SEGGER JLINK}
510 @* Link: @url{http://www.segger.com/jlink.html}
511 @item @b{IAR J-Link}
512 @* Link: @url{http://www.iar.com/website1/1.0.1.0/369/1/index.php}
513 @end itemize
514
515 @section USB RLINK based
516 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer, permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for SWD and not JTAG, thus not supported.
517
518 @itemize @bullet
519 @item @b{Raisonance RLink}
520 @* Link: @url{http://www.raisonance.com/products/RLink.php}
521 @item @b{STM32 Primer}
522 @* Link: @url{http://www.stm32circle.com/resources/stm32primer.php}
523 @item @b{STM32 Primer2}
524 @* Link: @url{http://www.stm32circle.com/resources/stm32primer2.php}
525 @end itemize
526
527 @section USB Other
528 @itemize @bullet
529 @item @b{USBprog}
530 @* Link: @url{http://www.embedded-projects.net/usbprog} - which uses an Atmel MEGA32 and a UBN9604
531
532 @item @b{USB - Presto}
533 @* Link: @url{http://tools.asix.net/prg_presto.htm}
534
535 @item @b{Versaloon-Link}
536 @* Link: @url{http://www.simonqian.com/en/Versaloon}
537
538 @item @b{ARM-JTAG-EW}
539 @* Link: @url{http://www.olimex.com/dev/arm-jtag-ew.html}
540 @end itemize
541
542 @section IBM PC Parallel Printer Port Based
543
544 The two well known ``JTAG Parallel Ports'' cables are the Xilnx DLC5
545 and the MacGraigor Wiggler. There are many clones and variations of
546 these on the market.
547
548 @itemize @bullet
549
550 @item @b{Wiggler} - There are many clones of this.
551 @* Link: @url{http://www.macraigor.com/wiggler.htm}
552
553 @item @b{DLC5} - From XILINX - There are many clones of this
554 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
555 produced, PDF schematics are easily found and it is easy to make.
556
557 @item @b{Amontec - JTAG Accelerator}
558 @* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
559
560 @item @b{GW16402}
561 @* Link: @url{http://www.gateworks.com/products/avila_accessories/gw16042.php}
562
563 @item @b{Wiggler2}
564 @* Link: @url{http://www.ccac.rwth-aachen.de/~michaels/index.php/hardware/armjtag}
565
566 @item @b{Wiggler_ntrst_inverted}
567 @* Yet another variation - See the source code, src/jtag/parport.c
568
569 @item @b{old_amt_wiggler}
570 @* Unknown - probably not on the market today
571
572 @item @b{arm-jtag}
573 @* Link: Most likely @url{http://www.olimex.com/dev/arm-jtag.html} [another wiggler clone]
574
575 @item @b{chameleon}
576 @* Link: @url{http://www.amontec.com/chameleon.shtml}
577
578 @item @b{Triton}
579 @* Unknown.
580
581 @item @b{Lattice}
582 @* ispDownload from Lattice Semiconductor @url{http://www.latticesemi.com/lit/docs/devtools/dlcable.pdf}
583
584 @item @b{flashlink}
585 @* From ST Microsystems, link:
586 @url{http://www.st.com/stonline/products/literature/um/7889.pdf}
587 Title: FlashLINK JTAG programing cable for PSD and uPSD
588
589 @end itemize
590
591 @section Other...
592 @itemize @bullet
593
594 @item @b{ep93xx}
595 @* An EP93xx based Linux machine using the GPIO pins directly.
596
597 @item @b{at91rm9200}
598 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
599
600 @end itemize
601
602 @node Running
603 @chapter Running
604 @cindex running OpenOCD
605 @cindex --configfile
606 @cindex --debug_level
607 @cindex --logfile
608 @cindex --search
609
610 The @option{--help} option shows:
611 @verbatim
612 bash$ openocd --help
613
614 --help | -h display this help
615 --version | -v display OpenOCD version
616 --file | -f use configuration file <name>
617 --search | -s dir to search for config files and scripts
618 --debug | -d set debug level <0-3>
619 --log_output | -l redirect log output to file <name>
620 --command | -c run <command>
621 --pipe | -p use pipes when talking to gdb
622 @end verbatim
623
624 By default OpenOCD reads the file configuration file ``openocd.cfg''
625 in the current directory. To specify a different (or multiple)
626 configuration file, you can use the ``-f'' option. For example:
627
628 @example
629 openocd -f config1.cfg -f config2.cfg -f config3.cfg
630 @end example
631
632 Once started, OpenOCD runs as a daemon, waiting for connections from
633 clients (Telnet, GDB, Other).
634
635 If you are having problems, you can enable internal debug messages via
636 the ``-d'' option.
637
638 Also it is possible to interleave commands w/config scripts using the
639 @option{-c} command line switch.
640
641 To enable debug output (when reporting problems or working on OpenOCD
642 itself), use the @option{-d} command line switch. This sets the
643 @option{debug_level} to "3", outputting the most information,
644 including debug messages. The default setting is "2", outputting only
645 informational messages, warnings and errors. You can also change this
646 setting from within a telnet or gdb session using @option{debug_level
647 <n>} @xref{debug_level}.
648
649 You can redirect all output from the daemon to a file using the
650 @option{-l <logfile>} switch.
651
652 Search paths for config/script files can be added to OpenOCD by using
653 the @option{-s <search>} switch. The current directory and the OpenOCD
654 target library is in the search path by default.
655
656 For details on the @option{-p} option. @xref{Connecting to GDB}.
657
658 Note! OpenOCD will launch the GDB & telnet server even if it can not
659 establish a connection with the target. In general, it is possible for
660 the JTAG controller to be unresponsive until the target is set up
661 correctly via e.g. GDB monitor commands in a GDB init script.
662
663 @node Simple Configuration Files
664 @chapter Simple Configuration Files
665 @cindex configuration
666
667 @section Outline
668 There are 4 basic ways of ``configurating'' OpenOCD to run, they are:
669
670 @enumerate
671 @item A small openocd.cfg file which ``sources'' other configuration files
672 @item A monolithic openocd.cfg file
673 @item Many -f filename options on the command line
674 @item Your Mixed Solution
675 @end enumerate
676
677 @section Small configuration file method
678
679 This is the preferred method. It is simple and works well for many
680 people. The developers of OpenOCD would encourage you to use this
681 method. If you create a new configuration please email new
682 configurations to the development list.
683
684 Here is an example of an openocd.cfg file for an ATMEL at91sam7x256
685
686 @example
687 source [find interface/signalyzer.cfg]
688
689 # GDB can also flash my flash!
690 gdb_memory_map enable
691 gdb_flash_program enable
692
693 source [find target/sam7x256.cfg]
694 @end example
695
696 There are many example configuration scripts you can work with. You
697 should look in the directory: @t{$(INSTALLDIR)/lib/openocd}. You
698 should find:
699
700 @enumerate
701 @item @b{board} - eval board level configurations
702 @item @b{interface} - specific dongle configurations
703 @item @b{target} - the target chips
704 @item @b{tcl} - helper scripts
705 @item @b{xscale} - things specific to the xscale.
706 @end enumerate
707
708 Look first in the ``boards'' area, then the ``targets'' area. Often a board
709 configuration is a good example to work from.
710
711 @section Many -f filename options
712 Some believe this is a wonderful solution, others find it painful.
713
714 You can use a series of ``-f filename'' options on the command line,
715 OpenOCD will read each filename in sequence, for example:
716
717 @example
718 openocd -f file1.cfg -f file2.cfg -f file2.cfg
719 @end example
720
721 You can also intermix various commands with the ``-c'' command line
722 option.
723
724 @section Monolithic file
725 The ``Monolithic File'' dispenses with all ``source'' statements and
726 puts everything in one self contained (monolithic) file. This is not
727 encouraged.
728
729 Please try to ``source'' various files or use the multiple -f
730 technique.
731
732 @section Advice for you
733 Often, one uses a ``mixed approach''. Where possible, please try to
734 ``source'' common things, and if needed cut/paste parts of the
735 standard distribution configuration files as needed.
736
737 @b{REMEMBER:} The ``important parts'' of your configuration file are:
738
739 @enumerate
740 @item @b{Interface} - Defines the dongle
741 @item @b{Taps} - Defines the JTAG Taps
742 @item @b{GDB Targets} - What GDB talks to
743 @item @b{Flash Programing} - Very Helpful
744 @end enumerate
745
746 Some key things you should look at and understand are:
747
748 @enumerate
749 @item The reset configuration of your debug environment as a whole
750 @item Is there a ``work area'' that OpenOCD can use?
751 @* For ARM - work areas mean up to 10x faster downloads.
752 @item For MMU/MPU based ARM chips (i.e.: ARM9 and later) will that work area still be available?
753 @item For complex targets (multiple chips) the JTAG SPEED becomes an issue.
754 @end enumerate
755
756
757
758 @node Config File Guidelines
759 @chapter Config File Guidelines
760
761 This section/chapter is aimed at developers and integrators of
762 OpenOCD. These are guidelines for creating new boards and new target
763 configurations as of 28/Nov/2008.
764
765 However, you, the user of OpenOCD, should be somewhat familiar with
766 this section as it should help explain some of the internals of what
767 you might be looking at.
768
769 The user should find the following directories under @t{$(INSTALLDIR)/lib/openocd} :
770
771 @itemize @bullet
772 @item @b{interface}
773 @*Think JTAG Dongle. Files that configure the JTAG dongle go here.
774 @item @b{board}
775 @* Think Circuit Board, PWA, PCB, they go by many names. Board files
776 contain initialization items that are specific to a board - for
777 example: The SDRAM initialization sequence for the board, or the type
778 of external flash and what address it is found at. Any initialization
779 sequence to enable that external flash or SDRAM should be found in the
780 board file. Boards may also contain multiple targets, i.e.: Two CPUs, or
781 a CPU and an FPGA or CPLD.
782 @item @b{target}
783 @* Think chip. The ``target'' directory represents a JTAG tap (or
784 chip) OpenOCD should control, not a board. Two common types of targets
785 are ARM chips and FPGA or CPLD chips.
786 @end itemize
787
788 @b{If needed...} The user in their ``openocd.cfg'' file or the board
789 file might override a specific feature in any of the above files by
790 setting a variable or two before sourcing the target file. Or adding
791 various commands specific to their situation.
792
793 @section Interface Config Files
794
795 The user should be able to source one of these files via a command like this:
796
797 @example
798 source [find interface/FOOBAR.cfg]
799 Or:
800 openocd -f interface/FOOBAR.cfg
801 @end example
802
803 A preconfigured interface file should exist for every interface in use
804 today, that said, perhaps some interfaces have only been used by the
805 sole developer who created it.
806
807 @b{FIXME/NOTE:} We need to add support for a variable like Tcl variable
808 tcl_platform(platform), it should be called jim_platform (because it
809 is jim, not real tcl) and it should contain 1 of 3 words: ``linux'',
810 ``cygwin'' or ``mingw''
811
812 Interface files should be found in @t{$(INSTALLDIR)/lib/openocd/interface}
813
814 @section Board Config Files
815
816 @b{Note: BOARD directory NEW as of 28/nov/2008}
817
818 The user should be able to source one of these files via a command like this:
819
820 @example
821 source [find board/FOOBAR.cfg]
822 Or:
823 openocd -f board/FOOBAR.cfg
824 @end example
825
826
827 The board file should contain one or more @t{source [find
828 target/FOO.cfg]} statements along with any board specific things.
829
830 In summary the board files should contain (if present)
831
832 @enumerate
833 @item External flash configuration (i.e.: NOR flash on CS0, two NANDs on CS2)
834 @item SDRAM configuration (size, speed, etc.
835 @item Board specific IO configuration (i.e.: GPIO pins might disable a 2nd flash)
836 @item Multiple TARGET source statements
837 @item All things that are not ``inside a chip''
838 @item Things inside a chip go in a 'target' file
839 @end enumerate
840
841 @section Target Config Files
842
843 The user should be able to source one of these files via a command like this:
844
845 @example
846 source [find target/FOOBAR.cfg]
847 Or:
848 openocd -f target/FOOBAR.cfg
849 @end example
850
851 In summary the target files should contain
852
853 @enumerate
854 @item Set defaults
855 @item Create taps
856 @item Reset configuration
857 @item Work areas
858 @item CPU/Chip/CPU-Core specific features
859 @item On-Chip flash
860 @end enumerate
861
862 @subsection Important variable names
863
864 By default, the end user should never need to set these
865 variables. However, if the user needs to override a setting they only
866 need to set the variable in a simple way.
867
868 @itemize @bullet
869 @item @b{CHIPNAME}
870 @* This gives a name to the overall chip, and is used as part of the
871 tap identifier dotted name.
872 @item @b{ENDIAN}
873 @* By default little - unless the chip or board is not normally used that way.
874 @item @b{CPUTAPID}
875 @* When OpenOCD examines the JTAG chain, it will attempt to identify
876 every chip. If the @t{-expected-id} is nonzero, OpenOCD attempts
877 to verify the tap id number verses configuration file and may issue an
878 error or warning like this. The hope is that this will help to pinpoint
879 problems in OpenOCD configurations.
880
881 @example
882 Info: JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
883 Error: ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
884 Error: ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
885 Error: ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
886 @end example
887
888 @item @b{_TARGETNAME}
889 @* By convention, this variable is created by the target configuration
890 script. The board configuration file may make use of this variable to
891 configure things like a ``reset init'' script, or other things
892 specific to that board and that target.
893
894 If the chip has 2 targets, use the names @b{_TARGETNAME0},
895 @b{_TARGETNAME1}, ... etc.
896
897 @b{Remember:} The ``board file'' may include multiple targets.
898
899 At no time should the name ``target0'' (the default target name if
900 none was specified) be used. The name ``target0'' is a hard coded name
901 - the next target on the board will be some other number.
902 In the same way, avoid using target numbers even when they are
903 permitted; use the right target name(s) for your board.
904
905 The user (or board file) should reasonably be able to:
906
907 @example
908 source [find target/FOO.cfg]
909 $_TARGETNAME configure ... FOO specific parameters
910
911 source [find target/BAR.cfg]
912 $_TARGETNAME configure ... BAR specific parameters
913 @end example
914
915 @end itemize
916
917 @subsection Tcl Variables Guide Line
918 The Full Tcl/Tk language supports ``namespaces'' - JIM-Tcl does not.
919
920 Thus the rule we follow in OpenOCD is this: Variables that begin with
921 a leading underscore are temporary in nature, and can be modified and
922 used at will within a ?TARGET? configuration file.
923
924 @b{EXAMPLE:} The user should be able to do this:
925
926 @example
927 # Board has 3 chips,
928 # PXA270 #1 network side, big endian
929 # PXA270 #2 video side, little endian
930 # Xilinx Glue logic
931 set CHIPNAME network
932 set ENDIAN big
933 source [find target/pxa270.cfg]
934 # variable: _TARGETNAME = network.cpu
935 # other commands can refer to the "network.cpu" tap.
936 $_TARGETNAME configure .... params for this CPU..
937
938 set ENDIAN little
939 set CHIPNAME video
940 source [find target/pxa270.cfg]
941 # variable: _TARGETNAME = video.cpu
942 # other commands can refer to the "video.cpu" tap.
943 $_TARGETNAME configure .... params for this CPU..
944
945 unset ENDIAN
946 set CHIPNAME xilinx
947 source [find target/spartan3.cfg]
948
949 # Since $_TARGETNAME is temporal..
950 # these names still work!
951 network.cpu configure ... params
952 video.cpu configure ... params
953
954 @end example
955
956 @subsection Default Value Boiler Plate Code
957
958 All target configuration files should start with this (or a modified form)
959
960 @example
961 # SIMPLE example
962 if @{ [info exists CHIPNAME] @} @{
963 set _CHIPNAME $CHIPNAME
964 @} else @{
965 set _CHIPNAME sam7x256
966 @}
967
968 if @{ [info exists ENDIAN] @} @{
969 set _ENDIAN $ENDIAN
970 @} else @{
971 set _ENDIAN little
972 @}
973
974 if @{ [info exists CPUTAPID ] @} @{
975 set _CPUTAPID $CPUTAPID
976 @} else @{
977 set _CPUTAPID 0x3f0f0f0f
978 @}
979
980 @end example
981
982 @subsection Creating Taps
983 After the ``defaults'' are choosen [see above] the taps are created.
984
985 @b{SIMPLE example:} such as an Atmel AT91SAM7X256
986
987 @example
988 # for an ARM7TDMI.
989 set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
990 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
991 @end example
992
993 @b{COMPLEX example:}
994
995 This is an SNIP/example for an STR912 - which has 3 internal taps. Key features shown:
996
997 @enumerate
998 @item @b{Unform tap names} - See: Tap Naming Convention
999 @item @b{_TARGETNAME} is created at the end where used.
1000 @end enumerate
1001
1002 @example
1003 if @{ [info exists FLASHTAPID ] @} @{
1004 set _FLASHTAPID $FLASHTAPID
1005 @} else @{
1006 set _FLASHTAPID 0x25966041
1007 @}
1008 jtag newtap $_CHIPNAME flash -irlen 8 -ircapture 0x1 -irmask 0x1 -expected-id $_FLASHTAPID
1009
1010 if @{ [info exists CPUTAPID ] @} @{
1011 set _CPUTAPID $CPUTAPID
1012 @} else @{
1013 set _CPUTAPID 0x25966041
1014 @}
1015 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0xf -irmask 0xe -expected-id $_CPUTAPID
1016
1017
1018 if @{ [info exists BSTAPID ] @} @{
1019 set _BSTAPID $BSTAPID
1020 @} else @{
1021 set _BSTAPID 0x1457f041
1022 @}
1023 jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BSTAPID
1024
1025 set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
1026 @end example
1027
1028 @b{Tap Naming Convention}
1029
1030 See the command ``jtag newtap'' for detail, but in brief the names you should use are:
1031
1032 @itemize @bullet
1033 @item @b{tap}
1034 @item @b{cpu}
1035 @item @b{flash}
1036 @item @b{bs}
1037 @item @b{etb}
1038 @item @b{jrc}
1039 @item @b{unknownN} - it happens :-(
1040 @end itemize
1041
1042 @subsection Reset Configuration
1043
1044 Some chips have specific ways the TRST and SRST signals are
1045 managed. If these are @b{CHIP SPECIFIC} they go here, if they are
1046 @b{BOARD SPECIFIC} they go in the board file.
1047
1048 @subsection Work Areas
1049
1050 Work areas are small RAM areas used by OpenOCD to speed up downloads,
1051 and to download small snippets of code to program flash chips.
1052
1053 If the chip includes a form of ``on-chip-ram'' - and many do - define
1054 a reasonable work area and use the ``backup'' option.
1055
1056 @b{PROBLEMS:} On more complex chips, this ``work area'' may become
1057 inaccessible if/when the application code enables or disables the MMU.
1058
1059 @subsection ARM Core Specific Hacks
1060
1061 If the chip has a DCC, enable it. If the chip is an ARM9 with some
1062 special high speed download features - enable it.
1063
1064 If the chip has an ARM ``vector catch'' feature - by default enable
1065 it for Undefined Instructions, Data Abort, and Prefetch Abort, if the
1066 user is really writing a handler for those situations - they can
1067 easily disable it. Experiance has shown the ``vector catch'' is
1068 helpful - for common programing errors.
1069
1070 If present, the MMU, the MPU and the CACHE should be disabled.
1071
1072 Some ARM cores are equipped with trace support, which permits
1073 examination of the instruction and data bus activity. Trace
1074 activity is controlled through an ``Embedded Trace Module'' (ETM)
1075 on one of the core's scan chains. The ETM emits voluminous data
1076 through a ``trace port''. The trace port is accessed in one
1077 of two ways. When its signals are pinned out from the chip,
1078 boards may provide a special high speed debugging connector;
1079 software support for this is not configured by default, use
1080 the ``--enable-oocd_trace'' option. Alternatively, trace data
1081 may be stored an on-chip SRAM which is packaged as an ``Embedded
1082 Trace Buffer'' (ETB). An ETB has its own TAP, usually right after
1083 its associated ARM core. OpenOCD supports the ETM, and your
1084 target configuration should set it up with the relevant trace
1085 port: ``etb'' for chips which use that, else the board-specific
1086 option will be either ``oocd_trace'' or ``dummy''.
1087
1088 @example
1089 etm config $_TARGETNAME 16 normal full etb
1090 etb config $_TARGETNAME $_CHIPNAME.etb
1091 @end example
1092
1093 @subsection Internal Flash Configuration
1094
1095 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
1096
1097 @b{Never ever} in the ``target configuration file'' define any type of
1098 flash that is external to the chip. (For example a BOOT flash on
1099 Chip Select 0.) Such flash information goes in a board file - not
1100 the TARGET (chip) file.
1101
1102 Examples:
1103 @itemize @bullet
1104 @item at91sam7x256 - has 256K flash YES enable it.
1105 @item str912 - has flash internal YES enable it.
1106 @item imx27 - uses boot flash on CS0 - it goes in the board file.
1107 @item pxa270 - again - CS0 flash - it goes in the board file.
1108 @end itemize
1109
1110 @node About JIM-Tcl
1111 @chapter About JIM-Tcl
1112 @cindex JIM Tcl
1113 @cindex tcl
1114
1115 OpenOCD includes a small ``TCL Interpreter'' known as JIM-TCL. You can
1116 learn more about JIM here: @url{http://jim.berlios.de}
1117
1118 @itemize @bullet
1119 @item @b{JIM vs. Tcl}
1120 @* JIM-TCL is a stripped down version of the well known Tcl language,
1121 which can be found here: @url{http://www.tcl.tk}. JIM-Tcl has far
1122 fewer features. JIM-Tcl is a single .C file and a single .H file and
1123 impliments the basic Tcl command set along. In contrast: Tcl 8.6 is a
1124 4.2 MB .zip file containing 1540 files.
1125
1126 @item @b{Missing Features}
1127 @* Our practice has been: Add/clone the real Tcl feature if/when
1128 needed. We welcome JIM Tcl improvements, not bloat.
1129
1130 @item @b{Scripts}
1131 @* OpenOCD configuration scripts are JIM Tcl Scripts. OpenOCD's
1132 command interpreter today (28/nov/2008) is a mixture of (newer)
1133 JIM-Tcl commands, and (older) the orginal command interpreter.
1134
1135 @item @b{Commands}
1136 @* At the OpenOCD telnet command line (or via the GDB mon command) one
1137 can type a Tcl for() loop, set variables, etc.
1138
1139 @item @b{Historical Note}
1140 @* JIM-Tcl was introduced to OpenOCD in spring 2008.
1141
1142 @item @b{Need a crash course in Tcl?}
1143 @* See: @xref{Tcl Crash Course}.
1144 @end itemize
1145
1146
1147 @node Daemon Configuration
1148 @chapter Daemon Configuration
1149 @cindex initialization
1150 The commands here are commonly found in the openocd.cfg file and are
1151 used to specify what TCP/IP ports are used, and how GDB should be
1152 supported.
1153
1154 @section Configuration Stage
1155 @cindex configuration stage
1156 @cindex configuration command
1157
1158 When the OpenOCD server process starts up, it enters a
1159 @emph{configuration stage} which is the only time that
1160 certain commands, @emph{configuration commands}, may be issued.
1161 Those configuration commands include declaration of TAPs
1162 and other basic setup.
1163 The server must leave the configuration stage before it
1164 may access or activate TAPs.
1165 After it leaves this stage, configuration commands may no
1166 longer be issued.
1167
1168 @deffn {Config Command} init
1169 This command terminates the configuration stage and
1170 enters the normal command mode. This can be useful to add commands to
1171 the startup scripts and commands such as resetting the target,
1172 programming flash, etc. To reset the CPU upon startup, add "init" and
1173 "reset" at the end of the config script or at the end of the OpenOCD
1174 command line using the @option{-c} command line switch.
1175
1176 If this command does not appear in any startup/configuration file
1177 OpenOCD executes the command for you after processing all
1178 configuration files and/or command line options.
1179
1180 @b{NOTE:} This command normally occurs at or near the end of your
1181 openocd.cfg file to force OpenOCD to ``initialize'' and make the
1182 targets ready. For example: If your openocd.cfg file needs to
1183 read/write memory on your target, @command{init} must occur before
1184 the memory read/write commands. This includes @command{nand probe}.
1185 @end deffn
1186
1187 @section TCP/IP Ports
1188 @cindex TCP port
1189 @cindex server
1190 @cindex port
1191 The OpenOCD server accepts remote commands in several syntaxes.
1192 Each syntax uses a different TCP/IP port, which you may specify
1193 only during configuration (before those ports are opened).
1194
1195 @deffn {Command} gdb_port (number)
1196 @cindex GDB server
1197 Specify or query the first port used for incoming GDB connections.
1198 The GDB port for the
1199 first target will be gdb_port, the second target will listen on gdb_port + 1, and so on.
1200 When not specified during the configuration stage,
1201 the port @var{number} defaults to 3333.
1202 @end deffn
1203
1204 @deffn {Command} tcl_port (number)
1205 Specify or query the port used for a simplified RPC
1206 connection that can be used by clients to issue TCL commands and get the
1207 output from the Tcl engine.
1208 Intended as a machine interface.
1209 When not specified during the configuration stage,
1210 the port @var{number} defaults to 6666.
1211 @end deffn
1212
1213 @deffn {Command} telnet_port (number)
1214 Specify or query the
1215 port on which to listen for incoming telnet connections.
1216 This port is intended for interaction with one human through TCL commands.
1217 When not specified during the configuration stage,
1218 the port @var{number} defaults to 4444.
1219 @end deffn
1220
1221 @section GDB Configuration
1222 @anchor{GDB Configuration}
1223 @cindex GDB
1224 @cindex GDB configuration
1225 You can reconfigure some GDB behaviors if needed.
1226 The ones listed here are static and global.
1227 @xref{Target Create}, about declaring individual targets.
1228 @xref{Target Events}, about configuring target-specific event handling.
1229
1230 @deffn {Command} gdb_breakpoint_override <hard|soft|disable>
1231 @anchor{gdb_breakpoint_override}
1232 Force breakpoint type for gdb @command{break} commands.
1233 The raison d'etre for this option is to support GDB GUI's which don't
1234 distinguish hard versus soft breakpoints, if the default OpenOCD and
1235 GDB behaviour is not sufficient. GDB normally uses hardware
1236 breakpoints if the memory map has been set up for flash regions.
1237
1238 This option replaces older arm7_9 target commands that addressed
1239 the same issue.
1240 @end deffn
1241
1242 @deffn {Config command} gdb_detach <resume|reset|halt|nothing>
1243 Configures what OpenOCD will do when GDB detaches from the daemon.
1244 Default behaviour is @var{resume}.
1245 @end deffn
1246
1247 @deffn {Config command} gdb_flash_program <enable|disable>
1248 @anchor{gdb_flash_program}
1249 Set to @var{enable} to cause OpenOCD to program the flash memory when a
1250 vFlash packet is received.
1251 The default behaviour is @var{enable}.
1252 @end deffn
1253
1254 @deffn {Config command} gdb_memory_map <enable|disable>
1255 Set to @var{enable} to cause OpenOCD to send the memory configuration to GDB when
1256 requested. GDB will then know when to set hardware breakpoints, and program flash
1257 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
1258 for flash programming to work.
1259 Default behaviour is @var{enable}.
1260 @xref{gdb_flash_program}.
1261 @end deffn
1262
1263 @deffn {Config command} gdb_report_data_abort <enable|disable>
1264 Specifies whether data aborts cause an error to be reported
1265 by GDB memory read packets.
1266 The default behaviour is @var{disable};
1267 use @var{enable} see these errors reported.
1268 @end deffn
1269
1270 @node Interface - Dongle Configuration
1271 @chapter Interface - Dongle Configuration
1272 Interface commands are normally found in an interface configuration
1273 file which is sourced by your openocd.cfg file. These commands tell
1274 OpenOCD what type of JTAG dongle you have and how to talk to it.
1275 @section Simple Complete Interface Examples
1276 @b{A Turtelizer FT2232 Based JTAG Dongle}
1277 @verbatim
1278 #interface
1279 interface ft2232
1280 ft2232_device_desc "Turtelizer JTAG/RS232 Adapter A"
1281 ft2232_layout turtelizer2
1282 ft2232_vid_pid 0x0403 0xbdc8
1283 @end verbatim
1284 @b{A SEGGER Jlink}
1285 @verbatim
1286 # jlink interface
1287 interface jlink
1288 @end verbatim
1289 @b{A Raisonance RLink}
1290 @verbatim
1291 # rlink interface
1292 interface rlink
1293 @end verbatim
1294 @b{Parallel Port}
1295 @verbatim
1296 interface parport
1297 parport_port 0xc8b8
1298 parport_cable wiggler
1299 jtag_speed 0
1300 @end verbatim
1301 @b{ARM-JTAG-EW}
1302 @verbatim
1303 interface arm-jtag-ew
1304 @end verbatim
1305 @section Interface Command
1306
1307 The interface command tells OpenOCD what type of JTAG dongle you are
1308 using. Depending on the type of dongle, you may need to have one or
1309 more additional commands.
1310
1311 @itemize @bullet
1312
1313 @item @b{interface} <@var{name}>
1314 @cindex interface
1315 @*Use the interface driver <@var{name}> to connect to the
1316 target. Currently supported interfaces are
1317
1318 @itemize @minus
1319
1320 @item @b{parport}
1321 @* PC parallel port bit-banging (Wigglers, PLD download cable, ...)
1322
1323 @item @b{amt_jtagaccel}
1324 @* Amontec Chameleon in its JTAG Accelerator configuration connected to a PC's EPP
1325 mode parallel port
1326
1327 @item @b{ft2232}
1328 @* FTDI FT2232 (USB) based devices using either the open-source libftdi or the binary only
1329 FTD2XX driver. The FTD2XX is superior in performance, but not available on every
1330 platform. The libftdi uses libusb, and should be portable to all systems that provide
1331 libusb.
1332
1333 @item @b{ep93xx}
1334 @*Cirrus Logic EP93xx based single-board computer bit-banging (in development)
1335
1336 @item @b{presto}
1337 @* ASIX PRESTO USB JTAG programmer.
1338
1339 @item @b{usbprog}
1340 @* usbprog is a freely programmable USB adapter.
1341
1342 @item @b{gw16012}
1343 @* Gateworks GW16012 JTAG programmer.
1344
1345 @item @b{jlink}
1346 @* Segger jlink USB adapter
1347
1348 @item @b{rlink}
1349 @* Raisonance RLink USB adapter
1350
1351 @item @b{vsllink}
1352 @* vsllink is part of Versaloon which is a versatile USB programmer.
1353
1354 @item @b{arm-jtag-ew}
1355 @* Olimex ARM-JTAG-EW USB adapter
1356 @comment - End parameters
1357 @end itemize
1358 @comment - End Interface
1359 @end itemize
1360 @subsection parport options
1361
1362 @itemize @bullet
1363 @item @b{parport_port} <@var{number}>
1364 @cindex parport_port
1365 @*Either the address of the I/O port (default: 0x378 for LPT1) or the number of
1366 the @file{/dev/parport} device
1367
1368 When using PPDEV to access the parallel port, use the number of the parallel port:
1369 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
1370 you may encounter a problem.
1371 @item @b{parport_cable} <@var{name}>
1372 @cindex parport_cable
1373 @*The layout of the parallel port cable used to connect to the target.
1374 Currently supported cables are
1375 @itemize @minus
1376 @item @b{wiggler}
1377 @cindex wiggler
1378 The original Wiggler layout, also supported by several clones, such
1379 as the Olimex ARM-JTAG
1380 @item @b{wiggler2}
1381 @cindex wiggler2
1382 Same as original wiggler except an led is fitted on D5.
1383 @item @b{wiggler_ntrst_inverted}
1384 @cindex wiggler_ntrst_inverted
1385 Same as original wiggler except TRST is inverted.
1386 @item @b{old_amt_wiggler}
1387 @cindex old_amt_wiggler
1388 The Wiggler configuration that comes with Amontec's Chameleon Programmer. The new
1389 version available from the website uses the original Wiggler layout ('@var{wiggler}')
1390 @item @b{chameleon}
1391 @cindex chameleon
1392 The Amontec Chameleon's CPLD when operated in configuration mode. This is only used to
1393 program the Chameleon itself, not a connected target.
1394 @item @b{dlc5}
1395 @cindex dlc5
1396 The Xilinx Parallel cable III.
1397 @item @b{triton}
1398 @cindex triton
1399 The parallel port adapter found on the 'Karo Triton 1 Development Board'.
1400 This is also the layout used by the HollyGates design
1401 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
1402 @item @b{flashlink}
1403 @cindex flashlink
1404 The ST Parallel cable.
1405 @item @b{arm-jtag}
1406 @cindex arm-jtag
1407 Same as original wiggler except SRST and TRST connections reversed and
1408 TRST is also inverted.
1409 @item @b{altium}
1410 @cindex altium
1411 Altium Universal JTAG cable.
1412 @end itemize
1413 @item @b{parport_write_on_exit} <@var{on}|@var{off}>
1414 @cindex parport_write_on_exit
1415 @*This will configure the parallel driver to write a known value to the parallel
1416 interface on exiting OpenOCD
1417 @end itemize
1418
1419 @subsection amt_jtagaccel options
1420 @itemize @bullet
1421 @item @b{parport_port} <@var{number}>
1422 @cindex parport_port
1423 @*Either the address of the I/O port (default: 0x378 for LPT1) or the number of the
1424 @file{/dev/parport} device
1425 @end itemize
1426 @subsection ft2232 options
1427
1428 @itemize @bullet
1429 @item @b{ft2232_device_desc} <@var{description}>
1430 @cindex ft2232_device_desc
1431 @*The USB device description of the FTDI FT2232 device. If not
1432 specified, the FTDI default value is used. This setting is only valid
1433 if compiled with FTD2XX support.
1434
1435 @b{TODO:} Confirm the following: On Windows the name needs to end with
1436 a ``space A''? Or not? It has to do with the FTD2xx driver. When must
1437 this be added and when must it not be added? Why can't the code in the
1438 interface or in OpenOCD automatically add this if needed? -- Duane.
1439
1440 @item @b{ft2232_serial} <@var{serial-number}>
1441 @cindex ft2232_serial
1442 @*The serial number of the FTDI FT2232 device. If not specified, the FTDI default
1443 values are used.
1444 @item @b{ft2232_layout} <@var{name}>
1445 @cindex ft2232_layout
1446 @*The layout of the FT2232 GPIO signals used to control output-enables and reset
1447 signals. Valid layouts are
1448 @itemize @minus
1449 @item @b{usbjtag}
1450 "USBJTAG-1" layout described in the original OpenOCD diploma thesis
1451 @item @b{jtagkey}
1452 Amontec JTAGkey and JTAGkey-Tiny
1453 @item @b{signalyzer}
1454 Signalyzer
1455 @item @b{olimex-jtag}
1456 Olimex ARM-USB-OCD
1457 @item @b{m5960}
1458 American Microsystems M5960
1459 @item @b{evb_lm3s811}
1460 Luminary Micro EVB_LM3S811 as a JTAG interface (not onboard processor), no TRST or
1461 SRST signals on external connector
1462 @item @b{comstick}
1463 Hitex STR9 comstick
1464 @item @b{stm32stick}
1465 Hitex STM32 Performance Stick
1466 @item @b{flyswatter}
1467 Tin Can Tools Flyswatter
1468 @item @b{turtelizer2}
1469 egnite Software turtelizer2
1470 @item @b{oocdlink}
1471 OOCDLink
1472 @item @b{axm0432_jtag}
1473 Axiom AXM-0432
1474 @end itemize
1475
1476 @item @b{ft2232_vid_pid} <@var{vid}> <@var{pid}>
1477 @*The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
1478 default values are used. Multiple <@var{vid}>, <@var{pid}> pairs may be given, e.g.
1479 @example
1480 ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
1481 @end example
1482 @item @b{ft2232_latency} <@var{ms}>
1483 @*On some systems using FT2232 based JTAG interfaces the FT_Read function call in
1484 ft2232_read() fails to return the expected number of bytes. This can be caused by
1485 USB communication delays and has proved hard to reproduce and debug. Setting the
1486 FT2232 latency timer to a larger value increases delays for short USB packets but it
1487 also reduces the risk of timeouts before receiving the expected number of bytes.
1488 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
1489 @end itemize
1490
1491 @subsection ep93xx options
1492 @cindex ep93xx options
1493 Currently, there are no options available for the ep93xx interface.
1494
1495 @section JTAG Speed
1496 @anchor{JTAG Speed}
1497 JTAG clock setup is part of system setup.
1498 It @emph{does not belong with interface setup} since any interface
1499 only knows a few of the constraints for the JTAG clock speed.
1500 Sometimes the JTAG speed is
1501 changed during the target initialization process: (1) slow at
1502 reset, (2) program the CPU clocks, (3) run fast.
1503 Both the "slow" and "fast" clock rates are functions of the
1504 oscillators used, the chip, the board design, and sometimes
1505 power management software that may be active.
1506
1507 The speed used during reset can be adjusted using pre_reset
1508 and post_reset event handlers.
1509 @xref{Target Events}.
1510
1511 If your system supports adaptive clocking (RTCK), configuring
1512 JTAG to use that is probably the most robust approach.
1513 However, it introduces delays to synchronize clocks; so it
1514 may not be the fastest solution.
1515
1516 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
1517 instead of @command{jtag_khz}.
1518
1519 @deffn {Command} jtag_khz max_speed_kHz
1520 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
1521 JTAG interfaces usually support a limited number of
1522 speeds. The speed actually used won't be faster
1523 than the speed specified.
1524
1525 As a rule of thumb, if you specify a clock rate make
1526 sure the JTAG clock is no more than @math{1/6th CPU-Clock}.
1527 This is especially true for synthesized cores (ARMxxx-S).
1528
1529 Speed 0 (khz) selects RTCK method.
1530 @xref{FAQ RTCK}.
1531 If your system uses RTCK, you won't need to change the
1532 JTAG clocking after setup.
1533 Not all interfaces, boards, or targets support ``rtck''.
1534 If the interface device can not
1535 support it, an error is returned when you try to use RTCK.
1536 @end deffn
1537
1538 @defun jtag_rclk fallback_speed_kHz
1539 @cindex RTCK
1540 This Tcl proc (defined in startup.tcl) attempts to enable RTCK/RCLK.
1541 If that fails (maybe the interface, board, or target doesn't
1542 support it), falls back to the specified frequency.
1543 @example
1544 # Fall back to 3mhz if RTCK is not supported
1545 jtag_rclk 3000
1546 @end example
1547 @end defun
1548
1549 @node Reset Configuration
1550 @chapter Reset Configuration
1551 @cindex Reset Configuration
1552
1553 Every system configuration may require a different reset
1554 configuration. This can also be quite confusing.
1555 Please see the various board files for examples.
1556
1557 @b{Note} to maintainers and integrators:
1558 Reset configuration touches several things at once.
1559 Normally the board configuration file
1560 should define it and assume that the JTAG adapter supports
1561 everything that's wired up to the board's JTAG connector.
1562 However, the target configuration file could also make note
1563 of something the silicon vendor has done inside the chip,
1564 which will be true for most (or all) boards using that chip.
1565 And when the JTAG adapter doesn't support everything, the
1566 system configuration file will need to override parts of
1567 the reset configuration provided by other files.
1568
1569 @section Types of Reset
1570
1571 There are many kinds of reset possible through JTAG, but
1572 they may not all work with a given board and adapter.
1573 That's part of why reset configuration can be error prone.
1574
1575 @itemize @bullet
1576 @item
1577 @emph{System Reset} ... the @emph{SRST} hardware signal
1578 resets all chips connected to the JTAG adapter, such as processors,
1579 power management chips, and I/O controllers. Normally resets triggered
1580 with this signal behave exactly like pressing a RESET button.
1581 @item
1582 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
1583 just the TAP controllers connected to the JTAG adapter.
1584 Such resets should not be visible to the rest of the system; resetting a
1585 device's the TAP controller just puts that controller into a known state.
1586 @item
1587 @emph{Emulation Reset} ... many devices can be reset through JTAG
1588 commands. These resets are often distinguishable from system
1589 resets, either explicitly (a "reset reason" register says so)
1590 or implicitly (not all parts of the chip get reset).
1591 @item
1592 @emph{Other Resets} ... system-on-chip devices often support
1593 several other types of reset.
1594 You may need to arrange that a watchdog timer stops
1595 while debugging, preventing a watchdog reset.
1596 There may be individual module resets.
1597 @end itemize
1598
1599 In the best case, OpenOCD can hold SRST, then reset
1600 the TAPs via TRST and send commands through JTAG to halt the
1601 CPU at the reset vector before the 1st instruction is executed.
1602 Then when it finally releases the SRST signal, the system is
1603 halted under debugger control before any code has executed.
1604 This is the behavior required to support the @command{reset halt}
1605 and @command{reset init} commands; after @command{reset init} a
1606 board-specific script might do things like setting up DRAM.
1607 (@xref{Reset Command}.)
1608
1609 @section SRST and TRST Signal Issues
1610
1611 Because SRST and TRST are hardware signals, they can have a
1612 variety of system-specific constraints. Some of the most
1613 common issues are:
1614
1615 @itemize @bullet
1616
1617 @item @emph{Signal not available} ... Some boards don't wire
1618 SRST or TRST to the JTAG connector. Some JTAG adapters don't
1619 support such signals even if they are wired up.
1620 Use the @command{reset_config} @var{signals} options to say
1621 when one of those signals is not connected.
1622 When SRST is not available, your code might not be able to rely
1623 on controllers having been fully reset during code startup.
1624
1625 @item @emph{Signals shorted} ... Sometimes a chip, board, or
1626 adapter will connect SRST to TRST, instead of keeping them separate.
1627 Use the @command{reset_config} @var{combination} options to say
1628 when those signals aren't properly independent.
1629
1630 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
1631 delay circuit, reset supervisor, or on-chip features can extend
1632 the effect of a JTAG adapter's reset for some time after the adapter
1633 stops issuing the reset. For example, there may be chip or board
1634 requirements that all reset pulses last for at least a
1635 certain amount of time; and reset buttons commonly have
1636 hardware debouncing.
1637 Use the @command{jtag_nsrst_delay} and @command{jtag_ntrst_delay}
1638 commands to say when extra delays are needed.
1639
1640 @item @emph{Drive type} ... Reset lines often have a pullup
1641 resistor, letting the JTAG interface treat them as open-drain
1642 signals. But that's not a requirement, so the adapter may need
1643 to use push/pull output drivers.
1644 Also, with weak pullups it may be advisable to drive
1645 signals to both levels (push/pull) to minimize rise times.
1646 Use the @command{reset_config} @var{trst_type} and
1647 @var{srst_type} parameters to say how to drive reset signals.
1648 @end itemize
1649
1650 There can also be other issues.
1651 Some devices don't fully conform to the JTAG specifications.
1652 Others have chip-specific extensions like extra steps needed
1653 during TAP reset, or a requirement to use the normally-optional TRST
1654 signal.
1655 Trivial system-specific differences are common, such as
1656 SRST and TRST using slightly different names.
1657
1658 @section Commands for Handling Resets
1659
1660 @deffn {Command} jtag_nsrst_delay milliseconds
1661 How long (in milliseconds) OpenOCD should wait after deasserting
1662 nSRST (active-low system reset) before starting new JTAG operations.
1663 When a board has a reset button connected to SRST line it will
1664 probably have hardware debouncing, implying you should use this.
1665 @end deffn
1666
1667 @deffn {Command} jtag_ntrst_delay milliseconds
1668 How long (in milliseconds) OpenOCD should wait after deasserting
1669 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
1670 @end deffn
1671
1672 @deffn {Command} reset_config signals [combination [trst_type [srst_type]]]
1673 This command tells OpenOCD the reset configuration
1674 of your combination of JTAG interface, board, and target.
1675 If the JTAG interface provides SRST, but the board doesn't connect
1676 that signal properly, then OpenOCD can't use it. @var{signals} can
1677 be @option{none}, @option{trst_only}, @option{srst_only} or
1678 @option{trst_and_srst}.
1679
1680 The @var{combination} is an optional value specifying broken reset
1681 signal implementations. @option{srst_pulls_trst} states that the
1682 test logic is reset together with the reset of the system (e.g. Philips
1683 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
1684 the system is reset together with the test logic (only hypothetical, I
1685 haven't seen hardware with such a bug, and can be worked around).
1686 @option{combined} implies both @option{srst_pulls_trst} and
1687 @option{trst_pulls_srst}. The default behaviour if no option given is
1688 @option{separate}.
1689
1690 The optional @var{trst_type} and @var{srst_type} parameters allow the
1691 driver type of the reset lines to be specified. Possible values are
1692 @option{trst_push_pull} (default) and @option{trst_open_drain} for the
1693 test reset signal, and @option{srst_open_drain} (default) and
1694 @option{srst_push_pull} for the system reset. These values only affect
1695 JTAG interfaces with support for different drivers, like the Amontec
1696 JTAGkey and JTAGAccelerator.
1697 @end deffn
1698
1699
1700 @node Tap Creation
1701 @chapter Tap Creation
1702 @cindex tap creation
1703 @cindex tap configuration
1704
1705 In order for OpenOCD to control a target, a JTAG tap must be
1706 defined/created.
1707
1708 Commands to create taps are normally found in a configuration file and
1709 are not normally typed by a human.
1710
1711 When a tap is created a @b{dotted.name} is created for the tap. Other
1712 commands use that dotted.name to manipulate or refer to the tap.
1713
1714 Tap Uses:
1715 @itemize @bullet
1716 @item @b{Debug Target} A tap can be used by a GDB debug target
1717 @item @b{Flash Programing} Some chips program the flash directly via JTAG,
1718 instead of indirectly by making a CPU do it.
1719 @item @b{Boundry Scan} Some chips support boundary scan.
1720 @end itemize
1721
1722
1723 @section jtag newtap
1724 @b{@t{jtag newtap CHIPNAME TAPNAME configparams ....}}
1725 @cindex jtag_device
1726 @cindex jtag newtap
1727 @cindex tap
1728 @cindex tap order
1729 @cindex tap geometry
1730
1731 @comment START options
1732 @itemize @bullet
1733 @item @b{CHIPNAME}
1734 @* is a symbolic name of the chip.
1735 @item @b{TAPNAME}
1736 @* is a symbol name of a tap present on the chip.
1737 @item @b{Required configparams}
1738 @* Every tap has 3 required configparams, and several ``optional
1739 parameters'', the required parameters are:
1740 @comment START REQUIRED
1741 @itemize @bullet
1742 @item @b{-irlen NUMBER} - the length in bits of the instruction register, mostly 4 or 5 bits.
1743 @item @b{-ircapture NUMBER} - the IDCODE capture command, usually 0x01.
1744 @item @b{-irmask NUMBER} - the corresponding mask for the IR register. For
1745 some devices, there are bits in the IR that aren't used. This lets you mask
1746 them off when doing comparisons. In general, this should just be all ones for
1747 the size of the IR.
1748 @comment END REQUIRED
1749 @end itemize
1750 An example of a FOOBAR Tap
1751 @example
1752 jtag newtap foobar tap -irlen 7 -ircapture 0x42 -irmask 0x55
1753 @end example
1754 Creates the tap ``foobar.tap'' with the instruction register (IR) is 7
1755 bits long, during Capture-IR 0x42 is loaded into the IR, and bits
1756 [6,4,2,0] are checked.
1757
1758 @item @b{Optional configparams}
1759 @comment START Optional
1760 @itemize @bullet
1761 @item @b{-expected-id NUMBER}
1762 @* By default it is zero. If non-zero represents the
1763 expected tap ID used when the JTAG chain is examined. Repeat
1764 the option as many times as required if multiple id's can be
1765 expected. See below.
1766 @item @b{-disable}
1767 @item @b{-enable}
1768 @* By default not specified the tap is enabled. Some chips have a
1769 JTAG route controller (JRC) that is used to enable and/or disable
1770 specific JTAG taps. You can later enable or disable any JTAG tap via
1771 the command @b{jtag tapenable DOTTED.NAME} or @b{jtag tapdisable
1772 DOTTED.NAME}
1773 @comment END Optional
1774 @end itemize
1775
1776 @comment END OPTIONS
1777 @end itemize
1778 @b{Notes:}
1779 @comment START NOTES
1780 @itemize @bullet
1781 @item @b{Technically}
1782 @* newtap is a sub command of the ``jtag'' command
1783 @item @b{Big Picture Background}
1784 @*GDB Talks to OpenOCD using the GDB protocol via
1785 TCP/IP. OpenOCD then uses the JTAG interface (the dongle) to
1786 control the JTAG chain on your board. Your board has one or more chips
1787 in a @i{daisy chain configuration}. Each chip may have one or more
1788 JTAG taps. GDB ends up talking via OpenOCD to one of the taps.
1789 @item @b{NAME Rules}
1790 @*Names follow ``C'' symbol name rules (start with alpha ...)
1791 @item @b{TAPNAME - Conventions}
1792 @itemize @bullet
1793 @item @b{tap} - should be used only FPGA or CPLD like devices with a single tap.
1794 @item @b{cpu} - the main CPU of the chip, alternatively @b{foo.arm} and @b{foo.dsp}
1795 @item @b{flash} - if the chip has a flash tap, example: str912.flash
1796 @item @b{bs} - for boundary scan if this is a seperate tap.
1797 @item @b{etb} - for an embedded trace buffer (example: an ARM ETB11)
1798 @item @b{jrc} - for JTAG route controller (example: OMAP3530 found on Beagleboards)
1799 @item @b{unknownN} - where N is a number if you have no idea what the tap is for
1800 @item @b{Other names} - Freescale IMX31 has a SDMA (smart dma) with a JTAG tap, that tap should be called the ``sdma'' tap.
1801 @item @b{When in doubt} - use the chip maker's name in their data sheet.
1802 @end itemize
1803 @item @b{DOTTED.NAME}
1804 @* @b{CHIPNAME}.@b{TAPNAME} creates the tap name, aka: the
1805 @b{Dotted.Name} is the @b{CHIPNAME} and @b{TAPNAME} combined with a
1806 dot (period); for example: @b{xilinx.tap}, @b{str912.flash},
1807 @b{omap3530.jrc}, or @b{stm32.cpu} The @b{dotted.name} is used in
1808 numerous other places to refer to various taps.
1809 @item @b{ORDER}
1810 @* The order this command appears via the config files is
1811 important.
1812 @item @b{Multi Tap Example}
1813 @* This example is based on the ST Microsystems STR912. See the ST
1814 document titled: @b{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
1815 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
1816
1817 @url{http://eu.st.com/stonline/products/literature/ds/13495.pdf}
1818 @*@b{checked: 28/nov/2008}
1819
1820 The diagram shows that the TDO pin connects to the flash tap, flash TDI
1821 connects to the CPU debug tap, CPU TDI connects to the boundary scan
1822 tap which then connects to the TDI pin.
1823
1824 @example
1825 # The order is...
1826 # create tap: 'str912.flash'
1827 jtag newtap str912 flash ... params ...
1828 # create tap: 'str912.cpu'
1829 jtag newtap str912 cpu ... params ...
1830 # create tap: 'str912.bs'
1831 jtag newtap str912 bs ... params ...
1832 @end example
1833
1834 @item @b{Note: Deprecated} - Index Numbers
1835 @* Prior to 28/nov/2008, JTAG taps where numbered from 0..N this
1836 feature is still present, however its use is highly discouraged and
1837 should not be counted upon. Update all of your scripts to use
1838 TAP names rather than numbers.
1839 @item @b{Multiple chips}
1840 @* If your board has multiple chips, you should be
1841 able to @b{source} two configuration files, in the proper order, and
1842 have the taps created in the proper order.
1843 @comment END NOTES
1844 @end itemize
1845 @comment at command level
1846 @comment DOCUMENT old command
1847 @section jtag_device - REMOVED
1848 @example
1849 @b{jtag_device} <@var{IR length}> <@var{IR capture}> <@var{IR mask}> <@var{IDCODE instruction}>
1850 @end example
1851 @cindex jtag_device
1852
1853 @* @b{Removed: 28/nov/2008} This command has been removed and replaced
1854 by the ``jtag newtap'' command. The documentation remains here so that
1855 one can easily convert the old syntax to the new syntax. About the old
1856 syntax: The old syntax is positional, i.e.: The 3rd parameter is the
1857 ``irmask''. The new syntax requires named prefixes, and supports
1858 additional options, for example ``-expected-id 0x3f0f0f0f''. Please refer to the
1859 @b{jtag newtap} command for details.
1860 @example
1861 OLD: jtag_device 8 0x01 0xe3 0xfe
1862 NEW: jtag newtap CHIPNAME TAPNAME -irlen 8 -ircapture 0x01 -irmask 0xe3
1863 @end example
1864
1865 @section Enable/Disable Taps
1866 @b{Note:} These commands are intended to be used as a machine/script
1867 interface. Humans might find the ``scan_chain'' command more helpful
1868 when querying the state of the JTAG taps.
1869
1870 @b{By default, all taps are enabled}
1871
1872 @itemize @bullet
1873 @item @b{jtag tapenable} @var{DOTTED.NAME}
1874 @item @b{jtag tapdisable} @var{DOTTED.NAME}
1875 @item @b{jtag tapisenabled} @var{DOTTED.NAME}
1876 @end itemize
1877 @cindex tap enable
1878 @cindex tap disable
1879 @cindex JRC
1880 @cindex route controller
1881
1882 These commands are used when your target has a JTAG route controller
1883 that effectively adds or removes a tap from the JTAG chain in a
1884 non-standard way.
1885
1886 The ``standard way'' to remove a tap would be to place the tap in
1887 bypass mode. But with the advent of modern chips, this is not always a
1888 good solution. Some taps operate slowly, others operate fast, and
1889 there are other JTAG clock synchronisation problems one must face. To
1890 solve that problem, the JTAG route controller was introduced. Rather
1891 than ``bypass'' the tap, the tap is completely removed from the
1892 circuit and skipped.
1893
1894
1895 From OpenOCD's point of view, a JTAG tap is in one of 3 states:
1896
1897 @itemize @bullet
1898 @item @b{Enabled - Not In ByPass} and has a variable bit length
1899 @item @b{Enabled - In ByPass} and has a length of exactly 1 bit.
1900 @item @b{Disabled} and has a length of ZERO and is removed from the circuit.
1901 @end itemize
1902
1903 The IEEE JTAG definition has no concept of a ``disabled'' tap.
1904 @b{Historical note:} this feature was added 28/nov/2008
1905
1906 @b{jtag tapisenabled DOTTED.NAME}
1907
1908 This command returns 1 if the named tap is currently enabled, 0 if not.
1909 This command exists so that scripts that manipulate a JRC (like the
1910 OMAP3530 has) can determine if OpenOCD thinks a tap is presently
1911 enabled or disabled.
1912
1913 @page
1914 @node Target Configuration
1915 @chapter Target Configuration
1916 @cindex GDB target
1917
1918 This chapter discusses how to create a GDB debug target. Before
1919 creating a ``target'' a JTAG tap DOTTED.NAME must exist first.
1920
1921 @section targets [NAME]
1922 @b{Note:} This command name is PLURAL - not singular.
1923
1924 With NO parameter, this plural @b{targets} command lists all known
1925 targets in a human friendly form.
1926
1927 With a parameter, this plural @b{targets} command sets the current
1928 target to the given name. (i.e.: If there are multiple debug targets)
1929
1930 Example:
1931 @verbatim
1932 (gdb) mon targets
1933 CmdName Type Endian ChainPos State
1934 -- ---------- ---------- ---------- -------- ----------
1935 0: target0 arm7tdmi little 0 halted
1936 @end verbatim
1937
1938 @section target COMMANDS
1939 @b{Note:} This command name is SINGULAR - not plural. It is used to
1940 manipulate specific targets, to create targets and other things.
1941
1942 Once a target is created, a TARGETNAME (object) command is created;
1943 see below for details.
1944
1945 The TARGET command accepts these sub-commands:
1946 @itemize @bullet
1947 @item @b{create} .. parameters ..
1948 @* creates a new target, see below for details.
1949 @item @b{types}
1950 @* Lists all supported target types (perhaps some are not yet in this document).
1951 @item @b{names}
1952 @* Lists all current debug target names, for example: 'str912.cpu' or 'pxa27.cpu' example usage:
1953 @verbatim
1954 foreach t [target names] {
1955 puts [format "Target: %s\n" $t]
1956 }
1957 @end verbatim
1958 @item @b{current}
1959 @* Returns the current target. OpenOCD always has, or refers to the ``current target'' in some way.
1960 By default, commands like: ``mww'' (used to write memory) operate on the current target.
1961 @item @b{number} @b{NUMBER}
1962 @* Internally OpenOCD maintains a list of targets - in numerical index
1963 (0..N-1) this command returns the name of the target at index N.
1964 Example usage:
1965 @verbatim
1966 set thename [target number $x]
1967 puts [format "Target %d is: %s\n" $x $thename]
1968 @end verbatim
1969 @item @b{count}
1970 @* Returns the number of targets known to OpenOCD (see number above)
1971 Example:
1972 @verbatim
1973 set c [target count]
1974 for { set x 0 } { $x < $c } { incr x } {
1975 # Assuming you have created this function
1976 print_target_details $x
1977 }
1978 @end verbatim
1979
1980 @end itemize
1981
1982 @section TARGETNAME (object) commands
1983 @b{Use:} Once a target is created, an ``object name'' that represents the
1984 target is created. By convention, the target name is identical to the
1985 tap name. In a multiple target system, one can preceed many common
1986 commands with a specific target name and effect only that target.
1987 @example
1988 str912.cpu mww 0x1234 0x42
1989 omap3530.cpu mww 0x5555 123
1990 @end example
1991
1992 @b{Model:} The Tcl/Tk language has the concept of object commands. A
1993 good example is a on screen button, once a button is created a button
1994 has a name (a path in Tk terms) and that name is useable as a 1st
1995 class command. For example in Tk, one can create a button and later
1996 configure it like this:
1997
1998 @example
1999 # Create
2000 button .foobar -background red -command @{ foo @}
2001 # Modify
2002 .foobar configure -foreground blue
2003 # Query
2004 set x [.foobar cget -background]
2005 # Report
2006 puts [format "The button is %s" $x]
2007 @end example
2008
2009 In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
2010 button. Commands available as a ``target object'' are:
2011
2012 @comment START targetobj commands.
2013 @itemize @bullet
2014 @item @b{configure} - configure the target; see Target Config/Cget Options below
2015 @item @b{cget} - query the target configuration; see Target Config/Cget Options below
2016 @item @b{curstate} - current target state (running, halt, etc.
2017 @item @b{eventlist}
2018 @* Intended for a human to see/read the currently configure target events.
2019 @item @b{Various Memory Commands} See the ``mww'' command elsewhere.
2020 @comment start memory
2021 @itemize @bullet
2022 @item @b{mww} ...
2023 @item @b{mwh} ...
2024 @item @b{mwb} ...
2025 @item @b{mdw} ...
2026 @item @b{mdh} ...
2027 @item @b{mdb} ...
2028 @comment end memory
2029 @end itemize
2030 @item @b{Memory To Array, Array To Memory}
2031 @* These are aimed at a machine interface to memory
2032 @itemize @bullet
2033 @item @b{mem2array ARRAYNAME WIDTH ADDRESS COUNT}
2034 @item @b{array2mem ARRAYNAME WIDTH ADDRESS COUNT}
2035 @* Where:
2036 @* @b{ARRAYNAME} is the name of an array variable
2037 @* @b{WIDTH} is 8/16/32 - indicating the memory access size
2038 @* @b{ADDRESS} is the target memory address
2039 @* @b{COUNT} is the number of elements to process
2040 @end itemize
2041 @item @b{Used during ``reset''}
2042 @* These commands are used internally by the OpenOCD scripts to deal
2043 with odd reset situations and are not documented here.
2044 @itemize @bullet
2045 @item @b{arp_examine}
2046 @item @b{arp_poll}
2047 @item @b{arp_reset}
2048 @item @b{arp_halt}
2049 @item @b{arp_waitstate}
2050 @end itemize
2051 @item @b{invoke-event} @b{EVENT-NAME}
2052 @* Invokes the specific event manually for the target
2053 @end itemize
2054
2055 @section Target Events
2056 @cindex events
2057 @anchor{Target Events}
2058 At various times, certain things can happen, or you want them to happen.
2059
2060 Examples:
2061 @itemize @bullet
2062 @item What should happen when GDB connects? Should your target reset?
2063 @item When GDB tries to flash the target, do you need to enable the flash via a special command?
2064 @item During reset, do you need to write to certain memory location to reconfigure the SDRAM?
2065 @end itemize
2066
2067 All of the above items are handled by target events.
2068
2069 To specify an event action, either during target creation, or later
2070 via ``$_TARGETNAME configure'' see this example.
2071
2072 Syntactially, the option is: ``-event NAME BODY'' where NAME is a
2073 target event name, and BODY is a Tcl procedure or string of commands
2074 to execute.
2075
2076 The programmers model is the ``-command'' option used in Tcl/Tk
2077 buttons and events. Below are two identical examples, the first
2078 creates and invokes small procedure. The second inlines the procedure.
2079
2080 @example
2081 proc my_attach_proc @{ @} @{
2082 puts "RESET...."
2083 reset halt
2084 @}
2085 mychip.cpu configure -event gdb-attach my_attach_proc
2086 mychip.cpu configure -event gdb-attach @{ puts "Reset..." ; reset halt @}
2087 @end example
2088
2089 @section Current Events
2090 The following events are available:
2091 @itemize @bullet
2092 @item @b{debug-halted}
2093 @* The target has halted for debug reasons (i.e.: breakpoint)
2094 @item @b{debug-resumed}
2095 @* The target has resumed (i.e.: gdb said run)
2096 @item @b{early-halted}
2097 @* Occurs early in the halt process
2098 @item @b{examine-end}
2099 @* Currently not used (goal: when JTAG examine completes)
2100 @item @b{examine-start}
2101 @* Currently not used (goal: when JTAG examine starts)
2102 @item @b{gdb-attach}
2103 @* When GDB connects
2104 @item @b{gdb-detach}
2105 @* When GDB disconnects
2106 @item @b{gdb-end}
2107 @* When the taret has halted and GDB is not doing anything (see early halt)
2108 @item @b{gdb-flash-erase-start}
2109 @* Before the GDB flash process tries to erase the flash
2110 @item @b{gdb-flash-erase-end}
2111 @* After the GDB flash process has finished erasing the flash
2112 @item @b{gdb-flash-write-start}
2113 @* Before GDB writes to the flash
2114 @item @b{gdb-flash-write-end}
2115 @* After GDB writes to the flash
2116 @item @b{gdb-start}
2117 @* Before the taret steps, gdb is trying to start/resume the target
2118 @item @b{halted}
2119 @* The target has halted
2120 @item @b{old-gdb_program_config}
2121 @* DO NOT USE THIS: Used internally
2122 @item @b{old-pre_resume}
2123 @* DO NOT USE THIS: Used internally
2124 @item @b{reset-assert-pre}
2125 @* Before reset is asserted on the tap.
2126 @item @b{reset-assert-post}
2127 @* Reset is now asserted on the tap.
2128 @item @b{reset-deassert-pre}
2129 @* Reset is about to be released on the tap
2130 @item @b{reset-deassert-post}
2131 @* Reset has been released on the tap
2132 @item @b{reset-end}
2133 @* Currently not used.
2134 @item @b{reset-halt-post}
2135 @* Currently not usd
2136 @item @b{reset-halt-pre}
2137 @* Currently not used
2138 @item @b{reset-init}
2139 @* Used by @b{reset init} command for board-specific initialization.
2140 This is where you would configure PLLs and clocking, set up DRAM so
2141 you can download programs that don't fit in on-chip SRAM, set up pin
2142 multiplexing, and so on.
2143 @item @b{reset-start}
2144 @* Currently not used
2145 @item @b{reset-wait-pos}
2146 @* Currently not used
2147 @item @b{reset-wait-pre}
2148 @* Currently not used
2149 @item @b{resume-start}
2150 @* Before any target is resumed
2151 @item @b{resume-end}
2152 @* After all targets have resumed
2153 @item @b{resume-ok}
2154 @* Success
2155 @item @b{resumed}
2156 @* Target has resumed
2157 @item @b{tap-enable}
2158 @* Executed by @b{jtag tapenable DOTTED.NAME} command. Example:
2159 @example
2160 jtag configure DOTTED.NAME -event tap-enable @{
2161 puts "Enabling CPU"
2162 ...
2163 @}
2164 @end example
2165 @item @b{tap-disable}
2166 @*Executed by @b{jtag tapdisable DOTTED.NAME} command. Example:
2167 @example
2168 jtag configure DOTTED.NAME -event tap-disable @{
2169 puts "Disabling CPU"
2170 ...
2171 @}
2172 @end example
2173 @end itemize
2174
2175 @section Target Create
2176 @anchor{Target Create}
2177 @cindex target
2178 @cindex target creation
2179
2180 @example
2181 @b{target} @b{create} <@var{NAME}> <@var{TYPE}> <@var{PARAMS ...}>
2182 @end example
2183 @*This command creates a GDB debug target that refers to a specific JTAG tap.
2184 @comment START params
2185 @itemize @bullet
2186 @item @b{NAME}
2187 @* Is the name of the debug target. By convention it should be the tap
2188 DOTTED.NAME. This name is also used to create the target object
2189 command, and in other places the target needs to be identified.
2190 @item @b{TYPE}
2191 @* Specifies the target type, i.e.: ARM7TDMI, or Cortex-M3. Currently supported targets are:
2192 @comment START types
2193 @itemize @minus
2194 @item @b{arm7tdmi}
2195 @item @b{arm720t}
2196 @item @b{arm9tdmi}
2197 @item @b{arm920t}
2198 @item @b{arm922t}
2199 @item @b{arm926ejs}
2200 @item @b{arm966e}
2201 @item @b{cortex_m3}
2202 @item @b{feroceon}
2203 @item @b{xscale}
2204 @item @b{arm11}
2205 @item @b{mips_m4k}
2206 @comment end TYPES
2207 @end itemize
2208 @item @b{PARAMS}
2209 @*PARAMs are various target configuration parameters. The following ones are mandatory:
2210 @comment START mandatory
2211 @itemize @bullet
2212 @item @b{-endian big|little}
2213 @item @b{-chain-position DOTTED.NAME}
2214 @comment end MANDATORY
2215 @end itemize
2216 @comment END params
2217 @end itemize
2218
2219 @section Target Config/Cget Options
2220 These options can be specified when the target is created, or later
2221 via the configure option or to query the target via cget.
2222
2223 You should specify a working area if you can; typically it uses some
2224 on-chip SRAM. Such a working area can speed up many things, including bulk
2225 writes to target memory; flash operations like checking to see if memory needs
2226 to be erased; GDB memory checksumming; and may help perform otherwise
2227 unavailable operations (like some coprocessor operations on ARM7/9 systems).
2228 @itemize @bullet
2229 @item @b{-type} - returns the target type
2230 @item @b{-event NAME BODY} see Target events
2231 @item @b{-work-area-virt [ADDRESS]} specify/set the work area base address
2232 which will be used when an MMU is active.
2233 @item @b{-work-area-phys [ADDRESS]} specify/set the work area base address
2234 which will be used when an MMU is inactive.
2235 @item @b{-work-area-size [ADDRESS]} specify/set the work area
2236 @item @b{-work-area-backup [0|1]} does the work area get backed up;
2237 by default, it doesn't. When possible, use a working_area that doesn't
2238 need to be backed up, since performing a backup slows down operations.
2239 @item @b{-endian [big|little]}
2240 @item @b{-variant [NAME]} some chips have variants OpenOCD needs to know about
2241 @item @b{-chain-position DOTTED.NAME} the tap name this target refers to.
2242 @end itemize
2243 Example:
2244 @example
2245 for @{ set x 0 @} @{ $x < [target count] @} @{ incr x @} @{
2246 set name [target number $x]
2247 set y [$name cget -endian]
2248 set z [$name cget -type]
2249 puts [format "Chip %d is %s, Endian: %s, type: %s" $x $y $z]
2250 @}
2251 @end example
2252
2253 @section Target Variants
2254 @itemize @bullet
2255 @item @b{arm7tdmi}
2256 @* Unknown (please write me)
2257 @item @b{arm720t}
2258 @* Unknown (please write me) (similar to arm7tdmi)
2259 @item @b{arm9tdmi}
2260 @* Variants: @option{arm920t}, @option{arm922t} and @option{arm940t}
2261 This enables the hardware single-stepping support found on these
2262 cores.
2263 @item @b{arm920t}
2264 @* None.
2265 @item @b{arm966e}
2266 @* None (this is also used as the ARM946)
2267 @item @b{cortex_m3}
2268 @* use variant <@var{-variant lm3s}> when debugging Luminary lm3s targets. This will cause
2269 OpenOCD to use a software reset rather than asserting SRST to avoid a issue with clearing
2270 the debug registers. This is fixed in Fury Rev B, DustDevil Rev B, Tempest, these revisions will
2271 be detected and the normal reset behaviour used.
2272 @item @b{xscale}
2273 @* Supported variants are @option{ixp42x}, @option{ixp45x}, @option{ixp46x},@option{pxa250}, @option{pxa255}, @option{pxa26x}.
2274 @item @b{arm11}
2275 @* Supported variants are @option{arm1136}, @option{arm1156}, @option{arm1176}
2276 @item @b{mips_m4k}
2277 @* Use variant @option{ejtag_srst} when debugging targets that do not
2278 provide a functional SRST line on the EJTAG connector. This causes
2279 OpenOCD to instead use an EJTAG software reset command to reset the
2280 processor. You still need to enable @option{srst} on the reset
2281 configuration command to enable OpenOCD hardware reset functionality.
2282 @comment END variants
2283 @end itemize
2284 @section working_area - Command Removed
2285 @cindex working_area
2286 @*@b{Please use the ``$_TARGETNAME configure -work-area-... parameters instead}
2287 @* This documentation remains because there are existing scripts that
2288 still use this that need to be converted.
2289 @example
2290 working_area target# address size backup| [virtualaddress]
2291 @end example
2292 @* The target# is a the 0 based target numerical index.
2293
2294 @node Flash Configuration
2295 @chapter Flash programming
2296 @cindex Flash Configuration
2297
2298 OpenOCD has different commands for NOR and NAND flash;
2299 the ``flash'' command works with NOR flash, while
2300 the ``nand'' command works with NAND flash.
2301 This partially reflects different hardware technologies:
2302 NOR flash usually supports direct CPU instruction and data bus access,
2303 while data from a NAND flash must be copied to memory before it can be
2304 used. (SPI flash must also be copied to memory before use.)
2305 However, the documentation also uses ``flash'' as a generic term;
2306 for example, ``Put flash configuration in board-specific files''.
2307
2308 @b{Note:} As of 28/nov/2008 OpenOCD does not know how to program a SPI
2309 flash that a micro may boot from. Perhaps you, the reader, would like to
2310 contribute support for this.
2311
2312 Flash Steps:
2313 @enumerate
2314 @item Configure via the command @b{flash bank}
2315 @* Normally this is done in a configuration file.
2316 @item Operate on the flash via @b{flash SOMECOMMAND}
2317 @* Often commands to manipulate the flash are typed by a human, or run
2318 via a script in some automated way. For example: To program the boot
2319 flash on your board.
2320 @item GDB Flashing
2321 @* Flashing via GDB requires the flash be configured via ``flash
2322 bank'', and the GDB flash features be enabled.
2323 @xref{GDB Configuration}.
2324 @end enumerate
2325
2326 @section Flash commands
2327 @cindex Flash commands
2328 @subsection flash banks
2329 @b{flash banks}
2330 @cindex flash banks
2331 @*List configured flash banks
2332 @*@b{NOTE:} the singular form: 'flash bank' is used to configure the flash banks.
2333 @subsection flash info
2334 @b{flash info} <@var{num}>
2335 @cindex flash info
2336 @*Print info about flash bank <@option{num}>
2337 @subsection flash probe
2338 @b{flash probe} <@var{num}>
2339 @cindex flash probe
2340 @*Identify the flash, or validate the parameters of the configured flash. Operation
2341 depends on the flash type.
2342 @subsection flash erase_check
2343 @b{flash erase_check} <@var{num}>
2344 @cindex flash erase_check
2345 @*Check erase state of sectors in flash bank <@var{num}>. This is the only operation that
2346 updates the erase state information displayed by @option{flash info}. That means you have
2347 to issue an @option{erase_check} command after erasing or programming the device to get
2348 updated information.
2349 @subsection flash protect_check
2350 @b{flash protect_check} <@var{num}>
2351 @cindex flash protect_check
2352 @*Check protection state of sectors in flash bank <num>.
2353 @option{flash erase_sector} using the same syntax.
2354 @subsection flash erase_sector
2355 @b{flash erase_sector} <@var{num}> <@var{first}> <@var{last}>
2356 @cindex flash erase_sector
2357 @anchor{flash erase_sector}
2358 @*Erase sectors at bank <@var{num}>, starting at sector <@var{first}> up to and including
2359 <@var{last}>. Sector numbering starts at 0. Depending on the flash type, erasing may
2360 require the protection to be disabled first (e.g. Intel Advanced Bootblock flash using
2361 the CFI driver).
2362 @subsection flash erase_address
2363 @b{flash erase_address} <@var{address}> <@var{length}>
2364 @cindex flash erase_address
2365 @*Erase sectors starting at <@var{address}> for <@var{length}> bytes
2366 @subsection flash write_bank
2367 @b{flash write_bank} <@var{num}> <@var{file}> <@var{offset}>
2368 @cindex flash write_bank
2369 @anchor{flash write_bank}
2370 @*Write the binary <@var{file}> to flash bank <@var{num}>, starting at
2371 <@option{offset}> bytes from the beginning of the bank.
2372 @subsection flash write_image
2373 @b{flash write_image} [@var{erase}] <@var{file}> [@var{offset}] [@var{type}]
2374 @cindex flash write_image
2375 @anchor{flash write_image}
2376 @*Write the image <@var{file}> to the current target's flash bank(s). A relocation
2377 [@var{offset}] can be specified and the file [@var{type}] can be specified
2378 explicitly as @option{bin} (binary), @option{ihex} (Intel hex), @option{elf}
2379 (ELF file) or @option{s19} (Motorola s19). Flash memory will be erased prior to programming
2380 if the @option{erase} parameter is given.
2381 @subsection flash protect
2382 @b{flash protect} <@var{num}> <@var{first}> <@var{last}> <@option{on}|@option{off}>
2383 @cindex flash protect
2384 @*Enable (@var{on}) or disable (@var{off}) protection of flash sectors <@var{first}> to
2385 <@var{last}> of @option{flash bank} <@var{num}>.
2386
2387 @subsection mFlash commands
2388 @cindex mFlash commands
2389 @itemize @bullet
2390 @item @b{mflash probe}
2391 @cindex mflash probe
2392 Probe mflash.
2393 @item @b{mflash write} <@var{num}> <@var{file}> <@var{offset}>
2394 @cindex mflash write
2395 Write the binary <@var{file}> to mflash bank <@var{num}>, starting at
2396 <@var{offset}> bytes from the beginning of the bank.
2397 @item @b{mflash dump} <@var{num}> <@var{file}> <@var{offset}> <@var{size}>
2398 @cindex mflash dump
2399 Dump <size> bytes, starting at <@var{offset}> bytes from the beginning of the <@var{num}> bank
2400 to a <@var{file}>.
2401 @end itemize
2402
2403 @section flash bank command
2404 The @b{flash bank} command is used to configure one or more flash chips (or banks in OpenOCD terms)
2405
2406 @example
2407 @b{flash bank} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}>
2408 <@var{bus_width}> <@var{target}> [@var{driver_options ...}]
2409 @end example
2410 @cindex flash bank
2411 @*Configures a flash bank at <@var{base}> of <@var{size}> bytes and <@var{chip_width}>
2412 and <@var{bus_width}> bytes using the selected flash <driver>.
2413
2414 @subsection External Flash - cfi options
2415 @cindex cfi options
2416 CFI flashes are external flash chips - often they are connected to a
2417 specific chip select on the CPU. By default, at hard reset, most
2418 CPUs have the ablity to ``boot'' from some flash chip - typically
2419 attached to the CPU's CS0 pin.
2420
2421 For other chip selects: OpenOCD does not know how to configure, or
2422 access a specific chip select. Instead you, the human, might need to
2423 configure additional chip selects via other commands (like: mww) , or
2424 perhaps configure a GPIO pin that controls the ``write protect'' pin
2425 on the flash chip.
2426
2427 @b{flash bank cfi} <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}>
2428 <@var{target}> [@var{jedec_probe}|@var{x16_as_x8}]
2429 @*CFI flashes require the name or number of the target they're connected to
2430 as an additional
2431 argument. The CFI driver makes use of a working area (specified for the target)
2432 to significantly speed up operation.
2433
2434 @var{chip_width} and @var{bus_width} are specified in bytes.
2435
2436 The @var{jedec_probe} option is used to detect certain non-CFI flash ROMs, like AM29LV010 and similar types.
2437
2438 @var{x16_as_x8} ???
2439
2440 @subsection Internal Flash (Microcontrollers)
2441 @subsubsection lpc2000 options
2442 @cindex lpc2000 options
2443
2444 @b{flash bank lpc2000} <@var{base}> <@var{size}> 0 0 <@var{target}> <@var{variant}>
2445 <@var{clock}> [@var{calc_checksum}]
2446 @*LPC flashes don't require the chip and bus width to be specified. Additional
2447 parameters are the <@var{variant}>, which may be @var{lpc2000_v1} (older LPC21xx and LPC22xx)
2448 or @var{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx),
2449 the name or number of the target this flash belongs to (first is 0),
2450 the frequency at which the core
2451 is currently running (in kHz - must be an integral number), and the optional keyword
2452 @var{calc_checksum}, telling the driver to calculate a valid checksum for the exception
2453 vector table.
2454
2455
2456 @subsubsection at91sam7 options
2457 @cindex at91sam7 options
2458
2459 @b{flash bank at91sam7} 0 0 0 0 <@var{target}>
2460 @*AT91SAM7 flashes only require the @var{target}, all other values are looked up after
2461 reading the chip-id and type.
2462
2463 @subsubsection str7 options
2464 @cindex str7 options
2465
2466 @b{flash bank str7x} <@var{base}> <@var{size}> 0 0 <@var{target}> <@var{variant}>
2467 @*variant can be either STR71x, STR73x or STR75x.
2468
2469 @subsubsection str9 options
2470 @cindex str9 options
2471
2472 @b{flash bank str9x} <@var{base}> <@var{size}> 0 0 <@var{target}>
2473 @*The str9 needs the flash controller to be configured prior to Flash programming, e.g.
2474 @example
2475 str9x flash_config 0 4 2 0 0x80000
2476 @end example
2477 This will setup the BBSR, NBBSR, BBADR and NBBADR registers respectively.
2478
2479 @subsubsection str9 options (str9xpec driver)
2480
2481 @b{flash bank str9xpec} <@var{base}> <@var{size}> 0 0 <@var{target}>
2482 @*Before using the flash commands the turbo mode must be enabled using str9xpec
2483 @option{enable_turbo} <@var{num>.}
2484
2485 Only use this driver for locking/unlocking the device or configuring the option bytes.
2486 Use the standard str9 driver for programming. @xref{STR9 specific commands}.
2487
2488 @subsubsection Stellaris (LM3Sxxx) options
2489 @cindex Stellaris (LM3Sxxx) options
2490
2491 @b{flash bank stellaris} <@var{base}> <@var{size}> 0 0 <@var{target}>
2492 @*Stellaris flash plugin only require the @var{target}.
2493
2494 @subsubsection stm32x options
2495 @cindex stm32x options
2496
2497 @b{flash bank stm32x} <@var{base}> <@var{size}> 0 0 <@var{target}>
2498 @*stm32x flash plugin only require the @var{target}.
2499
2500 @subsubsection aduc702x options
2501 @cindex aduc702x options
2502
2503 @b{flash bank aduc702x} 0 0 0 0 <@var{target}>
2504 @*The aduc702x flash plugin works with Analog Devices model numbers ADUC7019 through ADUC7028. The setup command only requires the @var{target} argument (all devices in this family have the same memory layout).
2505
2506 @subsection mFlash Configuration
2507 @cindex mFlash Configuration
2508 @b{mflash bank} <@var{soc}> <@var{base}> <@var{chip_width}> <@var{bus_width}>
2509 <@var{RST pin}> <@var{WP pin}> <@var{DPD pin}> <@var{target}>
2510 @cindex mflash bank
2511 @*Configures a mflash for <@var{soc}> host bank at
2512 <@var{base}>. <@var{chip_width}> and <@var{bus_width}> are bytes
2513 order. Pin number format is dependent on host GPIO calling convention.
2514 If WP or DPD pin was not used, write -1. Currently, mflash bank
2515 support s3c2440 and pxa270.
2516
2517 (ex. of s3c2440) mflash <@var{RST pin}> is GPIO B1, <@var{WP pin}> and <@var{DPD pin}> are not used.
2518 @example
2519 mflash bank s3c2440 0x10000000 2 2 1b -1 -1 0
2520 @end example
2521 (ex. of pxa270) mflash <@var{RST pin}> is GPIO 43, <@var{DPD pin}> is not used and <@var{DPD pin}> is GPIO 51.
2522 @example
2523 mflash bank pxa270 0x08000000 2 2 43 -1 51 0
2524 @end example
2525
2526 @section Microcontroller specific Flash Commands
2527
2528 @subsection AT91SAM7 specific commands
2529 @cindex AT91SAM7 specific commands
2530 The flash configuration is deduced from the chip identification register. The flash
2531 controller handles erases automatically on a page (128/265 byte) basis, so erase is
2532 not necessary for flash programming. AT91SAM7 processors with less than 512K flash
2533 only have a single flash bank embedded on chip. AT91SAM7xx512 have two flash planes
2534 that can be erased separatly. Only an EraseAll command is supported by the controller
2535 for each flash plane and this is called with
2536 @itemize @bullet
2537 @item @b{flash erase} <@var{num}> @var{first_plane} @var{last_plane}
2538 @*bulk erase flash planes first_plane to last_plane.
2539 @item @b{at91sam7 gpnvm} <@var{num}> <@var{bit}> <@option{set}|@option{clear}>
2540 @cindex at91sam7 gpnvm
2541 @*set or clear a gpnvm bit for the processor
2542 @end itemize
2543
2544 @subsection STR9 specific commands
2545 @cindex STR9 specific commands
2546 @anchor{STR9 specific commands}
2547 These are flash specific commands when using the str9xpec driver.
2548 @itemize @bullet
2549 @item @b{str9xpec enable_turbo} <@var{num}>
2550 @cindex str9xpec enable_turbo
2551 @*enable turbo mode, will simply remove the str9 from the chain and talk
2552 directly to the embedded flash controller.
2553 @item @b{str9xpec disable_turbo} <@var{num}>
2554 @cindex str9xpec disable_turbo
2555 @*restore the str9 into JTAG chain.
2556 @item @b{str9xpec lock} <@var{num}>
2557 @cindex str9xpec lock
2558 @*lock str9 device. The str9 will only respond to an unlock command that will
2559 erase the device.
2560 @item @b{str9xpec unlock} <@var{num}>
2561 @cindex str9xpec unlock
2562 @*unlock str9 device.
2563 @item @b{str9xpec options_read} <@var{num}>
2564 @cindex str9xpec options_read
2565 @*read str9 option bytes.
2566 @item @b{str9xpec options_write} <@var{num}>
2567 @cindex str9xpec options_write
2568 @*write str9 option bytes.
2569 @end itemize
2570
2571 Note: Before using the str9xpec driver here is some background info to help
2572 you better understand how the drivers works. OpenOCD has two flash drivers for
2573 the str9.
2574 @enumerate
2575 @item
2576 Standard driver @option{str9x} programmed via the str9 core. Normally used for
2577 flash programming as it is faster than the @option{str9xpec} driver.
2578 @item
2579 Direct programming @option{str9xpec} using the flash controller. This is an
2580 ISC compilant (IEEE 1532) tap connected in series with the str9 core. The str9
2581 core does not need to be running to program using this flash driver. Typical use
2582 for this driver is locking/unlocking the target and programming the option bytes.
2583 @end enumerate
2584
2585 Before we run any commands using the @option{str9xpec} driver we must first disable
2586 the str9 core. This example assumes the @option{str9xpec} driver has been
2587 configured for flash bank 0.
2588 @example
2589 # assert srst, we do not want core running
2590 # while accessing str9xpec flash driver
2591 jtag_reset 0 1
2592 # turn off target polling
2593 poll off
2594 # disable str9 core
2595 str9xpec enable_turbo 0
2596 # read option bytes
2597 str9xpec options_read 0
2598 # re-enable str9 core
2599 str9xpec disable_turbo 0
2600 poll on
2601 reset halt
2602 @end example
2603 The above example will read the str9 option bytes.
2604 When performing a unlock remember that you will not be able to halt the str9 - it
2605 has been locked. Halting the core is not required for the @option{str9xpec} driver
2606 as mentioned above, just issue the commands above manually or from a telnet prompt.
2607
2608 @subsection STR9 configuration
2609 @cindex STR9 configuration
2610 @itemize @bullet
2611 @item @b{str9x flash_config} <@var{bank}> <@var{BBSR}> <@var{NBBSR}>
2612 <@var{BBADR}> <@var{NBBADR}>
2613 @cindex str9x flash_config
2614 @*Configure str9 flash controller.
2615 @example
2616 e.g. str9x flash_config 0 4 2 0 0x80000
2617 This will setup
2618 BBSR - Boot Bank Size register
2619 NBBSR - Non Boot Bank Size register
2620 BBADR - Boot Bank Start Address register
2621 NBBADR - Boot Bank Start Address register
2622 @end example
2623 @end itemize
2624
2625 @subsection STR9 option byte configuration
2626 @cindex STR9 option byte configuration
2627 @itemize @bullet
2628 @item @b{str9xpec options_cmap} <@var{num}> <@option{bank0}|@option{bank1}>
2629 @cindex str9xpec options_cmap
2630 @*configure str9 boot bank.
2631 @item @b{str9xpec options_lvdthd} <@var{num}> <@option{2.4v}|@option{2.7v}>
2632 @cindex str9xpec options_lvdthd
2633 @*configure str9 lvd threshold.
2634 @item @b{str9xpec options_lvdsel} <@var{num}> <@option{vdd}|@option{vdd_vddq}>
2635 @cindex str9xpec options_lvdsel
2636 @*configure str9 lvd source.
2637 @item @b{str9xpec options_lvdwarn} <@var{bank}> <@option{vdd}|@option{vdd_vddq}>
2638 @cindex str9xpec options_lvdwarn
2639 @*configure str9 lvd reset warning source.
2640 @end itemize
2641
2642 @subsection STM32x specific commands
2643 @cindex STM32x specific commands
2644
2645 These are flash specific commands when using the stm32x driver.
2646 @itemize @bullet
2647 @item @b{stm32x lock} <@var{num}>
2648 @cindex stm32x lock
2649 @*lock stm32 device.
2650 @item @b{stm32x unlock} <@var{num}>
2651 @cindex stm32x unlock
2652 @*unlock stm32 device.
2653 @item @b{stm32x options_read} <@var{num}>
2654 @cindex stm32x options_read
2655 @*read stm32 option bytes.
2656 @item @b{stm32x options_write} <@var{num}> <@option{SWWDG}|@option{HWWDG}>
2657 <@option{RSTSTNDBY}|@option{NORSTSTNDBY}> <@option{RSTSTOP}|@option{NORSTSTOP}>
2658 @cindex stm32x options_write
2659 @*write stm32 option bytes.
2660 @item @b{stm32x mass_erase} <@var{num}>
2661 @cindex stm32x mass_erase
2662 @*mass erase flash memory.
2663 @end itemize
2664
2665 @subsection Stellaris specific commands
2666 @cindex Stellaris specific commands
2667
2668 These are flash specific commands when using the Stellaris driver.
2669 @itemize @bullet
2670 @item @b{stellaris mass_erase} <@var{num}>
2671 @cindex stellaris mass_erase
2672 @*mass erase flash memory.
2673 @end itemize
2674
2675 @node NAND Flash Commands
2676 @chapter NAND Flash Commands
2677 @cindex NAND
2678
2679 Compared to NOR or SPI flash, NAND devices are inexpensive
2680 and high density. Today's NAND chips, and multi-chip modules,
2681 commonly hold multiple GigaBytes of data.
2682
2683 NAND chips consist of a number of ``erase blocks'' of a given
2684 size (such as 128 KBytes), each of which is divided into a
2685 number of pages (of perhaps 512 or 2048 bytes each). Each
2686 page of a NAND flash has an ``out of band'' (OOB) area to hold
2687 Error Correcting Code (ECC) and other metadata, usually 16 bytes
2688 of OOB for every 512 bytes of page data.
2689
2690 One key characteristic of NAND flash is that its error rate
2691 is higher than that of NOR flash. In normal operation, that
2692 ECC is used to correct and detect errors. However, NAND
2693 blocks can also wear out and become unusable; those blocks
2694 are then marked "bad". NAND chips are even shipped from the
2695 manufacturer with a few bad blocks. The highest density chips
2696 use a technology (MLC) that wears out more quickly, so ECC
2697 support is increasingly important as a way to detect blocks
2698 that have begun to fail, and help to preserve data integrity
2699 with techniques such as wear leveling.
2700
2701 Software is used to manage the ECC. Some controllers don't
2702 support ECC directly; in those cases, software ECC is used.
2703 Other controllers speed up the ECC calculations with hardware.
2704 Single-bit error correction hardware is routine. Controllers
2705 geared for newer MLC chips may correct 4 or more errors for
2706 every 512 bytes of data.
2707
2708 You will need to make sure that any data you write using
2709 OpenOCD includes the apppropriate kind of ECC. For example,
2710 that may mean passing the @code{oob_softecc} flag when
2711 writing NAND data, or ensuring that the correct hardware
2712 ECC mode is used.
2713
2714 The basic steps for using NAND devices include:
2715 @enumerate
2716 @item Declare via the command @command{nand device}
2717 @* Do this in a board-specific configuration file,
2718 passing parameters as needed by the controller.
2719 @item Configure each device using @command{nand probe}.
2720 @* Do this only after the associated target is set up,
2721 such as in its reset-init script or in procures defined
2722 to access that device.
2723 @item Operate on the flash via @command{nand subcommand}
2724 @* Often commands to manipulate the flash are typed by a human, or run
2725 via a script in some automated way. Common task include writing a
2726 boot loader, operating system, or other data needed to initialize or
2727 de-brick a board.
2728 @end enumerate
2729
2730 @b{NOTE:} At the time this text was written, the largest NAND
2731 flash fully supported by OpenOCD is 2 GiBytes (16 GiBits).
2732 This is because the variables used to hold offsets and lengths
2733 are only 32 bits wide.
2734 (Larger chips may work in some cases, unless an offset or length
2735 is larger than 0xffffffff, the largest 32-bit unsigned integer.)
2736 Some larger devices will work, since they are actually multi-chip
2737 modules with two smaller chips and individual chipselect lines.
2738
2739 @section NAND Configuration Commands
2740 @cindex NAND configuration
2741
2742 NAND chips must be declared in configuration scripts,
2743 plus some additional configuration that's done after
2744 OpenOCD has initialized.
2745
2746 @deffn {Config Command} {nand device} controller target [configparams...]
2747 Declares a NAND device, which can be read and written to
2748 after it has been configured through @command{nand probe}.
2749 In OpenOCD, devices are single chips; this is unlike some
2750 operating systems, which may manage multiple chips as if
2751 they were a single (larger) device.
2752 In some cases, configuring a device will activate extra
2753 commands; see the controller-specific documentation.
2754
2755 @b{NOTE:} This command is not available after OpenOCD
2756 initialization has completed. Use it in board specific
2757 configuration files, not interactively.
2758
2759 @itemize @bullet
2760 @item @var{controller} ... identifies a the controller driver
2761 associated with the NAND device being declared.
2762 @xref{NAND Driver List}.
2763 @item @var{target} ... names the target used when issuing
2764 commands to the NAND controller.
2765 @comment Actually, it's currently a controller-specific parameter...
2766 @item @var{configparams} ... controllers may support, or require,
2767 additional parameters. See the controller-specific documentation
2768 for more information.
2769 @end itemize
2770 @end deffn
2771
2772 @deffn Command {nand list}
2773 Prints a one-line summary of each device declared
2774 using @command{nand device}, numbered from zero.
2775 Note that un-probed devices show no details.
2776 @end deffn
2777
2778 @deffn Command {nand probe} num
2779 Probes the specified device to determine key characteristics
2780 like its page and block sizes, and how many blocks it has.
2781 The @var{num} parameter is the value shown by @command{nand list}.
2782 You must (successfully) probe a device before you can use
2783 it with most other NAND commands.
2784 @end deffn
2785
2786 @section Erasing, Reading, Writing to NAND Flash
2787
2788 @deffn Command {nand dump} num filename offset length [oob_option]
2789 @cindex NAND reading
2790 Reads binary data from the NAND device and writes it to the file,
2791 starting at the specified offset.
2792 The @var{num} parameter is the value shown by @command{nand list}.
2793
2794 Use a complete path name for @var{filename}, so you don't depend
2795 on the directory used to start the OpenOCD server.
2796
2797 The @var{offset} and @var{length} must be exact multiples of the
2798 device's page size. They describe a data region; the OOB data
2799 associated with each such page may also be accessed.
2800
2801 @b{NOTE:} At the time this text was written, no error correction
2802 was done on the data that's read, unless raw access was disabled
2803 and the underlying NAND controller driver had a @code{read_page}
2804 method which handled that error correction.
2805
2806 By default, only page data is saved to the specified file.
2807 Use an @var{oob_option} parameter to save OOB data:
2808 @itemize @bullet
2809 @item no oob_* parameter
2810 @*Output file holds only page data; OOB is discarded.
2811 @item @code{oob_raw}
2812 @*Output file interleaves page data and OOB data;
2813 the file will be longer than "length" by the size of the
2814 spare areas associated with each data page.
2815 Note that this kind of "raw" access is different from
2816 what's implied by @command{nand raw_access}, which just
2817 controls whether a hardware-aware access method is used.
2818 @item @code{oob_only}
2819 @*Output file has only raw OOB data, and will
2820 be smaller than "length" since it will contain only the
2821 spare areas associated with each data page.
2822 @end itemize
2823 @end deffn
2824
2825 @deffn Command {nand erase} num offset length
2826 @cindex NAND erasing
2827 Erases blocks on the specified NAND device, starting at the
2828 specified @var{offset} and continuing for @var{length} bytes.
2829 Both of those values must be exact multiples of the device's
2830 block size, and the region they specify must fit entirely in the chip.
2831 The @var{num} parameter is the value shown by @command{nand list}.
2832
2833 @b{NOTE:} This command will try to erase bad blocks, when told
2834 to do so, which will probably invalidate the manufacturer's bad
2835 block marker.
2836 For the remainder of the current server session, @command{nand info}
2837 will still report that the block ``is'' bad.
2838 @end deffn
2839
2840 @deffn Command {nand write} num filename offset [option...]
2841 @cindex NAND writing
2842 Writes binary data from the file into the specified NAND device,
2843 starting at the specified offset. Those pages should already
2844 have been erased; you can't change zero bits to one bits.
2845 The @var{num} parameter is the value shown by @command{nand list}.
2846
2847 Use a complete path name for @var{filename}, so you don't depend
2848 on the directory used to start the OpenOCD server.
2849
2850 The @var{offset} must be an exact multiple of the device's page size.
2851 All data in the file will be written, assuming it doesn't run
2852 past the end of the device.
2853 Only full pages are written, and any extra space in the last
2854 page will be filled with 0xff bytes. (That includes OOB data,
2855 if that's being written.)
2856
2857 @b{NOTE:} At the time this text was written, bad blocks are
2858 ignored. That is, this routine will not skip bad blocks,
2859 but will instead try to write them. This can cause problems.
2860
2861 Provide at most one @var{option} parameter. With some
2862 NAND drivers, the meanings of these parameters may change
2863 if @command{nand raw_access} was used to disable hardware ECC.
2864 @itemize @bullet
2865 @item no oob_* parameter
2866 @*File has only page data, which is written.
2867 If raw acccess is in use, the OOB area will not be written.
2868 Otherwise, if the underlying NAND controller driver has
2869 a @code{write_page} routine, that routine may write the OOB
2870 with hardware-computed ECC data.
2871 @item @code{oob_only}
2872 @*File has only raw OOB data, which is written to the OOB area.
2873 Each page's data area stays untouched. @i{This can be a dangerous
2874 option}, since it can invalidate the ECC data.
2875 You may need to force raw access to use this mode.
2876 @item @code{oob_raw}
2877 @*File interleaves data and OOB data, both of which are written
2878 If raw access is enabled, the data is written first, then the
2879 un-altered OOB.
2880 Otherwise, if the underlying NAND controller driver has
2881 a @code{write_page} routine, that routine may modify the OOB
2882 before it's written, to include hardware-computed ECC data.
2883 @item @code{oob_softecc}
2884 @*File has only page data, which is written.
2885 The OOB area is filled with 0xff, except for a standard 1-bit
2886 software ECC code stored in conventional locations.
2887 You might need to force raw access to use this mode, to prevent
2888 the underlying driver from applying hardware ECC.
2889 @item @code{oob_softecc_kw}
2890 @*File has only page data, which is written.
2891 The OOB area is filled with 0xff, except for a 4-bit software ECC
2892 specific to the boot ROM in Marvell Kirkwood SoCs.
2893 You might need to force raw access to use this mode, to prevent
2894 the underlying driver from applying hardware ECC.
2895 @end itemize
2896 @end deffn
2897
2898 @section Other NAND commands
2899 @cindex NAND other commands
2900
2901 @deffn Command {nand check_bad_blocks} [offset length]
2902 Checks for manufacturer bad block markers on the specified NAND
2903 device. If no parameters are provided, checks the whole
2904 device; otherwise, starts at the specified @var{offset} and
2905 continues for @var{length} bytes.
2906 Both of those values must be exact multiples of the device's
2907 block size, and the region they specify must fit entirely in the chip.
2908 The @var{num} parameter is the value shown by @command{nand list}.
2909
2910 @b{NOTE:} Before using this command you should force raw access
2911 with @command{nand raw_access enable} to ensure that the underlying
2912 driver will not try to apply hardware ECC.
2913 @end deffn
2914
2915 @deffn Command {nand info} num
2916 The @var{num} parameter is the value shown by @command{nand list}.
2917 This prints the one-line summary from "nand list", plus for
2918 devices which have been probed this also prints any known
2919 status for each block.
2920 @end deffn
2921
2922 @deffn Command {nand raw_access} num <enable|disable>
2923 Sets or clears an flag affecting how page I/O is done.
2924 The @var{num} parameter is the value shown by @command{nand list}.
2925
2926 This flag is cleared (disabled) by default, but changing that
2927 value won't affect all NAND devices. The key factor is whether
2928 the underlying driver provides @code{read_page} or @code{write_page}
2929 methods. If it doesn't provide those methods, the setting of
2930 this flag is irrelevant; all access is effectively ``raw''.
2931
2932 When those methods exist, they are normally used when reading
2933 data (@command{nand dump} or reading bad block markers) or
2934 writing it (@command{nand write}). However, enabling
2935 raw access (setting the flag) prevents use of those methods,
2936 bypassing hardware ECC logic.
2937 @i{This can be a dangerous option}, since writing blocks
2938 with the wrong ECC data can cause them to be marked as bad.
2939 @end deffn
2940
2941 @section NAND Drivers; Driver-specific Options and Commands
2942 @anchor{NAND Driver List}
2943 As noted above, the @command{nand device} command allows
2944 driver-specific options and behaviors.
2945 Some controllers also activate controller-specific commands.
2946
2947 @deffn {NAND Driver} davinci
2948 This driver handles the NAND controllers found on DaVinci family
2949 chips from Texas Instruments.
2950 It takes three extra parameters:
2951 address of the NAND chip;
2952 hardware ECC mode to use (hwecc1, hwecc4, hwecc4_infix);
2953 address of the AEMIF controller on this processor.
2954 @example
2955 nand device davinci dm355.arm 0x02000000 hwecc4 0x01e10000
2956 @end example
2957 All DaVinci processors support the single-bit ECC hardware,
2958 and newer ones also support the four-bit ECC hardware.
2959 The @code{write_page} and @code{read_page} methods are used
2960 to implement those ECC modes, unless they are disabled using
2961 the @command{nand raw_access} command.
2962 @end deffn
2963
2964 @deffn {NAND Driver} lpc3180
2965 These controllers require an extra @command{nand device}
2966 parameter: the clock rate used by the controller.
2967 @deffn Command {nand lpc3180 select} num [mlc|slc]
2968 Configures use of the MLC or SLC controller mode.
2969 MLC implies use of hardware ECC.
2970 The @var{num} parameter is the value shown by @command{nand list}.
2971 @end deffn
2972
2973 At this writing, this driver includes @code{write_page}
2974 and @code{read_page} methods. Using @command{nand raw_access}
2975 to disable those methods will prevent use of hardware ECC
2976 in the MLC controller mode, but won't change SLC behavior.
2977 @end deffn
2978 @comment current lpc3180 code won't issue 5-byte address cycles
2979
2980 @deffn {NAND Driver} orion
2981 These controllers require an extra @command{nand device}
2982 parameter: the address of the controller.
2983 @example
2984 nand device orion 0xd8000000
2985 @end example
2986 These controllers don't define any specialized commands.
2987 At this writing, their drivers don't include @code{write_page}
2988 or @code{read_page} methods, so @command{nand raw_access} won't
2989 change any behavior.
2990 @end deffn
2991
2992 @deffn {NAND Driver} {s3c2410, s3c2412, s3c2440, s3c2443}
2993 These S3C24xx family controllers don't have any special
2994 @command{nand device} options, and don't define any
2995 specialized commands.
2996 At this writing, their drivers don't include @code{write_page}
2997 or @code{read_page} methods, so @command{nand raw_access} won't
2998 change any behavior.
2999 @end deffn
3000
3001 @node General Commands
3002 @chapter General Commands
3003 @cindex commands
3004
3005 The commands documented in this chapter here are common commands that
3006 you, as a human, may want to type and see the output of. Configuration type
3007 commands are documented elsewhere.
3008
3009 Intent:
3010 @itemize @bullet
3011 @item @b{Source Of Commands}
3012 @* OpenOCD commands can occur in a configuration script (discussed
3013 elsewhere) or typed manually by a human or supplied programatically,
3014 or via one of several TCP/IP Ports.
3015
3016 @item @b{From the human}
3017 @* A human should interact with the telnet interface (default port: 4444)
3018 or via GDB (default port 3333).
3019
3020 To issue commands from within a GDB session, use the @option{monitor}
3021 command, e.g. use @option{monitor poll} to issue the @option{poll}
3022 command. All output is relayed through the GDB session.
3023
3024 @item @b{Machine Interface}
3025 The Tcl interface's intent is to be a machine interface. The default Tcl
3026 port is 5555.
3027 @end itemize
3028
3029
3030 @section Daemon Commands
3031
3032 @subsection sleep [@var{msec}]
3033 @cindex sleep
3034 @*Wait for n milliseconds before resuming. Useful in connection with script files
3035 (@var{script} command and @var{target_script} configuration).
3036
3037 @subsection shutdown
3038 @cindex shutdown
3039 @*Close the OpenOCD daemon, disconnecting all clients (GDB, telnet, other).
3040
3041 @subsection debug_level [@var{n}]
3042 @cindex debug_level
3043 @anchor{debug_level}
3044 @*Display or adjust debug level to n<0-3>
3045
3046 @subsection fast [@var{enable|disable}]
3047 @cindex fast
3048 @*Default disabled. Set default behaviour of OpenOCD to be "fast and dangerous". For instance ARM7/9 DCC memory
3049 downloads and fast memory access will work if the JTAG interface isn't too fast and
3050 the core doesn't run at a too low frequency. Note that this option only changes the default
3051 and that the indvidual options, like DCC memory downloads, can be enabled and disabled
3052 individually.
3053
3054 The target specific "dangerous" optimisation tweaking options may come and go
3055 as more robust and user friendly ways are found to ensure maximum throughput
3056 and robustness with a minimum of configuration.
3057
3058 Typically the "fast enable" is specified first on the command line:
3059
3060 @example
3061 openocd -c "fast enable" -c "interface dummy" -f target/str710.cfg
3062 @end example
3063
3064 @subsection echo <@var{message}>
3065 @cindex echo
3066 @*Output message to stdio. e.g. echo "Programming - please wait"
3067
3068 @subsection log_output <@var{file}>
3069 @cindex log_output
3070 @*Redirect logging to <file> (default: stderr)
3071
3072 @subsection script <@var{file}>
3073 @cindex script
3074 @*Execute commands from <file>
3075 See also: ``source [find FILENAME]''
3076
3077 @section Target state handling
3078 @subsection power <@var{on}|@var{off}>
3079 @cindex reg
3080 @*Turn power switch to target on/off.
3081 No arguments: print status.
3082 Not all interfaces support this.
3083
3084 @subsection reg [@option{#}|@option{name}] [value]
3085 @cindex reg
3086 @*Access a single register by its number[@option{#}] or by its [@option{name}].
3087 No arguments: list all available registers for the current target.
3088 Number or name argument: display a register.
3089 Number or name and value arguments: set register value.
3090
3091 @subsection poll [@option{on}|@option{off}]
3092 @cindex poll
3093 @*Poll the target for its current state. If the target is in debug mode, architecture
3094 specific information about the current state is printed. An optional parameter
3095 allows continuous polling to be enabled and disabled.
3096
3097 @subsection halt [@option{ms}]
3098 @cindex halt
3099 @*Send a halt request to the target and wait for it to halt for up to [@option{ms}] milliseconds.
3100 Default [@option{ms}] is 5 seconds if no arg given.
3101 Optional arg @option{ms} is a timeout in milliseconds. Using 0 as the [@option{ms}]
3102 will stop OpenOCD from waiting.
3103
3104 @subsection wait_halt [@option{ms}]
3105 @cindex wait_halt
3106 @*Wait for the target to enter debug mode. Optional [@option{ms}] is
3107 a timeout in milliseconds. Default [@option{ms}] is 5 seconds if no
3108 arg is given.
3109
3110 @subsection resume [@var{address}]
3111 @cindex resume
3112 @*Resume the target at its current code position, or at an optional address.
3113 OpenOCD will wait 5 seconds for the target to resume.
3114
3115 @subsection step [@var{address}]
3116 @cindex step
3117 @*Single-step the target at its current code position, or at an optional address.
3118
3119 @anchor{Reset Command}
3120 @subsection reset [@option{run}|@option{halt}|@option{init}]
3121 @cindex reset
3122 @*Perform a hard-reset. The optional parameter specifies what should
3123 happen after the reset.
3124 If there is no parameter, a @command{reset run} is executed.
3125 The other options will not work on all systems.
3126 @xref{Reset Configuration}.
3127 @itemize @minus
3128 @item @b{run}
3129 @cindex reset run
3130 @*Let the target run.
3131 @item @b{halt}
3132 @cindex reset halt
3133 @*Immediately halt the target (works only with certain configurations).
3134 @item @b{init}
3135 @cindex reset init
3136 @*Immediately halt the target, and execute the reset script (works only with certain
3137 configurations)
3138 @end itemize
3139
3140 @subsection soft_reset_halt
3141 @cindex reset
3142 @*Requesting target halt and executing a soft reset. This is often used
3143 when a target cannot be reset and halted. The target, after reset is
3144 released begins to execute code. OpenOCD attempts to stop the CPU and
3145 then sets the program counter back to the reset vector. Unfortunately
3146 the code that was executed may have left the hardware in an unknown
3147 state.
3148
3149
3150 @section Memory access commands
3151 @subsection meminfo
3152 display available RAM memory.
3153 @subsection Memory peek/poke type commands
3154 These commands allow accesses of a specific size to the memory
3155 system. Often these are used to configure the current target in some
3156 special way. For example - one may need to write certian values to the
3157 SDRAM controller to enable SDRAM.
3158
3159 @enumerate
3160 @item To change the current target see the ``targets'' (plural) command
3161 @item In system level scripts these commands are deprecated, please use the TARGET object versions.
3162 @end enumerate
3163
3164 @itemize @bullet
3165 @item @b{mdw} <@var{addr}> [@var{count}]
3166 @cindex mdw
3167 @*display memory words (32bit)
3168 @item @b{mdh} <@var{addr}> [@var{count}]
3169 @cindex mdh
3170 @*display memory half-words (16bit)
3171 @item @b{mdb} <@var{addr}> [@var{count}]
3172 @cindex mdb
3173 @*display memory bytes (8bit)
3174 @item @b{mww} <@var{addr}> <@var{value}>
3175 @cindex mww
3176 @*write memory word (32bit)
3177 @item @b{mwh} <@var{addr}> <@var{value}>
3178 @cindex mwh
3179 @*write memory half-word (16bit)
3180 @item @b{mwb} <@var{addr}> <@var{value}>
3181 @cindex mwb
3182 @*write memory byte (8bit)
3183 @end itemize
3184
3185 @section Image loading commands
3186 @subsection load_image
3187 @b{load_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
3188 @cindex load_image
3189 @anchor{load_image}
3190 @*Load image <@var{file}> to target memory at <@var{address}>
3191 @subsection fast_load_image
3192 @b{fast_load_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
3193 @cindex fast_load_image
3194 @anchor{fast_load_image}
3195 @*Normally you should be using @b{load_image} or GDB load. However, for
3196 testing purposes or when I/O overhead is significant(OpenOCD running on an embedded
3197 host), storing the image in memory and uploading the image to the target
3198 can be a way to upload e.g. multiple debug sessions when the binary does not change.
3199 Arguments are the same as @b{load_image}, but the image is stored in OpenOCD host
3200 memory, i.e. does not affect target. This approach is also useful when profiling
3201 target programming performance as I/O and target programming can easily be profiled
3202 separately.
3203 @subsection fast_load
3204 @b{fast_load}
3205 @cindex fast_image
3206 @anchor{fast_image}
3207 @*Loads an image stored in memory by @b{fast_load_image} to the current target. Must be preceeded by fast_load_image.
3208 @subsection dump_image
3209 @b{dump_image} <@var{file}> <@var{address}> <@var{size}>
3210 @cindex dump_image
3211 @anchor{dump_image}
3212 @*Dump <@var{size}> bytes of target memory starting at <@var{address}> to a
3213 (binary) <@var{file}>.
3214 @subsection verify_image
3215 @b{verify_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
3216 @cindex verify_image
3217 @*Verify <@var{file}> against target memory starting at <@var{address}>.
3218 This will first attempt a comparison using a CRC checksum, if this fails it will try a binary compare.
3219
3220
3221 @section Breakpoint commands
3222 @cindex Breakpoint commands
3223 @itemize @bullet
3224 @item @b{bp} <@var{addr}> <@var{len}> [@var{hw}]
3225 @cindex bp
3226 @*set breakpoint <address> <length> [hw]
3227 @item @b{rbp} <@var{addr}>
3228 @cindex rbp
3229 @*remove breakpoint <adress>
3230 @item @b{wp} <@var{addr}> <@var{len}> <@var{r}|@var{w}|@var{a}> [@var{value}] [@var{mask}]
3231 @cindex wp
3232 @*set watchpoint <address> <length> <r/w/a> [value] [mask]
3233 @item @b{rwp} <@var{addr}>
3234 @cindex rwp
3235 @*remove watchpoint <adress>
3236 @end itemize
3237
3238 @section Misc Commands
3239 @cindex Other Target Commands
3240 @itemize
3241 @item @b{profile} <@var{seconds}> <@var{gmon.out}>
3242
3243 Profiling samples the CPU's program counter as quickly as possible, which is useful for non-intrusive stochastic profiling.
3244
3245 @end itemize
3246
3247 @section Target Specific Commands
3248 @cindex Target Specific Commands
3249
3250
3251 @page
3252 @section Architecture Specific Commands
3253 @cindex Architecture Specific Commands
3254
3255 @subsection ARMV4/5 specific commands
3256 @cindex ARMV4/5 specific commands
3257
3258 These commands are specific to ARM architecture v4 and v5, like all ARM7/9 systems
3259 or Intel XScale (XScale isn't supported yet).
3260 @itemize @bullet
3261 @item @b{armv4_5 reg}
3262 @cindex armv4_5 reg
3263 @*Display a list of all banked core registers, fetching the current value from every
3264 core mode if necessary. OpenOCD versions before rev. 60 didn't fetch the current
3265 register value.
3266 @item @b{armv4_5 core_mode} [@var{arm}|@var{thumb}]
3267 @cindex armv4_5 core_mode
3268 @*Displays the core_mode, optionally changing it to either ARM or Thumb mode.
3269 The target is resumed in the currently set @option{core_mode}.
3270 @end itemize
3271
3272 @subsection ARM7/9 specific commands
3273 @cindex ARM7/9 specific commands
3274
3275 These commands are specific to ARM7 and ARM9 targets, like ARM7TDMI, ARM720t,
3276 ARM920T or ARM926EJ-S.
3277 @itemize @bullet
3278 @item @b{arm7_9 dbgrq} <@var{enable}|@var{disable}>
3279 @cindex arm7_9 dbgrq
3280 @*Enable use of the DBGRQ bit to force entry into debug mode. This should be
3281 safe for all but ARM7TDMI--S cores (like Philips LPC).
3282 @item @b{arm7_9 fast_memory_access} <@var{enable}|@var{disable}>
3283 @cindex arm7_9 fast_memory_access
3284 @anchor{arm7_9 fast_memory_access}
3285 @*Allow OpenOCD to read and write memory without checking completion of
3286 the operation. This provides a huge speed increase, especially with USB JTAG
3287 cables (FT2232), but might be unsafe if used with targets running at very low
3288 speeds, like the 32kHz startup clock of an AT91RM9200.
3289 @item @b{arm7_9 dcc_downloads} <@var{enable}|@var{disable}>
3290 @cindex arm7_9 dcc_downloads
3291 @*Enable the use of the debug communications channel (DCC) to write larger (>128 byte)
3292 amounts of memory. DCC downloads offer a huge speed increase, but might be potentially
3293 unsafe, especially with targets running at very low speeds. This command was introduced
3294 with OpenOCD rev. 60, and requires a few bytes of working area.
3295 @end itemize
3296
3297 @subsection ARM720T specific commands
3298 @cindex ARM720T specific commands
3299
3300 @itemize @bullet
3301 @item @b{arm720t cp15} <@var{num}> [@var{value}]
3302 @cindex arm720t cp15
3303 @*display/modify cp15 register <@option{num}> [@option{value}].
3304 @item @b{arm720t md<bhw>_phys} <@var{addr}> [@var{count}]
3305 @cindex arm720t md<bhw>_phys
3306 @*Display memory at physical address addr.
3307 @item @b{arm720t mw<bhw>_phys} <@var{addr}> <@var{value}>
3308 @cindex arm720t mw<bhw>_phys
3309 @*Write memory at physical address addr.
3310 @item @b{arm720t virt2phys} <@var{va}>
3311 @cindex arm720t virt2phys
3312 @*Translate a virtual address to a physical address.
3313 @end itemize
3314
3315 @subsection ARM9TDMI specific commands
3316 @cindex ARM9TDMI specific commands
3317
3318 @itemize @bullet
3319 @item @b{arm9tdmi vector_catch} <@var{all}|@var{none}>
3320 @cindex arm9tdmi vector_catch
3321 @*Catch arm9 interrupt vectors, can be @option{all} @option{none} or any of the following:
3322 @option{reset} @option{undef} @option{swi} @option{pabt} @option{dabt} @option{reserved}
3323 @option{irq} @option{fiq}.
3324
3325 Can also be used on other ARM9 based cores such as ARM966, ARM920T and ARM926EJ-S.
3326 @end itemize
3327
3328 @subsection ARM966E specific commands
3329 @cindex ARM966E specific commands
3330
3331 @itemize @bullet
3332 @item @b{arm966e cp15} <@var{num}> [@var{value}]
3333 @cindex arm966e cp15
3334 @*display/modify cp15 register <@option{num}> [@option{value}].
3335 @end itemize
3336
3337 @subsection ARM920T specific commands
3338 @cindex ARM920T specific commands
3339
3340 @itemize @bullet
3341 @item @b{arm920t cp15} <@var{num}> [@var{value}]
3342 @cindex arm920t cp15
3343 @*display/modify cp15 register <@option{num}> [@option{value}].
3344 @item @b{arm920t cp15i} <@var{num}> [@var{value}] [@var{address}]
3345 @cindex arm920t cp15i
3346 @*display/modify cp15 (interpreted access) <@option{opcode}> [@option{value}] [@option{address}]
3347 @item @b{arm920t cache_info}
3348 @cindex arm920t cache_info
3349 @*Print information about the caches found. This allows to see whether your target
3350 is an ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
3351 @item @b{arm920t md<bhw>_phys} <@var{addr}> [@var{count}]
3352 @cindex arm920t md<bhw>_phys
3353 @*Display memory at physical address addr.
3354 @item @b{arm920t mw<bhw>_phys} <@var{addr}> <@var{value}>
3355 @cindex arm920t mw<bhw>_phys
3356 @*Write memory at physical address addr.
3357 @item @b{arm920t read_cache} <@var{filename}>
3358 @cindex arm920t read_cache
3359 @*Dump the content of ICache and DCache to a file.
3360 @item @b{arm920t read_mmu} <@var{filename}>
3361 @cindex arm920t read_mmu
3362 @*Dump the content of the ITLB and DTLB to a file.
3363 @item @b{arm920t virt2phys} <@var{va}>
3364 @cindex arm920t virt2phys
3365 @*Translate a virtual address to a physical address.
3366 @end itemize
3367
3368 @subsection ARM926EJ-S specific commands
3369 @cindex ARM926EJ-S specific commands
3370
3371 @itemize @bullet
3372 @item @b{arm926ejs cp15} <@var{num}> [@var{value}]
3373 @cindex arm926ejs cp15
3374 @*display/modify cp15 register <@option{num}> [@option{value}].
3375 @item @b{arm926ejs cache_info}
3376 @cindex arm926ejs cache_info
3377 @*Print information about the caches found.
3378 @item @b{arm926ejs md<bhw>_phys} <@var{addr}> [@var{count}]
3379 @cindex arm926ejs md<bhw>_phys
3380 @*Display memory at physical address addr.
3381 @item @b{arm926ejs mw<bhw>_phys} <@var{addr}> <@var{value}>
3382 @cindex arm926ejs mw<bhw>_phys
3383 @*Write memory at physical address addr.
3384 @item @b{arm926ejs virt2phys} <@var{va}>
3385 @cindex arm926ejs virt2phys
3386 @*Translate a virtual address to a physical address.
3387 @end itemize
3388
3389 @subsection CORTEX_M3 specific commands
3390 @cindex CORTEX_M3 specific commands
3391
3392 @itemize @bullet
3393 @item @b{cortex_m3 maskisr} <@var{on}|@var{off}>
3394 @cindex cortex_m3 maskisr
3395 @*Enable masking (disabling) interrupts during target step/resume.
3396 @end itemize
3397
3398 @page
3399 @section Debug commands
3400 @cindex Debug commands
3401 The following commands give direct access to the core, and are most likely
3402 only useful while debugging OpenOCD.
3403 @itemize @bullet
3404 @item @b{arm7_9 write_xpsr} <@var{32-bit value}> <@option{0=cpsr}, @option{1=spsr}>
3405 @cindex arm7_9 write_xpsr
3406 @*Immediately write either the current program status register (CPSR) or the saved
3407 program status register (SPSR), without changing the register cache (as displayed
3408 by the @option{reg} and @option{armv4_5 reg} commands).
3409 @item @b{arm7_9 write_xpsr_im8} <@var{8-bit value}> <@var{rotate 4-bit}>
3410 <@var{0=cpsr},@var{1=spsr}>
3411 @cindex arm7_9 write_xpsr_im8
3412 @*Write the 8-bit value rotated right by 2*rotate bits, using an immediate write
3413 operation (similar to @option{write_xpsr}).
3414 @item @b{arm7_9 write_core_reg} <@var{num}> <@var{mode}> <@var{value}>
3415 @cindex arm7_9 write_core_reg
3416 @*Write a core register, without changing the register cache (as displayed by the
3417 @option{reg} and @option{armv4_5 reg} commands). The <@var{mode}> argument takes the
3418 encoding of the [M4:M0] bits of the PSR.
3419 @end itemize
3420
3421 @section Target Requests
3422 @cindex Target Requests
3423 OpenOCD can handle certain target requests, currently debugmsg are only supported for arm7_9 and cortex_m3.
3424 See libdcc in the contrib dir for more details.
3425 @itemize @bullet
3426 @item @b{target_request debugmsgs} <@var{enable}|@var{disable}|@var{charmsg}>
3427 @cindex target_request debugmsgs
3428 @*Enable/disable target debugmsgs requests. debugmsgs enable messages to be sent to the debugger while the target is running. @var{charmsg} receives messages if Linux kernel ``Kernel low-level debugging via EmbeddedICE DCC channel'' option is enabled.
3429 @end itemize
3430
3431 @node JTAG Commands
3432 @chapter JTAG Commands
3433 @cindex JTAG Commands
3434 Generally most people will not use the bulk of these commands. They
3435 are mostly used by the OpenOCD developers or those who need to
3436 directly manipulate the JTAG taps.
3437
3438 In general these commands control JTAG taps at a very low level. For
3439 example if you need to control a JTAG Route Controller (i.e.: the
3440 OMAP3530 on the Beagle Board has one) you might use these commands in
3441 a script or an event procedure.
3442 @section Commands
3443 @cindex Commands
3444 @itemize @bullet
3445 @item @b{scan_chain}
3446 @cindex scan_chain
3447 @*Print current scan chain configuration.
3448 @item @b{jtag_reset} <@var{trst}> <@var{srst}>
3449 @cindex jtag_reset
3450 @*Toggle reset lines.
3451 @item @b{endstate} <@var{tap_state}>
3452 @cindex endstate
3453 @*Finish JTAG operations in <@var{tap_state}>.
3454 @item @b{runtest} <@var{num_cycles}>
3455 @cindex runtest
3456 @*Move to Run-Test/Idle, and execute <@var{num_cycles}>
3457 @item @b{statemove} [@var{tap_state}]
3458 @cindex statemove
3459 @*Move to current endstate or [@var{tap_state}]
3460 @item @b{irscan} <@var{device}> <@var{instr}> [@var{dev2}] [@var{instr2}] ...
3461 @cindex irscan
3462 @*Execute IR scan <@var{device}> <@var{instr}> [@var{dev2}] [@var{instr2}] ...
3463 @item @b{drscan} <@var{device}> [@var{dev2}] [@var{var2}] ...
3464 @cindex drscan
3465 @*Execute DR scan <@var{device}> [@var{dev2}] [@var{var2}] ...
3466 @item @b{verify_ircapture} <@option{enable}|@option{disable}>
3467 @cindex verify_ircapture
3468 @*Verify value captured during Capture-IR. Default is enabled.
3469 @item @b{var} <@var{name}> [@var{num_fields}|@var{del}] [@var{size1}] ...
3470 @cindex var
3471 @*Allocate, display or delete variable <@var{name}> [@var{num_fields}|@var{del}] [@var{size1}] ...
3472 @item @b{field} <@var{var}> <@var{field}> [@var{value}|@var{flip}]
3473 @cindex field
3474 Display/modify variable field <@var{var}> <@var{field}> [@var{value}|@var{flip}].
3475 @end itemize
3476
3477 @section Tap states
3478 @cindex Tap states
3479 Available tap_states are:
3480 @itemize @bullet
3481 @item @b{RESET}
3482 @cindex RESET
3483 @item @b{IDLE}
3484 @cindex IDLE
3485 @item @b{DRSELECT}
3486 @cindex DRSELECT
3487 @item @b{DRCAPTURE}
3488 @cindex DRCAPTURE
3489 @item @b{DRSHIFT}
3490 @cindex DRSHIFT
3491 @item @b{DREXIT1}
3492 @cindex DREXIT1
3493 @item @b{DRPAUSE}
3494 @cindex DRPAUSE
3495 @item @b{DREXIT2}
3496 @cindex DREXIT2
3497 @item @b{DRUPDATE}
3498 @cindex DRUPDATE
3499 @item @b{IRSELECT}
3500 @cindex IRSELECT
3501 @item @b{IRCAPTURE}
3502 @cindex IRCAPTURE
3503 @item @b{IRSHIFT}
3504 @cindex IRSHIFT
3505 @item @b{IREXIT1}
3506 @cindex IREXIT1
3507 @item @b{IRPAUSE}
3508 @cindex IRPAUSE
3509 @item @b{IREXIT2}
3510 @cindex IREXIT2
3511 @item @b{IRUPDATE}
3512 @cindex IRUPDATE
3513 @end itemize
3514
3515
3516 @node TFTP
3517 @chapter TFTP
3518 @cindex TFTP
3519 If OpenOCD runs on an embedded host(as ZY1000 does), then TFTP can
3520 be used to access files on PCs (either the developer's PC or some other PC).
3521
3522 The way this works on the ZY1000 is to prefix a filename by
3523 "/tftp/ip/" and append the TFTP path on the TFTP
3524 server (tftpd). E.g. "load_image /tftp/10.0.0.96/c:\temp\abc.elf" will
3525 load c:\temp\abc.elf from the developer pc (10.0.0.96) into memory as
3526 if the file was hosted on the embedded host.
3527
3528 In order to achieve decent performance, you must choose a TFTP server
3529 that supports a packet size bigger than the default packet size (512 bytes). There
3530 are numerous TFTP servers out there (free and commercial) and you will have to do
3531 a bit of googling to find something that fits your requirements.
3532
3533 @node Sample Scripts
3534 @chapter Sample Scripts
3535 @cindex scripts
3536
3537 This page shows how to use the Target Library.
3538
3539 The configuration script can be divided into the following sections:
3540 @itemize @bullet
3541 @item Daemon configuration
3542 @item Interface
3543 @item JTAG scan chain
3544 @item Target configuration
3545 @item Flash configuration
3546 @end itemize
3547
3548 Detailed information about each section can be found at OpenOCD configuration.
3549
3550 @section AT91R40008 example
3551 @cindex AT91R40008 example
3552 To start OpenOCD with a target script for the AT91R40008 CPU and reset
3553 the CPU upon startup of the OpenOCD daemon.
3554 @example
3555 openocd -f interface/parport.cfg -f target/at91r40008.cfg -c init -c reset
3556 @end example
3557
3558
3559 @node GDB and OpenOCD
3560 @chapter GDB and OpenOCD
3561 @cindex GDB
3562 OpenOCD complies with the remote gdbserver protocol, and as such can be used
3563 to debug remote targets.
3564
3565 @section Connecting to GDB
3566 @cindex Connecting to GDB
3567 @anchor{Connecting to GDB}
3568 Use GDB 6.7 or newer with OpenOCD if you run into trouble. For
3569 instance GDB 6.3 has a known bug that produces bogus memory access
3570 errors, which has since been fixed: look up 1836 in
3571 @url{http://sourceware.org/cgi-bin/gnatsweb.pl?database=gdb}
3572
3573 @*OpenOCD can communicate with GDB in two ways:
3574 @enumerate
3575 @item
3576 A socket (TCP/IP) connection is typically started as follows:
3577 @example
3578 target remote localhost:3333
3579 @end example
3580 This would cause GDB to connect to the gdbserver on the local pc using port 3333.
3581 @item
3582 A pipe connection is typically started as follows:
3583 @example
3584 target remote | openocd --pipe
3585 @end example
3586 This would cause GDB to run OpenOCD and communicate using pipes (stdin/stdout).
3587 Using this method has the advantage of GDB starting/stopping OpenOCD for the debug
3588 session.
3589 @end enumerate
3590
3591 @*To see a list of available OpenOCD commands type @option{monitor help} on the
3592 GDB command line.
3593
3594 OpenOCD supports the gdb @option{qSupported} packet, this enables information
3595 to be sent by the GDB remote server (i.e. OpenOCD) to GDB. Typical information includes
3596 packet size and the device's memory map.
3597
3598 Previous versions of OpenOCD required the following GDB options to increase
3599 the packet size and speed up GDB communication:
3600 @example
3601 set remote memory-write-packet-size 1024
3602 set remote memory-write-packet-size fixed
3603 set remote memory-read-packet-size 1024
3604 set remote memory-read-packet-size fixed
3605 @end example
3606 This is now handled in the @option{qSupported} PacketSize and should not be required.
3607
3608 @section Programming using GDB
3609 @cindex Programming using GDB
3610
3611 By default the target memory map is sent to GDB. This can be disabled by
3612 the following OpenOCD configuration option:
3613 @example
3614 gdb_memory_map disable
3615 @end example
3616 For this to function correctly a valid flash configuration must also be set
3617 in OpenOCD. For faster performance you should also configure a valid
3618 working area.
3619
3620 Informing GDB of the memory map of the target will enable GDB to protect any
3621 flash areas of the target and use hardware breakpoints by default. This means
3622 that the OpenOCD option @command{gdb_breakpoint_override} is not required when
3623 using a memory map. @xref{gdb_breakpoint_override}.
3624
3625 To view the configured memory map in GDB, use the GDB command @option{info mem}
3626 All other unassigned addresses within GDB are treated as RAM.
3627
3628 GDB 6.8 and higher set any memory area not in the memory map as inaccessible.
3629 This can be changed to the old behaviour by using the following GDB command
3630 @example
3631 set mem inaccessible-by-default off
3632 @end example
3633
3634 If @command{gdb_flash_program enable} is also used, GDB will be able to
3635 program any flash memory using the vFlash interface.
3636
3637 GDB will look at the target memory map when a load command is given, if any
3638 areas to be programmed lie within the target flash area the vFlash packets
3639 will be used.
3640
3641 If the target needs configuring before GDB programming, an event
3642 script can be executed:
3643 @example
3644 $_TARGETNAME configure -event EVENTNAME BODY
3645 @end example
3646
3647 To verify any flash programming the GDB command @option{compare-sections}
3648 can be used.
3649
3650 @node Tcl Scripting API
3651 @chapter Tcl Scripting API
3652 @cindex Tcl Scripting API
3653 @cindex Tcl scripts
3654 @section API rules
3655
3656 The commands are stateless. E.g. the telnet command line has a concept
3657 of currently active target, the Tcl API proc's take this sort of state
3658 information as an argument to each proc.
3659
3660 There are three main types of return values: single value, name value
3661 pair list and lists.
3662
3663 Name value pair. The proc 'foo' below returns a name/value pair
3664 list.
3665
3666 @verbatim
3667
3668 > set foo(me) Duane
3669 > set foo(you) Oyvind
3670 > set foo(mouse) Micky
3671 > set foo(duck) Donald
3672
3673 If one does this:
3674
3675 > set foo
3676
3677 The result is:
3678
3679 me Duane you Oyvind mouse Micky duck Donald
3680
3681 Thus, to get the names of the associative array is easy:
3682
3683 foreach { name value } [set foo] {
3684 puts "Name: $name, Value: $value"
3685 }
3686 @end verbatim
3687
3688 Lists returned must be relatively small. Otherwise a range
3689 should be passed in to the proc in question.
3690
3691 @section Internal low-level Commands
3692
3693 By low-level, the intent is a human would not directly use these commands.
3694
3695 Low-level commands are (should be) prefixed with "openocd_", e.g. openocd_flash_banks
3696 is the low level API upon which "flash banks" is implemented.
3697
3698 @itemize @bullet
3699 @item @b{ocd_mem2array} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
3700
3701 Read memory and return as a Tcl array for script processing
3702 @item @b{ocd_array2mem} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
3703
3704 Convert a Tcl array to memory locations and write the values
3705 @item @b{ocd_flash_banks} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}> <@var{target}> [@option{driver options} ...]
3706
3707 Return information about the flash banks
3708 @end itemize
3709
3710 OpenOCD commands can consist of two words, e.g. "flash banks". The
3711 startup.tcl "unknown" proc will translate this into a Tcl proc
3712 called "flash_banks".
3713
3714 @section OpenOCD specific Global Variables
3715
3716 @subsection HostOS
3717
3718 Real Tcl has ::tcl_platform(), and platform::identify, and many other
3719 variables. JimTCL, as implemented in OpenOCD creates $HostOS which
3720 holds one of the following values:
3721
3722 @itemize @bullet
3723 @item @b{winxx} Built using Microsoft Visual Studio
3724 @item @b{linux} Linux is the underlying operating sytem
3725 @item @b{darwin} Darwin (mac-os) is the underlying operating sytem.
3726 @item @b{cygwin} Running under Cygwin
3727 @item @b{mingw32} Running under MingW32
3728 @item @b{other} Unknown, none of the above.
3729 @end itemize
3730
3731 Note: 'winxx' was choosen because today (March-2009) no distinction is made between Win32 and Win64.
3732
3733 @node Upgrading
3734 @chapter Deprecated/Removed Commands
3735 @cindex Deprecated/Removed Commands
3736 Certain OpenOCD commands have been deprecated/removed during the various revisions.
3737
3738 @itemize @bullet
3739 @item @b{arm7_9 fast_writes}
3740 @cindex arm7_9 fast_writes
3741 @*use @option{arm7_9 fast_memory_access} command with same args. @xref{arm7_9 fast_memory_access}.
3742 @item @b{arm7_9 force_hw_bkpts}
3743 @cindex arm7_9 force_hw_bkpts
3744 @*Use @command{gdb_breakpoint_override} instead. Note that GDB will use hardware breakpoints
3745 for flash if the GDB memory map has been set up(default when flash is declared in
3746 target configuration). @xref{gdb_breakpoint_override}.
3747 @item @b{arm7_9 sw_bkpts}
3748 @cindex arm7_9 sw_bkpts
3749 @*On by default. @xref{gdb_breakpoint_override}.
3750 @item @b{daemon_startup}
3751 @cindex daemon_startup
3752 @*this config option has been removed, simply adding @option{init} and @option{reset halt} to
3753 the end of your config script will give the same behaviour as using @option{daemon_startup reset}
3754 and @option{target cortex_m3 little reset_halt 0}.
3755 @item @b{dump_binary}
3756 @cindex dump_binary
3757 @*use @option{dump_image} command with same args. @xref{dump_image}.
3758 @item @b{flash erase}
3759 @cindex flash erase
3760 @*use @option{flash erase_sector} command with same args. @xref{flash erase_sector}.
3761 @item @b{flash write}
3762 @cindex flash write
3763 @*use @option{flash write_bank} command with same args. @xref{flash write_bank}.
3764 @item @b{flash write_binary}
3765 @cindex flash write_binary
3766 @*use @option{flash write_bank} command with same args. @xref{flash write_bank}.
3767 @item @b{flash auto_erase}
3768 @cindex flash auto_erase
3769 @*use @option{flash write_image} command passing @option{erase} as the first parameter. @xref{flash write_image}.
3770
3771 @item @b{jtag_speed} value
3772 @*@xref{JTAG Speed}.
3773 Usually, a value of zero means maximum
3774 speed. The actual effect of this option depends on the JTAG interface used.
3775 @itemize @minus
3776 @item wiggler: maximum speed / @var{number}
3777 @item ft2232: 6MHz / (@var{number}+1)
3778 @item amt jtagaccel: 8 / 2**@var{number}
3779 @item jlink: maximum speed in kHz (0-12000), 0 will use RTCK
3780 @item rlink: 24MHz / @var{number}, but only for certain values of @var{number}
3781 @comment end speed list.
3782 @end itemize
3783
3784 @item @b{load_binary}
3785 @cindex load_binary
3786 @*use @option{load_image} command with same args. @xref{load_image}.
3787 @item @b{run_and_halt_time}
3788 @cindex run_and_halt_time
3789 @*This command has been removed for simpler reset behaviour, it can be simulated with the
3790 following commands:
3791 @smallexample
3792 reset run
3793 sleep 100
3794 halt
3795 @end smallexample
3796 @item @b{target} <@var{type}> <@var{endian}> <@var{jtag-position}>
3797 @cindex target
3798 @*use the create subcommand of @option{target}.
3799 @item @b{target_script} <@var{target#}> <@var{eventname}> <@var{scriptname}>
3800 @cindex target_script
3801 @*use <@var{target_name}> configure -event <@var{eventname}> "script <@var{scriptname}>"
3802 @item @b{working_area}
3803 @cindex working_area
3804 @*use the @option{configure} subcommand of @option{target} to set the work-area-virt, work-area-phy, work-area-size, and work-area-backup properties of the target.
3805 @end itemize
3806
3807 @node FAQ
3808 @chapter FAQ
3809 @cindex faq
3810 @enumerate
3811 @item @b{RTCK, also known as: Adaptive Clocking - What is it?}
3812 @anchor{FAQ RTCK}
3813 @cindex RTCK
3814 @cindex adaptive clocking
3815 @*
3816
3817 In digital circuit design it is often refered to as ``clock
3818 synchronisation'' the JTAG interface uses one clock (TCK or TCLK)
3819 operating at some speed, your target is operating at another. The two
3820 clocks are not synchronised, they are ``asynchronous''
3821
3822 In order for the two to work together they must be synchronised. Otherwise
3823 the two systems will get out of sync with each other and nothing will
3824 work. There are 2 basic options:
3825 @enumerate
3826 @item
3827 Use a special circuit.
3828 @item
3829 One clock must be some multiple slower than the other.
3830 @end enumerate
3831
3832 @b{Does this really matter?} For some chips and some situations, this
3833 is a non-issue (i.e.: A 500MHz ARM926) but for others - for example some
3834 Atmel SAM7 and SAM9 chips start operation from reset at 32kHz -
3835 program/enable the oscillators and eventually the main clock. It is in
3836 those critical times you must slow the JTAG clock to sometimes 1 to
3837 4kHz.
3838
3839 Imagine debugging a 500MHz ARM926 hand held battery powered device
3840 that ``deep sleeps'' at 32kHz between every keystroke. It can be
3841 painful.
3842
3843 @b{Solution #1 - A special circuit}
3844
3845 In order to make use of this, your JTAG dongle must support the RTCK
3846 feature. Not all dongles support this - keep reading!
3847
3848 The RTCK signal often found in some ARM chips is used to help with
3849 this problem. ARM has a good description of the problem described at
3850 this link: @url{http://www.arm.com/support/faqdev/4170.html} [checked
3851 28/nov/2008]. Link title: ``How does the JTAG synchronisation logic
3852 work? / how does adaptive clocking work?''.
3853
3854 The nice thing about adaptive clocking is that ``battery powered hand
3855 held device example'' - the adaptiveness works perfectly all the
3856 time. One can set a break point or halt the system in the deep power
3857 down code, slow step out until the system speeds up.
3858
3859 @b{Solution #2 - Always works - but may be slower}
3860
3861 Often this is a perfectly acceptable solution.
3862
3863 In most simple terms: Often the JTAG clock must be 1/10 to 1/12 of
3864 the target clock speed. But what that ``magic division'' is varies
3865 depending on the chips on your board. @b{ARM rule of thumb} Most ARM
3866 based systems require an 8:1 division. @b{Xilinx rule of thumb} is
3867 1/12 the clock speed.
3868
3869 Note: Many FTDI2232C based JTAG dongles are limited to 6MHz.
3870
3871 You can still debug the 'low power' situations - you just need to
3872 manually adjust the clock speed at every step. While painful and
3873 tedious, it is not always practical.
3874
3875 It is however easy to ``code your way around it'' - i.e.: Cheat a little,
3876 have a special debug mode in your application that does a ``high power
3877 sleep''. If you are careful - 98% of your problems can be debugged
3878 this way.
3879
3880 To set the JTAG frequency use the command:
3881
3882 @example
3883 # Example: 1.234MHz
3884 jtag_khz 1234
3885 @end example
3886
3887
3888 @item @b{Win32 Pathnames} Why don't backslashes work in Windows paths?
3889
3890 OpenOCD uses Tcl and a backslash is an escape char. Use @{ and @}
3891 around Windows filenames.
3892
3893 @example
3894 > echo \a
3895
3896 > echo @{\a@}
3897 \a
3898 > echo "\a"
3899
3900 >
3901 @end example
3902
3903
3904 @item @b{Missing: cygwin1.dll} OpenOCD complains about a missing cygwin1.dll.
3905
3906 Make sure you have Cygwin installed, or at least a version of OpenOCD that
3907 claims to come with all the necessary DLLs. When using Cygwin, try launching
3908 OpenOCD from the Cygwin shell.
3909
3910 @item @b{Breakpoint Issue} I'm trying to set a breakpoint using GDB (or a frontend like Insight or
3911 Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
3912 arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
3913
3914 GDB issues software breakpoints when a normal breakpoint is requested, or to implement
3915 source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720T or ARM920T,
3916 software breakpoints consume one of the two available hardware breakpoints.
3917
3918 @item @b{LPC2000 Flash} When erasing or writing LPC2000 on-chip flash, the operation fails at random.
3919
3920 Make sure the core frequency specified in the @option{flash lpc2000} line matches the
3921 clock at the time you're programming the flash. If you've specified the crystal's
3922 frequency, make sure the PLL is disabled. If you've specified the full core speed
3923 (e.g. 60MHz), make sure the PLL is enabled.
3924
3925 @item @b{Amontec Chameleon} When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
3926 I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
3927 out while waiting for end of scan, rtck was disabled".
3928
3929 Make sure your PC's parallel port operates in EPP mode. You might have to try several
3930 settings in your PC BIOS (ECP, EPP, and different versions of those).
3931
3932 @item @b{Data Aborts} When debugging with OpenOCD and GDB (plain GDB, Insight, or Eclipse),
3933 I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
3934 memory read caused data abort".
3935
3936 The errors are non-fatal, and are the result of GDB trying to trace stack frames
3937 beyond the last valid frame. It might be possible to prevent this by setting up
3938 a proper "initial" stack frame, if you happen to know what exactly has to
3939 be done, feel free to add this here.
3940
3941 @b{Simple:} In your startup code - push 8 registers of zeros onto the
3942 stack before calling main(). What GDB is doing is ``climbing'' the run
3943 time stack by reading various values on the stack using the standard
3944 call frame for the target. GDB keeps going - until one of 2 things
3945 happen @b{#1} an invalid frame is found, or @b{#2} some huge number of
3946 stackframes have been processed. By pushing zeros on the stack, GDB
3947 gracefully stops.
3948
3949 @b{Debugging Interrupt Service Routines} - In your ISR before you call
3950 your C code, do the same - artifically push some zeros onto the stack,
3951 remember to pop them off when the ISR is done.
3952
3953 @b{Also note:} If you have a multi-threaded operating system, they
3954 often do not @b{in the intrest of saving memory} waste these few
3955 bytes. Painful...
3956
3957
3958 @item @b{JTAG Reset Config} I get the following message in the OpenOCD console (or log file):
3959 "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
3960
3961 This warning doesn't indicate any serious problem, as long as you don't want to
3962 debug your core right out of reset. Your .cfg file specified @option{jtag_reset
3963 trst_and_srst srst_pulls_trst} to tell OpenOCD that either your board,
3964 your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals
3965 independently. With this setup, it's not possible to halt the core right out of
3966 reset, everything else should work fine.
3967
3968 @item @b{USB Power} When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
3969 toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
3970 unstable. When single-stepping over large blocks of code, GDB and OpenOCD
3971 quit with an error message. Is there a stability issue with OpenOCD?
3972
3973 No, this is not a stability issue concerning OpenOCD. Most users have solved
3974 this issue by simply using a self-powered USB hub, which they connect their
3975 Amontec JTAGkey to. Apparently, some computers do not provide a USB power
3976 supply stable enough for the Amontec JTAGkey to be operated.
3977
3978 @b{Laptops running on battery have this problem too...}
3979
3980 @item @b{USB Power} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the
3981 following error messages: "Error: ft2232.c:201 ft2232_read(): FT_Read returned:
3982 4" and "Error: ft2232.c:365 ft2232_send_and_recv(): couldn't read from FT2232".
3983 What does that mean and what might be the reason for this?
3984
3985 First of all, the reason might be the USB power supply. Try using a self-powered
3986 hub instead of a direct connection to your computer. Secondly, the error code 4
3987 corresponds to an FT_IO_ERROR, which means that the driver for the FTDI USB
3988 chip ran into some sort of error - this points us to a USB problem.
3989
3990 @item @b{GDB Disconnects} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
3991 error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
3992 What does that mean and what might be the reason for this?
3993
3994 Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
3995 has closed the connection to OpenOCD. This might be a GDB issue.
3996
3997 @item @b{LPC2000 Flash} In the configuration file in the section where flash device configurations
3998 are described, there is a parameter for specifying the clock frequency
3999 for LPC2000 internal flash devices (e.g. @option{flash bank lpc2000
4000 0x0 0x40000 0 0 0 lpc2000_v1 14746 calc_checksum}), which must be
4001 specified in kilohertz. However, I do have a quartz crystal of a
4002 frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz,
4003 i.e. 14,745.600 kHz). Is it possible to specify real numbers for the
4004 clock frequency?
4005
4006 No. The clock frequency specified here must be given as an integral number.
4007 However, this clock frequency is used by the In-Application-Programming (IAP)
4008 routines of the LPC2000 family only, which seems to be very tolerant concerning
4009 the given clock frequency, so a slight difference between the specified clock
4010 frequency and the actual clock frequency will not cause any trouble.
4011
4012 @item @b{Command Order} Do I have to keep a specific order for the commands in the configuration file?
4013
4014 Well, yes and no. Commands can be given in arbitrary order, yet the
4015 devices listed for the JTAG scan chain must be given in the right
4016 order (jtag newdevice), with the device closest to the TDO-Pin being
4017 listed first. In general, whenever objects of the same type exist
4018 which require an index number, then these objects must be given in the
4019 right order (jtag newtap, targets and flash banks - a target
4020 references a jtag newtap and a flash bank references a target).
4021
4022 You can use the ``scan_chain'' command to verify and display the tap order.
4023
4024 Also, some commands can't execute until after @command{init} has been
4025 processed. Such commands include @command{nand probe} and everything
4026 else that needs to write to controller registers, perhaps for setting
4027 up DRAM and loading it with code.
4028
4029 @item @b{JTAG Tap Order} JTAG tap order - command order
4030
4031 Many newer devices have multiple JTAG taps. For example: ST
4032 Microsystems STM32 chips have two taps, a ``boundary scan tap'' and
4033 ``Cortex-M3'' tap. Example: The STM32 reference manual, Document ID:
4034 RM0008, Section 26.5, Figure 259, page 651/681, the ``TDI'' pin is
4035 connected to the boundary scan tap, which then connects to the
4036 Cortex-M3 tap, which then connects to the TDO pin.
4037
4038 Thus, the proper order for the STM32 chip is: (1) The Cortex-M3, then
4039 (2) The boundary scan tap. If your board includes an additional JTAG
4040 chip in the scan chain (for example a Xilinx CPLD or FPGA) you could
4041 place it before or after the STM32 chip in the chain. For example:
4042
4043 @itemize @bullet
4044 @item OpenOCD_TDI(output) -> STM32 TDI Pin (BS Input)
4045 @item STM32 BS TDO (output) -> STM32 Cortex-M3 TDI (input)
4046 @item STM32 Cortex-M3 TDO (output) -> SM32 TDO Pin
4047 @item STM32 TDO Pin (output) -> Xilinx TDI Pin (input)
4048 @item Xilinx TDO Pin -> OpenOCD TDO (input)
4049 @end itemize
4050
4051 The ``jtag device'' commands would thus be in the order shown below. Note:
4052
4053 @itemize @bullet
4054 @item jtag newtap Xilinx tap -irlen ...
4055 @item jtag newtap stm32 cpu -irlen ...
4056 @item jtag newtap stm32 bs -irlen ...
4057 @item # Create the debug target and say where it is
4058 @item target create stm32.cpu -chain-position stm32.cpu ...
4059 @end itemize
4060
4061
4062 @item @b{SYSCOMP} Sometimes my debugging session terminates with an error. When I look into the
4063 log file, I can see these error messages: Error: arm7_9_common.c:561
4064 arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP
4065
4066 TODO.
4067
4068 @end enumerate
4069
4070 @node Tcl Crash Course
4071 @chapter Tcl Crash Course
4072 @cindex Tcl
4073
4074 Not everyone knows Tcl - this is not intended to be a replacement for
4075 learning Tcl, the intent of this chapter is to give you some idea of
4076 how the Tcl scripts work.
4077
4078 This chapter is written with two audiences in mind. (1) OpenOCD users
4079 who need to understand a bit more of how JIM-Tcl works so they can do
4080 something useful, and (2) those that want to add a new command to
4081 OpenOCD.
4082
4083 @section Tcl Rule #1
4084 There is a famous joke, it goes like this:
4085 @enumerate
4086 @item Rule #1: The wife is always correct
4087 @item Rule #2: If you think otherwise, See Rule #1
4088 @end enumerate
4089
4090 The Tcl equal is this:
4091
4092 @enumerate
4093 @item Rule #1: Everything is a string
4094 @item Rule #2: If you think otherwise, See Rule #1
4095 @end enumerate
4096
4097 As in the famous joke, the consequences of Rule #1 are profound. Once
4098 you understand Rule #1, you will understand Tcl.
4099
4100 @section Tcl Rule #1b
4101 There is a second pair of rules.
4102 @enumerate
4103 @item Rule #1: Control flow does not exist. Only commands
4104 @* For example: the classic FOR loop or IF statement is not a control
4105 flow item, they are commands, there is no such thing as control flow
4106 in Tcl.
4107 @item Rule #2: If you think otherwise, See Rule #1
4108 @* Actually what happens is this: There are commands that by
4109 convention, act like control flow key words in other languages. One of
4110 those commands is the word ``for'', another command is ``if''.
4111 @end enumerate
4112
4113 @section Per Rule #1 - All Results are strings
4114 Every Tcl command results in a string. The word ``result'' is used
4115 deliberatly. No result is just an empty string. Remember: @i{Rule #1 -
4116 Everything is a string}
4117
4118 @section Tcl Quoting Operators
4119 In life of a Tcl script, there are two important periods of time, the
4120 difference is subtle.
4121 @enumerate
4122 @item Parse Time
4123 @item Evaluation Time
4124 @end enumerate
4125
4126 The two key items here are how ``quoted things'' work in Tcl. Tcl has
4127 three primary quoting constructs, the [square-brackets] the
4128 @{curly-braces@} and ``double-quotes''
4129
4130 By now you should know $VARIABLES always start with a $DOLLAR
4131 sign. BTW: To set a variable, you actually use the command ``set'', as
4132 in ``set VARNAME VALUE'' much like the ancient BASIC langauge ``let x
4133 = 1'' statement, but without the equal sign.
4134
4135 @itemize @bullet
4136 @item @b{[square-brackets]}
4137 @* @b{[square-brackets]} are command substitutions. It operates much
4138 like Unix Shell `back-ticks`. The result of a [square-bracket]
4139 operation is exactly 1 string. @i{Remember Rule #1 - Everything is a
4140 string}. These two statements are roughly identical:
4141 @example
4142 # bash example
4143 X=`date`
4144 echo "The Date is: $X"
4145 # Tcl example
4146 set X [date]
4147 puts "The Date is: $X"
4148 @end example
4149 @item @b{``double-quoted-things''}
4150 @* @b{``double-quoted-things''} are just simply quoted
4151 text. $VARIABLES and [square-brackets] are expanded in place - the
4152 result however is exactly 1 string. @i{Remember Rule #1 - Everything
4153 is a string}
4154 @example
4155 set x "Dinner"
4156 puts "It is now \"[date]\", $x is in 1 hour"
4157 @end example
4158 @item @b{@{Curly-Braces@}}
4159 @*@b{@{Curly-Braces@}} are magic: $VARIABLES and [square-brackets] are
4160 parsed, but are NOT expanded or executed. @{Curly-Braces@} are like
4161 'single-quote' operators in BASH shell scripts, with the added
4162 feature: @{curly-braces@} can be nested, single quotes can not. @{@{@{this is
4163 nested 3 times@}@}@} NOTE: [date] is perhaps a bad example, as of
4164 28/nov/2008, Jim/OpenOCD does not have a date command.
4165 @end itemize
4166
4167 @section Consequences of Rule 1/2/3/4
4168
4169 The consequences of Rule 1 are profound.
4170
4171 @subsection Tokenisation & Execution.
4172
4173 Of course, whitespace, blank lines and #comment lines are handled in
4174 the normal way.
4175
4176 As a script is parsed, each (multi) line in the script file is
4177 tokenised and according to the quoting rules. After tokenisation, that
4178 line is immedatly executed.
4179
4180 Multi line statements end with one or more ``still-open''
4181 @{curly-braces@} which - eventually - closes a few lines later.
4182
4183 @subsection Command Execution