- add cfg file for Amontec JTAGKey2 jtag interface
[openocd.git] / doc / openocd.texi
1 \input texinfo @c -*-texinfo-*-
2 @c %**start of header
3 @setfilename openocd.info
4 @settitle OpenOCD User's Guide
5 @dircategory Development
6 @direntry
7 * OpenOCD: (openocd). OpenOCD User's Guide
8 @end direntry
9 @paragraphindent 0
10 @c %**end of header
11
12 @include version.texi
13
14 @copying
15
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
20
21 @itemize @bullet
22 @item Copyright @copyright{} 2008 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk}
24 @item Copyright @copyright{} 2008 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
26 @item Copyright @copyright{} 2009 David Brownell
27 @end itemize
28
29 @quotation
30 Permission is granted to copy, distribute and/or modify this document
31 under the terms of the GNU Free Documentation License, Version 1.2 or
32 any later version published by the Free Software Foundation; with no
33 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
34 Texts. A copy of the license is included in the section entitled ``GNU
35 Free Documentation License''.
36 @end quotation
37 @end copying
38
39 @titlepage
40 @titlefont{@emph{Open On-Chip Debugger:}}
41 @sp 1
42 @title OpenOCD User's Guide
43 @subtitle for release @value{VERSION}
44 @subtitle @value{UPDATED}
45
46 @page
47 @vskip 0pt plus 1filll
48 @insertcopying
49 @end titlepage
50
51 @summarycontents
52 @contents
53
54 @ifnottex
55 @node Top
56 @top OpenOCD User's Guide
57
58 @insertcopying
59 @end ifnottex
60
61 @menu
62 * About:: About OpenOCD
63 * Developers:: OpenOCD Developers
64 * JTAG Hardware Dongles:: JTAG Hardware Dongles
65 * About JIM-Tcl:: About JIM-Tcl
66 * Running:: Running OpenOCD
67 * OpenOCD Project Setup:: OpenOCD Project Setup
68 * Config File Guidelines:: Config File Guidelines
69 * Daemon Configuration:: Daemon Configuration
70 * Interface - Dongle Configuration:: Interface - Dongle Configuration
71 * Reset Configuration:: Reset Configuration
72 * TAP Declaration:: TAP Declaration
73 * CPU Configuration:: CPU Configuration
74 * Flash Commands:: Flash Commands
75 * NAND Flash Commands:: NAND Flash Commands
76 * PLD/FPGA Commands:: PLD/FPGA Commands
77 * General Commands:: General Commands
78 * Architecture and Core Commands:: Architecture and Core Commands
79 * JTAG Commands:: JTAG Commands
80 * Boundary Scan Commands:: Boundary Scan Commands
81 * TFTP:: TFTP
82 * GDB and OpenOCD:: Using GDB and OpenOCD
83 * Tcl Scripting API:: Tcl Scripting API
84 * Upgrading:: Deprecated/Removed Commands
85 * Target Library:: Target Library
86 * FAQ:: Frequently Asked Questions
87 * Tcl Crash Course:: Tcl Crash Course
88 * License:: GNU Free Documentation License
89
90 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
91 @comment case issue with ``Index.html'' and ``index.html''
92 @comment Occurs when creating ``--html --no-split'' output
93 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
94 * OpenOCD Concept Index:: Concept Index
95 * Command and Driver Index:: Command and Driver Index
96 @end menu
97
98 @node About
99 @unnumbered About
100 @cindex about
101
102 OpenOCD was created by Dominic Rath as part of a diploma thesis written at the
103 University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
104 Since that time, the project has grown into an active open-source project,
105 supported by a diverse community of software and hardware developers from
106 around the world.
107
108 @section What is OpenOCD?
109 @cindex TAP
110 @cindex JTAG
111
112 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
113 in-system programming and boundary-scan testing for embedded target
114 devices.
115
116 @b{JTAG:} OpenOCD uses a ``hardware interface dongle'' to communicate
117 with the JTAG (IEEE 1149.1) compliant TAPs on your target board.
118 A @dfn{TAP} is a ``Test Access Port'', a module which processes
119 special instructions and data. TAPs are daisy-chained within and
120 between chips and boards.
121
122 @b{Dongles:} OpenOCD currently supports many types of hardware dongles: USB
123 based, parallel port based, and other standalone boxes that run
124 OpenOCD internally. @xref{JTAG Hardware Dongles}.
125
126 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
127 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x) and
128 Cortex-M3 (Stellaris LM3 and ST STM32) based cores to be
129 debugged via the GDB protocol.
130
131 @b{Flash Programing:} Flash writing is supported for external CFI
132 compatible NOR flashes (Intel and AMD/Spansion command set) and several
133 internal flashes (LPC1700, LPC2000, AT91SAM7, AT91SAM3U, STR7x, STR9x, LM3, and
134 STM32x). Preliminary support for various NAND flash controllers
135 (LPC3180, Orion, S3C24xx, more) controller is included.
136
137 @section OpenOCD Web Site
138
139 The OpenOCD web site provides the latest public news from the community:
140
141 @uref{http://openocd.berlios.de/web/}
142
143 @section Latest User's Guide:
144
145 The user's guide you are now reading may not be the latest one
146 available. A version for more recent code may be available.
147 Its HTML form is published irregularly at:
148
149 @uref{http://openocd.berlios.de/doc/html/index.html}
150
151 PDF form is likewise published at:
152
153 @uref{http://openocd.berlios.de/doc/pdf/openocd.pdf}
154
155 @section OpenOCD User's Forum
156
157 There is an OpenOCD forum (phpBB) hosted by SparkFun:
158
159 @uref{http://forum.sparkfun.com/viewforum.php?f=18}
160
161
162 @node Developers
163 @chapter OpenOCD Developer Resources
164 @cindex developers
165
166 If you are interested in improving the state of OpenOCD's debugging and
167 testing support, new contributions will be welcome. Motivated developers
168 can produce new target, flash or interface drivers, improve the
169 documentation, as well as more conventional bug fixes and enhancements.
170
171 The resources in this chapter are available for developers wishing to explore
172 or expand the OpenOCD source code.
173
174 @section OpenOCD Subversion Repository
175
176 You can download the current SVN version with an SVN client of your
177 choice from the following repositories:
178
179 @uref{svn://svn.berlios.de/openocd/trunk}
180
181 or
182
183 @uref{http://svn.berlios.de/svnroot/repos/openocd/trunk}
184
185 Using the SVN command line client, you can use the following command to
186 fetch the latest version (make sure there is no (non-svn) directory
187 called "openocd" in the current directory):
188
189 svn checkout svn://svn.berlios.de/openocd/trunk openocd
190
191 If you prefer GIT based tools, the @command{git-svn} package works too:
192
193 git svn clone -s svn://svn.berlios.de/openocd
194
195 The ``README'' file contains the instructions for building the project
196 from the repository.
197
198 Developers that want to contribute patches to the OpenOCD system are
199 @b{strongly} encouraged to base their work off of the most recent trunk
200 revision. Patches created against older versions may require additional
201 work from their submitter in order to be updated for newer releases.
202
203 @section Doxygen Developer Manual
204
205 During the development of the 0.2.0 release, the OpenOCD project began
206 providing a Doxygen reference manual. This document contains more
207 technical information about the software internals, development
208 processes, and similar documentation:
209
210 @uref{http://openocd.berlios.de/doc/doxygen/index.html}
211
212 This document is a work-in-progress, but contributions would be welcome
213 to fill in the gaps. All of the source files are provided in-tree,
214 listed in the Doxyfile configuration in the top of the repository trunk.
215
216 @section OpenOCD Developer Mailing List
217
218 The OpenOCD Developer Mailing List provides the primary means of
219 communication between developers:
220
221 @uref{https://lists.berlios.de/mailman/listinfo/openocd-development}
222
223 All drivers developers are enouraged to also subscribe to the list of
224 SVN commits to keep pace with the ongoing changes:
225
226 @uref{https://lists.berlios.de/mailman/listinfo/openocd-svn}
227
228
229 @node JTAG Hardware Dongles
230 @chapter JTAG Hardware Dongles
231 @cindex dongles
232 @cindex FTDI
233 @cindex wiggler
234 @cindex zy1000
235 @cindex printer port
236 @cindex USB Adapter
237 @cindex RTCK
238
239 Defined: @b{dongle}: A small device that plugins into a computer and serves as
240 an adapter .... [snip]
241
242 In the OpenOCD case, this generally refers to @b{a small adapater} one
243 attaches to your computer via USB or the Parallel Printer Port. The
244 execption being the Zylin ZY1000 which is a small box you attach via
245 an ethernet cable. The Zylin ZY1000 has the advantage that it does not
246 require any drivers to be installed on the developer PC. It also has
247 a built in web interface. It supports RTCK/RCLK or adaptive clocking
248 and has a built in relay to power cycle targets remotely.
249
250
251 @section Choosing a Dongle
252
253 There are three things you should keep in mind when choosing a dongle.
254
255 @enumerate
256 @item @b{Voltage} What voltage is your target? 1.8, 2.8, 3.3, or 5V? Does your dongle support it?
257 @item @b{Connection} Printer Ports - Does your computer have one?
258 @item @b{Connection} Is that long printer bit-bang cable practical?
259 @item @b{RTCK} Do you require RTCK? Also known as ``adaptive clocking''
260 @end enumerate
261
262 @section Stand alone Systems
263
264 @b{ZY1000} See: @url{http://www.zylin.com/zy1000.html} Technically, not a
265 dongle, but a standalone box. The ZY1000 has the advantage that it does
266 not require any drivers installed on the developer PC. It also has
267 a built in web interface. It supports RTCK/RCLK or adaptive clocking
268 and has a built in relay to power cycle targets remotely.
269
270 @section USB FT2232 Based
271
272 There are many USB JTAG dongles on the market, many of them are based
273 on a chip from ``Future Technology Devices International'' (FTDI)
274 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
275 See: @url{http://www.ftdichip.com} for more information.
276 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
277 chips are starting to become available in JTAG adapters.
278
279 @itemize @bullet
280 @item @b{usbjtag}
281 @* Link @url{http://www.hs-augsburg.de/~hhoegl/proj/usbjtag/usbjtag.html}
282 @item @b{jtagkey}
283 @* See: @url{http://www.amontec.com/jtagkey.shtml}
284 @item @b{jtagkey2}
285 @* See: @url{http://www.amontec.com/jtagkey2.shtml}
286 @item @b{oocdlink}
287 @* See: @url{http://www.oocdlink.com} By Joern Kaipf
288 @item @b{signalyzer}
289 @* See: @url{http://www.signalyzer.com}
290 @item @b{evb_lm3s811}
291 @* See: @url{http://www.luminarymicro.com} - The Stellaris LM3S811 eval board has an FTD2232C chip built in.
292 @item @b{luminary_icdi}
293 @* See: @url{http://www.luminarymicro.com} - Luminary In-Circuit Debug Interface (ICDI) Board, included in the Stellaris LM3S9B90 and LM3S9B92 Evaluation Kits.
294 @item @b{olimex-jtag}
295 @* See: @url{http://www.olimex.com}
296 @item @b{flyswatter}
297 @* See: @url{http://www.tincantools.com}
298 @item @b{turtelizer2}
299 @* See:
300 @uref{http://www.ethernut.de/en/hardware/turtelizer/index.html, Turtelizer 2}, or
301 @url{http://www.ethernut.de}
302 @item @b{comstick}
303 @* Link: @url{http://www.hitex.com/index.php?id=383}
304 @item @b{stm32stick}
305 @* Link @url{http://www.hitex.com/stm32-stick}
306 @item @b{axm0432_jtag}
307 @* Axiom AXM-0432 Link @url{http://www.axman.com}
308 @item @b{cortino}
309 @* Link @url{http://www.hitex.com/index.php?id=cortino}
310 @end itemize
311
312 @section USB JLINK based
313 There are several OEM versions of the Segger @b{JLINK} adapter. It is
314 an example of a micro controller based JTAG adapter, it uses an
315 AT91SAM764 internally.
316
317 @itemize @bullet
318 @item @b{ATMEL SAMICE} Only works with ATMEL chips!
319 @* Link: @url{http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3892}
320 @item @b{SEGGER JLINK}
321 @* Link: @url{http://www.segger.com/jlink.html}
322 @item @b{IAR J-Link}
323 @* Link: @url{http://www.iar.com/website1/1.0.1.0/369/1/index.php}
324 @end itemize
325
326 @section USB RLINK based
327 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer, permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for SWD and not JTAG, thus not supported.
328
329 @itemize @bullet
330 @item @b{Raisonance RLink}
331 @* Link: @url{http://www.raisonance.com/products/RLink.php}
332 @item @b{STM32 Primer}
333 @* Link: @url{http://www.stm32circle.com/resources/stm32primer.php}
334 @item @b{STM32 Primer2}
335 @* Link: @url{http://www.stm32circle.com/resources/stm32primer2.php}
336 @end itemize
337
338 @section USB Other
339 @itemize @bullet
340 @item @b{USBprog}
341 @* Link: @url{http://www.embedded-projects.net/usbprog} - which uses an Atmel MEGA32 and a UBN9604
342
343 @item @b{USB - Presto}
344 @* Link: @url{http://tools.asix.net/prg_presto.htm}
345
346 @item @b{Versaloon-Link}
347 @* Link: @url{http://www.simonqian.com/en/Versaloon}
348
349 @item @b{ARM-JTAG-EW}
350 @* Link: @url{http://www.olimex.com/dev/arm-jtag-ew.html}
351 @end itemize
352
353 @section IBM PC Parallel Printer Port Based
354
355 The two well known ``JTAG Parallel Ports'' cables are the Xilnx DLC5
356 and the MacGraigor Wiggler. There are many clones and variations of
357 these on the market.
358
359 @itemize @bullet
360
361 @item @b{Wiggler} - There are many clones of this.
362 @* Link: @url{http://www.macraigor.com/wiggler.htm}
363
364 @item @b{DLC5} - From XILINX - There are many clones of this
365 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
366 produced, PDF schematics are easily found and it is easy to make.
367
368 @item @b{Amontec - JTAG Accelerator}
369 @* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
370
371 @item @b{GW16402}
372 @* Link: @url{http://www.gateworks.com/products/avila_accessories/gw16042.php}
373
374 @item @b{Wiggler2}
375 @*@uref{http://www.ccac.rwth-aachen.de/@/~michaels/@/index.php/hardware/@/armjtag,
376 Improved parallel-port wiggler-style JTAG adapter}
377
378 @item @b{Wiggler_ntrst_inverted}
379 @* Yet another variation - See the source code, src/jtag/parport.c
380
381 @item @b{old_amt_wiggler}
382 @* Unknown - probably not on the market today
383
384 @item @b{arm-jtag}
385 @* Link: Most likely @url{http://www.olimex.com/dev/arm-jtag.html} [another wiggler clone]
386
387 @item @b{chameleon}
388 @* Link: @url{http://www.amontec.com/chameleon.shtml}
389
390 @item @b{Triton}
391 @* Unknown.
392
393 @item @b{Lattice}
394 @* ispDownload from Lattice Semiconductor
395 @url{http://www.latticesemi.com/lit/docs/@/devtools/dlcable.pdf}
396
397 @item @b{flashlink}
398 @* From ST Microsystems;
399 @uref{http://www.st.com/stonline/@/products/literature/um/7889.pdf,
400 FlashLINK JTAG programing cable for PSD and uPSD}
401
402 @end itemize
403
404 @section Other...
405 @itemize @bullet
406
407 @item @b{ep93xx}
408 @* An EP93xx based Linux machine using the GPIO pins directly.
409
410 @item @b{at91rm9200}
411 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
412
413 @end itemize
414
415 @node About JIM-Tcl
416 @chapter About JIM-Tcl
417 @cindex JIM Tcl
418 @cindex tcl
419
420 OpenOCD includes a small ``Tcl Interpreter'' known as JIM-Tcl.
421 This programming language provides a simple and extensible
422 command interpreter.
423
424 All commands presented in this Guide are extensions to JIM-Tcl.
425 You can use them as simple commands, without needing to learn
426 much of anything about Tcl.
427 Alternatively, can write Tcl programs with them.
428
429 You can learn more about JIM at its website, @url{http://jim.berlios.de}.
430
431 @itemize @bullet
432 @item @b{JIM vs. Tcl}
433 @* JIM-TCL is a stripped down version of the well known Tcl language,
434 which can be found here: @url{http://www.tcl.tk}. JIM-Tcl has far
435 fewer features. JIM-Tcl is a single .C file and a single .H file and
436 implements the basic Tcl command set. In contrast: Tcl 8.6 is a
437 4.2 MB .zip file containing 1540 files.
438
439 @item @b{Missing Features}
440 @* Our practice has been: Add/clone the real Tcl feature if/when
441 needed. We welcome JIM Tcl improvements, not bloat.
442
443 @item @b{Scripts}
444 @* OpenOCD configuration scripts are JIM Tcl Scripts. OpenOCD's
445 command interpreter today is a mixture of (newer)
446 JIM-Tcl commands, and (older) the orginal command interpreter.
447
448 @item @b{Commands}
449 @* At the OpenOCD telnet command line (or via the GDB mon command) one
450 can type a Tcl for() loop, set variables, etc.
451 Some of the commands documented in this guide are implemented
452 as Tcl scripts, from a @file{startup.tcl} file internal to the server.
453
454 @item @b{Historical Note}
455 @* JIM-Tcl was introduced to OpenOCD in spring 2008.
456
457 @item @b{Need a crash course in Tcl?}
458 @*@xref{Tcl Crash Course}.
459 @end itemize
460
461 @node Running
462 @chapter Running
463 @cindex command line options
464 @cindex logfile
465 @cindex directory search
466
467 The @option{--help} option shows:
468 @verbatim
469 bash$ openocd --help
470
471 --help | -h display this help
472 --version | -v display OpenOCD version
473 --file | -f use configuration file <name>
474 --search | -s dir to search for config files and scripts
475 --debug | -d set debug level <0-3>
476 --log_output | -l redirect log output to file <name>
477 --command | -c run <command>
478 --pipe | -p use pipes when talking to gdb
479 @end verbatim
480
481 By default OpenOCD reads the file configuration file ``openocd.cfg''
482 in the current directory. To specify a different (or multiple)
483 configuration file, you can use the ``-f'' option. For example:
484
485 @example
486 openocd -f config1.cfg -f config2.cfg -f config3.cfg
487 @end example
488
489 Once started, OpenOCD runs as a daemon, waiting for connections from
490 clients (Telnet, GDB, Other).
491
492 If you are having problems, you can enable internal debug messages via
493 the ``-d'' option.
494
495 Also it is possible to interleave JIM-Tcl commands w/config scripts using the
496 @option{-c} command line switch.
497
498 To enable debug output (when reporting problems or working on OpenOCD
499 itself), use the @option{-d} command line switch. This sets the
500 @option{debug_level} to "3", outputting the most information,
501 including debug messages. The default setting is "2", outputting only
502 informational messages, warnings and errors. You can also change this
503 setting from within a telnet or gdb session using @command{debug_level
504 <n>} (@pxref{debug_level}).
505
506 You can redirect all output from the daemon to a file using the
507 @option{-l <logfile>} switch.
508
509 Search paths for config/script files can be added to OpenOCD by using
510 the @option{-s <search>} switch. The current directory and the OpenOCD
511 target library is in the search path by default.
512
513 For details on the @option{-p} option. @xref{Connecting to GDB}.
514
515 Note! OpenOCD will launch the GDB & telnet server even if it can not
516 establish a connection with the target. In general, it is possible for
517 the JTAG controller to be unresponsive until the target is set up
518 correctly via e.g. GDB monitor commands in a GDB init script.
519
520 @node OpenOCD Project Setup
521 @chapter OpenOCD Project Setup
522
523 To use OpenOCD with your development projects, you need to do more than
524 just connecting the JTAG adapter hardware (dongle) to your development board
525 and then starting the OpenOCD server.
526 You also need to configure that server so that it knows
527 about that adapter and board, and helps your work.
528
529 @section Hooking up the JTAG Adapter
530
531 Today's most common case is a dongle with a JTAG cable on one side
532 (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
533 and a USB cable on the other.
534 Instead of USB, some cables use Ethernet;
535 older ones may use a PC parallel port, or even a serial port.
536
537 @enumerate
538 @item @emph{Start with power to your target board turned off},
539 and nothing connected to your JTAG adapter.
540 If you're particularly paranoid, unplug power to the board.
541 It's important to have the ground signal properly set up,
542 unless you are using a JTAG adapter which provides
543 galvanic isolation between the target board and the
544 debugging host.
545
546 @item @emph{Be sure it's the right kind of JTAG connector.}
547 If your dongle has a 20-pin ARM connector, you need some kind
548 of adapter (or octopus, see below) to hook it up to
549 boards using 14-pin or 10-pin connectors ... or to 20-pin
550 connectors which don't use ARM's pinout.
551
552 In the same vein, make sure the voltage levels are compatible.
553 Not all JTAG adapters have the level shifters needed to work
554 with 1.2 Volt boards.
555
556 @item @emph{Be certain the cable is properly oriented} or you might
557 damage your board. In most cases there are only two possible
558 ways to connect the cable.
559 Connect the JTAG cable from your adapter to the board.
560 Be sure it's firmly connected.
561
562 In the best case, the connector is keyed to physically
563 prevent you from inserting it wrong.
564 This is most often done using a slot on the board's male connector
565 housing, which must match a key on the JTAG cable's female connector.
566 If there's no housing, then you must look carefully and
567 make sure pin 1 on the cable hooks up to pin 1 on the board.
568 Ribbon cables are frequently all grey except for a wire on one
569 edge, which is red. The red wire is pin 1.
570
571 Sometimes dongles provide cables where one end is an ``octopus'' of
572 color coded single-wire connectors, instead of a connector block.
573 These are great when converting from one JTAG pinout to another,
574 but are tedious to set up.
575 Use these with connector pinout diagrams to help you match up the
576 adapter signals to the right board pins.
577
578 @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
579 A USB, parallel, or serial port connector will go to the host which
580 you are using to run OpenOCD.
581 For Ethernet, consult the documentation and your network administrator.
582
583 For USB based JTAG adapters you have an easy sanity check at this point:
584 does the host operating system see the JTAG adapter?
585
586 @item @emph{Connect the adapter's power supply, if needed.}
587 This step is primarily for non-USB adapters,
588 but sometimes USB adapters need extra power.
589
590 @item @emph{Power up the target board.}
591 Unless you just let the magic smoke escape,
592 you're now ready to set up the OpenOCD server
593 so you can use JTAG to work with that board.
594
595 @end enumerate
596
597 Talk with the OpenOCD server using
598 telnet (@code{telnet localhost 4444} on many systems) or GDB.
599 @xref{GDB and OpenOCD}.
600
601 @section Project Directory
602
603 There are many ways you can configure OpenOCD and start it up.
604
605 A simple way to organize them all involves keeping a
606 single directory for your work with a given board.
607 When you start OpenOCD from that directory,
608 it searches there first for configuration files, scripts,
609 and for code you upload to the target board.
610 It is also the natural place to write files,
611 such as log files and data you download from the board.
612
613 @section Configuration Basics
614
615 There are two basic ways of configuring OpenOCD, and
616 a variety of ways you can mix them.
617 Think of the difference as just being how you start the server:
618
619 @itemize
620 @item Many @option{-f file} or @option{-c command} options on the command line
621 @item No options, but a @dfn{user config file}
622 in the current directory named @file{openocd.cfg}
623 @end itemize
624
625 Here is an example @file{openocd.cfg} file for a setup
626 using a Signalyzer FT2232-based JTAG adapter to talk to
627 a board with an Atmel AT91SAM7X256 microcontroller:
628
629 @example
630 source [find interface/signalyzer.cfg]
631
632 # GDB can also flash my flash!
633 gdb_memory_map enable
634 gdb_flash_program enable
635
636 source [find target/sam7x256.cfg]
637 @end example
638
639 Here is the command line equivalent of that configuration:
640
641 @example
642 openocd -f interface/signalyzer.cfg \
643 -c "gdb_memory_map enable" \
644 -c "gdb_flash_program enable" \
645 -f target/sam7x256.cfg
646 @end example
647
648 You could wrap such long command lines in shell scripts,
649 each supporting a different development task.
650 One might re-flash the board with a specific firmware version.
651 Another might set up a particular debugging or run-time environment.
652
653 Here we will focus on the simpler solution: one user config
654 file, including basic configuration plus any TCL procedures
655 to simplify your work.
656
657 @section User Config Files
658 @cindex config file, user
659 @cindex user config file
660 @cindex config file, overview
661
662 A user configuration file ties together all the parts of a project
663 in one place.
664 One of the following will match your situation best:
665
666 @itemize
667 @item Ideally almost everything comes from configuration files
668 provided by someone else.
669 For example, OpenOCD distributes a @file{scripts} directory
670 (probably in @file{/usr/share/openocd/scripts} on Linux).
671 Board and tool vendors can provide these too, as can individual
672 user sites; the @option{-s} command line option lets you say
673 where to find these files. (@xref{Running}.)
674 The AT91SAM7X256 example above works this way.
675
676 Three main types of non-user configuration file each have their
677 own subdirectory in the @file{scripts} directory:
678
679 @enumerate
680 @item @b{interface} -- one for each kind of JTAG adapter/dongle
681 @item @b{board} -- one for each different board
682 @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
683 @end enumerate
684
685 Best case: include just two files, and they handle everything else.
686 The first is an interface config file.
687 The second is board-specific, and it sets up the JTAG TAPs and
688 their GDB targets (by deferring to some @file{target.cfg} file),
689 declares all flash memory, and leaves you nothing to do except
690 meet your deadline:
691
692 @example
693 source [find interface/olimex-jtag-tiny.cfg]
694 source [find board/csb337.cfg]
695 @end example
696
697 Boards with a single microcontroller often won't need more
698 than the target config file, as in the AT91SAM7X256 example.
699 That's because there is no external memory (flash, DDR RAM), and
700 the board differences are encapsulated by application code.
701
702 @item You can often reuse some standard config files but
703 need to write a few new ones, probably a @file{board.cfg} file.
704 You will be using commands described later in this User's Guide,
705 and working with the guidelines in the next chapter.
706
707 For example, there may be configuration files for your JTAG adapter
708 and target chip, but you need a new board-specific config file
709 giving access to your particular flash chips.
710 Or you might need to write another target chip configuration file
711 for a new chip built around the Cortex M3 core.
712
713 @quotation Note
714 When you write new configuration files, please submit
715 them for inclusion in the next OpenOCD release.
716 For example, a @file{board/newboard.cfg} file will help the
717 next users of that board, and a @file{target/newcpu.cfg}
718 will help support users of any board using that chip.
719 @end quotation
720
721 @item
722 You may may need to write some C code.
723 It may be as simple as a supporting a new ft2232 or parport
724 based dongle; a bit more involved, like a NAND or NOR flash
725 controller driver; or a big piece of work like supporting
726 a new chip architecture.
727 @end itemize
728
729 Reuse the existing config files when you can.
730 Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
731 You may find a board configuration that's a good example to follow.
732
733 When you write config files, separate the reusable parts
734 (things every user of that interface, chip, or board needs)
735 from ones specific to your environment and debugging approach.
736
737 For example, a @code{gdb-attach} event handler that invokes
738 the @command{reset init} command will interfere with debugging
739 early boot code, which performs some of the same actions
740 that the @code{reset-init} event handler does.
741 Likewise, the @command{arm9tdmi vector_catch} command (or
742 @cindex vector_catch
743 its siblings @command{xscale vector_catch}
744 and @command{cortex_m3 vector_catch}) can be a timesaver
745 during some debug sessions, but don't make everyone use that either.
746 Keep those kinds of debugging aids in your user config file,
747 along with messaging and tracing setup.
748 (@xref{Software Debug Messages and Tracing}.)
749
750 TCP/IP port configuration is another example of something which
751 is environment-specific, and should only appear in
752 a user config file. @xref{TCP/IP Ports}.
753
754 @section Project-Specific Utilities
755
756 A few project-specific utility
757 routines may well speed up your work.
758 Write them, and keep them in your project's user config file.
759
760 For example, if you are making a boot loader work on a
761 board, it's nice to be able to debug the ``after it's
762 loaded to RAM'' parts separately from the finicky early
763 code which sets up the DDR RAM controller and clocks.
764 A script like this one, or a more GDB-aware sibling,
765 may help:
766
767 @example
768 proc ramboot @{ @} @{
769 # Reset, running the target's "reset-init" scripts
770 # to initialize clocks and the DDR RAM controller.
771 # Leave the CPU halted.
772 reset init
773
774 # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
775 load_image u-boot.bin 0x20000000
776
777 # Start running.
778 resume 0x20000000
779 @}
780 @end example
781
782 Then once that code is working you will need to make it
783 boot from NOR flash; a different utility would help.
784 Alternatively, some developers write to flash using GDB.
785 (You might use a similar script if you're working with a flash
786 based microcontroller application instead of a boot loader.)
787
788 @example
789 proc newboot @{ @} @{
790 # Reset, leaving the CPU halted. The "reset-init" event
791 # proc gives faster access to the CPU and to NOR flash;
792 # "reset halt" would be slower.
793 reset init
794
795 # Write standard version of U-Boot into the first two
796 # sectors of NOR flash ... the standard version should
797 # do the same lowlevel init as "reset-init".
798 flash protect 0 0 1 off
799 flash erase_sector 0 0 1
800 flash write_bank 0 u-boot.bin 0x0
801 flash protect 0 0 1 on
802
803 # Reboot from scratch using that new boot loader.
804 reset run
805 @}
806 @end example
807
808 You may need more complicated utility procedures when booting
809 from NAND.
810 That often involves an extra bootloader stage,
811 running from on-chip SRAM to perform DDR RAM setup so it can load
812 the main bootloader code (which won't fit into that SRAM).
813
814 Other helper scripts might be used to write production system images,
815 involving considerably more than just a three stage bootloader.
816
817
818 @node Config File Guidelines
819 @chapter Config File Guidelines
820
821 This chapter is aimed at any user who needs to write a config file,
822 including developers and integrators of OpenOCD and any user who
823 needs to get a new board working smoothly.
824 It provides guidelines for creating those files.
825
826 You should find the following directories under @t{$(INSTALLDIR)/scripts}:
827
828 @itemize @bullet
829 @item @file{interface} ...
830 think JTAG Dongle. Files that configure JTAG adapters go here.
831 @item @file{board} ...
832 think Circuit Board, PWA, PCB, they go by many names. Board files
833 contain initialization items that are specific to a board. For
834 example, the SDRAM initialization sequence for the board, or the type
835 of external flash and what address it uses. Any initialization
836 sequence to enable that external flash or SDRAM should be found in the
837 board file. Boards may also contain multiple targets: two CPUs; or
838 a CPU and an FPGA or CPLD.
839 @item @file{target} ...
840 think chip. The ``target'' directory represents the JTAG TAPs
841 on a chip
842 which OpenOCD should control, not a board. Two common types of targets
843 are ARM chips and FPGA or CPLD chips.
844 When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
845 the target config file defines all of them.
846 @end itemize
847
848 The @file{openocd.cfg} user config
849 file may override features in any of the above files by
850 setting variables before sourcing the target file, or by adding
851 commands specific to their situation.
852
853 @section Interface Config Files
854
855 The user config file
856 should be able to source one of these files with a command like this:
857
858 @example
859 source [find interface/FOOBAR.cfg]
860 @end example
861
862 A preconfigured interface file should exist for every interface in use
863 today, that said, perhaps some interfaces have only been used by the
864 sole developer who created it.
865
866 A separate chapter gives information about how to set these up.
867 @xref{Interface - Dongle Configuration}.
868 Read the OpenOCD source code if you have a new kind of hardware interface
869 and need to provide a driver for it.
870
871 @section Board Config Files
872 @cindex config file, board
873 @cindex board config file
874
875 The user config file
876 should be able to source one of these files with a command like this:
877
878 @example
879 source [find board/FOOBAR.cfg]
880 @end example
881
882 The point of a board config file is to package everything
883 about a given board that user config files need to know.
884 In summary the board files should contain (if present)
885
886 @enumerate
887 @item One or more @command{source [target/...cfg]} statements
888 @item NOR flash configuration (@pxref{NOR Configuration})
889 @item NAND flash configuration (@pxref{NAND Configuration})
890 @item Target @code{reset} handlers for SDRAM and I/O configuration
891 @item JTAG adapter reset configuration (@pxref{Reset Configuration})
892 @item All things that are not ``inside a chip''
893 @end enumerate
894
895 Generic things inside target chips belong in target config files,
896 not board config files. So for example a @code{reset-init} event
897 handler should know board-specific oscillator and PLL parameters,
898 which it passes to target-specific utility code.
899
900 The most complex task of a board config file is creating such a
901 @code{reset-init} event handler.
902 Define those handlers last, after you verify the rest of the board
903 configuration works.
904
905 @subsection Communication Between Config files
906
907 In addition to target-specific utility code, another way that
908 board and target config files communicate is by following a
909 convention on how to use certain variables.
910
911 The full Tcl/Tk language supports ``namespaces'', but JIM-Tcl does not.
912 Thus the rule we follow in OpenOCD is this: Variables that begin with
913 a leading underscore are temporary in nature, and can be modified and
914 used at will within a target configuration file.
915
916 Complex board config files can do the things like this,
917 for a board with three chips:
918
919 @example
920 # Chip #1: PXA270 for network side, big endian
921 set CHIPNAME network
922 set ENDIAN big
923 source [find target/pxa270.cfg]
924 # on return: _TARGETNAME = network.cpu
925 # other commands can refer to the "network.cpu" target.
926 $_TARGETNAME configure .... events for this CPU..
927
928 # Chip #2: PXA270 for video side, little endian
929 set CHIPNAME video
930 set ENDIAN little
931 source [find target/pxa270.cfg]
932 # on return: _TARGETNAME = video.cpu
933 # other commands can refer to the "video.cpu" target.
934 $_TARGETNAME configure .... events for this CPU..
935
936 # Chip #3: Xilinx FPGA for glue logic
937 set CHIPNAME xilinx
938 unset ENDIAN
939 source [find target/spartan3.cfg]
940 @end example
941
942 That example is oversimplified because it doesn't show any flash memory,
943 or the @code{reset-init} event handlers to initialize external DRAM
944 or (assuming it needs it) load a configuration into the FPGA.
945 Such features are usually needed for low-level work with many boards,
946 where ``low level'' implies that the board initialization software may
947 not be working. (That's a common reason to need JTAG tools. Another
948 is to enable working with microcontroller-based systems, which often
949 have no debugging support except a JTAG connector.)
950
951 Target config files may also export utility functions to board and user
952 config files. Such functions should use name prefixes, to help avoid
953 naming collisions.
954
955 Board files could also accept input variables from user config files.
956 For example, there might be a @code{J4_JUMPER} setting used to identify
957 what kind of flash memory a development board is using, or how to set
958 up other clocks and peripherals.
959
960 @subsection Variable Naming Convention
961 @cindex variable names
962
963 Most boards have only one instance of a chip.
964 However, it should be easy to create a board with more than
965 one such chip (as shown above).
966 Accordingly, we encourage these conventions for naming
967 variables associated with different @file{target.cfg} files,
968 to promote consistency and
969 so that board files can override target defaults.
970
971 Inputs to target config files include:
972
973 @itemize @bullet
974 @item @code{CHIPNAME} ...
975 This gives a name to the overall chip, and is used as part of
976 tap identifier dotted names.
977 While the default is normally provided by the chip manufacturer,
978 board files may need to distinguish between instances of a chip.
979 @item @code{ENDIAN} ...
980 By default @option{little} - although chips may hard-wire @option{big}.
981 Chips that can't change endianness don't need to use this variable.
982 @item @code{CPUTAPID} ...
983 When OpenOCD examines the JTAG chain, it can be told verify the
984 chips against the JTAG IDCODE register.
985 The target file will hold one or more defaults, but sometimes the
986 chip in a board will use a different ID (perhaps a newer revision).
987 @end itemize
988
989 Outputs from target config files include:
990
991 @itemize @bullet
992 @item @code{_TARGETNAME} ...
993 By convention, this variable is created by the target configuration
994 script. The board configuration file may make use of this variable to
995 configure things like a ``reset init'' script, or other things
996 specific to that board and that target.
997 If the chip has 2 targets, the names are @code{_TARGETNAME0},
998 @code{_TARGETNAME1}, ... etc.
999 @end itemize
1000
1001 @subsection The reset-init Event Handler
1002 @cindex event, reset-init
1003 @cindex reset-init handler
1004
1005 Board config files run in the OpenOCD configuration stage;
1006 they can't use TAPs or targets, since they haven't been
1007 fully set up yet.
1008 This means you can't write memory or access chip registers;
1009 you can't even verify that a flash chip is present.
1010 That's done later in event handlers, of which the target @code{reset-init}
1011 handler is one of the most important.
1012
1013 Except on microcontrollers, the basic job of @code{reset-init} event
1014 handlers is setting up flash and DRAM, as normally handled by boot loaders.
1015 Microcontrollers rarely use boot loaders; they run right out of their
1016 on-chip flash and SRAM memory. But they may want to use one of these
1017 handlers too, if just for developer convenience.
1018
1019 @quotation Note
1020 Because this is so very board-specific, and chip-specific, no examples
1021 are included here.
1022 Instead, look at the board config files distributed with OpenOCD.
1023 If you have a boot loader, its source code may also be useful.
1024 @end quotation
1025
1026 Some of this code could probably be shared between different boards.
1027 For example, setting up a DRAM controller often doesn't differ by
1028 much except the bus width (16 bits or 32?) and memory timings, so a
1029 reusable TCL procedure loaded by the @file{target.cfg} file might take
1030 those as parameters.
1031 Similarly with oscillator, PLL, and clock setup;
1032 and disabling the watchdog.
1033 Structure the code cleanly, and provide comments to help
1034 the next developer doing such work.
1035 (@emph{You might be that next person} trying to reuse init code!)
1036
1037 The last thing normally done in a @code{reset-init} handler is probing
1038 whatever flash memory was configured. For most chips that needs to be
1039 done while the associated target is halted, either because JTAG memory
1040 access uses the CPU or to prevent conflicting CPU access.
1041
1042 @subsection JTAG Clock Rate
1043
1044 Before your @code{reset-init} handler has set up
1045 the PLLs and clocking, you may need to use
1046 a low JTAG clock rate; then you'd increase it later.
1047 (The rule of thumb for ARM-based processors is 1/8 the CPU clock.)
1048 If the board supports adaptive clocking, use the @command{jtag_rclk}
1049 command, in case your board is used with JTAG adapter which
1050 also supports it. Otherwise use @command{jtag_khz}.
1051 Set the slow rate at the beginning of the reset sequence,
1052 and the faster rate as soon as the clocks are at full speed.
1053
1054 @section Target Config Files
1055 @cindex config file, target
1056 @cindex target config file
1057
1058 Board config files communicate with target config files using
1059 naming conventions as described above, and may source one or
1060 more target config files like this:
1061
1062 @example
1063 source [find target/FOOBAR.cfg]
1064 @end example
1065
1066 The point of a target config file is to package everything
1067 about a given chip that board config files need to know.
1068 In summary the target files should contain
1069
1070 @enumerate
1071 @item Set defaults
1072 @item Add TAPs to the scan chain
1073 @item Add CPU targets (includes GDB support)
1074 @item CPU/Chip/CPU-Core specific features
1075 @item On-Chip flash
1076 @end enumerate
1077
1078 As a rule of thumb, a target file sets up only one chip.
1079 For a microcontroller, that will often include a single TAP,
1080 which is a CPU needing a GDB target, and its on-chip flash.
1081
1082 More complex chips may include multiple TAPs, and the target
1083 config file may need to define them all before OpenOCD
1084 can talk to the chip.
1085 For example, some phone chips have JTAG scan chains that include
1086 an ARM core for operating system use, a DSP,
1087 another ARM core embedded in an image processing engine,
1088 and other processing engines.
1089
1090 @subsection Default Value Boiler Plate Code
1091
1092 All target configuration files should start with code like this,
1093 letting board config files express environment-specific
1094 differences in how things should be set up.
1095
1096 @example
1097 # Boards may override chip names, perhaps based on role,
1098 # but the default should match what the vendor uses
1099 if @{ [info exists CHIPNAME] @} @{
1100 set _CHIPNAME $CHIPNAME
1101 @} else @{
1102 set _CHIPNAME sam7x256
1103 @}
1104
1105 # ONLY use ENDIAN with targets that can change it.
1106 if @{ [info exists ENDIAN] @} @{
1107 set _ENDIAN $ENDIAN
1108 @} else @{
1109 set _ENDIAN little
1110 @}
1111
1112 # TAP identifiers may change as chips mature, for example with
1113 # new revision fields (the "3" here). Pick a good default; you
1114 # can pass several such identifiers to the "jtag newtap" command.
1115 if @{ [info exists CPUTAPID ] @} @{
1116 set _CPUTAPID $CPUTAPID
1117 @} else @{
1118 set _CPUTAPID 0x3f0f0f0f
1119 @}
1120 @end example
1121 @c but 0x3f0f0f0f is for an str73x part ...
1122
1123 @emph{Remember:} Board config files may include multiple target
1124 config files, or the same target file multiple times
1125 (changing at least @code{CHIPNAME}).
1126
1127 Likewise, the target configuration file should define
1128 @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
1129 use it later on when defining debug targets:
1130
1131 @example
1132 set _TARGETNAME $_CHIPNAME.cpu
1133 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1134 @end example
1135
1136 @subsection Adding TAPs to the Scan Chain
1137 After the ``defaults'' are set up,
1138 add the TAPs on each chip to the JTAG scan chain.
1139 @xref{TAP Declaration}, and the naming convention
1140 for taps.
1141
1142 In the simplest case the chip has only one TAP,
1143 probably for a CPU or FPGA.
1144 The config file for the Atmel AT91SAM7X256
1145 looks (in part) like this:
1146
1147 @example
1148 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \
1149 -expected-id $_CPUTAPID
1150 @end example
1151
1152 A board with two such at91sam7 chips would be able
1153 to source such a config file twice, with different
1154 values for @code{CHIPNAME}, so
1155 it adds a different TAP each time.
1156
1157 If there are one or more nonzero @option{-expected-id} values,
1158 OpenOCD attempts to verify the actual tap id against those values.
1159 It will issue error messages if there is mismatch, which
1160 can help to pinpoint problems in OpenOCD configurations.
1161
1162 @example
1163 JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
1164 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
1165 ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
1166 ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
1167 ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
1168 @end example
1169
1170 There are more complex examples too, with chips that have
1171 multiple TAPs. Ones worth looking at include:
1172
1173 @itemize
1174 @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
1175 plus a JRC to enable them
1176 @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
1177 @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
1178 is not currently used)
1179 @end itemize
1180
1181 @subsection Add CPU targets
1182
1183 After adding a TAP for a CPU, you should set it up so that
1184 GDB and other commands can use it.
1185 @xref{CPU Configuration}.
1186 For the at91sam7 example above, the command can look like this;
1187 note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
1188 to little endian, and this chip doesn't support changing that.
1189
1190 @example
1191 set _TARGETNAME $_CHIPNAME.cpu
1192 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1193 @end example
1194
1195 Work areas are small RAM areas associated with CPU targets.
1196 They are used by OpenOCD to speed up downloads,
1197 and to download small snippets of code to program flash chips.
1198 If the chip includes a form of ``on-chip-ram'' - and many do - define
1199 a work area if you can.
1200 Again using the at91sam7 as an example, this can look like:
1201
1202 @example
1203 $_TARGETNAME configure -work-area-phys 0x00200000 \
1204 -work-area-size 0x4000 -work-area-backup 0
1205 @end example
1206
1207 @subsection Chip Reset Setup
1208
1209 As a rule, you should put the @command{reset_config} command
1210 into the board file. Most things you think you know about a
1211 chip can be tweaked by the board.
1212
1213 Some chips have specific ways the TRST and SRST signals are
1214 managed. In the unusual case that these are @emph{chip specific}
1215 and can never be changed by board wiring, they could go here.
1216
1217 Some chips need special attention during reset handling if
1218 they're going to be used with JTAG.
1219 An example might be needing to send some commands right
1220 after the target's TAP has been reset, providing a
1221 @code{reset-deassert-post} event handler that writes a chip
1222 register to report that JTAG debugging is being done.
1223
1224 @subsection ARM Core Specific Hacks
1225
1226 If the chip has a DCC, enable it. If the chip is an ARM9 with some
1227 special high speed download features - enable it.
1228
1229 If present, the MMU, the MPU and the CACHE should be disabled.
1230
1231 Some ARM cores are equipped with trace support, which permits
1232 examination of the instruction and data bus activity. Trace
1233 activity is controlled through an ``Embedded Trace Module'' (ETM)
1234 on one of the core's scan chains. The ETM emits voluminous data
1235 through a ``trace port''. (@xref{ARM Hardware Tracing}.)
1236 If you are using an external trace port,
1237 configure it in your board config file.
1238 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
1239 configure it in your target config file.
1240
1241 @example
1242 etm config $_TARGETNAME 16 normal full etb
1243 etb config $_TARGETNAME $_CHIPNAME.etb
1244 @end example
1245
1246 @subsection Internal Flash Configuration
1247
1248 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
1249
1250 @b{Never ever} in the ``target configuration file'' define any type of
1251 flash that is external to the chip. (For example a BOOT flash on
1252 Chip Select 0.) Such flash information goes in a board file - not
1253 the TARGET (chip) file.
1254
1255 Examples:
1256 @itemize @bullet
1257 @item at91sam7x256 - has 256K flash YES enable it.
1258 @item str912 - has flash internal YES enable it.
1259 @item imx27 - uses boot flash on CS0 - it goes in the board file.
1260 @item pxa270 - again - CS0 flash - it goes in the board file.
1261 @end itemize
1262
1263 @node Daemon Configuration
1264 @chapter Daemon Configuration
1265 @cindex initialization
1266 The commands here are commonly found in the openocd.cfg file and are
1267 used to specify what TCP/IP ports are used, and how GDB should be
1268 supported.
1269
1270 @section Configuration Stage
1271 @cindex configuration stage
1272 @cindex config command
1273
1274 When the OpenOCD server process starts up, it enters a
1275 @emph{configuration stage} which is the only time that
1276 certain commands, @emph{configuration commands}, may be issued.
1277 In this manual, the definition of a configuration command is
1278 presented as a @emph{Config Command}, not as a @emph{Command}
1279 which may be issued interactively.
1280
1281 Those configuration commands include declaration of TAPs,
1282 flash banks,
1283 the interface used for JTAG communication,
1284 and other basic setup.
1285 The server must leave the configuration stage before it
1286 may access or activate TAPs.
1287 After it leaves this stage, configuration commands may no
1288 longer be issued.
1289
1290 @deffn {Config Command} init
1291 This command terminates the configuration stage and
1292 enters the normal command mode. This can be useful to add commands to
1293 the startup scripts and commands such as resetting the target,
1294 programming flash, etc. To reset the CPU upon startup, add "init" and
1295 "reset" at the end of the config script or at the end of the OpenOCD
1296 command line using the @option{-c} command line switch.
1297
1298 If this command does not appear in any startup/configuration file
1299 OpenOCD executes the command for you after processing all
1300 configuration files and/or command line options.
1301
1302 @b{NOTE:} This command normally occurs at or near the end of your
1303 openocd.cfg file to force OpenOCD to ``initialize'' and make the
1304 targets ready. For example: If your openocd.cfg file needs to
1305 read/write memory on your target, @command{init} must occur before
1306 the memory read/write commands. This includes @command{nand probe}.
1307 @end deffn
1308
1309 @anchor{TCP/IP Ports}
1310 @section TCP/IP Ports
1311 @cindex TCP port
1312 @cindex server
1313 @cindex port
1314 @cindex security
1315 The OpenOCD server accepts remote commands in several syntaxes.
1316 Each syntax uses a different TCP/IP port, which you may specify
1317 only during configuration (before those ports are opened).
1318
1319 For reasons including security, you may wish to prevent remote
1320 access using one or more of these ports.
1321 In such cases, just specify the relevant port number as zero.
1322 If you disable all access through TCP/IP, you will need to
1323 use the command line @option{-pipe} option.
1324
1325 @deffn {Command} gdb_port (number)
1326 @cindex GDB server
1327 Specify or query the first port used for incoming GDB connections.
1328 The GDB port for the
1329 first target will be gdb_port, the second target will listen on gdb_port + 1, and so on.
1330 When not specified during the configuration stage,
1331 the port @var{number} defaults to 3333.
1332 When specified as zero, this port is not activated.
1333 @end deffn
1334
1335 @deffn {Command} tcl_port (number)
1336 Specify or query the port used for a simplified RPC
1337 connection that can be used by clients to issue TCL commands and get the
1338 output from the Tcl engine.
1339 Intended as a machine interface.
1340 When not specified during the configuration stage,
1341 the port @var{number} defaults to 6666.
1342 When specified as zero, this port is not activated.
1343 @end deffn
1344
1345 @deffn {Command} telnet_port (number)
1346 Specify or query the
1347 port on which to listen for incoming telnet connections.
1348 This port is intended for interaction with one human through TCL commands.
1349 When not specified during the configuration stage,
1350 the port @var{number} defaults to 4444.
1351 When specified as zero, this port is not activated.
1352 @end deffn
1353
1354 @anchor{GDB Configuration}
1355 @section GDB Configuration
1356 @cindex GDB
1357 @cindex GDB configuration
1358 You can reconfigure some GDB behaviors if needed.
1359 The ones listed here are static and global.
1360 @xref{Target Configuration}, about configuring individual targets.
1361 @xref{Target Events}, about configuring target-specific event handling.
1362
1363 @anchor{gdb_breakpoint_override}
1364 @deffn {Command} gdb_breakpoint_override [@option{hard}|@option{soft}|@option{disable}]
1365 Force breakpoint type for gdb @command{break} commands.
1366 This option supports GDB GUIs which don't
1367 distinguish hard versus soft breakpoints, if the default OpenOCD and
1368 GDB behaviour is not sufficient. GDB normally uses hardware
1369 breakpoints if the memory map has been set up for flash regions.
1370 @end deffn
1371
1372 @deffn {Config Command} gdb_detach (@option{resume}|@option{reset}|@option{halt}|@option{nothing})
1373 Configures what OpenOCD will do when GDB detaches from the daemon.
1374 Default behaviour is @option{resume}.
1375 @end deffn
1376
1377 @anchor{gdb_flash_program}
1378 @deffn {Config Command} gdb_flash_program (@option{enable}|@option{disable})
1379 Set to @option{enable} to cause OpenOCD to program the flash memory when a
1380 vFlash packet is received.
1381 The default behaviour is @option{enable}.
1382 @end deffn
1383
1384 @deffn {Config Command} gdb_memory_map (@option{enable}|@option{disable})
1385 Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
1386 requested. GDB will then know when to set hardware breakpoints, and program flash
1387 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
1388 for flash programming to work.
1389 Default behaviour is @option{enable}.
1390 @xref{gdb_flash_program}.
1391 @end deffn
1392
1393 @deffn {Config Command} gdb_report_data_abort (@option{enable}|@option{disable})
1394 Specifies whether data aborts cause an error to be reported
1395 by GDB memory read packets.
1396 The default behaviour is @option{disable};
1397 use @option{enable} see these errors reported.
1398 @end deffn
1399
1400 @anchor{Event Polling}
1401 @section Event Polling
1402
1403 Hardware debuggers are parts of asynchronous systems,
1404 where significant events can happen at any time.
1405 The OpenOCD server needs to detect some of these events,
1406 so it can report them to through TCL command line
1407 or to GDB.
1408
1409 Examples of such events include:
1410
1411 @itemize
1412 @item One of the targets can stop running ... maybe it triggers
1413 a code breakpoint or data watchpoint, or halts itself.
1414 @item Messages may be sent over ``debug message'' channels ... many
1415 targets support such messages sent over JTAG,
1416 for receipt by the person debugging or tools.
1417 @item Loss of power ... some adapters can detect these events.
1418 @item Resets not issued through JTAG ... such reset sources
1419 can include button presses or other system hardware, sometimes
1420 including the target itself (perhaps through a watchdog).
1421 @item Debug instrumentation sometimes supports event triggering
1422 such as ``trace buffer full'' (so it can quickly be emptied)
1423 or other signals (to correlate with code behavior).
1424 @end itemize
1425
1426 None of those events are signaled through standard JTAG signals.
1427 However, most conventions for JTAG connectors include voltage
1428 level and system reset (SRST) signal detection.
1429 Some connectors also include instrumentation signals, which
1430 can imply events when those signals are inputs.
1431
1432 In general, OpenOCD needs to periodically check for those events,
1433 either by looking at the status of signals on the JTAG connector
1434 or by sending synchronous ``tell me your status'' JTAG requests
1435 to the various active targets.
1436 There is a command to manage and monitor that polling,
1437 which is normally done in the background.
1438
1439 @deffn Command poll [@option{on}|@option{off}]
1440 Poll the current target for its current state.
1441 (Also, @pxref{target curstate}.)
1442 If that target is in debug mode, architecture
1443 specific information about the current state is printed.
1444 An optional parameter
1445 allows background polling to be enabled and disabled.
1446
1447 You could use this from the TCL command shell, or
1448 from GDB using @command{monitor poll} command.
1449 @example
1450 > poll
1451 background polling: on
1452 target state: halted
1453 target halted in ARM state due to debug-request, \
1454 current mode: Supervisor
1455 cpsr: 0x800000d3 pc: 0x11081bfc
1456 MMU: disabled, D-Cache: disabled, I-Cache: enabled
1457 >
1458 @end example
1459 @end deffn
1460
1461 @node Interface - Dongle Configuration
1462 @chapter Interface - Dongle Configuration
1463 @cindex config file, interface
1464 @cindex interface config file
1465
1466 JTAG Adapters/Interfaces/Dongles are normally configured
1467 through commands in an interface configuration
1468 file which is sourced by your @file{openocd.cfg} file, or
1469 through a command line @option{-f interface/....cfg} option.
1470
1471 @example
1472 source [find interface/olimex-jtag-tiny.cfg]
1473 @end example
1474
1475 These commands tell
1476 OpenOCD what type of JTAG adapter you have, and how to talk to it.
1477 A few cases are so simple that you only need to say what driver to use:
1478
1479 @example
1480 # jlink interface
1481 interface jlink
1482 @end example
1483
1484 Most adapters need a bit more configuration than that.
1485
1486
1487 @section Interface Configuration
1488
1489 The interface command tells OpenOCD what type of JTAG dongle you are
1490 using. Depending on the type of dongle, you may need to have one or
1491 more additional commands.
1492
1493 @deffn {Config Command} {interface} name
1494 Use the interface driver @var{name} to connect to the
1495 target.
1496 @end deffn
1497
1498 @deffn Command {interface_list}
1499 List the interface drivers that have been built into
1500 the running copy of OpenOCD.
1501 @end deffn
1502
1503 @deffn Command {jtag interface}
1504 Returns the name of the interface driver being used.
1505 @end deffn
1506
1507 @section Interface Drivers
1508
1509 Each of the interface drivers listed here must be explicitly
1510 enabled when OpenOCD is configured, in order to be made
1511 available at run time.
1512
1513 @deffn {Interface Driver} {amt_jtagaccel}
1514 Amontec Chameleon in its JTAG Accelerator configuration,
1515 connected to a PC's EPP mode parallel port.
1516 This defines some driver-specific commands:
1517
1518 @deffn {Config Command} {parport_port} number
1519 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
1520 the number of the @file{/dev/parport} device.
1521 @end deffn
1522
1523 @deffn {Config Command} rtck [@option{enable}|@option{disable}]
1524 Displays status of RTCK option.
1525 Optionally sets that option first.
1526 @end deffn
1527 @end deffn
1528
1529 @deffn {Interface Driver} {arm-jtag-ew}
1530 Olimex ARM-JTAG-EW USB adapter
1531 This has one driver-specific command:
1532
1533 @deffn Command {armjtagew_info}
1534 Logs some status
1535 @end deffn
1536 @end deffn
1537
1538 @deffn {Interface Driver} {at91rm9200}
1539 Supports bitbanged JTAG from the local system,
1540 presuming that system is an Atmel AT91rm9200
1541 and a specific set of GPIOs is used.
1542 @c command: at91rm9200_device NAME
1543 @c chooses among list of bit configs ... only one option
1544 @end deffn
1545
1546 @deffn {Interface Driver} {dummy}
1547 A dummy software-only driver for debugging.
1548 @end deffn
1549
1550 @deffn {Interface Driver} {ep93xx}
1551 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
1552 @end deffn
1553
1554 @deffn {Interface Driver} {ft2232}
1555 FTDI FT2232 (USB) based devices over one of the userspace libraries.
1556 These interfaces have several commands, used to configure the driver
1557 before initializing the JTAG scan chain:
1558
1559 @deffn {Config Command} {ft2232_device_desc} description
1560 Provides the USB device description (the @emph{iProduct string})
1561 of the FTDI FT2232 device. If not
1562 specified, the FTDI default value is used. This setting is only valid
1563 if compiled with FTD2XX support.
1564 @end deffn
1565
1566 @deffn {Config Command} {ft2232_serial} serial-number
1567 Specifies the @var{serial-number} of the FTDI FT2232 device to use,
1568 in case the vendor provides unique IDs and more than one FT2232 device
1569 is connected to the host.
1570 If not specified, serial numbers are not considered.
1571 (Note that USB serial numbers can be arbitrary Unicode strings,
1572 and are not restricted to containing only decimal digits.)
1573 @end deffn
1574
1575 @deffn {Config Command} {ft2232_layout} name
1576 Each vendor's FT2232 device can use different GPIO signals
1577 to control output-enables, reset signals, and LEDs.
1578 Currently valid layout @var{name} values include:
1579 @itemize @minus
1580 @item @b{axm0432_jtag} Axiom AXM-0432
1581 @item @b{comstick} Hitex STR9 comstick
1582 @item @b{cortino} Hitex Cortino JTAG interface
1583 @item @b{evb_lm3s811} Luminary Micro EVB_LM3S811 as a JTAG interface,
1584 either for the local Cortex-M3 (SRST only)
1585 or in a passthrough mode (neither SRST nor TRST)
1586 @item @b{luminary_icdi} Luminary In-Circuit Debug Interface (ICDI) Board
1587 @item @b{flyswatter} Tin Can Tools Flyswatter
1588 @item @b{icebear} ICEbear JTAG adapter from Section 5
1589 @item @b{jtagkey} Amontec JTAGkey and JTAGkey-Tiny (and compatibles)
1590 @item @b{jtagkey2} Amontec JTAGkey2 (and compatibles)
1591 @item @b{m5960} American Microsystems M5960
1592 @item @b{olimex-jtag} Olimex ARM-USB-OCD and ARM-USB-Tiny
1593 @item @b{oocdlink} OOCDLink
1594 @c oocdlink ~= jtagkey_prototype_v1
1595 @item @b{sheevaplug} Marvell Sheevaplug development kit
1596 @item @b{signalyzer} Xverve Signalyzer
1597 @item @b{stm32stick} Hitex STM32 Performance Stick
1598 @item @b{turtelizer2} egnite Software turtelizer2
1599 @item @b{usbjtag} "USBJTAG-1" layout described in the OpenOCD diploma thesis
1600 @end itemize
1601 @end deffn
1602
1603 @deffn {Config Command} {ft2232_vid_pid} [vid pid]+
1604 The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
1605 default values are used.
1606 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
1607 @example
1608 ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
1609 @end example
1610 @end deffn
1611
1612 @deffn {Config Command} {ft2232_latency} ms
1613 On some systems using FT2232 based JTAG interfaces the FT_Read function call in
1614 ft2232_read() fails to return the expected number of bytes. This can be caused by
1615 USB communication delays and has proved hard to reproduce and debug. Setting the
1616 FT2232 latency timer to a larger value increases delays for short USB packets but it
1617 also reduces the risk of timeouts before receiving the expected number of bytes.
1618 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
1619 @end deffn
1620
1621 For example, the interface config file for a
1622 Turtelizer JTAG Adapter looks something like this:
1623
1624 @example
1625 interface ft2232
1626 ft2232_device_desc "Turtelizer JTAG/RS232 Adapter"
1627 ft2232_layout turtelizer2
1628 ft2232_vid_pid 0x0403 0xbdc8
1629 @end example
1630 @end deffn
1631
1632 @deffn {Interface Driver} {gw16012}
1633 Gateworks GW16012 JTAG programmer.
1634 This has one driver-specific command:
1635
1636 @deffn {Config Command} {parport_port} number
1637 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
1638 the number of the @file{/dev/parport} device.
1639 @end deffn
1640 @end deffn
1641
1642 @deffn {Interface Driver} {jlink}
1643 Segger jlink USB adapter
1644 @c command: jlink_info
1645 @c dumps status
1646 @c command: jlink_hw_jtag (2|3)
1647 @c sets version 2 or 3
1648 @end deffn
1649
1650 @deffn {Interface Driver} {parport}
1651 Supports PC parallel port bit-banging cables:
1652 Wigglers, PLD download cable, and more.
1653 These interfaces have several commands, used to configure the driver
1654 before initializing the JTAG scan chain:
1655
1656 @deffn {Config Command} {parport_cable} name
1657 The layout of the parallel port cable used to connect to the target.
1658 Currently valid cable @var{name} values include:
1659
1660 @itemize @minus
1661 @item @b{altium} Altium Universal JTAG cable.
1662 @item @b{arm-jtag} Same as original wiggler except SRST and
1663 TRST connections reversed and TRST is also inverted.
1664 @item @b{chameleon} The Amontec Chameleon's CPLD when operated
1665 in configuration mode. This is only used to
1666 program the Chameleon itself, not a connected target.
1667 @item @b{dlc5} The Xilinx Parallel cable III.
1668 @item @b{flashlink} The ST Parallel cable.
1669 @item @b{lattice} Lattice ispDOWNLOAD Cable
1670 @item @b{old_amt_wiggler} The Wiggler configuration that comes with
1671 some versions of
1672 Amontec's Chameleon Programmer. The new version available from
1673 the website uses the original Wiggler layout ('@var{wiggler}')
1674 @item @b{triton} The parallel port adapter found on the
1675 ``Karo Triton 1 Development Board''.
1676 This is also the layout used by the HollyGates design
1677 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
1678 @item @b{wiggler} The original Wiggler layout, also supported by
1679 several clones, such as the Olimex ARM-JTAG
1680 @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
1681 @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
1682 @end itemize
1683 @end deffn
1684
1685 @deffn {Config Command} {parport_port} number
1686 Either the address of the I/O port (default: 0x378 for LPT1) or the number of
1687 the @file{/dev/parport} device
1688
1689 When using PPDEV to access the parallel port, use the number of the parallel port:
1690 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
1691 you may encounter a problem.
1692 @end deffn
1693
1694 @deffn {Config Command} {parport_write_on_exit} (on|off)
1695 This will configure the parallel driver to write a known
1696 cable-specific value to the parallel interface on exiting OpenOCD
1697 @end deffn
1698
1699 For example, the interface configuration file for a
1700 classic ``Wiggler'' cable might look something like this:
1701
1702 @example
1703 interface parport
1704 parport_port 0xc8b8
1705 parport_cable wiggler
1706 @end example
1707 @end deffn
1708
1709 @deffn {Interface Driver} {presto}
1710 ASIX PRESTO USB JTAG programmer.
1711 @c command: presto_serial str
1712 @c sets serial number
1713 @end deffn
1714
1715 @deffn {Interface Driver} {rlink}
1716 Raisonance RLink USB adapter
1717 @end deffn
1718
1719 @deffn {Interface Driver} {usbprog}
1720 usbprog is a freely programmable USB adapter.
1721 @end deffn
1722
1723 @deffn {Interface Driver} {vsllink}
1724 vsllink is part of Versaloon which is a versatile USB programmer.
1725
1726 @quotation Note
1727 This defines quite a few driver-specific commands,
1728 which are not currently documented here.
1729 @end quotation
1730 @end deffn
1731
1732 @deffn {Interface Driver} {ZY1000}
1733 This is the Zylin ZY1000 JTAG debugger.
1734
1735 @quotation Note
1736 This defines some driver-specific commands,
1737 which are not currently documented here.
1738 @end quotation
1739
1740 @deffn Command power [@option{on}|@option{off}]
1741 Turn power switch to target on/off.
1742 No arguments: print status.
1743 @end deffn
1744
1745 @end deffn
1746
1747 @anchor{JTAG Speed}
1748 @section JTAG Speed
1749 JTAG clock setup is part of system setup.
1750 It @emph{does not belong with interface setup} since any interface
1751 only knows a few of the constraints for the JTAG clock speed.
1752 Sometimes the JTAG speed is
1753 changed during the target initialization process: (1) slow at
1754 reset, (2) program the CPU clocks, (3) run fast.
1755 Both the "slow" and "fast" clock rates are functions of the
1756 oscillators used, the chip, the board design, and sometimes
1757 power management software that may be active.
1758
1759 The speed used during reset can be adjusted using pre_reset
1760 and post_reset event handlers.
1761 @xref{Target Events}.
1762
1763 If your system supports adaptive clocking (RTCK), configuring
1764 JTAG to use that is probably the most robust approach.
1765 However, it introduces delays to synchronize clocks; so it
1766 may not be the fastest solution.
1767
1768 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
1769 instead of @command{jtag_khz}.
1770
1771 @deffn {Command} jtag_khz max_speed_kHz
1772 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
1773 JTAG interfaces usually support a limited number of
1774 speeds. The speed actually used won't be faster
1775 than the speed specified.
1776
1777 As a rule of thumb, if you specify a clock rate make
1778 sure the JTAG clock is no more than @math{1/6th CPU-Clock}.
1779 This is especially true for synthesized cores (ARMxxx-S).
1780
1781 Speed 0 (khz) selects RTCK method.
1782 @xref{FAQ RTCK}.
1783 If your system uses RTCK, you won't need to change the
1784 JTAG clocking after setup.
1785 Not all interfaces, boards, or targets support ``rtck''.
1786 If the interface device can not
1787 support it, an error is returned when you try to use RTCK.
1788 @end deffn
1789
1790 @defun jtag_rclk fallback_speed_kHz
1791 @cindex RTCK
1792 This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
1793 If that fails (maybe the interface, board, or target doesn't
1794 support it), falls back to the specified frequency.
1795 @example
1796 # Fall back to 3mhz if RTCK is not supported
1797 jtag_rclk 3000
1798 @end example
1799 @end defun
1800
1801 @node Reset Configuration
1802 @chapter Reset Configuration
1803 @cindex Reset Configuration
1804
1805 Every system configuration may require a different reset
1806 configuration. This can also be quite confusing.
1807 Resets also interact with @var{reset-init} event handlers,
1808 which do things like setting up clocks and DRAM, and
1809 JTAG clock rates. (@xref{JTAG Speed}.)
1810 They can also interact with JTAG routers.
1811 Please see the various board files for examples.
1812
1813 @quotation Note
1814 To maintainers and integrators:
1815 Reset configuration touches several things at once.
1816 Normally the board configuration file
1817 should define it and assume that the JTAG adapter supports
1818 everything that's wired up to the board's JTAG connector.
1819
1820 However, the target configuration file could also make note
1821 of something the silicon vendor has done inside the chip,
1822 which will be true for most (or all) boards using that chip.
1823 And when the JTAG adapter doesn't support everything, the
1824 user configuration file will need to override parts of
1825 the reset configuration provided by other files.
1826 @end quotation
1827
1828 @section Types of Reset
1829
1830 There are many kinds of reset possible through JTAG, but
1831 they may not all work with a given board and adapter.
1832 That's part of why reset configuration can be error prone.
1833
1834 @itemize @bullet
1835 @item
1836 @emph{System Reset} ... the @emph{SRST} hardware signal
1837 resets all chips connected to the JTAG adapter, such as processors,
1838 power management chips, and I/O controllers. Normally resets triggered
1839 with this signal behave exactly like pressing a RESET button.
1840 @item
1841 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
1842 just the TAP controllers connected to the JTAG adapter.
1843 Such resets should not be visible to the rest of the system; resetting a
1844 device's the TAP controller just puts that controller into a known state.
1845 @item
1846 @emph{Emulation Reset} ... many devices can be reset through JTAG
1847 commands. These resets are often distinguishable from system
1848 resets, either explicitly (a "reset reason" register says so)
1849 or implicitly (not all parts of the chip get reset).
1850 @item
1851 @emph{Other Resets} ... system-on-chip devices often support
1852 several other types of reset.
1853 You may need to arrange that a watchdog timer stops
1854 while debugging, preventing a watchdog reset.
1855 There may be individual module resets.
1856 @end itemize
1857
1858 In the best case, OpenOCD can hold SRST, then reset
1859 the TAPs via TRST and send commands through JTAG to halt the
1860 CPU at the reset vector before the 1st instruction is executed.
1861 Then when it finally releases the SRST signal, the system is
1862 halted under debugger control before any code has executed.
1863 This is the behavior required to support the @command{reset halt}
1864 and @command{reset init} commands; after @command{reset init} a
1865 board-specific script might do things like setting up DRAM.
1866 (@xref{Reset Command}.)
1867
1868 @anchor{SRST and TRST Issues}
1869 @section SRST and TRST Issues
1870
1871 Because SRST and TRST are hardware signals, they can have a
1872 variety of system-specific constraints. Some of the most
1873 common issues are:
1874
1875 @itemize @bullet
1876
1877 @item @emph{Signal not available} ... Some boards don't wire
1878 SRST or TRST to the JTAG connector. Some JTAG adapters don't
1879 support such signals even if they are wired up.
1880 Use the @command{reset_config} @var{signals} options to say
1881 when either of those signals is not connected.
1882 When SRST is not available, your code might not be able to rely
1883 on controllers having been fully reset during code startup.
1884 Missing TRST is not a problem, since JTAG level resets can
1885 be triggered using with TMS signaling.
1886
1887 @item @emph{Signals shorted} ... Sometimes a chip, board, or
1888 adapter will connect SRST to TRST, instead of keeping them separate.
1889 Use the @command{reset_config} @var{combination} options to say
1890 when those signals aren't properly independent.
1891
1892 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
1893 delay circuit, reset supervisor, or on-chip features can extend
1894 the effect of a JTAG adapter's reset for some time after the adapter
1895 stops issuing the reset. For example, there may be chip or board
1896 requirements that all reset pulses last for at least a
1897 certain amount of time; and reset buttons commonly have
1898 hardware debouncing.
1899 Use the @command{jtag_nsrst_delay} and @command{jtag_ntrst_delay}
1900 commands to say when extra delays are needed.
1901
1902 @item @emph{Drive type} ... Reset lines often have a pullup
1903 resistor, letting the JTAG interface treat them as open-drain
1904 signals. But that's not a requirement, so the adapter may need
1905 to use push/pull output drivers.
1906 Also, with weak pullups it may be advisable to drive
1907 signals to both levels (push/pull) to minimize rise times.
1908 Use the @command{reset_config} @var{trst_type} and
1909 @var{srst_type} parameters to say how to drive reset signals.
1910
1911 @item @emph{Special initialization} ... Targets sometimes need
1912 special JTAG initialization sequences to handle chip-specific
1913 issues (not limited to errata).
1914 For example, certain JTAG commands might need to be issued while
1915 the system as a whole is in a reset state (SRST active)
1916 but the JTAG scan chain is usable (TRST inactive).
1917 (@xref{JTAG Commands}, where the @command{jtag_reset}
1918 command is presented.)
1919 @end itemize
1920
1921 There can also be other issues.
1922 Some devices don't fully conform to the JTAG specifications.
1923 Trivial system-specific differences are common, such as
1924 SRST and TRST using slightly different names.
1925 There are also vendors who distribute key JTAG documentation for
1926 their chips only to developers who have signed a Non-Disclosure
1927 Agreement (NDA).
1928
1929 Sometimes there are chip-specific extensions like a requirement to use
1930 the normally-optional TRST signal (precluding use of JTAG adapters which
1931 don't pass TRST through), or needing extra steps to complete a TAP reset.
1932
1933 In short, SRST and especially TRST handling may be very finicky,
1934 needing to cope with both architecture and board specific constraints.
1935
1936 @section Commands for Handling Resets
1937
1938 @deffn {Command} jtag_nsrst_delay milliseconds
1939 How long (in milliseconds) OpenOCD should wait after deasserting
1940 nSRST (active-low system reset) before starting new JTAG operations.
1941 When a board has a reset button connected to SRST line it will
1942 probably have hardware debouncing, implying you should use this.
1943 @end deffn
1944
1945 @deffn {Command} jtag_ntrst_delay milliseconds
1946 How long (in milliseconds) OpenOCD should wait after deasserting
1947 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
1948 @end deffn
1949
1950 @deffn {Command} reset_config mode_flag ...
1951 This command tells OpenOCD the reset configuration
1952 of your combination of JTAG board and target in target
1953 configuration scripts.
1954
1955 Information earlier in this section describes the kind of problems
1956 the command is intended to address (@pxref{SRST and TRST Issues}).
1957 As a rule this command belongs only in board config files,
1958 describing issues like @emph{board doesn't connect TRST};
1959 or in user config files, addressing limitations derived
1960 from a particular combination of interface and board.
1961 (An unlikely example would be using a TRST-only adapter
1962 with a board that only wires up SRST.)
1963
1964 The @var{mode_flag} options can be specified in any order, but only one
1965 of each type -- @var{signals}, @var{combination}, @var{trst_type},
1966 and @var{srst_type} -- may be specified at a time.
1967 If you don't provide a new value for a given type, its previous
1968 value (perhaps the default) is unchanged.
1969 For example, this means that you don't need to say anything at all about
1970 TRST just to declare that if the JTAG adapter should want to drive SRST,
1971 it must explicitly be driven high (@option{srst_push_pull}).
1972
1973 @var{signals} can specify which of the reset signals are connected.
1974 For example, If the JTAG interface provides SRST, but the board doesn't
1975 connect that signal properly, then OpenOCD can't use it.
1976 Possible values are @option{none} (the default), @option{trst_only},
1977 @option{srst_only} and @option{trst_and_srst}.
1978
1979 @quotation Tip
1980 If your board provides SRST or TRST through the JTAG connector,
1981 you must declare that or else those signals will not be used.
1982 @end quotation
1983
1984 The @var{combination} is an optional value specifying broken reset
1985 signal implementations.
1986 The default behaviour if no option given is @option{separate},
1987 indicating everything behaves normally.
1988 @option{srst_pulls_trst} states that the
1989 test logic is reset together with the reset of the system (e.g. Philips
1990 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
1991 the system is reset together with the test logic (only hypothetical, I
1992 haven't seen hardware with such a bug, and can be worked around).
1993 @option{combined} implies both @option{srst_pulls_trst} and
1994 @option{trst_pulls_srst}.
1995
1996 The optional @var{trst_type} and @var{srst_type} parameters allow the
1997 driver mode of each reset line to be specified. These values only affect
1998 JTAG interfaces with support for different driver modes, like the Amontec
1999 JTAGkey and JTAGAccelerator. Also, they are necessarily ignored if the
2000 relevant signal (TRST or SRST) is not connected.
2001
2002 Possible @var{trst_type} driver modes for the test reset signal (TRST)
2003 are @option{trst_push_pull} (default) and @option{trst_open_drain}.
2004 Most boards connect this signal to a pulldown, so the JTAG TAPs
2005 never leave reset unless they are hooked up to a JTAG adapter.
2006
2007 Possible @var{srst_type} driver modes for the system reset signal (SRST)
2008 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
2009 Most boards connect this signal to a pullup, and allow the
2010 signal to be pulled low by various events including system
2011 powerup and pressing a reset button.
2012 @end deffn
2013
2014
2015 @node TAP Declaration
2016 @chapter TAP Declaration
2017 @cindex TAP declaration
2018 @cindex TAP configuration
2019
2020 @emph{Test Access Ports} (TAPs) are the core of JTAG.
2021 TAPs serve many roles, including:
2022
2023 @itemize @bullet
2024 @item @b{Debug Target} A CPU TAP can be used as a GDB debug target
2025 @item @b{Flash Programing} Some chips program the flash directly via JTAG.
2026 Others do it indirectly, making a CPU do it.
2027 @item @b{Program Download} Using the same CPU support GDB uses,
2028 you can initialize a DRAM controller, download code to DRAM, and then
2029 start running that code.
2030 @item @b{Boundary Scan} Most chips support boundary scan, which
2031 helps test for board assembly problems like solder bridges
2032 and missing connections
2033 @end itemize
2034
2035 OpenOCD must know about the active TAPs on your board(s).
2036 Setting up the TAPs is the core task of your configuration files.
2037 Once those TAPs are set up, you can pass their names to code
2038 which sets up CPUs and exports them as GDB targets,
2039 probes flash memory, performs low-level JTAG operations, and more.
2040
2041 @section Scan Chains
2042 @cindex scan chain
2043
2044 TAPs are part of a hardware @dfn{scan chain},
2045 which is daisy chain of TAPs.
2046 They also need to be added to
2047 OpenOCD's software mirror of that hardware list,
2048 giving each member a name and associating other data with it.
2049 Simple scan chains, with a single TAP, are common in
2050 systems with a single microcontroller or microprocessor.
2051 More complex chips may have several TAPs internally.
2052 Very complex scan chains might have a dozen or more TAPs:
2053 several in one chip, more in the next, and connecting
2054 to other boards with their own chips and TAPs.
2055
2056 You can display the list with the @command{scan_chain} command.
2057 (Don't confuse this with the list displayed by the @command{targets}
2058 command, presented in the next chapter.
2059 That only displays TAPs for CPUs which are configured as
2060 debugging targets.)
2061 Here's what the scan chain might look like for a chip more than one TAP:
2062
2063 @verbatim
2064 TapName Enabled IdCode Expected IrLen IrCap IrMask Instr
2065 -- ------------------ ------- ---------- ---------- ----- ----- ------ -----
2066 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0 0 0x...
2067 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x1 0 0xc
2068 2 omap5912.unknown Y 0x00000000 0x00000000 8 0 0 0xff
2069 @end verbatim
2070
2071 Unfortunately those TAPs can't always be autoconfigured,
2072 because not all devices provide good support for that.
2073 JTAG doesn't require supporting IDCODE instructions, and
2074 chips with JTAG routers may not link TAPs into the chain
2075 until they are told to do so.
2076
2077 The configuration mechanism currently supported by OpenOCD
2078 requires explicit configuration of all TAP devices using
2079 @command{jtag newtap} commands, as detailed later in this chapter.
2080 A command like this would declare one tap and name it @code{chip1.cpu}:
2081
2082 @example
2083 jtag newtap chip1 cpu -irlen 7 -ircapture 0x01 -irmask 0x55
2084 @end example
2085
2086 Each target configuration file lists the TAPs provided
2087 by a given chip.
2088 Board configuration files combine all the targets on a board,
2089 and so forth.
2090 Note that @emph{the order in which TAPs are declared is very important.}
2091 It must match the order in the JTAG scan chain, both inside
2092 a single chip and between them.
2093 @xref{FAQ TAP Order}.
2094
2095 For example, the ST Microsystems STR912 chip has
2096 three separate TAPs@footnote{See the ST
2097 document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
2098 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
2099 @url{http://eu.st.com/stonline/products/literature/ds/13495.pdf}}.
2100 To configure those taps, @file{target/str912.cfg}
2101 includes commands something like this:
2102
2103 @example
2104 jtag newtap str912 flash ... params ...
2105 jtag newtap str912 cpu ... params ...
2106 jtag newtap str912 bs ... params ...
2107 @end example
2108
2109 Actual config files use a variable instead of literals like
2110 @option{str912}, to support more than one chip of each type.
2111 @xref{Config File Guidelines}.
2112
2113 @deffn Command {jtag names}
2114 Returns the names of all current TAPs in the scan chain.
2115 Use @command{jtag cget} or @command{jtag tapisenabled}
2116 to examine attributes and state of each TAP.
2117 @example
2118 foreach t [jtag names] @{
2119 puts [format "TAP: %s\n" $t]
2120 @}
2121 @end example
2122 @end deffn
2123
2124 @deffn Command {scan_chain}
2125 Displays the TAPs in the scan chain configuration,
2126 and their status.
2127 The set of TAPs listed by this command is fixed by
2128 exiting the OpenOCD configuration stage,
2129 but systems with a JTAG router can
2130 enable or disable TAPs dynamically.
2131 In addition to the enable/disable status, the contents of
2132 each TAP's instruction register can also change.
2133 @end deffn
2134
2135 @c FIXME! "jtag cget" should be able to return all TAP
2136 @c attributes, like "$target_name cget" does for targets.
2137
2138 @c Probably want "jtag eventlist", and a "tap-reset" event
2139 @c (on entry to RESET state).
2140
2141 @section TAP Names
2142 @cindex dotted name
2143
2144 When TAP objects are declared with @command{jtag newtap},
2145 a @dfn{dotted.name} is created for the TAP, combining the
2146 name of a module (usually a chip) and a label for the TAP.
2147 For example: @code{xilinx.tap}, @code{str912.flash},
2148 @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
2149 Many other commands use that dotted.name to manipulate or
2150 refer to the TAP. For example, CPU configuration uses the
2151 name, as does declaration of NAND or NOR flash banks.
2152
2153 The components of a dotted name should follow ``C'' symbol
2154 name rules: start with an alphabetic character, then numbers
2155 and underscores are OK; while others (including dots!) are not.
2156
2157 @quotation Tip
2158 In older code, JTAG TAPs were numbered from 0..N.
2159 This feature is still present.
2160 However its use is highly discouraged, and
2161 should not be relied on; it will be removed by mid-2010.
2162 Update all of your scripts to use TAP names rather than numbers,
2163 by paying attention to the runtime warnings they trigger.
2164 Using TAP numbers in target configuration scripts prevents
2165 reusing those scripts on boards with multiple targets.
2166 @end quotation
2167
2168 @section TAP Declaration Commands
2169
2170 @c shouldn't this be(come) a {Config Command}?
2171 @anchor{jtag newtap}
2172 @deffn Command {jtag newtap} chipname tapname configparams...
2173 Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
2174 and configured according to the various @var{configparams}.
2175
2176 The @var{chipname} is a symbolic name for the chip.
2177 Conventionally target config files use @code{$_CHIPNAME},
2178 defaulting to the model name given by the chip vendor but
2179 overridable.
2180
2181 @cindex TAP naming convention
2182 The @var{tapname} reflects the role of that TAP,
2183 and should follow this convention:
2184
2185 @itemize @bullet
2186 @item @code{bs} -- For boundary scan if this is a seperate TAP;
2187 @item @code{cpu} -- The main CPU of the chip, alternatively
2188 @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
2189 @code{arm1} and @code{arm2} on chips two ARMs, and so forth;
2190 @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
2191 @item @code{flash} -- If the chip has a flash TAP, like the str912;
2192 @item @code{jrc} -- For JTAG route controller (example: the ICEpick modules
2193 on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
2194 @item @code{tap} -- Should be used only FPGA or CPLD like devices
2195 with a single TAP;
2196 @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
2197 @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
2198 For example, the Freescale IMX31 has a SDMA (Smart DMA) with
2199 a JTAG TAP; that TAP should be named @code{sdma}.
2200 @end itemize
2201
2202 Every TAP requires at least the following @var{configparams}:
2203
2204 @itemize @bullet
2205 @item @code{-ircapture} @var{NUMBER}
2206 @*The bit pattern loaded by the TAP into the JTAG shift register
2207 on entry to the @sc{ircapture} state, such as 0x01.
2208 JTAG requires the two LSBs of this value to be 01.
2209 The value is used to verify that instruction scans work correctly.
2210 @item @code{-irlen} @var{NUMBER}
2211 @*The length in bits of the
2212 instruction register, such as 4 or 5 bits.
2213 @item @code{-irmask} @var{NUMBER}
2214 @*A mask for the IR register.
2215 For some devices, there are bits in the IR that aren't used.
2216 This lets OpenOCD mask them off when doing IDCODE comparisons.
2217 In general, this should just be all ones for the size of the IR.
2218 @end itemize
2219
2220 A TAP may also provide optional @var{configparams}:
2221
2222 @itemize @bullet
2223 @item @code{-disable} (or @code{-enable})
2224 @*Use the @code{-disable} parameter to flag a TAP which is not
2225 linked in to the scan chain after a reset using either TRST
2226 or the JTAG state machine's @sc{reset} state.
2227 You may use @code{-enable} to highlight the default state
2228 (the TAP is linked in).
2229 @xref{Enabling and Disabling TAPs}.
2230 @item @code{-expected-id} @var{number}
2231 @*A non-zero value represents the expected 32-bit IDCODE
2232 found when the JTAG chain is examined.
2233 These codes are not required by all JTAG devices.
2234 @emph{Repeat the option} as many times as required if more than one
2235 ID code could appear (for example, multiple versions).
2236 @end itemize
2237 @end deffn
2238
2239 @c @deffn Command {jtag arp_init-reset}
2240 @c ... more or less "init" ?
2241
2242 @anchor{Enabling and Disabling TAPs}
2243 @section Enabling and Disabling TAPs
2244 @cindex TAP events
2245 @cindex JTAG Route Controller
2246 @cindex jrc
2247
2248 In some systems, a @dfn{JTAG Route Controller} (JRC)
2249 is used to enable and/or disable specific JTAG TAPs.
2250 Many ARM based chips from Texas Instruments include
2251 an ``ICEpick'' module, which is a JRC.
2252 Such chips include DaVinci and OMAP3 processors.
2253
2254 A given TAP may not be visible until the JRC has been
2255 told to link it into the scan chain; and if the JRC
2256 has been told to unlink that TAP, it will no longer
2257 be visible.
2258 Such routers address problems that JTAG ``bypass mode''
2259 ignores, such as:
2260
2261 @itemize
2262 @item The scan chain can only go as fast as its slowest TAP.
2263 @item Having many TAPs slows instruction scans, since all
2264 TAPs receive new instructions.
2265 @item TAPs in the scan chain must be powered up, which wastes
2266 power and prevents debugging some power management mechanisms.
2267 @end itemize
2268
2269 The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
2270 as implied by the existence of JTAG routers.
2271 However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
2272 does include a kind of JTAG router functionality.
2273
2274 @c (a) currently the event handlers don't seem to be able to
2275 @c fail in a way that could lead to no-change-of-state.
2276 @c (b) eventually non-event configuration should be possible,
2277 @c in which case some this documentation must move.
2278
2279 @deffn Command {jtag cget} dotted.name @option{-event} name
2280 @deffnx Command {jtag configure} dotted.name @option{-event} name string
2281 At this writing this mechanism is used only for event handling,
2282 and the only two events relate to TAP enabling and disabling.
2283
2284 The @code{configure} subcommand assigns an event handler,
2285 a TCL string which is evaluated when the event is triggered.
2286 The @code{cget} subcommand returns that handler.
2287 The two possible values for an event @var{name}
2288 are @option{tap-disable} and @option{tap-enable}.
2289
2290 So for example, when defining a TAP for a CPU connected to
2291 a JTAG router, you should define TAP event handlers using
2292 code that looks something like this:
2293
2294 @example
2295 jtag configure CHIP.cpu -event tap-enable @{
2296 echo "Enabling CPU TAP"
2297 ... jtag operations using CHIP.jrc
2298 @}
2299 jtag configure CHIP.cpu -event tap-disable @{
2300 echo "Disabling CPU TAP"
2301 ... jtag operations using CHIP.jrc
2302 @}
2303 @end example
2304 @end deffn
2305
2306 @deffn Command {jtag tapdisable} dotted.name
2307 @deffnx Command {jtag tapenable} dotted.name
2308 @deffnx Command {jtag tapisenabled} dotted.name
2309 These three commands all return the string "1" if the tap
2310 specified by @var{dotted.name} is enabled,
2311 and "0" if it is disbabled.
2312 The @command{tapenable} variant first enables the tap
2313 by sending it a @option{tap-enable} event.
2314 The @command{tapdisable} variant first disables the tap
2315 by sending it a @option{tap-disable} event.
2316
2317 @quotation Note
2318 Humans will find the @command{scan_chain} command more helpful
2319 than the script-oriented @command{tapisenabled}
2320 for querying the state of the JTAG taps.
2321 @end quotation
2322 @end deffn
2323
2324 @node CPU Configuration
2325 @chapter CPU Configuration
2326 @cindex GDB target
2327
2328 This chapter discusses how to set up GDB debug targets for CPUs.
2329 You can also access these targets without GDB
2330 (@pxref{Architecture and Core Commands},
2331 and @ref{Target State handling}) and
2332 through various kinds of NAND and NOR flash commands.
2333 If you have multiple CPUs you can have multiple such targets.
2334
2335 We'll start by looking at how to examine the targets you have,
2336 then look at how to add one more target and how to configure it.
2337
2338 @section Target List
2339 @cindex target, current
2340 @cindex target, list
2341
2342 All targets that have been set up are part of a list,
2343 where each member has a name.
2344 That name should normally be the same as the TAP name.
2345 You can display the list with the @command{targets}
2346 (plural!) command.
2347 This display often has only one CPU; here's what it might
2348 look like with more than one:
2349 @verbatim
2350 TargetName Type Endian TapName State
2351 -- ------------------ ---------- ------ ------------------ ------------
2352 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
2353 1 MyTarget cortex_m3 little mychip.foo tap-disabled
2354 @end verbatim
2355
2356 One member of that list is the @dfn{current target}, which
2357 is implicitly referenced by many commands.
2358 It's the one marked with a @code{*} near the target name.
2359 In particular, memory addresses often refer to the address
2360 space seen by that current target.
2361 Commands like @command{mdw} (memory display words)
2362 and @command{flash erase_address} (erase NOR flash blocks)
2363 are examples; and there are many more.
2364
2365 Several commands let you examine the list of targets:
2366
2367 @deffn Command {target count}
2368 Returns the number of targets, @math{N}.
2369 The highest numbered target is @math{N - 1}.
2370 @example
2371 set c [target count]
2372 for @{ set x 0 @} @{ $x < $c @} @{ incr x @} @{
2373 # Assuming you have created this function
2374 print_target_details $x
2375 @}
2376 @end example
2377 @end deffn
2378
2379 @deffn Command {target current}
2380 Returns the name of the current target.
2381 @end deffn
2382
2383 @deffn Command {target names}
2384 Lists the names of all current targets in the list.
2385 @example
2386 foreach t [target names] @{
2387 puts [format "Target: %s\n" $t]
2388 @}
2389 @end example
2390 @end deffn
2391
2392 @deffn Command {target number} number
2393 The list of targets is numbered starting at zero.
2394 This command returns the name of the target at index @var{number}.
2395 @example
2396 set thename [target number $x]
2397 puts [format "Target %d is: %s\n" $x $thename]
2398 @end example
2399 @end deffn
2400
2401 @c yep, "target list" would have been better.
2402 @c plus maybe "target setdefault".
2403
2404 @deffn Command targets [name]
2405 @emph{Note: the name of this command is plural. Other target
2406 command names are singular.}
2407
2408 With no parameter, this command displays a table of all known
2409 targets in a user friendly form.
2410
2411 With a parameter, this command sets the current target to
2412 the given target with the given @var{name}; this is
2413 only relevant on boards which have more than one target.
2414 @end deffn
2415
2416 @section Target CPU Types and Variants
2417 @cindex target type
2418 @cindex CPU type
2419 @cindex CPU variant
2420
2421 Each target has a @dfn{CPU type}, as shown in the output of
2422 the @command{targets} command. You need to specify that type
2423 when calling @command{target create}.
2424 The CPU type indicates more than just the instruction set.
2425 It also indicates how that instruction set is implemented,
2426 what kind of debug support it integrates,
2427 whether it has an MMU (and if so, what kind),
2428 what core-specific commands may be available
2429 (@pxref{Architecture and Core Commands}),
2430 and more.
2431
2432 For some CPU types, OpenOCD also defines @dfn{variants} which
2433 indicate differences that affect their handling.
2434 For example, a particular implementation bug might need to be
2435 worked around in some chip versions.
2436
2437 It's easy to see what target types are supported,
2438 since there's a command to list them.
2439 However, there is currently no way to list what target variants
2440 are supported (other than by reading the OpenOCD source code).
2441
2442 @anchor{target types}
2443 @deffn Command {target types}
2444 Lists all supported target types.
2445 At this writing, the supported CPU types and variants are:
2446
2447 @itemize @bullet
2448 @item @code{arm11} -- this is a generation of ARMv6 cores
2449 @item @code{arm720t} -- this is an ARMv4 core
2450 @item @code{arm7tdmi} -- this is an ARMv4 core
2451 @item @code{arm920t} -- this is an ARMv5 core
2452 @item @code{arm926ejs} -- this is an ARMv5 core
2453 @item @code{arm966e} -- this is an ARMv5 core
2454 @item @code{arm9tdmi} -- this is an ARMv4 core
2455 @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
2456 (Support for this is preliminary and incomplete.)
2457 @item @code{cortex_a8} -- this is an ARMv7 core
2458 @item @code{cortex_m3} -- this is an ARMv7 core, supporting only the
2459 compact Thumb2 instruction set. It supports one variant:
2460 @itemize @minus
2461 @item @code{lm3s} ... Use this when debugging older Stellaris LM3S targets.
2462 This will cause OpenOCD to use a software reset rather than asserting
2463 SRST, to avoid a issue with clearing the debug registers.
2464 This is fixed in Fury Rev B, DustDevil Rev B, Tempest; these revisions will
2465 be detected and the normal reset behaviour used.
2466 @end itemize
2467 @item @code{fa526} -- resembles arm920 (w/o Thumb)
2468 @item @code{feroceon} -- resembles arm926
2469 @item @code{mips_m4k} -- a MIPS core. This supports one variant:
2470 @itemize @minus
2471 @item @code{ejtag_srst} ... Use this when debugging targets that do not
2472 provide a functional SRST line on the EJTAG connector. This causes
2473 OpenOCD to instead use an EJTAG software reset command to reset the
2474 processor.
2475 You still need to enable @option{srst} on the @command{reset_config}
2476 command to enable OpenOCD hardware reset functionality.
2477 @end itemize
2478 @item @code{xscale} -- this is actually an architecture,
2479 not a CPU type. It is based on the ARMv5 architecture.
2480 There are several variants defined:
2481 @itemize @minus
2482 @item @code{ixp42x}, @code{ixp45x}, @code{ixp46x},
2483 @code{pxa27x} ... instruction register length is 7 bits
2484 @item @code{pxa250}, @code{pxa255},
2485 @code{pxa26x} ... instruction register length is 5 bits
2486 @end itemize
2487 @end itemize
2488 @end deffn
2489
2490 To avoid being confused by the variety of ARM based cores, remember
2491 this key point: @emph{ARM is a technology licencing company}.
2492 (See: @url{http://www.arm.com}.)
2493 The CPU name used by OpenOCD will reflect the CPU design that was
2494 licenced, not a vendor brand which incorporates that design.
2495 Name prefixes like arm7, arm9, arm11, and cortex
2496 reflect design generations;
2497 while names like ARMv4, ARMv5, ARMv6, and ARMv7
2498 reflect an architecture version implemented by a CPU design.
2499
2500 @anchor{Target Configuration}
2501 @section Target Configuration
2502
2503 Before creating a ``target'', you must have added its TAP to the scan chain.
2504 When you've added that TAP, you will have a @code{dotted.name}
2505 which is used to set up the CPU support.
2506 The chip-specific configuration file will normally configure its CPU(s)
2507 right after it adds all of the chip's TAPs to the scan chain.
2508
2509 Although you can set up a target in one step, it's often clearer if you
2510 use shorter commands and do it in two steps: create it, then configure
2511 optional parts.
2512 All operations on the target after it's created will use a new
2513 command, created as part of target creation.
2514
2515 The two main things to configure after target creation are
2516 a work area, which usually has target-specific defaults even
2517 if the board setup code overrides them later;
2518 and event handlers (@pxref{Target Events}), which tend
2519 to be much more board-specific.
2520 The key steps you use might look something like this
2521
2522 @example
2523 target create MyTarget cortex_m3 -chain-position mychip.cpu
2524 $MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
2525 $MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
2526 $MyTarget configure -event reset-init @{ myboard_reinit @}
2527 @end example
2528
2529 You should specify a working area if you can; typically it uses some
2530 on-chip SRAM.
2531 Such a working area can speed up many things, including bulk
2532 writes to target memory;
2533 flash operations like checking to see if memory needs to be erased;
2534 GDB memory checksumming;
2535 and more.
2536
2537 @quotation Warning
2538 On more complex chips, the work area can become
2539 inaccessible when application code
2540 (such as an operating system)
2541 enables or disables the MMU.
2542 For example, the particular MMU context used to acess the virtual
2543 address will probably matter ... and that context might not have
2544 easy access to other addresses needed.
2545 At this writing, OpenOCD doesn't have much MMU intelligence.
2546 @end quotation
2547
2548 It's often very useful to define a @code{reset-init} event handler.
2549 For systems that are normally used with a boot loader,
2550 common tasks include updating clocks and initializing memory
2551 controllers.
2552 That may be needed to let you write the boot loader into flash,
2553 in order to ``de-brick'' your board; or to load programs into
2554 external DDR memory without having run the boot loader.
2555
2556 @deffn Command {target create} target_name type configparams...
2557 This command creates a GDB debug target that refers to a specific JTAG tap.
2558 It enters that target into a list, and creates a new
2559 command (@command{@var{target_name}}) which is used for various
2560 purposes including additional configuration.
2561
2562 @itemize @bullet
2563 @item @var{target_name} ... is the name of the debug target.
2564 By convention this should be the same as the @emph{dotted.name}
2565 of the TAP associated with this target, which must be specified here
2566 using the @code{-chain-position @var{dotted.name}} configparam.
2567
2568 This name is also used to create the target object command,
2569 referred to here as @command{$target_name},
2570 and in other places the target needs to be identified.
2571 @item @var{type} ... specifies the target type. @xref{target types}.
2572 @item @var{configparams} ... all parameters accepted by
2573 @command{$target_name configure} are permitted.
2574 If the target is big-endian, set it here with @code{-endian big}.
2575 If the variant matters, set it here with @code{-variant}.
2576
2577 You @emph{must} set the @code{-chain-position @var{dotted.name}} here.
2578 @end itemize
2579 @end deffn
2580
2581 @deffn Command {$target_name configure} configparams...
2582 The options accepted by this command may also be
2583 specified as parameters to @command{target create}.
2584 Their values can later be queried one at a time by
2585 using the @command{$target_name cget} command.
2586
2587 @emph{Warning:} changing some of these after setup is dangerous.
2588 For example, moving a target from one TAP to another;
2589 and changing its endianness or variant.
2590
2591 @itemize @bullet
2592
2593 @item @code{-chain-position} @var{dotted.name} -- names the TAP
2594 used to access this target.
2595
2596 @item @code{-endian} (@option{big}|@option{little}) -- specifies
2597 whether the CPU uses big or little endian conventions
2598
2599 @item @code{-event} @var{event_name} @var{event_body} --
2600 @xref{Target Events}.
2601 Note that this updates a list of named event handlers.
2602 Calling this twice with two different event names assigns
2603 two different handlers, but calling it twice with the
2604 same event name assigns only one handler.
2605
2606 @item @code{-variant} @var{name} -- specifies a variant of the target,
2607 which OpenOCD needs to know about.
2608
2609 @item @code{-work-area-backup} (@option{0}|@option{1}) -- says
2610 whether the work area gets backed up; by default, it doesn't.
2611 When possible, use a working_area that doesn't need to be backed up,
2612 since performing a backup slows down operations.
2613
2614 @item @code{-work-area-size} @var{size} -- specify/set the work area
2615
2616 @item @code{-work-area-phys} @var{address} -- set the work area
2617 base @var{address} to be used when no MMU is active.
2618
2619 @item @code{-work-area-virt} @var{address} -- set the work area
2620 base @var{address} to be used when an MMU is active.
2621
2622 @end itemize
2623 @end deffn
2624
2625 @section Other $target_name Commands
2626 @cindex object command
2627
2628 The Tcl/Tk language has the concept of object commands,
2629 and OpenOCD adopts that same model for targets.
2630
2631 A good Tk example is a on screen button.
2632 Once a button is created a button
2633 has a name (a path in Tk terms) and that name is useable as a first
2634 class command. For example in Tk, one can create a button and later
2635 configure it like this:
2636
2637 @example
2638 # Create
2639 button .foobar -background red -command @{ foo @}
2640 # Modify
2641 .foobar configure -foreground blue
2642 # Query
2643 set x [.foobar cget -background]
2644 # Report
2645 puts [format "The button is %s" $x]
2646 @end example
2647
2648 In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
2649 button, and its object commands are invoked the same way.
2650
2651 @example
2652 str912.cpu mww 0x1234 0x42
2653 omap3530.cpu mww 0x5555 123
2654 @end example
2655
2656 The commands supported by OpenOCD target objects are:
2657
2658 @deffn Command {$target_name arp_examine}
2659 @deffnx Command {$target_name arp_halt}
2660 @deffnx Command {$target_name arp_poll}
2661 @deffnx Command {$target_name arp_reset}
2662 @deffnx Command {$target_name arp_waitstate}
2663 Internal OpenOCD scripts (most notably @file{startup.tcl})
2664 use these to deal with specific reset cases.
2665 They are not otherwise documented here.
2666 @end deffn
2667
2668 @deffn Command {$target_name array2mem} arrayname width address count
2669 @deffnx Command {$target_name mem2array} arrayname width address count
2670 These provide an efficient script-oriented interface to memory.
2671 The @code{array2mem} primitive writes bytes, halfwords, or words;
2672 while @code{mem2array} reads them.
2673 In both cases, the TCL side uses an array, and
2674 the target side uses raw memory.
2675
2676 The efficiency comes from enabling the use of
2677 bulk JTAG data transfer operations.
2678 The script orientation comes from working with data
2679 values that are packaged for use by TCL scripts;
2680 @command{mdw} type primitives only print data they retrieve,
2681 and neither store nor return those values.
2682
2683 @itemize
2684 @item @var{arrayname} ... is the name of an array variable
2685 @item @var{width} ... is 8/16/32 - indicating the memory access size
2686 @item @var{address} ... is the target memory address
2687 @item @var{count} ... is the number of elements to process
2688 @end itemize
2689 @end deffn
2690
2691 @deffn Command {$target_name cget} queryparm
2692 Each configuration parameter accepted by
2693 @command{$target_name configure}
2694 can be individually queried, to return its current value.
2695 The @var{queryparm} is a parameter name
2696 accepted by that command, such as @code{-work-area-phys}.
2697 There are a few special cases:
2698
2699 @itemize @bullet
2700 @item @code{-event} @var{event_name} -- returns the handler for the
2701 event named @var{event_name}.
2702 This is a special case because setting a handler requires
2703 two parameters.
2704 @item @code{-type} -- returns the target type.
2705 This is a special case because this is set using
2706 @command{target create} and can't be changed
2707 using @command{$target_name configure}.
2708 @end itemize
2709
2710 For example, if you wanted to summarize information about
2711 all the targets you might use something like this:
2712
2713 @example
2714 for @{ set x 0 @} @{ $x < [target count] @} @{ incr x @} @{
2715 set name [target number $x]
2716 set y [$name cget -endian]
2717 set z [$name cget -type]
2718 puts [format "Chip %d is %s, Endian: %s, type: %s" \
2719 $x $name $y $z]
2720 @}
2721 @end example
2722 @end deffn
2723
2724 @anchor{target curstate}
2725 @deffn Command {$target_name curstate}
2726 Displays the current target state:
2727 @code{debug-running},
2728 @code{halted},
2729 @code{reset},
2730 @code{running}, or @code{unknown}.
2731 (Also, @pxref{Event Polling}.)
2732 @end deffn
2733
2734 @deffn Command {$target_name eventlist}
2735 Displays a table listing all event handlers
2736 currently associated with this target.
2737 @xref{Target Events}.
2738 @end deffn
2739
2740 @deffn Command {$target_name invoke-event} event_name
2741 Invokes the handler for the event named @var{event_name}.
2742 (This is primarily intended for use by OpenOCD framework
2743 code, for example by the reset code in @file{startup.tcl}.)
2744 @end deffn
2745
2746 @deffn Command {$target_name mdw} addr [count]
2747 @deffnx Command {$target_name mdh} addr [count]
2748 @deffnx Command {$target_name mdb} addr [count]
2749 Display contents of address @var{addr}, as
2750 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
2751 or 8-bit bytes (@command{mdb}).
2752 If @var{count} is specified, displays that many units.
2753 (If you want to manipulate the data instead of displaying it,
2754 see the @code{mem2array} primitives.)
2755 @end deffn
2756
2757 @deffn Command {$target_name mww} addr word
2758 @deffnx Command {$target_name mwh} addr halfword
2759 @deffnx Command {$target_name mwb} addr byte
2760 Writes the specified @var{word} (32 bits),
2761 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
2762 at the specified address @var{addr}.
2763 @end deffn
2764
2765 @anchor{Target Events}
2766 @section Target Events
2767 @cindex events
2768 At various times, certain things can happen, or you want them to happen.
2769 For example:
2770 @itemize @bullet
2771 @item What should happen when GDB connects? Should your target reset?
2772 @item When GDB tries to flash the target, do you need to enable the flash via a special command?
2773 @item During reset, do you need to write to certain memory locations
2774 to set up system clocks or
2775 to reconfigure the SDRAM?
2776 @end itemize
2777
2778 All of the above items can be addressed by target event handlers.
2779 These are set up by @command{$target_name configure -event} or
2780 @command{target create ... -event}.
2781
2782 The programmer's model matches the @code{-command} option used in Tcl/Tk
2783 buttons and events. The two examples below act the same, but one creates
2784 and invokes a small procedure while the other inlines it.
2785
2786 @example
2787 proc my_attach_proc @{ @} @{
2788 echo "Reset..."
2789 reset halt
2790 @}
2791 mychip.cpu configure -event gdb-attach my_attach_proc
2792 mychip.cpu configure -event gdb-attach @{
2793 echo "Reset..."
2794 reset halt
2795 @}
2796 @end example
2797
2798 The following target events are defined:
2799
2800 @itemize @bullet
2801 @item @b{debug-halted}
2802 @* The target has halted for debug reasons (i.e.: breakpoint)
2803 @item @b{debug-resumed}
2804 @* The target has resumed (i.e.: gdb said run)
2805 @item @b{early-halted}
2806 @* Occurs early in the halt process
2807 @ignore
2808 @item @b{examine-end}
2809 @* Currently not used (goal: when JTAG examine completes)
2810 @item @b{examine-start}
2811 @* Currently not used (goal: when JTAG examine starts)
2812 @end ignore
2813 @item @b{gdb-attach}
2814 @* When GDB connects
2815 @item @b{gdb-detach}
2816 @* When GDB disconnects
2817 @item @b{gdb-end}
2818 @* When the target has halted and GDB is not doing anything (see early halt)
2819 @item @b{gdb-flash-erase-start}
2820 @* Before the GDB flash process tries to erase the flash
2821 @item @b{gdb-flash-erase-end}
2822 @* After the GDB flash process has finished erasing the flash
2823 @item @b{gdb-flash-write-start}
2824 @* Before GDB writes to the flash
2825 @item @b{gdb-flash-write-end}
2826 @* After GDB writes to the flash
2827 @item @b{gdb-start}
2828 @* Before the target steps, gdb is trying to start/resume the target
2829 @item @b{halted}
2830 @* The target has halted
2831 @ignore
2832 @item @b{old-gdb_program_config}
2833 @* DO NOT USE THIS: Used internally
2834 @item @b{old-pre_resume}
2835 @* DO NOT USE THIS: Used internally
2836 @end ignore
2837 @item @b{reset-assert-pre}
2838 @* Issued as part of @command{reset} processing
2839 after SRST and/or TRST were activated and deactivated,
2840 but before reset is asserted on the tap.
2841 @item @b{reset-assert-post}
2842 @* Issued as part of @command{reset} processing
2843 when reset is asserted on the tap.
2844 @item @b{reset-deassert-pre}
2845 @* Issued as part of @command{reset} processing
2846 when reset is about to be released on the tap.
2847
2848 For some chips, this may be a good place to make sure
2849 the JTAG clock is slow enough to work before the PLL
2850 has been set up to allow faster JTAG speeds.
2851 @item @b{reset-deassert-post}
2852 @* Issued as part of @command{reset} processing
2853 when reset has been released on the tap.
2854 @item @b{reset-end}
2855 @* Issued as the final step in @command{reset} processing.
2856 @ignore
2857 @item @b{reset-halt-post}
2858 @* Currently not used
2859 @item @b{reset-halt-pre}
2860 @* Currently not used
2861 @end ignore
2862 @item @b{reset-init}
2863 @* Used by @b{reset init} command for board-specific initialization.
2864 This event fires after @emph{reset-deassert-post}.
2865
2866 This is where you would configure PLLs and clocking, set up DRAM so
2867 you can download programs that don't fit in on-chip SRAM, set up pin
2868 multiplexing, and so on.
2869 @item @b{reset-start}
2870 @* Issued as part of @command{reset} processing
2871 before either SRST or TRST are activated.
2872 @ignore
2873 @item @b{reset-wait-pos}
2874 @* Currently not used
2875 @item @b{reset-wait-pre}
2876 @* Currently not used
2877 @end ignore
2878 @item @b{resume-start}
2879 @* Before any target is resumed
2880 @item @b{resume-end}
2881 @* After all targets have resumed
2882 @item @b{resume-ok}
2883 @* Success
2884 @item @b{resumed}
2885 @* Target has resumed
2886 @end itemize
2887
2888
2889 @node Flash Commands
2890 @chapter Flash Commands
2891
2892 OpenOCD has different commands for NOR and NAND flash;
2893 the ``flash'' command works with NOR flash, while
2894 the ``nand'' command works with NAND flash.
2895 This partially reflects different hardware technologies:
2896 NOR flash usually supports direct CPU instruction and data bus access,
2897 while data from a NAND flash must be copied to memory before it can be
2898 used. (SPI flash must also be copied to memory before use.)
2899 However, the documentation also uses ``flash'' as a generic term;
2900 for example, ``Put flash configuration in board-specific files''.
2901
2902 Flash Steps:
2903 @enumerate
2904 @item Configure via the command @command{flash bank}
2905 @* Do this in a board-specific configuration file,
2906 passing parameters as needed by the driver.
2907 @item Operate on the flash via @command{flash subcommand}
2908 @* Often commands to manipulate the flash are typed by a human, or run
2909 via a script in some automated way. Common tasks include writing a
2910 boot loader, operating system, or other data.
2911 @item GDB Flashing
2912 @* Flashing via GDB requires the flash be configured via ``flash
2913 bank'', and the GDB flash features be enabled.
2914 @xref{GDB Configuration}.
2915 @end enumerate
2916
2917 Many CPUs have the ablity to ``boot'' from the first flash bank.
2918 This means that misprogramming that bank can ``brick'' a system,
2919 so that it can't boot.
2920 JTAG tools, like OpenOCD, are often then used to ``de-brick'' the
2921 board by (re)installing working boot firmware.
2922
2923 @anchor{NOR Configuration}
2924 @section Flash Configuration Commands
2925 @cindex flash configuration
2926
2927 @deffn {Config Command} {flash bank} driver base size chip_width bus_width target [driver_options]
2928 Configures a flash bank which provides persistent storage
2929 for addresses from @math{base} to @math{base + size - 1}.
2930 These banks will often be visible to GDB through the target's memory map.
2931 In some cases, configuring a flash bank will activate extra commands;
2932 see the driver-specific documentation.
2933
2934 @itemize @bullet
2935 @item @var{driver} ... identifies the controller driver
2936 associated with the flash bank being declared.
2937 This is usually @code{cfi} for external flash, or else
2938 the name of a microcontroller with embedded flash memory.
2939 @xref{Flash Driver List}.
2940 @item @var{base} ... Base address of the flash chip.
2941 @item @var{size} ... Size of the chip, in bytes.
2942 For some drivers, this value is detected from the hardware.
2943 @item @var{chip_width} ... Width of the flash chip, in bytes;
2944 ignored for most microcontroller drivers.
2945 @item @var{bus_width} ... Width of the data bus used to access the
2946 chip, in bytes; ignored for most microcontroller drivers.
2947 @item @var{target} ... Names the target used to issue
2948 commands to the flash controller.
2949 @comment Actually, it's currently a controller-specific parameter...
2950 @item @var{driver_options} ... drivers may support, or require,
2951 additional parameters. See the driver-specific documentation
2952 for more information.
2953 @end itemize
2954 @quotation Note
2955 This command is not available after OpenOCD initialization has completed.
2956 Use it in board specific configuration files, not interactively.
2957 @end quotation
2958 @end deffn
2959
2960 @comment the REAL name for this command is "ocd_flash_banks"
2961 @comment less confusing would be: "flash list" (like "nand list")
2962 @deffn Command {flash banks}
2963 Prints a one-line summary of each device declared
2964 using @command{flash bank}, numbered from zero.
2965 Note that this is the @emph{plural} form;
2966 the @emph{singular} form is a very different command.
2967 @end deffn
2968
2969 @deffn Command {flash probe} num
2970 Identify the flash, or validate the parameters of the configured flash. Operation
2971 depends on the flash type.
2972 The @var{num} parameter is a value shown by @command{flash banks}.
2973 Most flash commands will implicitly @emph{autoprobe} the bank;
2974 flash drivers can distinguish between probing and autoprobing,
2975 but most don't bother.
2976 @end deffn
2977
2978 @section Erasing, Reading, Writing to Flash
2979 @cindex flash erasing
2980 @cindex flash reading
2981 @cindex flash writing
2982 @cindex flash programming
2983
2984 One feature distinguishing NOR flash from NAND or serial flash technologies
2985 is that for read access, it acts exactly like any other addressible memory.
2986 This means you can use normal memory read commands like @command{mdw} or
2987 @command{dump_image} with it, with no special @command{flash} subcommands.
2988 @xref{Memory access}, and @ref{Image access}.
2989
2990 Write access works differently. Flash memory normally needs to be erased
2991 before it's written. Erasing a sector turns all of its bits to ones, and
2992 writing can turn ones into zeroes. This is why there are special commands
2993 for interactive erasing and writing, and why GDB needs to know which parts
2994 of the address space hold NOR flash memory.
2995
2996 @quotation Note
2997 Most of these erase and write commands leverage the fact that NOR flash
2998 chips consume target address space. They implicitly refer to the current
2999 JTAG target, and map from an address in that target's address space
3000 back to a flash bank.
3001 @comment In May 2009, those mappings may fail if any bank associated
3002 @comment with that target doesn't succesfuly autoprobe ... bug worth fixing?
3003 A few commands use abstract addressing based on bank and sector numbers,
3004 and don't depend on searching the current target and its address space.
3005 Avoid confusing the two command models.
3006 @end quotation
3007
3008 Some flash chips implement software protection against accidental writes,
3009 since such buggy writes could in some cases ``brick'' a system.
3010 For such systems, erasing and writing may require sector protection to be
3011 disabled first.
3012 Examples include CFI flash such as ``Intel Advanced Bootblock flash'',
3013 and AT91SAM7 on-chip flash.
3014 @xref{flash protect}.
3015
3016 @anchor{flash erase_sector}
3017 @deffn Command {flash erase_sector} num first last
3018 Erase sectors in bank @var{num}, starting at sector @var{first} up to and including
3019 @var{last}. Sector numbering starts at 0.
3020 The @var{num} parameter is a value shown by @command{flash banks}.
3021 @end deffn
3022
3023 @deffn Command {flash erase_address} address length
3024 Erase sectors starting at @var{address} for @var{length} bytes.
3025 The flash bank to use is inferred from the @var{address}, and
3026 the specified length must stay within that bank.
3027 As a special case, when @var{length} is zero and @var{address} is
3028 the start of the bank, the whole flash is erased.
3029 @end deffn
3030
3031 @deffn Command {flash fillw} address word length
3032 @deffnx Command {flash fillh} address halfword length
3033 @deffnx Command {flash fillb} address byte length
3034 Fills flash memory with the specified @var{word} (32 bits),
3035 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
3036 starting at @var{address} and continuing
3037 for @var{length} units (word/halfword/byte).
3038 No erasure is done before writing; when needed, that must be done
3039 before issuing this command.
3040 Writes are done in blocks of up to 1024 bytes, and each write is
3041 verified by reading back the data and comparing it to what was written.
3042 The flash bank to use is inferred from the @var{address} of
3043 each block, and the specified length must stay within that bank.
3044 @end deffn
3045 @comment no current checks for errors if fill blocks touch multiple banks!
3046
3047 @anchor{flash write_bank}
3048 @deffn Command {flash write_bank} num filename offset
3049 Write the binary @file{filename} to flash bank @var{num},
3050 starting at @var{offset} bytes from the beginning of the bank.
3051 The @var{num} parameter is a value shown by @command{flash banks}.
3052 @end deffn
3053
3054 @anchor{flash write_image}
3055 @deffn Command {flash write_image} [erase] filename [offset] [type]
3056 Write the image @file{filename} to the current target's flash bank(s).
3057 A relocation @var{offset} may be specified, in which case it is added
3058 to the base address for each section in the image.
3059 The file [@var{type}] can be specified
3060 explicitly as @option{bin} (binary), @option{ihex} (Intel hex),
3061 @option{elf} (ELF file), @option{s19} (Motorola s19).
3062 @option{mem}, or @option{builder}.
3063 The relevant flash sectors will be erased prior to programming
3064 if the @option{erase} parameter is given.
3065 The flash bank to use is inferred from the @var{address} of
3066 each image segment.
3067 @end deffn
3068
3069 @section Other Flash commands
3070 @cindex flash protection
3071
3072 @deffn Command {flash erase_check} num
3073 Check erase state of sectors in flash bank @var{num},
3074 and display that status.
3075 The @var{num} parameter is a value shown by @command{flash banks}.
3076 This is the only operation that
3077 updates the erase state information displayed by @option{flash info}. That means you have
3078 to issue an @command{flash erase_check} command after erasing or programming the device
3079 to get updated information.
3080 (Code execution may have invalidated any state records kept by OpenOCD.)
3081 @end deffn
3082
3083 @deffn Command {flash info} num
3084 Print info about flash bank @var{num}
3085 The @var{num} parameter is a value shown by @command{flash banks}.
3086 The information includes per-sector protect status.
3087 @end deffn
3088
3089 @anchor{flash protect}
3090 @deffn Command {flash protect} num first last (on|off)
3091 Enable (@var{on}) or disable (@var{off}) protection of flash sectors
3092 @var{first} to @var{last} of flash bank @var{num}.
3093 The @var{num} parameter is a value shown by @command{flash banks}.
3094 @end deffn
3095
3096 @deffn Command {flash protect_check} num
3097 Check protection state of sectors in flash bank @var{num}.
3098 The @var{num} parameter is a value shown by @command{flash banks}.
3099 @comment @option{flash erase_sector} using the same syntax.
3100 @end deffn
3101
3102 @anchor{Flash Driver List}
3103 @section Flash Drivers, Options, and Commands
3104 As noted above, the @command{flash bank} command requires a driver name,
3105 and allows driver-specific options and behaviors.
3106 Some drivers also activate driver-specific commands.
3107
3108 @subsection External Flash
3109
3110 @deffn {Flash Driver} cfi
3111 @cindex Common Flash Interface
3112 @cindex CFI
3113 The ``Common Flash Interface'' (CFI) is the main standard for
3114 external NOR flash chips, each of which connects to a
3115 specific external chip select on the CPU.
3116 Frequently the first such chip is used to boot the system.
3117 Your board's @code{reset-init} handler might need to
3118 configure additional chip selects using other commands (like: @command{mww} to
3119 configure a bus and its timings) , or
3120 perhaps configure a GPIO pin that controls the ``write protect'' pin
3121 on the flash chip.
3122 The CFI driver can use a target-specific working area to significantly
3123 speed up operation.
3124
3125 The CFI driver can accept the following optional parameters, in any order:
3126
3127 @itemize
3128 @item @var{jedec_probe} ... is used to detect certain non-CFI flash ROMs,
3129 like AM29LV010 and similar types.
3130 @item @var{x16_as_x8} ... when a 16-bit flash is hooked up to an 8-bit bus.
3131 @end itemize
3132
3133 To configure two adjacent banks of 16 MBytes each, both sixteen bits (two bytes)
3134 wide on a sixteen bit bus:
3135
3136 @example
3137 flash bank cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
3138 flash bank cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
3139 @end example
3140 @c "cfi part_id" disabled
3141 @end deffn
3142
3143 @subsection Internal Flash (Microcontrollers)
3144
3145 @deffn {Flash Driver} aduc702x
3146 The ADUC702x analog microcontrollers from Analog Devices
3147 include internal flash and use ARM7TDMI cores.
3148 The aduc702x flash driver works with models ADUC7019 through ADUC7028.
3149 The setup command only requires the @var{target} argument
3150 since all devices in this family have the same memory layout.
3151
3152 @example
3153 flash bank aduc702x 0 0 0 0 $_TARGETNAME
3154 @end example
3155 @end deffn
3156
3157 @deffn {Flash Driver} at91sam3
3158 @cindex at91sam3
3159 All members of the AT91SAM3 microcontroller family from
3160 Atmel include internal flash and use ARM's Cortex-M3 core. The driver
3161 currently (6/22/09) recognizes the AT91SAM3U[1/2/4][C/E] chips. Note
3162 that the driver was orginaly developed and tested using the
3163 AT91SAM3U4E, using a SAM3U-EK eval board. Support for other chips in
3164 the family was cribbed from the data sheet. @emph{Note to future
3165 readers/updaters: Please remove this worrysome comment after other
3166 chips are confirmed.}
3167
3168 The AT91SAM3U4[E/C] (256K) chips have two flash banks; most other chips
3169 have one flash bank. In all cases the flash banks are at
3170 the following fixed locations:
3171
3172 @example
3173 # Flash bank 0 - all chips
3174 flash bank at91sam3 0x00080000 0 1 1 $_TARGETNAME
3175 # Flash bank 1 - only 256K chips
3176 flash bank at91sam3 0x00100000 0 1 1 $_TARGETNAME
3177 @end example
3178
3179 Internally, the AT91SAM3 flash memory is organized as follows.
3180 Unlike the AT91SAM7 chips, these are not used as parameters
3181 to the @command{flash bank} command:
3182
3183 @itemize
3184 @item @emph{N-Banks:} 256K chips have 2 banks, others have 1 bank.
3185 @item @emph{Bank Size:} 128K/64K Per flash bank
3186 @item @emph{Sectors:} 16 or 8 per bank
3187 @item @emph{SectorSize:} 8K Per Sector
3188 @item @emph{PageSize:} 256 bytes per page. Note that OpenOCD operates on 'sector' sizes, not page sizes.
3189 @end itemize
3190
3191 The AT91SAM3 driver adds some additional commands:
3192
3193 @deffn Command {at91sam3 gpnvm}
3194 @deffnx Command {at91sam3 gpnvm clear} number
3195 @deffnx Command {at91sam3 gpnvm set} number
3196 @deffnx Command {at91sam3 gpnvm show} [@option{all}|number]
3197 With no parameters, @command{show} or @command{show all},
3198 shows the status of all GPNVM bits.
3199 With @command{show} @var{number}, displays that bit.
3200
3201 With @command{set} @var{number} or @command{clear} @var{number},
3202 modifies that GPNVM bit.
3203 @end deffn
3204
3205 @deffn Command {at91sam3 info}
3206 This command attempts to display information about the AT91SAM3
3207 chip. @emph{First} it read the @code{CHIPID_CIDR} [address 0x400e0740, see
3208 Section 28.2.1, page 505 of the AT91SAM3U 29/may/2009 datasheet,
3209 document id: doc6430A] and decodes the values. @emph{Second} it reads the
3210 various clock configuration registers and attempts to display how it
3211 believes the chip is configured. By default, the SLOWCLK is assumed to
3212 be 32768 Hz, see the command @command{at91sam3 slowclk}.
3213 @end deffn
3214
3215 @deffn Command {at91sam3 slowclk} [value]
3216 This command shows/sets the slow clock frequency used in the
3217 @command{at91sam3 info} command calculations above.
3218 @end deffn
3219 @end deffn
3220
3221 @deffn {Flash Driver} at91sam7
3222 All members of the AT91SAM7 microcontroller family from Atmel include
3223 internal flash and use ARM7TDMI cores. The driver automatically
3224 recognizes a number of these chips using the chip identification
3225 register, and autoconfigures itself.
3226
3227 @example
3228 flash bank at91sam7 0 0 0 0 $_TARGETNAME
3229 @end example
3230
3231 For chips which are not recognized by the controller driver, you must
3232 provide additional parameters in the following order:
3233
3234 @itemize
3235 @item @var{chip_model} ... label used with @command{flash info}
3236 @item @var{banks}
3237 @item @var{sectors_per_bank}
3238 @item @var{pages_per_sector}
3239 @item @var{pages_size}
3240 @item @var{num_nvm_bits}
3241 @item @var{freq_khz} ... required if an external clock is provided,
3242 optional (but recommended) when the oscillator frequency is known
3243 @end itemize
3244
3245 It is recommended that you provide zeroes for all of those values
3246 except the clock frequency, so that everything except that frequency
3247 will be autoconfigured.
3248 Knowing the frequency helps ensure correct timings for flash access.
3249
3250 The flash controller handles erases automatically on a page (128/256 byte)
3251 basis, so explicit erase commands are not necessary for flash programming.
3252 However, there is an ``EraseAll`` command that can erase an entire flash
3253 plane (of up to 256KB), and it will be used automatically when you issue
3254 @command{flash erase_sector} or @command{flash erase_address} commands.
3255
3256 @deffn Command {at91sam7 gpnvm} bitnum (@option{set}|@option{clear})
3257 Set or clear a ``General Purpose Non-Volatle Memory'' (GPNVM)
3258 bit for the processor. Each processor has a number of such bits,
3259 used for controlling features such as brownout detection (so they
3260 are not truly general purpose).
3261 @quotation Note
3262 This assumes that the first flash bank (number 0) is associated with
3263 the appropriate at91sam7 target.
3264 @end quotation
3265 @end deffn
3266 @end deffn
3267
3268 @deffn {Flash Driver} avr
3269 The AVR 8-bit microcontrollers from Atmel integrate flash memory.
3270 @emph{The current implementation is incomplete.}
3271 @comment - defines mass_erase ... pointless given flash_erase_address
3272 @end deffn
3273
3274 @deffn {Flash Driver} ecosflash
3275 @emph{No idea what this is...}
3276 The @var{ecosflash} driver defines one mandatory parameter,
3277 the name of a modules of target code which is downloaded
3278 and executed.
3279 @end deffn
3280
3281 @deffn {Flash Driver} lpc2000
3282 Most members of the LPC1700 and LPC2000 microcontroller families from NXP
3283 include internal flash and use Cortex-M3 (LPC1700) or ARM7TDMI (LPC2000) cores.
3284 The @var{lpc2000} driver defines two mandatory and one optional parameters,
3285 which must appear in the following order:
3286
3287 @itemize
3288 @item @var{variant} ... required, may be
3289 @var{lpc2000_v1} (older LPC21xx and LPC22xx)
3290 @var{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx)
3291 or @var{lpc1700} (LPC175x and LPC176x)
3292 @item @var{clock_kHz} ... the frequency, in kiloHertz,
3293 at which the core is running
3294 @item @var{calc_checksum} ... optional (but you probably want to provide this!),
3295 telling the driver to calculate a valid checksum for the exception vector table.
3296 @end itemize
3297
3298 LPC flashes don't require the chip and bus width to be specified.
3299
3300 @example
3301 flash bank lpc2000 0x0 0x7d000 0 0 $_TARGETNAME \
3302 lpc2000_v2 14765 calc_checksum
3303 @end example
3304
3305 @deffn {Command} {lpc2000 part_id} bank
3306 Displays the four byte part identifier associated with
3307 the specified flash @var{bank}.
3308 @end deffn
3309 @end deffn
3310
3311 @deffn {Flash Driver} lpc288x
3312 The LPC2888 microcontroller from NXP needs slightly different flash
3313 support from its lpc2000 siblings.
3314 The @var{lpc288x} driver defines one mandatory parameter,
3315 the programming clock rate in Hz.
3316 LPC flashes don't require the chip and bus width to be specified.
3317
3318 @example
3319 flash bank lpc288x 0 0 0 0 $_TARGETNAME 12000000
3320 @end example
3321 @end deffn
3322
3323 @deffn {Flash Driver} ocl
3324 @emph{No idea what this is, other than using some arm7/arm9 core.}
3325
3326 @example
3327 flash bank ocl 0 0 0 0 $_TARGETNAME
3328 @end example
3329 @end deffn
3330
3331 @deffn {Flash Driver} pic32mx
3332 The PIC32MX microcontrollers are based on the MIPS 4K cores,
3333 and integrate flash memory.
3334 @emph{The current implementation is incomplete.}
3335
3336 @example
3337 flash bank pix32mx 0 0 0 0 $_TARGETNAME
3338 @end example
3339
3340 @comment numerous *disabled* commands are defined:
3341 @comment - chip_erase ... pointless given flash_erase_address
3342 @comment - lock, unlock ... pointless given protect on/off (yes?)
3343 @comment - pgm_word ... shouldn't bank be deduced from address??
3344 Some pic32mx-specific commands are defined:
3345 @deffn Command {pic32mx pgm_word} address value bank
3346 Programs the specified 32-bit @var{value} at the given @var{address}
3347 in the specified chip @var{bank}.
3348 @end deffn
3349 @end deffn
3350
3351 @deffn {Flash Driver} stellaris
3352 All members of the Stellaris LM3Sxxx microcontroller family from
3353 Texas Instruments
3354 include internal flash and use ARM Cortex M3 cores.
3355 The driver automatically recognizes a number of these chips using
3356 the chip identification register, and autoconfigures itself.
3357 @footnote{Currently there is a @command{stellaris mass_erase} command.
3358 That seems pointless since the same effect can be had using the
3359 standard @command{flash erase_address} command.}
3360
3361 @example
3362 flash bank stellaris 0 0 0 0 $_TARGETNAME
3363 @end example
3364 @end deffn
3365
3366 @deffn {Flash Driver} stm32x
3367 All members of the STM32 microcontroller family from ST Microelectronics
3368 include internal flash and use ARM Cortex M3 cores.
3369 The driver automatically recognizes a number of these chips using
3370 the chip identification register, and autoconfigures itself.
3371
3372 @example
3373 flash bank stm32x 0 0 0 0 $_TARGETNAME
3374 @end example
3375
3376 Some stm32x-specific commands
3377 @footnote{Currently there is a @command{stm32x mass_erase} command.
3378 That seems pointless since the same effect can be had using the
3379 standard @command{flash erase_address} command.}
3380 are defined:
3381
3382 @deffn Command {stm32x lock} num
3383 Locks the entire stm32 device.
3384 The @var{num} parameter is a value shown by @command{flash banks}.
3385 @end deffn
3386
3387 @deffn Command {stm32x unlock} num
3388 Unlocks the entire stm32 device.
3389 The @var{num} parameter is a value shown by @command{flash banks}.
3390 @end deffn
3391
3392 @deffn Command {stm32x options_read} num
3393 Read and display the stm32 option bytes written by
3394 the @command{stm32x options_write} command.
3395 The @var{num} parameter is a value shown by @command{flash banks}.
3396 @end deffn
3397
3398 @deffn Command {stm32x options_write} num (@option{SWWDG}|@option{HWWDG}) (@option{RSTSTNDBY}|@option{NORSTSTNDBY}) (@option{RSTSTOP}|@option{NORSTSTOP})
3399 Writes the stm32 option byte with the specified values.
3400 The @var{num} parameter is a value shown by @command{flash banks}.
3401 @end deffn
3402 @end deffn
3403
3404 @deffn {Flash Driver} str7x
3405 All members of the STR7 microcontroller family from ST Microelectronics
3406 include internal flash and use ARM7TDMI cores.
3407 The @var{str7x} driver defines one mandatory parameter, @var{variant},
3408 which is either @code{STR71x}, @code{STR73x} or @code{STR75x}.
3409
3410 @example
3411 flash bank str7x 0x40000000 0x00040000 0 0 $_TARGETNAME STR71x
3412 @end example
3413
3414 @deffn Command {str7x disable_jtag} bank
3415 Activate the Debug/Readout protection mechanism
3416 for the specified flash bank.
3417 @end deffn
3418 @end deffn
3419
3420 @deffn {Flash Driver} str9x
3421 Most members of the STR9 microcontroller family from ST Microelectronics
3422 include internal flash and use ARM966E cores.
3423 The str9 needs the flash controller to be configured using
3424 the @command{str9x flash_config} command prior to Flash programming.
3425
3426 @example
3427 flash bank str9x 0x40000000 0x00040000 0 0 $_TARGETNAME
3428 str9x flash_config 0 4 2 0 0x80000
3429 @end example
3430
3431 @deffn Command {str9x flash_config} num bbsr nbbsr bbadr nbbadr
3432 Configures the str9 flash controller.
3433 The @var{num} parameter is a value shown by @command{flash banks}.
3434
3435 @itemize @bullet
3436 @item @var{bbsr} - Boot Bank Size register
3437 @item @var{nbbsr} - Non Boot Bank Size register
3438 @item @var{bbadr} - Boot Bank Start Address register
3439 @item @var{nbbadr} - Boot Bank Start Address register
3440 @end itemize
3441 @end deffn
3442
3443 @end deffn
3444
3445 @deffn {Flash Driver} tms470
3446 Most members of the TMS470 microcontroller family from Texas Instruments
3447 include internal flash and use ARM7TDMI cores.
3448 This driver doesn't require the chip and bus width to be specified.
3449
3450 Some tms470-specific commands are defined:
3451
3452 @deffn Command {tms470 flash_keyset} key0 key1 key2 key3
3453 Saves programming keys in a register, to enable flash erase and write commands.
3454 @end deffn
3455
3456 @deffn Command {tms470 osc_mhz} clock_mhz
3457 Reports the clock speed, which is used to calculate timings.
3458 @end deffn
3459
3460 @deffn Command {tms470 plldis} (0|1)
3461 Disables (@var{1}) or enables (@var{0}) use of the PLL to speed up
3462 the flash clock.
3463 @end deffn
3464 @end deffn
3465
3466 @subsection str9xpec driver
3467 @cindex str9xpec
3468
3469 Here is some background info to help
3470 you better understand how this driver works. OpenOCD has two flash drivers for
3471 the str9:
3472 @enumerate
3473 @item
3474 Standard driver @option{str9x} programmed via the str9 core. Normally used for
3475 flash programming as it is faster than the @option{str9xpec} driver.
3476 @item
3477 Direct programming @option{str9xpec} using the flash controller. This is an
3478 ISC compilant (IEEE 1532) tap connected in series with the str9 core. The str9
3479 core does not need to be running to program using this flash driver. Typical use
3480 for this driver is locking/unlocking the target and programming the option bytes.
3481 @end enumerate
3482
3483 Before we run any commands using the @option{str9xpec} driver we must first disable
3484 the str9 core. This example assumes the @option{str9xpec} driver has been
3485 configured for flash bank 0.
3486 @example
3487 # assert srst, we do not want core running
3488 # while accessing str9xpec flash driver
3489 jtag_reset 0 1
3490 # turn off target polling
3491 poll off
3492 # disable str9 core
3493 str9xpec enable_turbo 0
3494 # read option bytes
3495 str9xpec options_read 0
3496 # re-enable str9 core
3497 str9xpec disable_turbo 0
3498 poll on
3499 reset halt
3500 @end example
3501 The above example will read the str9 option bytes.
3502 When performing a unlock remember that you will not be able to halt the str9 - it
3503 has been locked. Halting the core is not required for the @option{str9xpec} driver
3504 as mentioned above, just issue the commands above manually or from a telnet prompt.
3505
3506 @deffn {Flash Driver} str9xpec
3507 Only use this driver for locking/unlocking the device or configuring the option bytes.
3508 Use the standard str9 driver for programming.
3509 Before using the flash commands the turbo mode must be enabled using the
3510 @command{str9xpec enable_turbo} command.
3511
3512 Several str9xpec-specific commands are defined:
3513
3514 @deffn Command {str9xpec disable_turbo} num
3515 Restore the str9 into JTAG chain.
3516 @end deffn
3517
3518 @deffn Command {str9xpec enable_turbo} num
3519 Enable turbo mode, will simply remove the str9 from the chain and talk
3520 directly to the embedded flash controller.
3521 @end deffn
3522
3523 @deffn Command {str9xpec lock} num
3524 Lock str9 device. The str9 will only respond to an unlock command that will
3525 erase the device.
3526 @end deffn
3527
3528 @deffn Command {str9xpec part_id} num
3529 Prints the part identifier for bank @var{num}.
3530 @end deffn
3531
3532 @deffn Command {str9xpec options_cmap} num (@option{bank0}|@option{bank1})
3533 Configure str9 boot bank.
3534 @end deffn
3535
3536 @deffn Command {str9xpec options_lvdsel} num (@option{vdd}|@option{vdd_vddq})
3537 Configure str9 lvd source.
3538 @end deffn
3539
3540 @deffn Command {str9xpec options_lvdthd} num (@option{2.4v}|@option{2.7v})
3541 Configure str9 lvd threshold.
3542 @end deffn
3543
3544 @deffn Command {str9xpec options_lvdwarn} bank (@option{vdd}|@option{vdd_vddq})
3545 Configure str9 lvd reset warning source.
3546 @end deffn
3547
3548 @deffn Command {str9xpec options_read} num
3549 Read str9 option bytes.
3550 @end deffn
3551
3552 @deffn Command {str9xpec options_write} num
3553 Write str9 option bytes.
3554 @end deffn
3555
3556 @deffn Command {str9xpec unlock} num
3557 unlock str9 device.
3558 @end deffn
3559
3560 @end deffn
3561
3562
3563 @section mFlash
3564
3565 @subsection mFlash Configuration
3566 @cindex mFlash Configuration
3567
3568 @deffn {Config Command} {mflash bank} soc base RST_pin target
3569 Configures a mflash for @var{soc} host bank at
3570 address @var{base}.
3571 The pin number format depends on the host GPIO naming convention.
3572 Currently, the mflash driver supports s3c2440 and pxa270.
3573
3574 Example for s3c2440 mflash where @var{RST pin} is GPIO B1:
3575
3576 @example
3577 mflash bank s3c2440 0x10000000 1b 0
3578 @end example
3579
3580 Example for pxa270 mflash where @var{RST pin} is GPIO 43:
3581
3582 @example
3583 mflash bank pxa270 0x08000000 43 0
3584 @end example
3585 @end deffn
3586
3587 @subsection mFlash commands
3588 @cindex mFlash commands
3589
3590 @deffn Command {mflash config pll} frequency
3591 Configure mflash PLL.
3592 The @var{frequency} is the mflash input frequency, in Hz.
3593 Issuing this command will erase mflash's whole internal nand and write new pll.
3594 After this command, mflash needs power-on-reset for normal operation.
3595 If pll was newly configured, storage and boot(optional) info also need to be update.
3596 @end deffn
3597
3598 @deffn Command {mflash config boot}
3599 Configure bootable option.
3600 If bootable option is set, mflash offer the first 8 sectors
3601 (4kB) for boot.
3602 @end deffn
3603
3604 @deffn Command {mflash config storage}
3605 Configure storage information.
3606 For the normal storage operation, this information must be
3607 written.
3608 @end deffn
3609
3610 @deffn Command {mflash dump} num filename offset size
3611 Dump @var{size} bytes, starting at @var{offset} bytes from the
3612 beginning of the bank @var{num}, to the file named @var{filename}.
3613 @end deffn
3614
3615 @deffn Command {mflash probe}
3616 Probe mflash.
3617 @end deffn
3618
3619 @deffn Command {mflash write} num filename offset
3620 Write the binary file @var{filename} to mflash bank @var{num}, starting at
3621 @var{offset} bytes from the beginning of the bank.
3622 @end deffn
3623
3624 @node NAND Flash Commands
3625 @chapter NAND Flash Commands
3626 @cindex NAND
3627
3628 Compared to NOR or SPI flash, NAND devices are inexpensive
3629 and high density. Today's NAND chips, and multi-chip modules,
3630 commonly hold multiple GigaBytes of data.
3631
3632 NAND chips consist of a number of ``erase blocks'' of a given
3633 size (such as 128 KBytes), each of which is divided into a
3634 number of pages (of perhaps 512 or 2048 bytes each). Each
3635 page of a NAND flash has an ``out of band'' (OOB) area to hold
3636 Error Correcting Code (ECC) and other metadata, usually 16 bytes
3637 of OOB for every 512 bytes of page data.
3638
3639 One key characteristic of NAND flash is that its error rate
3640 is higher than that of NOR flash. In normal operation, that
3641 ECC is used to correct and detect errors. However, NAND
3642 blocks can also wear out and become unusable; those blocks
3643 are then marked "bad". NAND chips are even shipped from the
3644 manufacturer with a few bad blocks. The highest density chips
3645 use a technology (MLC) that wears out more quickly, so ECC
3646 support is increasingly important as a way to detect blocks
3647 that have begun to fail, and help to preserve data integrity
3648 with techniques such as wear leveling.
3649
3650 Software is used to manage the ECC. Some controllers don't
3651 support ECC directly; in those cases, software ECC is used.
3652 Other controllers speed up the ECC calculations with hardware.
3653 Single-bit error correction hardware is routine. Controllers
3654 geared for newer MLC chips may correct 4 or more errors for
3655 every 512 bytes of data.
3656
3657 You will need to make sure that any data you write using
3658 OpenOCD includes the apppropriate kind of ECC. For example,
3659 that may mean passing the @code{oob_softecc} flag when
3660 writing NAND data, or ensuring that the correct hardware
3661 ECC mode is used.
3662
3663 The basic steps for using NAND devices include:
3664 @enumerate
3665 @item Declare via the command @command{nand device}
3666 @* Do this in a board-specific configuration file,
3667 passing parameters as needed by the controller.
3668 @item Configure each device using @command{nand probe}.
3669 @* Do this only after the associated target is set up,
3670 such as in its reset-init script or in procures defined
3671 to access that device.
3672 @item Operate on the flash via @command{nand subcommand}
3673 @* Often commands to manipulate the flash are typed by a human, or run
3674 via a script in some automated way. Common task include writing a
3675 boot loader, operating system, or other data needed to initialize or
3676 de-brick a board.
3677 @end enumerate
3678
3679 @b{NOTE:} At the time this text was written, the largest NAND
3680 flash fully supported by OpenOCD is 2 GiBytes (16 GiBits).
3681 This is because the variables used to hold offsets and lengths
3682 are only 32 bits wide.
3683 (Larger chips may work in some cases, unless an offset or length
3684 is larger than 0xffffffff, the largest 32-bit unsigned integer.)
3685 Some larger devices will work, since they are actually multi-chip
3686 modules with two smaller chips and individual chipselect lines.
3687
3688 @anchor{NAND Configuration}
3689 @section NAND Configuration Commands
3690 @cindex NAND configuration
3691
3692 NAND chips must be declared in configuration scripts,
3693 plus some additional configuration that's done after
3694 OpenOCD has initialized.
3695
3696 @deffn {Config Command} {nand device} controller target [configparams...]
3697 Declares a NAND device, which can be read and written to
3698 after it has been configured through @command{nand probe}.
3699 In OpenOCD, devices are single chips; this is unlike some
3700 operating systems, which may manage multiple chips as if
3701 they were a single (larger) device.
3702 In some cases, configuring a device will activate extra
3703 commands; see the controller-specific documentation.
3704
3705 @b{NOTE:} This command is not available after OpenOCD
3706 initialization has completed. Use it in board specific
3707 configuration files, not interactively.
3708
3709 @itemize @bullet
3710 @item @var{controller} ... identifies the controller driver
3711 associated with the NAND device being declared.
3712 @xref{NAND Driver List}.
3713 @item @var{target} ... names the target used when issuing
3714 commands to the NAND controller.
3715 @comment Actually, it's currently a controller-specific parameter...
3716 @item @var{configparams} ... controllers may support, or require,
3717 additional parameters. See the controller-specific documentation
3718 for more information.
3719 @end itemize
3720 @end deffn
3721
3722 @deffn Command {nand list}
3723 Prints a one-line summary of each device declared
3724 using @command{nand device}, numbered from zero.
3725 Note that un-probed devices show no details.
3726 @end deffn
3727
3728 @deffn Command {nand probe} num
3729 Probes the specified device to determine key characteristics
3730 like its page and block sizes, and how many blocks it has.
3731 The @var{num} parameter is the value shown by @command{nand list}.
3732 You must (successfully) probe a device before you can use
3733 it with most other NAND commands.
3734 @end deffn
3735
3736 @section Erasing, Reading, Writing to NAND Flash
3737
3738 @deffn Command {nand dump} num filename offset length [oob_option]
3739 @cindex NAND reading
3740 Reads binary data from the NAND device and writes it to the file,
3741 starting at the specified offset.
3742 The @var{num} parameter is the value shown by @command{nand list}.
3743
3744 Use a complete path name for @var{filename}, so you don't depend
3745 on the directory used to start the OpenOCD server.
3746
3747 The @var{offset} and @var{length} must be exact multiples of the
3748 device's page size. They describe a data region; the OOB data
3749 associated with each such page may also be accessed.
3750
3751 @b{NOTE:} At the time this text was written, no error correction
3752 was done on the data that's read, unless raw access was disabled
3753 and the underlying NAND controller driver had a @code{read_page}
3754 method which handled that error correction.
3755
3756 By default, only page data is saved to the specified file.
3757 Use an @var{oob_option} parameter to save OOB data:
3758 @itemize @bullet
3759 @item no oob_* parameter
3760 @*Output file holds only page data; OOB is discarded.
3761 @item @code{oob_raw}
3762 @*Output file interleaves page data and OOB data;
3763 the file will be longer than "length" by the size of the
3764 spare areas associated with each data page.
3765 Note that this kind of "raw" access is different from
3766 what's implied by @command{nand raw_access}, which just
3767 controls whether a hardware-aware access method is used.
3768 @item @code{oob_only}
3769 @*Output file has only raw OOB data, and will
3770 be smaller than "length" since it will contain only the
3771 spare areas associated with each data page.
3772 @end itemize
3773 @end deffn
3774
3775 @deffn Command {nand erase} num offset length
3776 @cindex NAND erasing
3777 @cindex NAND programming
3778 Erases blocks on the specified NAND device, starting at the
3779 specified @var{offset} and continuing for @var{length} bytes.
3780 Both of those values must be exact multiples of the device's
3781 block size, and the region they specify must fit entirely in the chip.
3782 The @var{num} parameter is the value shown by @command{nand list}.
3783
3784 @b{NOTE:} This command will try to erase bad blocks, when told
3785 to do so, which will probably invalidate the manufacturer's bad
3786 block marker.
3787 For the remainder of the current server session, @command{nand info}
3788 will still report that the block ``is'' bad.
3789 @end deffn
3790
3791 @deffn Command {nand write} num filename offset [option...]
3792 @cindex NAND writing
3793 @cindex NAND programming
3794 Writes binary data from the file into the specified NAND device,
3795 starting at the specified offset. Those pages should already
3796 have been erased; you can't change zero bits to one bits.
3797 The @var{num} parameter is the value shown by @command{nand list}.
3798
3799 Use a complete path name for @var{filename}, so you don't depend
3800 on the directory used to start the OpenOCD server.
3801
3802 The @var{offset} must be an exact multiple of the device's page size.
3803 All data in the file will be written, assuming it doesn't run
3804 past the end of the device.
3805 Only full pages are written, and any extra space in the last
3806 page will be filled with 0xff bytes. (That includes OOB data,
3807 if that's being written.)
3808
3809 @b{NOTE:} At the time this text was written, bad blocks are
3810 ignored. That is, this routine will not skip bad blocks,
3811 but will instead try to write them. This can cause problems.
3812
3813 Provide at most one @var{option} parameter. With some
3814 NAND drivers, the meanings of these parameters may change
3815 if @command{nand raw_access} was used to disable hardware ECC.
3816 @itemize @bullet
3817 @item no oob_* parameter
3818 @*File has only page data, which is written.
3819 If raw acccess is in use, the OOB area will not be written.
3820 Otherwise, if the underlying NAND controller driver has
3821 a @code{write_page} routine, that routine may write the OOB
3822 with hardware-computed ECC data.
3823 @item @code{oob_only}
3824 @*File has only raw OOB data, which is written to the OOB area.
3825 Each page's data area stays untouched. @i{This can be a dangerous
3826 option}, since it can invalidate the ECC data.
3827 You may need to force raw access to use this mode.
3828 @item @code{oob_raw}
3829 @*File interleaves data and OOB data, both of which are written
3830 If raw access is enabled, the data is written first, then the
3831 un-altered OOB.
3832 Otherwise, if the underlying NAND controller driver has
3833 a @code{write_page} routine, that routine may modify the OOB
3834 before it's written, to include hardware-computed ECC data.
3835 @item @code{oob_softecc}
3836 @*File has only page data, which is written.
3837 The OOB area is filled with 0xff, except for a standard 1-bit
3838 software ECC code stored in conventional locations.
3839 You might need to force raw access to use this mode, to prevent
3840 the underlying driver from applying hardware ECC.
3841 @item @code{oob_softecc_kw}
3842 @*File has only page data, which is written.
3843 The OOB area is filled with 0xff, except for a 4-bit software ECC
3844 specific to the boot ROM in Marvell Kirkwood SoCs.
3845 You might need to force raw access to use this mode, to prevent
3846 the underlying driver from applying hardware ECC.
3847 @end itemize
3848 @end deffn
3849
3850 @section Other NAND commands
3851 @cindex NAND other commands
3852
3853 @deffn Command {nand check_bad_blocks} [offset length]
3854 Checks for manufacturer bad block markers on the specified NAND
3855 device. If no parameters are provided, checks the whole
3856 device; otherwise, starts at the specified @var{offset} and
3857 continues for @var{length} bytes.
3858 Both of those values must be exact multiples of the device's
3859 block size, and the region they specify must fit entirely in the chip.
3860 The @var{num} parameter is the value shown by @command{nand list}.
3861
3862 @b{NOTE:} Before using this command you should force raw access
3863 with @command{nand raw_access enable} to ensure that the underlying
3864 driver will not try to apply hardware ECC.
3865 @end deffn
3866
3867 @deffn Command {nand info} num
3868 The @var{num} parameter is the value shown by @command{nand list}.
3869 This prints the one-line summary from "nand list", plus for
3870 devices which have been probed this also prints any known
3871 status for each block.
3872 @end deffn
3873
3874 @deffn Command {nand raw_access} num (@option{enable}|@option{disable})
3875 Sets or clears an flag affecting how page I/O is done.
3876 The @var{num} parameter is the value shown by @command{nand list}.
3877
3878 This flag is cleared (disabled) by default, but changing that
3879 value won't affect all NAND devices. The key factor is whether
3880 the underlying driver provides @code{read_page} or @code{write_page}
3881 methods. If it doesn't provide those methods, the setting of
3882 this flag is irrelevant; all access is effectively ``raw''.
3883
3884 When those methods exist, they are normally used when reading
3885 data (@command{nand dump} or reading bad block markers) or
3886 writing it (@command{nand write}). However, enabling
3887 raw access (setting the flag) prevents use of those methods,
3888 bypassing hardware ECC logic.
3889 @i{This can be a dangerous option}, since writing blocks
3890 with the wrong ECC data can cause them to be marked as bad.
3891 @end deffn
3892
3893 @anchor{NAND Driver List}
3894 @section NAND Drivers, Options, and Commands
3895 As noted above, the @command{nand device} command allows
3896 driver-specific options and behaviors.
3897 Some controllers also activate controller-specific commands.
3898
3899 @deffn {NAND Driver} davinci
3900 This driver handles the NAND controllers found on DaVinci family
3901 chips from Texas Instruments.
3902 It takes three extra parameters:
3903 address of the NAND chip;
3904 hardware ECC mode to use (hwecc1, hwecc4, hwecc4_infix);
3905 address of the AEMIF controller on this processor.
3906 @example
3907 nand device davinci dm355.arm 0x02000000 hwecc4 0x01e10000
3908 @end example
3909 All DaVinci processors support the single-bit ECC hardware,
3910 and newer ones also support the four-bit ECC hardware.
3911 The @code{write_page} and @code{read_page} methods are used
3912 to implement those ECC modes, unless they are disabled using
3913 the @command{nand raw_access} command.
3914 @end deffn
3915
3916 @deffn {NAND Driver} lpc3180
3917 These controllers require an extra @command{nand device}
3918 parameter: the clock rate used by the controller.
3919 @deffn Command {lpc3180 select} num [mlc|slc]
3920 Configures use of the MLC or SLC controller mode.
3921 MLC implies use of hardware ECC.
3922 The @var{num} parameter is the value shown by @command{nand list}.
3923 @end deffn
3924
3925 At this writing, this driver includes @code{write_page}
3926 and @code{read_page} methods. Using @command{nand raw_access}
3927 to disable those methods will prevent use of hardware ECC
3928 in the MLC controller mode, but won't change SLC behavior.
3929 @end deffn
3930 @comment current lpc3180 code won't issue 5-byte address cycles
3931
3932 @deffn {NAND Driver} orion
3933 These controllers require an extra @command{nand device}
3934 parameter: the address of the controller.
3935 @example
3936 nand device orion 0xd8000000
3937 @end example
3938 These controllers don't define any specialized commands.
3939 At this writing, their drivers don't include @code{write_page}
3940 or @code{read_page} methods, so @command{nand raw_access} won't
3941 change any behavior.
3942 @end deffn
3943
3944 @deffn {NAND Driver} s3c2410
3945 @deffnx {NAND Driver} s3c2412
3946 @deffnx {NAND Driver} s3c2440
3947 @deffnx {NAND Driver} s3c2443
3948 These S3C24xx family controllers don't have any special
3949 @command{nand device} options, and don't define any
3950 specialized commands.
3951 At this writing, their drivers don't include @code{write_page}
3952 or @code{read_page} methods, so @command{nand raw_access} won't
3953 change any behavior.
3954 @end deffn
3955
3956 @node PLD/FPGA Commands
3957 @chapter PLD/FPGA Commands
3958 @cindex PLD
3959 @cindex FPGA
3960
3961 Programmable Logic Devices (PLDs) and the more flexible
3962 Field Programmable Gate Arrays (FPGAs) are both types of programmable hardware.
3963 OpenOCD can support programming them.
3964 Although PLDs are generally restrictive (cells are less functional, and
3965 there are no special purpose cells for memory or computational tasks),
3966 they share the same OpenOCD infrastructure.
3967 Accordingly, both are called PLDs here.
3968
3969 @section PLD/FPGA Configuration and Commands
3970
3971 As it does for JTAG TAPs, debug targets, and flash chips (both NOR and NAND),
3972 OpenOCD maintains a list of PLDs available for use in various commands.
3973 Also, each such PLD requires a driver.
3974
3975 They are referenced by the number shown by the @command{pld devices} command,
3976 and new PLDs are defined by @command{pld device driver_name}.
3977
3978 @deffn {Config Command} {pld device} driver_name tap_name [driver_options]
3979 Defines a new PLD device, supported by driver @var{driver_name},
3980 using the TAP named @var{tap_name}.
3981 The driver may make use of any @var{driver_options} to configure its
3982 behavior.
3983 @end deffn
3984
3985 @deffn {Command} {pld devices}
3986 Lists the PLDs and their numbers.
3987 @end deffn
3988
3989 @deffn {Command} {pld load} num filename
3990 Loads the file @file{filename} into the PLD identified by @var{num}.
3991 The file format must be inferred by the driver.
3992 @end deffn
3993
3994 @section PLD/FPGA Drivers, Options, and Commands
3995
3996 Drivers may support PLD-specific options to the @command{pld device}
3997 definition command, and may also define commands usable only with
3998 that particular type of PLD.
3999
4000 @deffn {FPGA Driver} virtex2
4001 Virtex-II is a family of FPGAs sold by Xilinx.
4002 It supports the IEEE 1532 standard for In-System Configuration (ISC).
4003 No driver-specific PLD definition options are used,
4004 and one driver-specific command is defined.
4005
4006 @deffn {Command} {virtex2 read_stat} num
4007 Reads and displays the Virtex-II status register (STAT)
4008 for FPGA @var{num}.
4009 @end deffn
4010 @end deffn
4011
4012 @node General Commands
4013 @chapter General Commands
4014 @cindex commands
4015
4016 The commands documented in this chapter here are common commands that
4017 you, as a human, may want to type and see the output of. Configuration type
4018 commands are documented elsewhere.
4019
4020 Intent:
4021 @itemize @bullet
4022 @item @b{Source Of Commands}
4023 @* OpenOCD commands can occur in a configuration script (discussed
4024 elsewhere) or typed manually by a human or supplied programatically,
4025 or via one of several TCP/IP Ports.
4026
4027 @item @b{From the human}
4028 @* A human should interact with the telnet interface (default port: 4444)
4029 or via GDB (default port 3333).
4030
4031 To issue commands from within a GDB session, use the @option{monitor}
4032 command, e.g. use @option{monitor poll} to issue the @option{poll}
4033 command. All output is relayed through the GDB session.
4034
4035 @item @b{Machine Interface}
4036 The Tcl interface's intent is to be a machine interface. The default Tcl
4037 port is 5555.
4038 @end itemize
4039
4040
4041 @section Daemon Commands
4042
4043 @deffn {Command} exit
4044 Exits the current telnet session.
4045 @end deffn
4046
4047 @c note EXTREMELY ANNOYING word wrap at column 75
4048 @c even when lines are e.g. 100+ columns ...
4049 @c coded in startup.tcl
4050 @deffn {Command} help [string]
4051 With no parameters, prints help text for all commands.
4052 Otherwise, prints each helptext containing @var{string}.
4053 Not every command provides helptext.
4054 @end deffn
4055
4056 @deffn Command sleep msec [@option{busy}]
4057 Wait for at least @var{msec} milliseconds before resuming.
4058 If @option{busy} is passed, busy-wait instead of sleeping.
4059 (This option is strongly discouraged.)
4060 Useful in connection with script files
4061 (@command{script} command and @command{target_name} configuration).
4062 @end deffn
4063
4064 @deffn Command shutdown
4065 Close the OpenOCD daemon, disconnecting all clients (GDB, telnet, other).
4066 @end deffn
4067
4068 @anchor{debug_level}
4069 @deffn Command debug_level [n]
4070 @cindex message level
4071 Display debug level.
4072 If @var{n} (from 0..3) is provided, then set it to that level.
4073 This affects the kind of messages sent to the server log.
4074 Level 0 is error messages only;
4075 level 1 adds warnings;
4076 level 2 adds informational messages;
4077 and level 3 adds debugging messages.
4078 The default is level 2, but that can be overridden on
4079 the command line along with the location of that log
4080 file (which is normally the server's standard output).
4081 @xref{Running}.
4082 @end deffn
4083
4084 @deffn Command fast (@option{enable}|@option{disable})
4085 Default disabled.
4086 Set default behaviour of OpenOCD to be "fast and dangerous".
4087
4088 At this writing, this only affects the defaults for two ARM7/ARM9 parameters:
4089 fast memory access, and DCC downloads. Those parameters may still be
4090 individually overridden.
4091
4092 The target specific "dangerous" optimisation tweaking options may come and go
4093 as more robust and user friendly ways are found to ensure maximum throughput
4094 and robustness with a minimum of configuration.
4095
4096 Typically the "fast enable" is specified first on the command line:
4097
4098 @example
4099 openocd -c "fast enable" -c "interface dummy" -f target/str710.cfg
4100 @end example
4101 @end deffn
4102
4103 @deffn Command echo message
4104 Logs a message at "user" priority.
4105 Output @var{message} to stdout.
4106 @example
4107 echo "Downloading kernel -- please wait"
4108 @end example
4109 @end deffn
4110
4111 @deffn Command log_output [filename]
4112 Redirect logging to @var{filename};
4113 the initial log output channel is stderr.
4114 @end deffn
4115
4116 @anchor{Target State handling}
4117 @section Target State handling
4118 @cindex reset
4119 @cindex halt
4120 @cindex target initialization
4121
4122 In this section ``target'' refers to a CPU configured as
4123 shown earlier (@pxref{CPU Configuration}).
4124 These commands, like many, implicitly refer to
4125 a current target which is used to perform the
4126 various operations. The current target may be changed
4127 by using @command{targets} command with the name of the
4128 target which should become current.
4129
4130 @deffn Command reg [(number|name) [value]]
4131 Access a single register by @var{number} or by its @var{name}.
4132
4133 @emph{With no arguments}:
4134 list all available registers for the current target,
4135 showing number, name, size, value, and cache status.
4136
4137 @emph{With number/name}: display that register's value.
4138
4139 @emph{With both number/name and value}: set register's value.
4140
4141 Cores may have surprisingly many registers in their
4142 Debug and trace infrastructure:
4143
4144 @example
4145 > reg
4146 (0) r0 (/32): 0x0000D3C2 (dirty: 1, valid: 1)
4147 (1) r1 (/32): 0xFD61F31C (dirty: 0, valid: 1)
4148 (2) r2 (/32): 0x00022551 (dirty: 0, valid: 1)
4149 ...
4150 (164) ETM_CONTEXTID_COMPARATOR_MASK (/32): \
4151 0x00000000 (dirty: 0, valid: 0)
4152 >
4153 @end example
4154 @end deffn
4155
4156 @deffn Command halt [ms]
4157 @deffnx Command wait_halt [ms]
4158 The @command{halt} command first sends a halt request to the target,
4159 which @command{wait_halt} doesn't.
4160 Otherwise these behave the same: wait up to @var{ms} milliseconds,
4161 or 5 seconds if there is no parameter, for the target to halt
4162 (and enter debug mode).
4163 Using 0 as the @var{ms} parameter prevents OpenOCD from waiting.
4164 @end deffn
4165
4166 @deffn Command resume [address]
4167 Resume the target at its current code position,
4168 or the optional @var{address} if it is provided.
4169 OpenOCD will wait 5 seconds for the target to resume.
4170 @end deffn
4171
4172 @deffn Command step [address]
4173 Single-step the target at its current code position,
4174 or the optional @var{address} if it is provided.
4175 @end deffn
4176
4177 @anchor{Reset Command}
4178 @deffn Command reset
4179 @deffnx Command {reset run}
4180 @deffnx Command {reset halt}
4181 @deffnx Command {reset init}
4182 Perform as hard a reset as possible, using SRST if possible.
4183 @emph{All defined targets will be reset, and target
4184 events will fire during the reset sequence.}
4185
4186 The optional parameter specifies what should
4187 happen after the reset.
4188 If there is no parameter, a @command{reset run} is executed.
4189 The other options will not work on all systems.
4190 @xref{Reset Configuration}.
4191
4192 @itemize @minus
4193 @item @b{run} Let the target run
4194 @item @b{halt} Immediately halt the target
4195 @item @b{init} Immediately halt the target, and execute the reset-init script
4196 @end itemize
4197 @end deffn
4198
4199 @deffn Command soft_reset_halt
4200 Requesting target halt and executing a soft reset. This is often used
4201 when a target cannot be reset and halted. The target, after reset is
4202 released begins to execute code. OpenOCD attempts to stop the CPU and
4203 then sets the program counter back to the reset vector. Unfortunately
4204 the code that was executed may have left the hardware in an unknown
4205 state.
4206 @end deffn
4207