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7946e3447402dda28019fb87ab0c28387a28b016
[openocd.git] / src / flash / nand.c
1 /***************************************************************************
2 * Copyright (C) 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Partially based on drivers/mtd/nand_ids.c from Linux. *
6 * Copyright (C) 2002 Thomas Gleixner <tglx@linutronix.de> *
7 * *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
12 * *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
17 * *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
23 #ifdef HAVE_CONFIG_H
24 #include "config.h"
25 #endif
26
27 #include "replacements.h"
28 #include "log.h"
29
30 #include <stdlib.h>
31 #include <string.h>
32 #include <inttypes.h>
33
34 #include <errno.h>
35
36 #include "nand.h"
37 #include "flash.h"
38 #include "time_support.h"
39 #include "fileio.h"
40 #include "image.h"
41
42 int nand_register_commands(struct command_context_s *cmd_ctx);
43 int handle_nand_list_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
44 int handle_nand_probe_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
45 int handle_nand_check_bad_blocks_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
46 int handle_nand_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
47 int handle_nand_copy_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
48 int handle_nand_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
49 int handle_nand_dump_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
50 int handle_nand_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
51
52 int handle_nand_raw_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
53
54 int nand_read_page_raw(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
55 int nand_read_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
56 int nand_read_plain(struct nand_device_s *device, u32 address, u8 *data, u32 data_size);
57
58 int nand_write_page_raw(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
59 int nand_write_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
60
61 /* NAND flash controller
62 */
63 extern nand_flash_controller_t lpc3180_nand_controller;
64 extern nand_flash_controller_t orion_nand_controller;
65 extern nand_flash_controller_t s3c2410_nand_controller;
66 extern nand_flash_controller_t s3c2412_nand_controller;
67 extern nand_flash_controller_t s3c2440_nand_controller;
68 extern nand_flash_controller_t s3c2443_nand_controller;
69
70 /* extern nand_flash_controller_t boundary_scan_nand_controller; */
71
72 nand_flash_controller_t *nand_flash_controllers[] =
73 {
74 &lpc3180_nand_controller,
75 &orion_nand_controller,
76 &s3c2410_nand_controller,
77 &s3c2412_nand_controller,
78 &s3c2440_nand_controller,
79 &s3c2443_nand_controller,
80 /* &boundary_scan_nand_controller, */
81 NULL
82 };
83
84 /* configured NAND devices and NAND Flash command handler */
85 nand_device_t *nand_devices = NULL;
86 static command_t *nand_cmd;
87
88 /* Chip ID list
89 *
90 * Name, ID code, pagesize, chipsize in MegaByte, eraseblock size,
91 * options
92 *
93 * Pagesize; 0, 256, 512
94 * 0 get this information from the extended chip ID
95 * 256 256 Byte page size
96 * 512 512 Byte page size
97 */
98 nand_info_t nand_flash_ids[] =
99 {
100 {"NAND 1MiB 5V 8-bit", 0x6e, 256, 1, 0x1000, 0},
101 {"NAND 2MiB 5V 8-bit", 0x64, 256, 2, 0x1000, 0},
102 {"NAND 4MiB 5V 8-bit", 0x6b, 512, 4, 0x2000, 0},
103 {"NAND 1MiB 3,3V 8-bit", 0xe8, 256, 1, 0x1000, 0},
104 {"NAND 1MiB 3,3V 8-bit", 0xec, 256, 1, 0x1000, 0},
105 {"NAND 2MiB 3,3V 8-bit", 0xea, 256, 2, 0x1000, 0},
106 {"NAND 4MiB 3,3V 8-bit", 0xd5, 512, 4, 0x2000, 0},
107 {"NAND 4MiB 3,3V 8-bit", 0xe3, 512, 4, 0x2000, 0},
108 {"NAND 4MiB 3,3V 8-bit", 0xe5, 512, 4, 0x2000, 0},
109 {"NAND 8MiB 3,3V 8-bit", 0xd6, 512, 8, 0x2000, 0},
110
111 {"NAND 8MiB 1,8V 8-bit", 0x39, 512, 8, 0x2000, 0},
112 {"NAND 8MiB 3,3V 8-bit", 0xe6, 512, 8, 0x2000, 0},
113 {"NAND 8MiB 1,8V 16-bit", 0x49, 512, 8, 0x2000, NAND_BUSWIDTH_16},
114 {"NAND 8MiB 3,3V 16-bit", 0x59, 512, 8, 0x2000, NAND_BUSWIDTH_16},
115
116 {"NAND 16MiB 1,8V 8-bit", 0x33, 512, 16, 0x4000, 0},
117 {"NAND 16MiB 3,3V 8-bit", 0x73, 512, 16, 0x4000, 0},
118 {"NAND 16MiB 1,8V 16-bit", 0x43, 512, 16, 0x4000, NAND_BUSWIDTH_16},
119 {"NAND 16MiB 3,3V 16-bit", 0x53, 512, 16, 0x4000, NAND_BUSWIDTH_16},
120
121 {"NAND 32MiB 1,8V 8-bit", 0x35, 512, 32, 0x4000, 0},
122 {"NAND 32MiB 3,3V 8-bit", 0x75, 512, 32, 0x4000, 0},
123 {"NAND 32MiB 1,8V 16-bit", 0x45, 512, 32, 0x4000, NAND_BUSWIDTH_16},
124 {"NAND 32MiB 3,3V 16-bit", 0x55, 512, 32, 0x4000, NAND_BUSWIDTH_16},
125
126 {"NAND 64MiB 1,8V 8-bit", 0x36, 512, 64, 0x4000, 0},
127 {"NAND 64MiB 3,3V 8-bit", 0x76, 512, 64, 0x4000, 0},
128 {"NAND 64MiB 1,8V 16-bit", 0x46, 512, 64, 0x4000, NAND_BUSWIDTH_16},
129 {"NAND 64MiB 3,3V 16-bit", 0x56, 512, 64, 0x4000, NAND_BUSWIDTH_16},
130
131 {"NAND 128MiB 1,8V 8-bit", 0x78, 512, 128, 0x4000, 0},
132 {"NAND 128MiB 1,8V 8-bit", 0x39, 512, 128, 0x4000, 0},
133 {"NAND 128MiB 3,3V 8-bit", 0x79, 512, 128, 0x4000, 0},
134 {"NAND 128MiB 1,8V 16-bit", 0x72, 512, 128, 0x4000, NAND_BUSWIDTH_16},
135 {"NAND 128MiB 1,8V 16-bit", 0x49, 512, 128, 0x4000, NAND_BUSWIDTH_16},
136 {"NAND 128MiB 3,3V 16-bit", 0x74, 512, 128, 0x4000, NAND_BUSWIDTH_16},
137 {"NAND 128MiB 3,3V 16-bit", 0x59, 512, 128, 0x4000, NAND_BUSWIDTH_16},
138
139 {"NAND 256MiB 3,3V 8-bit", 0x71, 512, 256, 0x4000, 0},
140
141 {"NAND 64MiB 1,8V 8-bit", 0xA2, 0, 64, 0, LP_OPTIONS},
142 {"NAND 64MiB 3,3V 8-bit", 0xF2, 0, 64, 0, LP_OPTIONS},
143 {"NAND 64MiB 1,8V 16-bit", 0xB2, 0, 64, 0, LP_OPTIONS16},
144 {"NAND 64MiB 3,3V 16-bit", 0xC2, 0, 64, 0, LP_OPTIONS16},
145
146 {"NAND 128MiB 1,8V 8-bit", 0xA1, 0, 128, 0, LP_OPTIONS},
147 {"NAND 128MiB 3,3V 8-bit", 0xF1, 0, 128, 0, LP_OPTIONS},
148 {"NAND 128MiB 1,8V 16-bit", 0xB1, 0, 128, 0, LP_OPTIONS16},
149 {"NAND 128MiB 3,3V 16-bit", 0xC1, 0, 128, 0, LP_OPTIONS16},
150
151 {"NAND 256MiB 1,8V 8-bit", 0xAA, 0, 256, 0, LP_OPTIONS},
152 {"NAND 256MiB 3,3V 8-bit", 0xDA, 0, 256, 0, LP_OPTIONS},
153 {"NAND 256MiB 1,8V 16-bit", 0xBA, 0, 256, 0, LP_OPTIONS16},
154 {"NAND 256MiB 3,3V 16-bit", 0xCA, 0, 256, 0, LP_OPTIONS16},
155
156 {"NAND 512MiB 1,8V 8-bit", 0xAC, 0, 512, 0, LP_OPTIONS},
157 {"NAND 512MiB 3,3V 8-bit", 0xDC, 0, 512, 0, LP_OPTIONS},
158 {"NAND 512MiB 1,8V 16-bit", 0xBC, 0, 512, 0, LP_OPTIONS16},
159 {"NAND 512MiB 3,3V 16-bit", 0xCC, 0, 512, 0, LP_OPTIONS16},
160
161 {"NAND 1GiB 1,8V 8-bit", 0xA3, 0, 1024, 0, LP_OPTIONS},
162 {"NAND 1GiB 3,3V 8-bit", 0xD3, 0, 1024, 0, LP_OPTIONS},
163 {"NAND 1GiB 1,8V 16-bit", 0xB3, 0, 1024, 0, LP_OPTIONS16},
164 {"NAND 1GiB 3,3V 16-bit", 0xC3, 0, 1024, 0, LP_OPTIONS16},
165
166 {"NAND 2GiB 1,8V 8-bit", 0xA5, 0, 2048, 0, LP_OPTIONS},
167 {"NAND 2GiB 3,3V 8-bit", 0xD5, 0, 2048, 0, LP_OPTIONS},
168 {"NAND 2GiB 1,8V 16-bit", 0xB5, 0, 2048, 0, LP_OPTIONS16},
169 {"NAND 2GiB 3,3V 16-bit", 0xC5, 0, 2048, 0, LP_OPTIONS16},
170
171 {NULL, 0,}
172 };
173
174 /* Manufacturer ID list
175 */
176 nand_manufacturer_t nand_manuf_ids[] =
177 {
178 {0x0, "unknown"},
179 {NAND_MFR_TOSHIBA, "Toshiba"},
180 {NAND_MFR_SAMSUNG, "Samsung"},
181 {NAND_MFR_FUJITSU, "Fujitsu"},
182 {NAND_MFR_NATIONAL, "National"},
183 {NAND_MFR_RENESAS, "Renesas"},
184 {NAND_MFR_STMICRO, "ST Micro"},
185 {NAND_MFR_HYNIX, "Hynix"},
186 {0x0, NULL},
187 };
188
189 /* nand device <nand_controller> [controller options]
190 */
191 int handle_nand_device_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
192 {
193 int i;
194 int retval;
195
196 if (argc < 1)
197 {
198 LOG_WARNING("incomplete flash device nand configuration");
199 return ERROR_FLASH_BANK_INVALID;
200 }
201
202 for (i = 0; nand_flash_controllers[i]; i++)
203 {
204 nand_device_t *p, *c;
205
206 if (strcmp(args[0], nand_flash_controllers[i]->name) == 0)
207 {
208 /* register flash specific commands */
209 if ((retval = nand_flash_controllers[i]->register_commands(cmd_ctx)) != ERROR_OK)
210 {
211 LOG_ERROR("couldn't register '%s' commands", args[0]);
212 return retval;
213 }
214
215 c = malloc(sizeof(nand_device_t));
216
217 c->controller = nand_flash_controllers[i];
218 c->controller_priv = NULL;
219 c->manufacturer = NULL;
220 c->device = NULL;
221 c->bus_width = 0;
222 c->address_cycles = 0;
223 c->page_size = 0;
224 c->use_raw = 0;
225 c->next = NULL;
226
227 if ((retval = nand_flash_controllers[i]->nand_device_command(cmd_ctx, cmd, args, argc, c)) != ERROR_OK)
228 {
229 LOG_ERROR("'%s' driver rejected nand flash", c->controller->name);
230 free(c);
231 return ERROR_OK;
232 }
233
234 /* put NAND device in linked list */
235 if (nand_devices)
236 {
237 /* find last flash device */
238 for (p = nand_devices; p && p->next; p = p->next);
239 if (p)
240 p->next = c;
241 }
242 else
243 {
244 nand_devices = c;
245 }
246
247 return ERROR_OK;
248 }
249 }
250
251 /* no valid NAND controller was found (i.e. the configuration option,
252 * didn't match one of the compiled-in controllers)
253 */
254 LOG_ERROR("No valid NAND flash controller found (%s)", args[0]);
255 LOG_ERROR("compiled-in NAND flash controllers:");
256 for (i = 0; nand_flash_controllers[i]; i++)
257 {
258 LOG_ERROR("%i: %s", i, nand_flash_controllers[i]->name);
259 }
260
261 return ERROR_OK;
262 }
263
264 int nand_register_commands(struct command_context_s *cmd_ctx)
265 {
266 nand_cmd = register_command(cmd_ctx, NULL, "nand", NULL, COMMAND_ANY, "NAND specific commands");
267
268 register_command(cmd_ctx, nand_cmd, "device", handle_nand_device_command, COMMAND_CONFIG, NULL);
269
270 return ERROR_OK;
271 }
272
273 int nand_init(struct command_context_s *cmd_ctx)
274 {
275 if (nand_devices)
276 {
277 register_command(cmd_ctx, nand_cmd, "list", handle_nand_list_command, COMMAND_EXEC,
278 "list configured NAND flash devices");
279 register_command(cmd_ctx, nand_cmd, "info", handle_nand_info_command, COMMAND_EXEC,
280 "print info about NAND flash device <num>");
281 register_command(cmd_ctx, nand_cmd, "probe", handle_nand_probe_command, COMMAND_EXEC,
282 "identify NAND flash device <num>");
283 register_command(cmd_ctx, nand_cmd, "check_bad_blocks", handle_nand_check_bad_blocks_command, COMMAND_EXEC,
284 "check NAND flash device <num> for bad blocks [<first> <last>]");
285 register_command(cmd_ctx, nand_cmd, "erase", handle_nand_erase_command, COMMAND_EXEC,
286 "erase blocks on NAND flash device <num> <first> <last>");
287 register_command(cmd_ctx, nand_cmd, "copy", handle_nand_copy_command, COMMAND_EXEC,
288 "copy from NAND flash device <num> <offset> <length> <ram-address>");
289 register_command(cmd_ctx, nand_cmd, "dump", handle_nand_dump_command, COMMAND_EXEC,
290 "dump from NAND flash device <num> <filename> <offset> <size> [options]");
291 register_command(cmd_ctx, nand_cmd, "write", handle_nand_write_command, COMMAND_EXEC,
292 "write to NAND flash device <num> <filename> <offset> [oob_raw|oob_only]");
293 register_command(cmd_ctx, nand_cmd, "raw_access", handle_nand_raw_access_command, COMMAND_EXEC,
294 "raw access to NAND flash device <num> ['enable'|'disable']");
295 }
296
297 return ERROR_OK;
298 }
299
300 nand_device_t *get_nand_device_by_num(int num)
301 {
302 nand_device_t *p;
303 int i = 0;
304
305 for (p = nand_devices; p; p = p->next)
306 {
307 if (i++ == num)
308 {
309 return p;
310 }
311 }
312
313 return NULL;
314 }
315
316 int nand_build_bbt(struct nand_device_s *device, int first, int last)
317 {
318 u32 page = 0x0;
319 int i;
320 u8 oob[6];
321
322 if ((first < 0) || (first >= device->num_blocks))
323 first = 0;
324
325 if ((last >= device->num_blocks) || (last == -1))
326 last = device->num_blocks - 1;
327
328 for (i = first; i < last; i++)
329 {
330 nand_read_page(device, page, NULL, 0, oob, 6);
331
332 if (((device->device->options & NAND_BUSWIDTH_16) && ((oob[0] & oob[1]) != 0xff))
333 || (((device->page_size == 512) && (oob[5] != 0xff)) ||
334 ((device->page_size == 2048) && (oob[0] != 0xff))))
335 {
336 LOG_WARNING("invalid block: %i", i);
337 device->blocks[i].is_bad = 1;
338 }
339 else
340 {
341 device->blocks[i].is_bad = 0;
342 }
343
344 page += (device->erase_size / device->page_size);
345 }
346
347 return ERROR_OK;
348 }
349
350 int nand_read_status(struct nand_device_s *device, u8 *status)
351 {
352 if (!device->device)
353 return ERROR_NAND_DEVICE_NOT_PROBED;
354
355 /* Send read status command */
356 device->controller->command(device, NAND_CMD_STATUS);
357
358 alive_sleep(1);
359
360 /* read status */
361 if (device->device->options & NAND_BUSWIDTH_16)
362 {
363 u16 data;
364 device->controller->read_data(device, &data);
365 *status = data & 0xff;
366 }
367 else
368 {
369 device->controller->read_data(device, status);
370 }
371
372 return ERROR_OK;
373 }
374
375 int nand_poll_ready(struct nand_device_s *device, int timeout)
376 {
377 u8 status;
378
379 device->controller->command(device, NAND_CMD_STATUS);
380 do {
381 if (device->device->options & NAND_BUSWIDTH_16) {
382 u16 data;
383 device->controller->read_data(device, &data);
384 status = data & 0xff;
385 } else {
386 device->controller->read_data(device, &status);
387 }
388 if (status & NAND_STATUS_READY)
389 break;
390 alive_sleep(1);
391 } while (timeout--);
392
393 return (status & NAND_STATUS_READY) != 0;
394 }
395
396 int nand_probe(struct nand_device_s *device)
397 {
398 u8 manufacturer_id, device_id;
399 u8 id_buff[6];
400 int retval;
401 int i;
402
403 /* clear device data */
404 device->device = NULL;
405 device->manufacturer = NULL;
406
407 /* clear device parameters */
408 device->bus_width = 0;
409 device->address_cycles = 0;
410 device->page_size = 0;
411 device->erase_size = 0;
412
413 /* initialize controller (device parameters are zero, use controller default) */
414 if ((retval = device->controller->init(device) != ERROR_OK))
415 {
416 switch (retval)
417 {
418 case ERROR_NAND_OPERATION_FAILED:
419 LOG_DEBUG("controller initialization failed");
420 return ERROR_NAND_OPERATION_FAILED;
421 case ERROR_NAND_OPERATION_NOT_SUPPORTED:
422 LOG_ERROR("BUG: controller reported that it doesn't support default parameters");
423 return ERROR_NAND_OPERATION_FAILED;
424 default:
425 LOG_ERROR("BUG: unknown controller initialization failure");
426 return ERROR_NAND_OPERATION_FAILED;
427 }
428 }
429
430 device->controller->command(device, NAND_CMD_RESET);
431 device->controller->reset(device);
432
433 device->controller->command(device, NAND_CMD_READID);
434 device->controller->address(device, 0x0);
435
436 if (device->bus_width == 8)
437 {
438 device->controller->read_data(device, &manufacturer_id);
439 device->controller->read_data(device, &device_id);
440 }
441 else
442 {
443 u16 data_buf;
444 device->controller->read_data(device, &data_buf);
445 manufacturer_id = data_buf & 0xff;
446 device->controller->read_data(device, &data_buf);
447 device_id = data_buf & 0xff;
448 }
449
450 for (i = 0; nand_flash_ids[i].name; i++)
451 {
452 if (nand_flash_ids[i].id == device_id)
453 {
454 device->device = &nand_flash_ids[i];
455 break;
456 }
457 }
458
459 for (i = 0; nand_manuf_ids[i].name; i++)
460 {
461 if (nand_manuf_ids[i].id == manufacturer_id)
462 {
463 device->manufacturer = &nand_manuf_ids[i];
464 break;
465 }
466 }
467
468 if (!device->manufacturer)
469 {
470 device->manufacturer = &nand_manuf_ids[0];
471 device->manufacturer->id = manufacturer_id;
472 }
473
474 if (!device->device)
475 {
476 LOG_ERROR("unknown NAND flash device found, manufacturer id: 0x%2.2x device id: 0x%2.2x",
477 manufacturer_id, device_id);
478 return ERROR_NAND_OPERATION_FAILED;
479 }
480
481 LOG_DEBUG("found %s (%s)", device->device->name, device->manufacturer->name);
482
483 /* initialize device parameters */
484
485 /* bus width */
486 if (device->device->options & NAND_BUSWIDTH_16)
487 device->bus_width = 16;
488 else
489 device->bus_width = 8;
490
491 /* Do we need extended device probe information? */
492 if (device->device->page_size == 0 ||
493 device->device->erase_size == 0)
494 {
495 if (device->bus_width == 8)
496 {
497 device->controller->read_data(device, id_buff+3);
498 device->controller->read_data(device, id_buff+4);
499 device->controller->read_data(device, id_buff+5);
500 }
501 else
502 {
503 u16 data_buf;
504
505 device->controller->read_data(device, &data_buf);
506 id_buff[3] = data_buf;
507
508 device->controller->read_data(device, &data_buf);
509 id_buff[4] = data_buf;
510
511 device->controller->read_data(device, &data_buf);
512 id_buff[5] = data_buf >> 8;
513 }
514 }
515
516 /* page size */
517 if (device->device->page_size == 0)
518 {
519 device->page_size = 1 << (10 + (id_buff[4] & 3));
520 }
521 else if (device->device->page_size == 256)
522 {
523 LOG_ERROR("NAND flashes with 256 byte pagesize are not supported");
524 return ERROR_NAND_OPERATION_FAILED;
525 }
526 else
527 {
528 device->page_size = device->device->page_size;
529 }
530
531 /* number of address cycles */
532 if (device->page_size <= 512)
533 {
534 /* small page devices */
535 if (device->device->chip_size <= 32)
536 device->address_cycles = 3;
537 else if (device->device->chip_size <= 8*1024)
538 device->address_cycles = 4;
539 else
540 {
541 LOG_ERROR("BUG: small page NAND device with more than 8 GiB encountered");
542 device->address_cycles = 5;
543 }
544 }
545 else
546 {
547 /* large page devices */
548 if (device->device->chip_size <= 128)
549 device->address_cycles = 4;
550 else if (device->device->chip_size <= 32*1024)
551 device->address_cycles = 5;
552 else
553 {
554 LOG_ERROR("BUG: large page NAND device with more than 32 GiB encountered");
555 device->address_cycles = 6;
556 }
557 }
558
559 /* erase size */
560 if (device->device->erase_size == 0)
561 {
562 switch ((id_buff[4] >> 4) & 3) {
563 case 0:
564 device->erase_size = 64 << 10;
565 break;
566 case 1:
567 device->erase_size = 128 << 10;
568 break;
569 case 2:
570 device->erase_size = 256 << 10;
571 break;
572 case 3:
573 device->erase_size =512 << 10;
574 break;
575 }
576 }
577 else
578 {
579 device->erase_size = device->device->erase_size;
580 }
581
582 /* initialize controller, but leave parameters at the controllers default */
583 if ((retval = device->controller->init(device) != ERROR_OK))
584 {
585 switch (retval)
586 {
587 case ERROR_NAND_OPERATION_FAILED:
588 LOG_DEBUG("controller initialization failed");
589 return ERROR_NAND_OPERATION_FAILED;
590 case ERROR_NAND_OPERATION_NOT_SUPPORTED:
591 LOG_ERROR("controller doesn't support requested parameters (buswidth: %i, address cycles: %i, page size: %i)",
592 device->bus_width, device->address_cycles, device->page_size);
593 return ERROR_NAND_OPERATION_FAILED;
594 default:
595 LOG_ERROR("BUG: unknown controller initialization failure");
596 return ERROR_NAND_OPERATION_FAILED;
597 }
598 }
599
600 device->num_blocks = (device->device->chip_size * 1024) / (device->erase_size / 1024);
601 device->blocks = malloc(sizeof(nand_block_t) * device->num_blocks);
602
603 for (i = 0; i < device->num_blocks; i++)
604 {
605 device->blocks[i].size = device->erase_size;
606 device->blocks[i].offset = i * device->erase_size;
607 device->blocks[i].is_erased = -1;
608 device->blocks[i].is_bad = -1;
609 }
610
611 return ERROR_OK;
612 }
613
614 int nand_erase(struct nand_device_s *device, int first_block, int last_block)
615 {
616 int i;
617 u32 page;
618 u8 status;
619 int retval;
620
621 if (!device->device)
622 return ERROR_NAND_DEVICE_NOT_PROBED;
623
624 if ((first_block < 0) || (last_block > device->num_blocks))
625 return ERROR_INVALID_ARGUMENTS;
626
627 /* make sure we know if a block is bad before erasing it */
628 for (i = first_block; i <= last_block; i++)
629 {
630 if (device->blocks[i].is_bad == -1)
631 {
632 nand_build_bbt(device, i, last_block);
633 break;
634 }
635 }
636
637 for (i = first_block; i <= last_block; i++)
638 {
639 /* Send erase setup command */
640 device->controller->command(device, NAND_CMD_ERASE1);
641
642 page = i * (device->erase_size / device->page_size);
643
644 /* Send page address */
645 if (device->page_size <= 512)
646 {
647 /* row */
648 device->controller->address(device, page & 0xff);
649 device->controller->address(device, (page >> 8) & 0xff);
650
651 /* 3rd cycle only on devices with more than 32 MiB */
652 if (device->address_cycles >= 4)
653 device->controller->address(device, (page >> 16) & 0xff);
654
655 /* 4th cycle only on devices with more than 8 GiB */
656 if (device->address_cycles >= 5)
657 device->controller->address(device, (page >> 24) & 0xff);
658 }
659 else
660 {
661 /* row */
662 device->controller->address(device, page & 0xff);
663 device->controller->address(device, (page >> 8) & 0xff);
664
665 /* 3rd cycle only on devices with more than 128 MiB */
666 if (device->address_cycles >= 5)
667 device->controller->address(device, (page >> 16) & 0xff);
668 }
669
670 /* Send erase confirm command */
671 device->controller->command(device, NAND_CMD_ERASE2);
672
673 retval = device->controller->nand_ready ?
674 device->controller->nand_ready(device, 1000) :
675 nand_poll_ready(device, 1000);
676 if (!retval) {
677 LOG_ERROR("timeout waiting for NAND flash block erase to complete");
678 return ERROR_NAND_OPERATION_TIMEOUT;
679 }
680
681 if ((retval = nand_read_status(device, &status)) != ERROR_OK)
682 {
683 LOG_ERROR("couldn't read status");
684 return ERROR_NAND_OPERATION_FAILED;
685 }
686
687 if (status & 0x1)
688 {
689 LOG_ERROR("erase operation didn't pass, status: 0x%2.2x", status);
690 return ERROR_NAND_OPERATION_FAILED;
691 }
692
693 device->blocks[i].is_erased = 1;
694 }
695
696 return ERROR_OK;
697 }
698
699 int nand_read_plain(struct nand_device_s *device, u32 address, u8 *data, u32 data_size)
700 {
701 u8 *page;
702
703 if (!device->device)
704 return ERROR_NAND_DEVICE_NOT_PROBED;
705
706 if (address % device->page_size)
707 {
708 LOG_ERROR("reads need to be page aligned");
709 return ERROR_NAND_OPERATION_FAILED;
710 }
711
712 page = malloc(device->page_size);
713
714 while (data_size > 0 )
715 {
716 u32 thisrun_size = (data_size > device->page_size) ? device->page_size : data_size;
717 u32 page_address;
718
719
720 page_address = address / device->page_size;
721
722 nand_read_page(device, page_address, page, device->page_size, NULL, 0);
723
724 memcpy(data, page, thisrun_size);
725
726 address += thisrun_size;
727 data += thisrun_size;
728 data_size -= thisrun_size;
729 }
730
731 free(page);
732
733 return ERROR_OK;
734 }
735
736 int nand_write_plain(struct nand_device_s *device, u32 address, u8 *data, u32 data_size)
737 {
738 u8 *page;
739
740 if (!device->device)
741 return ERROR_NAND_DEVICE_NOT_PROBED;
742
743 if (address % device->page_size)
744 {
745 LOG_ERROR("writes need to be page aligned");
746 return ERROR_NAND_OPERATION_FAILED;
747 }
748
749 page = malloc(device->page_size);
750
751 while (data_size > 0 )
752 {
753 u32 thisrun_size = (data_size > device->page_size) ? device->page_size : data_size;
754 u32 page_address;
755
756 memset(page, 0xff, device->page_size);
757 memcpy(page, data, thisrun_size);
758
759 page_address = address / device->page_size;
760
761 nand_write_page(device, page_address, page, device->page_size, NULL, 0);
762
763 address += thisrun_size;
764 data += thisrun_size;
765 data_size -= thisrun_size;
766 }
767
768 free(page);
769
770 return ERROR_OK;
771 }
772
773 int nand_write_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
774 {
775 u32 block;
776
777 if (!device->device)
778 return ERROR_NAND_DEVICE_NOT_PROBED;
779
780 block = page / (device->erase_size / device->page_size);
781 if (device->blocks[block].is_erased == 1)
782 device->blocks[block].is_erased = 0;
783
784 if (device->use_raw || device->controller->write_page == NULL)
785 return nand_write_page_raw(device, page, data, data_size, oob, oob_size);
786 else
787 return device->controller->write_page(device, page, data, data_size, oob, oob_size);
788 }
789
790 int nand_read_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
791 {
792 if (!device->device)
793 return ERROR_NAND_DEVICE_NOT_PROBED;
794
795 if (device->use_raw || device->controller->read_page == NULL)
796 return nand_read_page_raw(device, page, data, data_size, oob, oob_size);
797 else
798 return device->controller->read_page(device, page, data, data_size, oob, oob_size);
799 }
800
801 int nand_read_page_raw(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
802 {
803 int i;
804
805 if (!device->device)
806 return ERROR_NAND_DEVICE_NOT_PROBED;
807
808 if (device->page_size <= 512)
809 {
810 /* small page device */
811 if (data)
812 device->controller->command(device, NAND_CMD_READ0);
813 else
814 device->controller->command(device, NAND_CMD_READOOB);
815
816 /* column (always 0, we start at the beginning of a page/OOB area) */
817 device->controller->address(device, 0x0);
818
819 /* row */
820 device->controller->address(device, page & 0xff);
821 device->controller->address(device, (page >> 8) & 0xff);
822
823 /* 4th cycle only on devices with more than 32 MiB */
824 if (device->address_cycles >= 4)
825 device->controller->address(device, (page >> 16) & 0xff);
826
827 /* 5th cycle only on devices with more than 8 GiB */
828 if (device->address_cycles >= 5)
829 device->controller->address(device, (page >> 24) & 0xff);
830 }
831 else
832 {
833 /* large page device */
834 device->controller->command(device, NAND_CMD_READ0);
835
836 /* column (0 when we start at the beginning of a page,
837 * or 2048 for the beginning of OOB area)
838 */
839 device->controller->address(device, 0x0);
840 if (data)
841 device->controller->address(device, 0x0);
842 else
843 device->controller->address(device, 0x8);
844
845 /* row */
846 device->controller->address(device, page & 0xff);
847 device->controller->address(device, (page >> 8) & 0xff);
848
849 /* 5th cycle only on devices with more than 128 MiB */
850 if (device->address_cycles >= 5)
851 device->controller->address(device, (page >> 16) & 0xff);
852
853 /* large page devices need a start command */
854 device->controller->command(device, NAND_CMD_READSTART);
855 }
856
857 if (device->controller->nand_ready) {
858 if (!device->controller->nand_ready(device, 100))
859 return ERROR_NAND_OPERATION_TIMEOUT;
860 } else {
861 alive_sleep(1);
862 }
863
864 if (data)
865 {
866 if (device->controller->read_block_data != NULL)
867 (device->controller->read_block_data)(device, data, data_size);
868 else
869 {
870 for (i = 0; i < data_size;)
871 {
872 if (device->device->options & NAND_BUSWIDTH_16)
873 {
874 device->controller->read_data(device, data);
875 data += 2;
876 i += 2;
877 }
878 else
879 {
880 device->controller->read_data(device, data);
881 data += 1;
882 i += 1;
883 }
884 }
885 }
886 }
887
888 if (oob)
889 {
890 if (device->controller->read_block_data != NULL)
891 (device->controller->read_block_data)(device, oob, oob_size);
892 else
893 {
894 for (i = 0; i < oob_size;)
895 {
896 if (device->device->options & NAND_BUSWIDTH_16)
897 {
898 device->controller->read_data(device, oob);
899 oob += 2;
900 i += 2;
901 }
902 else
903 {
904 device->controller->read_data(device, oob);
905 oob += 1;
906 i += 1;
907 }
908 }
909 }
910 }
911
912 return ERROR_OK;
913 }
914
915 int nand_write_page_raw(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
916 {
917 int i;
918 int retval;
919 u8 status;
920
921 if (!device->device)
922 return ERROR_NAND_DEVICE_NOT_PROBED;
923
924 device->controller->command(device, NAND_CMD_SEQIN);
925
926 if (device->page_size <= 512)
927 {
928 /* column (always 0, we start at the beginning of a page/OOB area) */
929 device->controller->address(device, 0x0);
930
931 /* row */
932 device->controller->address(device, page & 0xff);
933 device->controller->address(device, (page >> 8) & 0xff);
934
935 /* 4th cycle only on devices with more than 32 MiB */
936 if (device->address_cycles >= 4)
937 device->controller->address(device, (page >> 16) & 0xff);
938
939 /* 5th cycle only on devices with more than 8 GiB */
940 if (device->address_cycles >= 5)
941 device->controller->address(device, (page >> 24) & 0xff);
942 }
943 else
944 {
945 /* column (0 when we start at the beginning of a page,
946 * or 2048 for the beginning of OOB area)
947 */
948 device->controller->address(device, 0x0);
949 if (data)
950 device->controller->address(device, 0x0);
951 else
952 device->controller->address(device, 0x8);
953
954 /* row */
955 device->controller->address(device, page & 0xff);
956 device->controller->address(device, (page >> 8) & 0xff);
957
958 /* 5th cycle only on devices with more than 128 MiB */
959 if (device->address_cycles >= 5)
960 device->controller->address(device, (page >> 16) & 0xff);
961 }
962
963 if (data)
964 {
965 if (device->controller->write_block_data != NULL)
966 (device->controller->write_block_data)(device, data, data_size);
967 else
968 {
969 for (i = 0; i < data_size;)
970 {
971 if (device->device->options & NAND_BUSWIDTH_16)
972 {
973 u16 data_buf = le_to_h_u16(data);
974 device->controller->write_data(device, data_buf);
975 data += 2;
976 i += 2;
977 }
978 else
979 {
980 device->controller->write_data(device, *data);
981 data += 1;
982 i += 1;
983 }
984 }
985 }
986 }
987
988 if (oob)
989 {
990 if (device->controller->write_block_data != NULL)
991 (device->controller->write_block_data)(device, oob, oob_size);
992 else
993 {
994 for (i = 0; i < oob_size;)
995 {
996 if (device->device->options & NAND_BUSWIDTH_16)
997 {
998 u16 oob_buf = le_to_h_u16(data);
999 device->controller->write_data(device, oob_buf);
1000 oob += 2;
1001 i += 2;
1002 }
1003 else
1004 {
1005 device->controller->write_data(device, *oob);
1006 oob += 1;
1007 i += 1;
1008 }
1009 }
1010 }
1011 }
1012
1013 device->controller->command(device, NAND_CMD_PAGEPROG);
1014
1015 retval = device->controller->nand_ready ?
1016 device->controller->nand_ready(device, 100) :
1017 nand_poll_ready(device, 100);
1018 if (!retval)
1019 return ERROR_NAND_OPERATION_TIMEOUT;
1020
1021 if ((retval = nand_read_status(device, &status)) != ERROR_OK)
1022 {
1023 LOG_ERROR("couldn't read status");
1024 return ERROR_NAND_OPERATION_FAILED;
1025 }
1026
1027 if (status & NAND_STATUS_FAIL)
1028 {
1029 LOG_ERROR("write operation didn't pass, status: 0x%2.2x", status);
1030 return ERROR_NAND_OPERATION_FAILED;
1031 }
1032
1033 return ERROR_OK;
1034 }
1035
1036 int handle_nand_list_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1037 {
1038 nand_device_t *p;
1039 int i = 0;
1040
1041 if (!nand_devices)
1042 {
1043 command_print(cmd_ctx, "no NAND flash devices configured");
1044 return ERROR_OK;
1045 }
1046
1047 for (p = nand_devices; p; p = p->next)
1048 {
1049 if (p->device)
1050 command_print(cmd_ctx, "#%i: %s (%s) pagesize: %i, buswidth: %i, erasesize: %i",
1051 i++, p->device->name, p->manufacturer->name, p->page_size, p->bus_width, p->erase_size);
1052 else
1053 command_print(cmd_ctx, "#%i: not probed");
1054 }
1055
1056 return ERROR_OK;
1057 }
1058
1059 int handle_nand_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1060 {
1061 nand_device_t *p;
1062 int i = 0;
1063 int j = 0;
1064 int first = -1;
1065 int last = -1;
1066
1067 if ((argc < 1) || (argc > 3))
1068 {
1069 return ERROR_COMMAND_SYNTAX_ERROR;
1070
1071 }
1072
1073 if (argc == 2)
1074 {
1075 first = last = strtoul(args[1], NULL, 0);
1076 }
1077 else if (argc == 3)
1078 {
1079 first = strtoul(args[1], NULL, 0);
1080 last = strtoul(args[2], NULL, 0);
1081 }
1082
1083 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1084 if (p)
1085 {
1086 if (p->device)
1087 {
1088 if (first >= p->num_blocks)
1089 first = p->num_blocks - 1;
1090
1091 if (last >= p->num_blocks)
1092 last = p->num_blocks - 1;
1093
1094 command_print(cmd_ctx, "#%i: %s (%s) pagesize: %i, buswidth: %i, erasesize: %i",
1095 i++, p->device->name, p->manufacturer->name, p->page_size, p->bus_width, p->erase_size);
1096
1097 for (j = first; j <= last; j++)
1098 {
1099 char *erase_state, *bad_state;
1100
1101 if (p->blocks[j].is_erased == 0)
1102 erase_state = "not erased";
1103 else if (p->blocks[j].is_erased == 1)
1104 erase_state = "erased";
1105 else
1106 erase_state = "erase state unknown";
1107
1108 if (p->blocks[j].is_bad == 0)
1109 bad_state = "";
1110 else if (p->blocks[j].is_bad == 1)
1111 bad_state = " (marked bad)";
1112 else
1113 bad_state = " (block condition unknown)";
1114
1115 command_print(cmd_ctx, "\t#%i: 0x%8.8x (0x%xkB) %s%s",
1116 j, p->blocks[j].offset, p->blocks[j].size / 1024,
1117 erase_state, bad_state);
1118 }
1119 }
1120 else
1121 {
1122 command_print(cmd_ctx, "#%i: not probed");
1123 }
1124 }
1125
1126 return ERROR_OK;
1127 }
1128
1129 int handle_nand_probe_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1130 {
1131 nand_device_t *p;
1132 int retval;
1133
1134 if (argc != 1)
1135 {
1136 return ERROR_COMMAND_SYNTAX_ERROR;
1137 }
1138
1139 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1140 if (p)
1141 {
1142 if ((retval = nand_probe(p)) == ERROR_OK)
1143 {
1144 command_print(cmd_ctx, "NAND flash device '%s' found", p->device->name);
1145 }
1146 else if (retval == ERROR_NAND_OPERATION_FAILED)
1147 {
1148 command_print(cmd_ctx, "probing failed for NAND flash device");
1149 }
1150 else
1151 {
1152 command_print(cmd_ctx, "unknown error when probing NAND flash device");
1153 }
1154 }
1155 else
1156 {
1157 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1158 }
1159
1160 return ERROR_OK;
1161 }
1162
1163 int handle_nand_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1164 {
1165 nand_device_t *p;
1166 int retval;
1167
1168 if (argc != 3)
1169 {
1170 return ERROR_COMMAND_SYNTAX_ERROR;
1171
1172 }
1173
1174 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1175 if (p)
1176 {
1177 int first = strtoul(args[1], NULL, 0);
1178 int last = strtoul(args[2], NULL, 0);
1179
1180 if ((retval = nand_erase(p, first, last)) == ERROR_OK)
1181 {
1182 command_print(cmd_ctx, "successfully erased blocks %i to %i on NAND flash device '%s'", first, last, p->device->name);
1183 }
1184 else if (retval == ERROR_NAND_OPERATION_FAILED)
1185 {
1186 command_print(cmd_ctx, "erase failed");
1187 }
1188 else
1189 {
1190 command_print(cmd_ctx, "unknown error when erasing NAND flash device");
1191 }
1192 }
1193 else
1194 {
1195 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1196 }
1197
1198 return ERROR_OK;
1199 }
1200
1201 int handle_nand_check_bad_blocks_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1202 {
1203 nand_device_t *p;
1204 int retval;
1205 int first = -1;
1206 int last = -1;
1207
1208 if ((argc < 1) || (argc > 3) || (argc == 2))
1209 {
1210 return ERROR_COMMAND_SYNTAX_ERROR;
1211
1212 }
1213
1214 if (argc == 3)
1215 {
1216 first = strtoul(args[1], NULL, 0);
1217 last = strtoul(args[2], NULL, 0);
1218 }
1219
1220 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1221 if (p)
1222 {
1223 if ((retval = nand_build_bbt(p, first, last)) == ERROR_OK)
1224 {
1225 command_print(cmd_ctx, "checked NAND flash device for bad blocks, use \"nand info\" command to list blocks", p->device->name);
1226 }
1227 else if (retval == ERROR_NAND_OPERATION_FAILED)
1228 {
1229 command_print(cmd_ctx, "error when checking for bad blocks on NAND flash device");
1230 }
1231 else
1232 {
1233 command_print(cmd_ctx, "unknown error when checking for bad blocks on NAND flash device");
1234 }
1235 }
1236 else
1237 {
1238 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1239 }
1240
1241 return ERROR_OK;
1242 }
1243
1244 int handle_nand_copy_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1245 {
1246 nand_device_t *p;
1247
1248 if (argc != 4)
1249 {
1250 return ERROR_COMMAND_SYNTAX_ERROR;
1251
1252 }
1253
1254 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1255 if (p)
1256 {
1257
1258 }
1259 else
1260 {
1261 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1262 }
1263
1264 return ERROR_OK;
1265 }
1266
1267 int handle_nand_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1268 {
1269 u32 offset;
1270 u32 binary_size;
1271 u32 buf_cnt;
1272 enum oob_formats oob_format = NAND_OOB_NONE;
1273
1274 fileio_t fileio;
1275
1276 duration_t duration;
1277 char *duration_text;
1278
1279 nand_device_t *p;
1280
1281 if (argc < 3)
1282 {
1283 return ERROR_COMMAND_SYNTAX_ERROR;
1284
1285 }
1286
1287 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1288 if (p)
1289 {
1290 u8 *page = NULL;
1291 u32 page_size = 0;
1292 u8 *oob = NULL;
1293 u32 oob_size = 0;
1294
1295 offset = strtoul(args[2], NULL, 0);
1296
1297 if (argc > 3)
1298 {
1299 int i;
1300 for (i = 3; i < argc; i++)
1301 {
1302 if (!strcmp(args[i], "oob_raw"))
1303 oob_format |= NAND_OOB_RAW;
1304 else if (!strcmp(args[i], "oob_only"))
1305 oob_format |= NAND_OOB_RAW | NAND_OOB_ONLY;
1306 else
1307 {
1308 command_print(cmd_ctx, "unknown option: %s", args[i]);
1309 return ERROR_COMMAND_SYNTAX_ERROR;
1310 }
1311 }
1312 }
1313
1314 duration_start_measure(&duration);
1315
1316 if (fileio_open(&fileio, args[1], FILEIO_READ, FILEIO_BINARY) != ERROR_OK)
1317 {
1318 return ERROR_OK;
1319 }
1320
1321 buf_cnt = binary_size = fileio.size;
1322
1323 if (!(oob_format & NAND_OOB_ONLY))
1324 {
1325 page_size = p->page_size;
1326 page = malloc(p->page_size);
1327 }
1328
1329 if (oob_format & NAND_OOB_RAW)
1330 {
1331 if (p->page_size == 512)
1332 oob_size = 16;
1333 else if (p->page_size == 2048)
1334 oob_size = 64;
1335 oob = malloc(oob_size);
1336 }
1337
1338 if (offset % p->page_size)
1339 {
1340 command_print(cmd_ctx, "only page size aligned offsets and sizes are supported");
1341 fileio_close(&fileio);
1342 free(oob);
1343 free(page);
1344 return ERROR_OK;
1345 }
1346
1347 while (buf_cnt > 0)
1348 {
1349 u32 size_read;
1350
1351 if (NULL != page)
1352 {
1353 fileio_read(&fileio, page_size, page, &size_read);
1354 buf_cnt -= size_read;
1355 if (size_read < page_size)
1356 {
1357 memset(page + size_read, 0xff, page_size - size_read);
1358 }
1359 }
1360
1361 if (NULL != oob)
1362 {
1363 fileio_read(&fileio, oob_size, oob, &size_read);
1364 buf_cnt -= size_read;
1365 if (size_read < oob_size)
1366 {
1367 memset(oob + size_read, 0xff, oob_size - size_read);
1368 }
1369 }
1370
1371 if (nand_write_page(p, offset / p->page_size, page, page_size, oob, oob_size) != ERROR_OK)
1372 {
1373 command_print(cmd_ctx, "failed writing file %s to NAND flash %s at offset 0x%8.8x",
1374 args[1], args[0], offset);
1375
1376 fileio_close(&fileio);
1377 free(oob);
1378 free(page);
1379
1380 return ERROR_OK;
1381 }
1382 offset += page_size;
1383 }
1384
1385 fileio_close(&fileio);
1386 free(oob);
1387 free(page);
1388 oob = NULL;
1389 page = NULL;
1390 duration_stop_measure(&duration, &duration_text);
1391 command_print(cmd_ctx, "wrote file %s to NAND flash %s up to offset 0x%8.8x in %s",
1392 args[1], args[0], offset, duration_text);
1393 free(duration_text);
1394 duration_text = NULL;
1395 }
1396 else
1397 {
1398 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1399 }
1400
1401 return ERROR_OK;
1402 }
1403
1404 int handle_nand_dump_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1405 {
1406 nand_device_t *p;
1407
1408 if (argc < 4)
1409 {
1410 return ERROR_COMMAND_SYNTAX_ERROR;
1411 }
1412
1413 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1414 if (p)
1415 {
1416 if (p->device)
1417 {
1418 fileio_t fileio;
1419 duration_t duration;
1420 char *duration_text;
1421 int retval;
1422
1423 u8 *page = NULL;
1424 u32 page_size = 0;
1425 u8 *oob = NULL;
1426 u32 oob_size = 0;
1427 u32 address = strtoul(args[2], NULL, 0);
1428 u32 size = strtoul(args[3], NULL, 0);
1429 u32 bytes_done = 0;
1430 enum oob_formats oob_format = NAND_OOB_NONE;
1431
1432 if (argc > 4)
1433 {
1434 int i;
1435 for (i = 4; i < argc; i++)
1436 {
1437 if (!strcmp(args[i], "oob_raw"))
1438 oob_format |= NAND_OOB_RAW;
1439 else if (!strcmp(args[i], "oob_only"))
1440 oob_format |= NAND_OOB_RAW | NAND_OOB_ONLY;
1441 else
1442 command_print(cmd_ctx, "unknown option: '%s'", args[i]);
1443 }
1444 }
1445
1446 if ((address % p->page_size) || (size % p->page_size))
1447 {
1448 command_print(cmd_ctx, "only page size aligned addresses and sizes are supported");
1449 return ERROR_OK;
1450 }
1451
1452 if (!(oob_format & NAND_OOB_ONLY))
1453 {
1454 page_size = p->page_size;
1455 page = malloc(p->page_size);
1456 }
1457
1458 if (oob_format & NAND_OOB_RAW)
1459 {
1460 if (p->page_size == 512)
1461 oob_size = 16;
1462 else if (p->page_size == 2048)
1463 oob_size = 64;
1464 oob = malloc(oob_size);
1465 }
1466
1467 if (fileio_open(&fileio, args[1], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
1468 {
1469 return ERROR_OK;
1470 }
1471
1472 duration_start_measure(&duration);
1473
1474 while (size > 0)
1475 {
1476 u32 size_written;
1477 if ((retval = nand_read_page(p, address / p->page_size, page, page_size, oob, oob_size)) != ERROR_OK)
1478 {
1479 command_print(cmd_ctx, "reading NAND flash page failed");
1480 free(page);
1481 free(oob);
1482 fileio_close(&fileio);
1483 return ERROR_OK;
1484 }
1485
1486 if (NULL != page)
1487 {
1488 fileio_write(&fileio, page_size, page, &size_written);
1489 bytes_done += page_size;
1490 }
1491
1492 if (NULL != oob)
1493 {
1494 fileio_write(&fileio, oob_size, oob, &size_written);
1495 bytes_done += oob_size;
1496 }
1497
1498 size -= p->page_size;
1499 address += p->page_size;
1500 }
1501
1502 free(page);
1503 page = NULL;
1504 free(oob);
1505 oob = NULL;
1506 fileio_close(&fileio);
1507
1508 duration_stop_measure(&duration, &duration_text);
1509 command_print(cmd_ctx, "dumped %"PRIi64" byte in %s", fileio.size, duration_text);
1510 free(duration_text);
1511 duration_text = NULL;
1512 }
1513 else
1514 {
1515 command_print(cmd_ctx, "#%i: not probed");
1516 }
1517 }
1518 else
1519 {
1520 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1521 }
1522
1523 return ERROR_OK;
1524 }
1525
1526 int handle_nand_raw_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1527 {
1528 nand_device_t *p;
1529
1530 if ((argc < 1) || (argc > 2))
1531 {
1532 return ERROR_COMMAND_SYNTAX_ERROR;
1533 }
1534
1535 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1536 if (p)
1537 {
1538 if (p->device)
1539 {
1540 if (argc == 2)
1541 {
1542 if (strcmp("enable", args[1]) == 0)
1543 {
1544 p->use_raw = 1;
1545 }
1546 else if (strcmp("disable", args[1]) == 0)
1547 {
1548 p->use_raw = 0;
1549 }
1550 else
1551 {
1552 return ERROR_COMMAND_SYNTAX_ERROR;
1553 }
1554 }
1555
1556 command_print(cmd_ctx, "raw access is %s", (p->use_raw) ? "enabled" : "disabled");
1557 }
1558 else
1559 {
1560 command_print(cmd_ctx, "#%i: not probed");
1561 }
1562 }
1563 else
1564 {
1565 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1566 }
1567
1568 return ERROR_OK;
1569 }
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