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Nicolas Pitre nico at cam.org list the new flag in the "nand write" help line.
[openocd.git] / src / flash / nand.c
1 /***************************************************************************
2 * Copyright (C) 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Partially based on drivers/mtd/nand_ids.c from Linux. *
6 * Copyright (C) 2002 Thomas Gleixner <tglx@linutronix.de> *
7 * *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
12 * *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
17 * *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
23 #ifdef HAVE_CONFIG_H
24 #include "config.h"
25 #endif
26
27 #include "replacements.h"
28 #include "log.h"
29
30 #include <stdlib.h>
31 #include <string.h>
32 #include <inttypes.h>
33
34 #include <errno.h>
35
36 #include "nand.h"
37 #include "flash.h"
38 #include "time_support.h"
39 #include "fileio.h"
40 #include "image.h"
41
42 int nand_register_commands(struct command_context_s *cmd_ctx);
43 int handle_nand_list_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
44 int handle_nand_probe_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
45 int handle_nand_check_bad_blocks_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
46 int handle_nand_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
47 int handle_nand_copy_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
48 int handle_nand_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
49 int handle_nand_dump_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
50 int handle_nand_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
51
52 int handle_nand_raw_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
53
54 int nand_read_page_raw(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
55 int nand_read_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
56 int nand_read_plain(struct nand_device_s *device, u32 address, u8 *data, u32 data_size);
57
58 int nand_write_page_raw(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
59 int nand_write_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
60
61 /* NAND flash controller
62 */
63 extern nand_flash_controller_t lpc3180_nand_controller;
64 extern nand_flash_controller_t orion_nand_controller;
65 extern nand_flash_controller_t s3c2410_nand_controller;
66 extern nand_flash_controller_t s3c2412_nand_controller;
67 extern nand_flash_controller_t s3c2440_nand_controller;
68 extern nand_flash_controller_t s3c2443_nand_controller;
69
70 /* extern nand_flash_controller_t boundary_scan_nand_controller; */
71
72 nand_flash_controller_t *nand_flash_controllers[] =
73 {
74 &lpc3180_nand_controller,
75 &orion_nand_controller,
76 &s3c2410_nand_controller,
77 &s3c2412_nand_controller,
78 &s3c2440_nand_controller,
79 &s3c2443_nand_controller,
80 /* &boundary_scan_nand_controller, */
81 NULL
82 };
83
84 /* configured NAND devices and NAND Flash command handler */
85 nand_device_t *nand_devices = NULL;
86 static command_t *nand_cmd;
87
88 /* Chip ID list
89 *
90 * Name, ID code, pagesize, chipsize in MegaByte, eraseblock size,
91 * options
92 *
93 * Pagesize; 0, 256, 512
94 * 0 get this information from the extended chip ID
95 * 256 256 Byte page size
96 * 512 512 Byte page size
97 */
98 nand_info_t nand_flash_ids[] =
99 {
100 {"NAND 1MiB 5V 8-bit", 0x6e, 256, 1, 0x1000, 0},
101 {"NAND 2MiB 5V 8-bit", 0x64, 256, 2, 0x1000, 0},
102 {"NAND 4MiB 5V 8-bit", 0x6b, 512, 4, 0x2000, 0},
103 {"NAND 1MiB 3,3V 8-bit", 0xe8, 256, 1, 0x1000, 0},
104 {"NAND 1MiB 3,3V 8-bit", 0xec, 256, 1, 0x1000, 0},
105 {"NAND 2MiB 3,3V 8-bit", 0xea, 256, 2, 0x1000, 0},
106 {"NAND 4MiB 3,3V 8-bit", 0xd5, 512, 4, 0x2000, 0},
107 {"NAND 4MiB 3,3V 8-bit", 0xe3, 512, 4, 0x2000, 0},
108 {"NAND 4MiB 3,3V 8-bit", 0xe5, 512, 4, 0x2000, 0},
109 {"NAND 8MiB 3,3V 8-bit", 0xd6, 512, 8, 0x2000, 0},
110
111 {"NAND 8MiB 1,8V 8-bit", 0x39, 512, 8, 0x2000, 0},
112 {"NAND 8MiB 3,3V 8-bit", 0xe6, 512, 8, 0x2000, 0},
113 {"NAND 8MiB 1,8V 16-bit", 0x49, 512, 8, 0x2000, NAND_BUSWIDTH_16},
114 {"NAND 8MiB 3,3V 16-bit", 0x59, 512, 8, 0x2000, NAND_BUSWIDTH_16},
115
116 {"NAND 16MiB 1,8V 8-bit", 0x33, 512, 16, 0x4000, 0},
117 {"NAND 16MiB 3,3V 8-bit", 0x73, 512, 16, 0x4000, 0},
118 {"NAND 16MiB 1,8V 16-bit", 0x43, 512, 16, 0x4000, NAND_BUSWIDTH_16},
119 {"NAND 16MiB 3,3V 16-bit", 0x53, 512, 16, 0x4000, NAND_BUSWIDTH_16},
120
121 {"NAND 32MiB 1,8V 8-bit", 0x35, 512, 32, 0x4000, 0},
122 {"NAND 32MiB 3,3V 8-bit", 0x75, 512, 32, 0x4000, 0},
123 {"NAND 32MiB 1,8V 16-bit", 0x45, 512, 32, 0x4000, NAND_BUSWIDTH_16},
124 {"NAND 32MiB 3,3V 16-bit", 0x55, 512, 32, 0x4000, NAND_BUSWIDTH_16},
125
126 {"NAND 64MiB 1,8V 8-bit", 0x36, 512, 64, 0x4000, 0},
127 {"NAND 64MiB 3,3V 8-bit", 0x76, 512, 64, 0x4000, 0},
128 {"NAND 64MiB 1,8V 16-bit", 0x46, 512, 64, 0x4000, NAND_BUSWIDTH_16},
129 {"NAND 64MiB 3,3V 16-bit", 0x56, 512, 64, 0x4000, NAND_BUSWIDTH_16},
130
131 {"NAND 128MiB 1,8V 8-bit", 0x78, 512, 128, 0x4000, 0},
132 {"NAND 128MiB 1,8V 8-bit", 0x39, 512, 128, 0x4000, 0},
133 {"NAND 128MiB 3,3V 8-bit", 0x79, 512, 128, 0x4000, 0},
134 {"NAND 128MiB 1,8V 16-bit", 0x72, 512, 128, 0x4000, NAND_BUSWIDTH_16},
135 {"NAND 128MiB 1,8V 16-bit", 0x49, 512, 128, 0x4000, NAND_BUSWIDTH_16},
136 {"NAND 128MiB 3,3V 16-bit", 0x74, 512, 128, 0x4000, NAND_BUSWIDTH_16},
137 {"NAND 128MiB 3,3V 16-bit", 0x59, 512, 128, 0x4000, NAND_BUSWIDTH_16},
138
139 {"NAND 256MiB 3,3V 8-bit", 0x71, 512, 256, 0x4000, 0},
140
141 {"NAND 64MiB 1,8V 8-bit", 0xA2, 0, 64, 0, LP_OPTIONS},
142 {"NAND 64MiB 3,3V 8-bit", 0xF2, 0, 64, 0, LP_OPTIONS},
143 {"NAND 64MiB 1,8V 16-bit", 0xB2, 0, 64, 0, LP_OPTIONS16},
144 {"NAND 64MiB 3,3V 16-bit", 0xC2, 0, 64, 0, LP_OPTIONS16},
145
146 {"NAND 128MiB 1,8V 8-bit", 0xA1, 0, 128, 0, LP_OPTIONS},
147 {"NAND 128MiB 3,3V 8-bit", 0xF1, 0, 128, 0, LP_OPTIONS},
148 {"NAND 128MiB 1,8V 16-bit", 0xB1, 0, 128, 0, LP_OPTIONS16},
149 {"NAND 128MiB 3,3V 16-bit", 0xC1, 0, 128, 0, LP_OPTIONS16},
150
151 {"NAND 256MiB 1,8V 8-bit", 0xAA, 0, 256, 0, LP_OPTIONS},
152 {"NAND 256MiB 3,3V 8-bit", 0xDA, 0, 256, 0, LP_OPTIONS},
153 {"NAND 256MiB 1,8V 16-bit", 0xBA, 0, 256, 0, LP_OPTIONS16},
154 {"NAND 256MiB 3,3V 16-bit", 0xCA, 0, 256, 0, LP_OPTIONS16},
155
156 {"NAND 512MiB 1,8V 8-bit", 0xAC, 0, 512, 0, LP_OPTIONS},
157 {"NAND 512MiB 3,3V 8-bit", 0xDC, 0, 512, 0, LP_OPTIONS},
158 {"NAND 512MiB 1,8V 16-bit", 0xBC, 0, 512, 0, LP_OPTIONS16},
159 {"NAND 512MiB 3,3V 16-bit", 0xCC, 0, 512, 0, LP_OPTIONS16},
160
161 {"NAND 1GiB 1,8V 8-bit", 0xA3, 0, 1024, 0, LP_OPTIONS},
162 {"NAND 1GiB 3,3V 8-bit", 0xD3, 0, 1024, 0, LP_OPTIONS},
163 {"NAND 1GiB 1,8V 16-bit", 0xB3, 0, 1024, 0, LP_OPTIONS16},
164 {"NAND 1GiB 3,3V 16-bit", 0xC3, 0, 1024, 0, LP_OPTIONS16},
165
166 {"NAND 2GiB 1,8V 8-bit", 0xA5, 0, 2048, 0, LP_OPTIONS},
167 {"NAND 2GiB 3,3V 8-bit", 0xD5, 0, 2048, 0, LP_OPTIONS},
168 {"NAND 2GiB 1,8V 16-bit", 0xB5, 0, 2048, 0, LP_OPTIONS16},
169 {"NAND 2GiB 3,3V 16-bit", 0xC5, 0, 2048, 0, LP_OPTIONS16},
170
171 {NULL, 0,}
172 };
173
174 /* Manufacturer ID list
175 */
176 nand_manufacturer_t nand_manuf_ids[] =
177 {
178 {0x0, "unknown"},
179 {NAND_MFR_TOSHIBA, "Toshiba"},
180 {NAND_MFR_SAMSUNG, "Samsung"},
181 {NAND_MFR_FUJITSU, "Fujitsu"},
182 {NAND_MFR_NATIONAL, "National"},
183 {NAND_MFR_RENESAS, "Renesas"},
184 {NAND_MFR_STMICRO, "ST Micro"},
185 {NAND_MFR_HYNIX, "Hynix"},
186 {0x0, NULL},
187 };
188
189 /*
190 * Define default oob placement schemes for large and small page devices
191 */
192
193 nand_ecclayout_t nand_oob_8 = {
194 .eccbytes = 3,
195 .eccpos = {0, 1, 2},
196 .oobfree = {
197 {.offset = 3,
198 .length = 2},
199 {.offset = 6,
200 .length = 2}}
201 };
202
203 nand_ecclayout_t nand_oob_16 = {
204 .eccbytes = 6,
205 .eccpos = {0, 1, 2, 3, 6, 7},
206 .oobfree = {
207 {.offset = 8,
208 . length = 8}}
209 };
210
211 nand_ecclayout_t nand_oob_64 = {
212 .eccbytes = 24,
213 .eccpos = {
214 40, 41, 42, 43, 44, 45, 46, 47,
215 48, 49, 50, 51, 52, 53, 54, 55,
216 56, 57, 58, 59, 60, 61, 62, 63},
217 .oobfree = {
218 {.offset = 2,
219 .length = 38}}
220 };
221
222 /* nand device <nand_controller> [controller options]
223 */
224 int handle_nand_device_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
225 {
226 int i;
227 int retval;
228
229 if (argc < 1)
230 {
231 LOG_WARNING("incomplete flash device nand configuration");
232 return ERROR_FLASH_BANK_INVALID;
233 }
234
235 for (i = 0; nand_flash_controllers[i]; i++)
236 {
237 nand_device_t *p, *c;
238
239 if (strcmp(args[0], nand_flash_controllers[i]->name) == 0)
240 {
241 /* register flash specific commands */
242 if ((retval = nand_flash_controllers[i]->register_commands(cmd_ctx)) != ERROR_OK)
243 {
244 LOG_ERROR("couldn't register '%s' commands", args[0]);
245 return retval;
246 }
247
248 c = malloc(sizeof(nand_device_t));
249
250 c->controller = nand_flash_controllers[i];
251 c->controller_priv = NULL;
252 c->manufacturer = NULL;
253 c->device = NULL;
254 c->bus_width = 0;
255 c->address_cycles = 0;
256 c->page_size = 0;
257 c->use_raw = 0;
258 c->next = NULL;
259
260 if ((retval = nand_flash_controllers[i]->nand_device_command(cmd_ctx, cmd, args, argc, c)) != ERROR_OK)
261 {
262 LOG_ERROR("'%s' driver rejected nand flash", c->controller->name);
263 free(c);
264 return ERROR_OK;
265 }
266
267 /* put NAND device in linked list */
268 if (nand_devices)
269 {
270 /* find last flash device */
271 for (p = nand_devices; p && p->next; p = p->next);
272 if (p)
273 p->next = c;
274 }
275 else
276 {
277 nand_devices = c;
278 }
279
280 return ERROR_OK;
281 }
282 }
283
284 /* no valid NAND controller was found (i.e. the configuration option,
285 * didn't match one of the compiled-in controllers)
286 */
287 LOG_ERROR("No valid NAND flash controller found (%s)", args[0]);
288 LOG_ERROR("compiled-in NAND flash controllers:");
289 for (i = 0; nand_flash_controllers[i]; i++)
290 {
291 LOG_ERROR("%i: %s", i, nand_flash_controllers[i]->name);
292 }
293
294 return ERROR_OK;
295 }
296
297 int nand_register_commands(struct command_context_s *cmd_ctx)
298 {
299 nand_cmd = register_command(cmd_ctx, NULL, "nand", NULL, COMMAND_ANY, "NAND specific commands");
300
301 register_command(cmd_ctx, nand_cmd, "device", handle_nand_device_command, COMMAND_CONFIG, NULL);
302
303 return ERROR_OK;
304 }
305
306 int nand_init(struct command_context_s *cmd_ctx)
307 {
308 if (nand_devices)
309 {
310 register_command(cmd_ctx, nand_cmd, "list", handle_nand_list_command, COMMAND_EXEC,
311 "list configured NAND flash devices");
312 register_command(cmd_ctx, nand_cmd, "info", handle_nand_info_command, COMMAND_EXEC,
313 "print info about NAND flash device <num>");
314 register_command(cmd_ctx, nand_cmd, "probe", handle_nand_probe_command, COMMAND_EXEC,
315 "identify NAND flash device <num>");
316 register_command(cmd_ctx, nand_cmd, "check_bad_blocks", handle_nand_check_bad_blocks_command, COMMAND_EXEC,
317 "check NAND flash device <num> for bad blocks [<first> <last>]");
318 register_command(cmd_ctx, nand_cmd, "erase", handle_nand_erase_command, COMMAND_EXEC,
319 "erase blocks on NAND flash device <num> <first> <last>");
320 register_command(cmd_ctx, nand_cmd, "copy", handle_nand_copy_command, COMMAND_EXEC,
321 "copy from NAND flash device <num> <offset> <length> <ram-address>");
322 register_command(cmd_ctx, nand_cmd, "dump", handle_nand_dump_command, COMMAND_EXEC,
323 "dump from NAND flash device <num> <filename> <offset> <size> [options]");
324 register_command(cmd_ctx, nand_cmd, "write", handle_nand_write_command, COMMAND_EXEC,
325 "write to NAND flash device <num> <filename> <offset> [oob_raw|oob_only|oob_softecc]");
326 register_command(cmd_ctx, nand_cmd, "raw_access", handle_nand_raw_access_command, COMMAND_EXEC,
327 "raw access to NAND flash device <num> ['enable'|'disable']");
328 }
329
330 return ERROR_OK;
331 }
332
333 nand_device_t *get_nand_device_by_num(int num)
334 {
335 nand_device_t *p;
336 int i = 0;
337
338 for (p = nand_devices; p; p = p->next)
339 {
340 if (i++ == num)
341 {
342 return p;
343 }
344 }
345
346 return NULL;
347 }
348
349 int nand_build_bbt(struct nand_device_s *device, int first, int last)
350 {
351 u32 page = 0x0;
352 int i;
353 u8 oob[6];
354
355 if ((first < 0) || (first >= device->num_blocks))
356 first = 0;
357
358 if ((last >= device->num_blocks) || (last == -1))
359 last = device->num_blocks - 1;
360
361 for (i = first; i < last; i++)
362 {
363 nand_read_page(device, page, NULL, 0, oob, 6);
364
365 if (((device->device->options & NAND_BUSWIDTH_16) && ((oob[0] & oob[1]) != 0xff))
366 || (((device->page_size == 512) && (oob[5] != 0xff)) ||
367 ((device->page_size == 2048) && (oob[0] != 0xff))))
368 {
369 LOG_WARNING("invalid block: %i", i);
370 device->blocks[i].is_bad = 1;
371 }
372 else
373 {
374 device->blocks[i].is_bad = 0;
375 }
376
377 page += (device->erase_size / device->page_size);
378 }
379
380 return ERROR_OK;
381 }
382
383 int nand_read_status(struct nand_device_s *device, u8 *status)
384 {
385 if (!device->device)
386 return ERROR_NAND_DEVICE_NOT_PROBED;
387
388 /* Send read status command */
389 device->controller->command(device, NAND_CMD_STATUS);
390
391 alive_sleep(1);
392
393 /* read status */
394 if (device->device->options & NAND_BUSWIDTH_16)
395 {
396 u16 data;
397 device->controller->read_data(device, &data);
398 *status = data & 0xff;
399 }
400 else
401 {
402 device->controller->read_data(device, status);
403 }
404
405 return ERROR_OK;
406 }
407
408 int nand_poll_ready(struct nand_device_s *device, int timeout)
409 {
410 u8 status;
411
412 device->controller->command(device, NAND_CMD_STATUS);
413 do {
414 if (device->device->options & NAND_BUSWIDTH_16) {
415 u16 data;
416 device->controller->read_data(device, &data);
417 status = data & 0xff;
418 } else {
419 device->controller->read_data(device, &status);
420 }
421 if (status & NAND_STATUS_READY)
422 break;
423 alive_sleep(1);
424 } while (timeout--);
425
426 return (status & NAND_STATUS_READY) != 0;
427 }
428
429 int nand_probe(struct nand_device_s *device)
430 {
431 u8 manufacturer_id, device_id;
432 u8 id_buff[6];
433 int retval;
434 int i;
435
436 /* clear device data */
437 device->device = NULL;
438 device->manufacturer = NULL;
439
440 /* clear device parameters */
441 device->bus_width = 0;
442 device->address_cycles = 0;
443 device->page_size = 0;
444 device->erase_size = 0;
445
446 /* initialize controller (device parameters are zero, use controller default) */
447 if ((retval = device->controller->init(device) != ERROR_OK))
448 {
449 switch (retval)
450 {
451 case ERROR_NAND_OPERATION_FAILED:
452 LOG_DEBUG("controller initialization failed");
453 return ERROR_NAND_OPERATION_FAILED;
454 case ERROR_NAND_OPERATION_NOT_SUPPORTED:
455 LOG_ERROR("BUG: controller reported that it doesn't support default parameters");
456 return ERROR_NAND_OPERATION_FAILED;
457 default:
458 LOG_ERROR("BUG: unknown controller initialization failure");
459 return ERROR_NAND_OPERATION_FAILED;
460 }
461 }
462
463 device->controller->command(device, NAND_CMD_RESET);
464 device->controller->reset(device);
465
466 device->controller->command(device, NAND_CMD_READID);
467 device->controller->address(device, 0x0);
468
469 if (device->bus_width == 8)
470 {
471 device->controller->read_data(device, &manufacturer_id);
472 device->controller->read_data(device, &device_id);
473 }
474 else
475 {
476 u16 data_buf;
477 device->controller->read_data(device, &data_buf);
478 manufacturer_id = data_buf & 0xff;
479 device->controller->read_data(device, &data_buf);
480 device_id = data_buf & 0xff;
481 }
482
483 for (i = 0; nand_flash_ids[i].name; i++)
484 {
485 if (nand_flash_ids[i].id == device_id)
486 {
487 device->device = &nand_flash_ids[i];
488 break;
489 }
490 }
491
492 for (i = 0; nand_manuf_ids[i].name; i++)
493 {
494 if (nand_manuf_ids[i].id == manufacturer_id)
495 {
496 device->manufacturer = &nand_manuf_ids[i];
497 break;
498 }
499 }
500
501 if (!device->manufacturer)
502 {
503 device->manufacturer = &nand_manuf_ids[0];
504 device->manufacturer->id = manufacturer_id;
505 }
506
507 if (!device->device)
508 {
509 LOG_ERROR("unknown NAND flash device found, manufacturer id: 0x%2.2x device id: 0x%2.2x",
510 manufacturer_id, device_id);
511 return ERROR_NAND_OPERATION_FAILED;
512 }
513
514 LOG_DEBUG("found %s (%s)", device->device->name, device->manufacturer->name);
515
516 /* initialize device parameters */
517
518 /* bus width */
519 if (device->device->options & NAND_BUSWIDTH_16)
520 device->bus_width = 16;
521 else
522 device->bus_width = 8;
523
524 /* Do we need extended device probe information? */
525 if (device->device->page_size == 0 ||
526 device->device->erase_size == 0)
527 {
528 if (device->bus_width == 8)
529 {
530 device->controller->read_data(device, id_buff+3);
531 device->controller->read_data(device, id_buff+4);
532 device->controller->read_data(device, id_buff+5);
533 }
534 else
535 {
536 u16 data_buf;
537
538 device->controller->read_data(device, &data_buf);
539 id_buff[3] = data_buf;
540
541 device->controller->read_data(device, &data_buf);
542 id_buff[4] = data_buf;
543
544 device->controller->read_data(device, &data_buf);
545 id_buff[5] = data_buf >> 8;
546 }
547 }
548
549 /* page size */
550 if (device->device->page_size == 0)
551 {
552 device->page_size = 1 << (10 + (id_buff[4] & 3));
553 }
554 else if (device->device->page_size == 256)
555 {
556 LOG_ERROR("NAND flashes with 256 byte pagesize are not supported");
557 return ERROR_NAND_OPERATION_FAILED;
558 }
559 else
560 {
561 device->page_size = device->device->page_size;
562 }
563
564 /* number of address cycles */
565 if (device->page_size <= 512)
566 {
567 /* small page devices */
568 if (device->device->chip_size <= 32)
569 device->address_cycles = 3;
570 else if (device->device->chip_size <= 8*1024)
571 device->address_cycles = 4;
572 else
573 {
574 LOG_ERROR("BUG: small page NAND device with more than 8 GiB encountered");
575 device->address_cycles = 5;
576 }
577 }
578 else
579 {
580 /* large page devices */
581 if (device->device->chip_size <= 128)
582 device->address_cycles = 4;
583 else if (device->device->chip_size <= 32*1024)
584 device->address_cycles = 5;
585 else
586 {
587 LOG_ERROR("BUG: large page NAND device with more than 32 GiB encountered");
588 device->address_cycles = 6;
589 }
590 }
591
592 /* erase size */
593 if (device->device->erase_size == 0)
594 {
595 switch ((id_buff[4] >> 4) & 3) {
596 case 0:
597 device->erase_size = 64 << 10;
598 break;
599 case 1:
600 device->erase_size = 128 << 10;
601 break;
602 case 2:
603 device->erase_size = 256 << 10;
604 break;
605 case 3:
606 device->erase_size =512 << 10;
607 break;
608 }
609 }
610 else
611 {
612 device->erase_size = device->device->erase_size;
613 }
614
615 /* initialize controller, but leave parameters at the controllers default */
616 if ((retval = device->controller->init(device) != ERROR_OK))
617 {
618 switch (retval)
619 {
620 case ERROR_NAND_OPERATION_FAILED:
621 LOG_DEBUG("controller initialization failed");
622 return ERROR_NAND_OPERATION_FAILED;
623 case ERROR_NAND_OPERATION_NOT_SUPPORTED:
624 LOG_ERROR("controller doesn't support requested parameters (buswidth: %i, address cycles: %i, page size: %i)",
625 device->bus_width, device->address_cycles, device->page_size);
626 return ERROR_NAND_OPERATION_FAILED;
627 default:
628 LOG_ERROR("BUG: unknown controller initialization failure");
629 return ERROR_NAND_OPERATION_FAILED;
630 }
631 }
632
633 device->num_blocks = (device->device->chip_size * 1024) / (device->erase_size / 1024);
634 device->blocks = malloc(sizeof(nand_block_t) * device->num_blocks);
635
636 for (i = 0; i < device->num_blocks; i++)
637 {
638 device->blocks[i].size = device->erase_size;
639 device->blocks[i].offset = i * device->erase_size;
640 device->blocks[i].is_erased = -1;
641 device->blocks[i].is_bad = -1;
642 }
643
644 return ERROR_OK;
645 }
646
647 int nand_erase(struct nand_device_s *device, int first_block, int last_block)
648 {
649 int i;
650 u32 page;
651 u8 status;
652 int retval;
653
654 if (!device->device)
655 return ERROR_NAND_DEVICE_NOT_PROBED;
656
657 if ((first_block < 0) || (last_block > device->num_blocks))
658 return ERROR_INVALID_ARGUMENTS;
659
660 /* make sure we know if a block is bad before erasing it */
661 for (i = first_block; i <= last_block; i++)
662 {
663 if (device->blocks[i].is_bad == -1)
664 {
665 nand_build_bbt(device, i, last_block);
666 break;
667 }
668 }
669
670 for (i = first_block; i <= last_block; i++)
671 {
672 /* Send erase setup command */
673 device->controller->command(device, NAND_CMD_ERASE1);
674
675 page = i * (device->erase_size / device->page_size);
676
677 /* Send page address */
678 if (device->page_size <= 512)
679 {
680 /* row */
681 device->controller->address(device, page & 0xff);
682 device->controller->address(device, (page >> 8) & 0xff);
683
684 /* 3rd cycle only on devices with more than 32 MiB */
685 if (device->address_cycles >= 4)
686 device->controller->address(device, (page >> 16) & 0xff);
687
688 /* 4th cycle only on devices with more than 8 GiB */
689 if (device->address_cycles >= 5)
690 device->controller->address(device, (page >> 24) & 0xff);
691 }
692 else
693 {
694 /* row */
695 device->controller->address(device, page & 0xff);
696 device->controller->address(device, (page >> 8) & 0xff);
697
698 /* 3rd cycle only on devices with more than 128 MiB */
699 if (device->address_cycles >= 5)
700 device->controller->address(device, (page >> 16) & 0xff);
701 }
702
703 /* Send erase confirm command */
704 device->controller->command(device, NAND_CMD_ERASE2);
705
706 retval = device->controller->nand_ready ?
707 device->controller->nand_ready(device, 1000) :
708 nand_poll_ready(device, 1000);
709 if (!retval) {
710 LOG_ERROR("timeout waiting for NAND flash block erase to complete");
711 return ERROR_NAND_OPERATION_TIMEOUT;
712 }
713
714 if ((retval = nand_read_status(device, &status)) != ERROR_OK)
715 {
716 LOG_ERROR("couldn't read status");
717 return ERROR_NAND_OPERATION_FAILED;
718 }
719
720 if (status & 0x1)
721 {
722 LOG_ERROR("erase operation didn't pass, status: 0x%2.2x", status);
723 return ERROR_NAND_OPERATION_FAILED;
724 }
725
726 device->blocks[i].is_erased = 1;
727 }
728
729 return ERROR_OK;
730 }
731
732 int nand_read_plain(struct nand_device_s *device, u32 address, u8 *data, u32 data_size)
733 {
734 u8 *page;
735
736 if (!device->device)
737 return ERROR_NAND_DEVICE_NOT_PROBED;
738
739 if (address % device->page_size)
740 {
741 LOG_ERROR("reads need to be page aligned");
742 return ERROR_NAND_OPERATION_FAILED;
743 }
744
745 page = malloc(device->page_size);
746
747 while (data_size > 0 )
748 {
749 u32 thisrun_size = (data_size > device->page_size) ? device->page_size : data_size;
750 u32 page_address;
751
752
753 page_address = address / device->page_size;
754
755 nand_read_page(device, page_address, page, device->page_size, NULL, 0);
756
757 memcpy(data, page, thisrun_size);
758
759 address += thisrun_size;
760 data += thisrun_size;
761 data_size -= thisrun_size;
762 }
763
764 free(page);
765
766 return ERROR_OK;
767 }
768
769 int nand_write_plain(struct nand_device_s *device, u32 address, u8 *data, u32 data_size)
770 {
771 u8 *page;
772
773 if (!device->device)
774 return ERROR_NAND_DEVICE_NOT_PROBED;
775
776 if (address % device->page_size)
777 {
778 LOG_ERROR("writes need to be page aligned");
779 return ERROR_NAND_OPERATION_FAILED;
780 }
781
782 page = malloc(device->page_size);
783
784 while (data_size > 0 )
785 {
786 u32 thisrun_size = (data_size > device->page_size) ? device->page_size : data_size;
787 u32 page_address;
788
789 memset(page, 0xff, device->page_size);
790 memcpy(page, data, thisrun_size);
791
792 page_address = address / device->page_size;
793
794 nand_write_page(device, page_address, page, device->page_size, NULL, 0);
795
796 address += thisrun_size;
797 data += thisrun_size;
798 data_size -= thisrun_size;
799 }
800
801 free(page);
802
803 return ERROR_OK;
804 }
805
806 int nand_write_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
807 {
808 u32 block;
809
810 if (!device->device)
811 return ERROR_NAND_DEVICE_NOT_PROBED;
812
813 block = page / (device->erase_size / device->page_size);
814 if (device->blocks[block].is_erased == 1)
815 device->blocks[block].is_erased = 0;
816
817 if (device->use_raw || device->controller->write_page == NULL)
818 return nand_write_page_raw(device, page, data, data_size, oob, oob_size);
819 else
820 return device->controller->write_page(device, page, data, data_size, oob, oob_size);
821 }
822
823 int nand_read_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
824 {
825 if (!device->device)
826 return ERROR_NAND_DEVICE_NOT_PROBED;
827
828 if (device->use_raw || device->controller->read_page == NULL)
829 return nand_read_page_raw(device, page, data, data_size, oob, oob_size);
830 else
831 return device->controller->read_page(device, page, data, data_size, oob, oob_size);
832 }
833
834 int nand_read_page_raw(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
835 {
836 int i;
837
838 if (!device->device)
839 return ERROR_NAND_DEVICE_NOT_PROBED;
840
841 if (device->page_size <= 512)
842 {
843 /* small page device */
844 if (data)
845 device->controller->command(device, NAND_CMD_READ0);
846 else
847 device->controller->command(device, NAND_CMD_READOOB);
848
849 /* column (always 0, we start at the beginning of a page/OOB area) */
850 device->controller->address(device, 0x0);
851
852 /* row */
853 device->controller->address(device, page & 0xff);
854 device->controller->address(device, (page >> 8) & 0xff);
855
856 /* 4th cycle only on devices with more than 32 MiB */
857 if (device->address_cycles >= 4)
858 device->controller->address(device, (page >> 16) & 0xff);
859
860 /* 5th cycle only on devices with more than 8 GiB */
861 if (device->address_cycles >= 5)
862 device->controller->address(device, (page >> 24) & 0xff);
863 }
864 else
865 {
866 /* large page device */
867 device->controller->command(device, NAND_CMD_READ0);
868
869 /* column (0 when we start at the beginning of a page,
870 * or 2048 for the beginning of OOB area)
871 */
872 device->controller->address(device, 0x0);
873 if (data)
874 device->controller->address(device, 0x0);
875 else
876 device->controller->address(device, 0x8);
877
878 /* row */
879 device->controller->address(device, page & 0xff);
880 device->controller->address(device, (page >> 8) & 0xff);
881
882 /* 5th cycle only on devices with more than 128 MiB */
883 if (device->address_cycles >= 5)
884 device->controller->address(device, (page >> 16) & 0xff);
885
886 /* large page devices need a start command */
887 device->controller->command(device, NAND_CMD_READSTART);
888 }
889
890 if (device->controller->nand_ready) {
891 if (!device->controller->nand_ready(device, 100))
892 return ERROR_NAND_OPERATION_TIMEOUT;
893 } else {
894 alive_sleep(1);
895 }
896
897 if (data)
898 {
899 if (device->controller->read_block_data != NULL)
900 (device->controller->read_block_data)(device, data, data_size);
901 else
902 {
903 for (i = 0; i < data_size;)
904 {
905 if (device->device->options & NAND_BUSWIDTH_16)
906 {
907 device->controller->read_data(device, data);
908 data += 2;
909 i += 2;
910 }
911 else
912 {
913 device->controller->read_data(device, data);
914 data += 1;
915 i += 1;
916 }
917 }
918 }
919 }
920
921 if (oob)
922 {
923 if (device->controller->read_block_data != NULL)
924 (device->controller->read_block_data)(device, oob, oob_size);
925 else
926 {
927 for (i = 0; i < oob_size;)
928 {
929 if (device->device->options & NAND_BUSWIDTH_16)
930 {
931 device->controller->read_data(device, oob);
932 oob += 2;
933 i += 2;
934 }
935 else
936 {
937 device->controller->read_data(device, oob);
938 oob += 1;
939 i += 1;
940 }
941 }
942 }
943 }
944
945 return ERROR_OK;
946 }
947
948 int nand_write_page_raw(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
949 {
950 int i;
951 int retval;
952 u8 status;
953
954 if (!device->device)
955 return ERROR_NAND_DEVICE_NOT_PROBED;
956
957 device->controller->command(device, NAND_CMD_SEQIN);
958
959 if (device->page_size <= 512)
960 {
961 /* column (always 0, we start at the beginning of a page/OOB area) */
962 device->controller->address(device, 0x0);
963
964 /* row */
965 device->controller->address(device, page & 0xff);
966 device->controller->address(device, (page >> 8) & 0xff);
967
968 /* 4th cycle only on devices with more than 32 MiB */
969 if (device->address_cycles >= 4)
970 device->controller->address(device, (page >> 16) & 0xff);
971
972 /* 5th cycle only on devices with more than 8 GiB */
973 if (device->address_cycles >= 5)
974 device->controller->address(device, (page >> 24) & 0xff);
975 }
976 else
977 {
978 /* column (0 when we start at the beginning of a page,
979 * or 2048 for the beginning of OOB area)
980 */
981 device->controller->address(device, 0x0);
982 if (data)
983 device->controller->address(device, 0x0);
984 else
985 device->controller->address(device, 0x8);
986
987 /* row */
988 device->controller->address(device, page & 0xff);
989 device->controller->address(device, (page >> 8) & 0xff);
990
991 /* 5th cycle only on devices with more than 128 MiB */
992 if (device->address_cycles >= 5)
993 device->controller->address(device, (page >> 16) & 0xff);
994 }
995
996 if (data)
997 {
998 if (device->controller->write_block_data != NULL)
999 (device->controller->write_block_data)(device, data, data_size);
1000 else
1001 {
1002 for (i = 0; i < data_size;)
1003 {
1004 if (device->device->options & NAND_BUSWIDTH_16)
1005 {
1006 u16 data_buf = le_to_h_u16(data);
1007 device->controller->write_data(device, data_buf);
1008 data += 2;
1009 i += 2;
1010 }
1011 else
1012 {
1013 device->controller->write_data(device, *data);
1014 data += 1;
1015 i += 1;
1016 }
1017 }
1018 }
1019 }
1020
1021 if (oob)
1022 {
1023 if (device->controller->write_block_data != NULL)
1024 (device->controller->write_block_data)(device, oob, oob_size);
1025 else
1026 {
1027 for (i = 0; i < oob_size;)
1028 {
1029 if (device->device->options & NAND_BUSWIDTH_16)
1030 {
1031 u16 oob_buf = le_to_h_u16(data);
1032 device->controller->write_data(device, oob_buf);
1033 oob += 2;
1034 i += 2;
1035 }
1036 else
1037 {
1038 device->controller->write_data(device, *oob);
1039 oob += 1;
1040 i += 1;
1041 }
1042 }
1043 }
1044 }
1045
1046 device->controller->command(device, NAND_CMD_PAGEPROG);
1047
1048 retval = device->controller->nand_ready ?
1049 device->controller->nand_ready(device, 100) :
1050 nand_poll_ready(device, 100);
1051 if (!retval)
1052 return ERROR_NAND_OPERATION_TIMEOUT;
1053
1054 if ((retval = nand_read_status(device, &status)) != ERROR_OK)
1055 {
1056 LOG_ERROR("couldn't read status");
1057 return ERROR_NAND_OPERATION_FAILED;
1058 }
1059
1060 if (status & NAND_STATUS_FAIL)
1061 {
1062 LOG_ERROR("write operation didn't pass, status: 0x%2.2x", status);
1063 return ERROR_NAND_OPERATION_FAILED;
1064 }
1065
1066 return ERROR_OK;
1067 }
1068
1069 int handle_nand_list_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1070 {
1071 nand_device_t *p;
1072 int i = 0;
1073
1074 if (!nand_devices)
1075 {
1076 command_print(cmd_ctx, "no NAND flash devices configured");
1077 return ERROR_OK;
1078 }
1079
1080 for (p = nand_devices; p; p = p->next)
1081 {
1082 if (p->device)
1083 command_print(cmd_ctx, "#%i: %s (%s) pagesize: %i, buswidth: %i, erasesize: %i",
1084 i++, p->device->name, p->manufacturer->name, p->page_size, p->bus_width, p->erase_size);
1085 else
1086 command_print(cmd_ctx, "#%i: not probed");
1087 }
1088
1089 return ERROR_OK;
1090 }
1091
1092 int handle_nand_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1093 {
1094 nand_device_t *p;
1095 int i = 0;
1096 int j = 0;
1097 int first = -1;
1098 int last = -1;
1099
1100 if ((argc < 1) || (argc > 3))
1101 {
1102 return ERROR_COMMAND_SYNTAX_ERROR;
1103
1104 }
1105
1106 if (argc == 2)
1107 {
1108 first = last = strtoul(args[1], NULL, 0);
1109 }
1110 else if (argc == 3)
1111 {
1112 first = strtoul(args[1], NULL, 0);
1113 last = strtoul(args[2], NULL, 0);
1114 }
1115
1116 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1117 if (p)
1118 {
1119 if (p->device)
1120 {
1121 if (first >= p->num_blocks)
1122 first = p->num_blocks - 1;
1123
1124 if (last >= p->num_blocks)
1125 last = p->num_blocks - 1;
1126
1127 command_print(cmd_ctx, "#%i: %s (%s) pagesize: %i, buswidth: %i, erasesize: %i",
1128 i++, p->device->name, p->manufacturer->name, p->page_size, p->bus_width, p->erase_size);
1129
1130 for (j = first; j <= last; j++)
1131 {
1132 char *erase_state, *bad_state;
1133
1134 if (p->blocks[j].is_erased == 0)
1135 erase_state = "not erased";
1136 else if (p->blocks[j].is_erased == 1)
1137 erase_state = "erased";
1138 else
1139 erase_state = "erase state unknown";
1140
1141 if (p->blocks[j].is_bad == 0)
1142 bad_state = "";
1143 else if (p->blocks[j].is_bad == 1)
1144 bad_state = " (marked bad)";
1145 else
1146 bad_state = " (block condition unknown)";
1147
1148 command_print(cmd_ctx, "\t#%i: 0x%8.8x (0x%xkB) %s%s",
1149 j, p->blocks[j].offset, p->blocks[j].size / 1024,
1150 erase_state, bad_state);
1151 }
1152 }
1153 else
1154 {
1155 command_print(cmd_ctx, "#%i: not probed");
1156 }
1157 }
1158
1159 return ERROR_OK;
1160 }
1161
1162 int handle_nand_probe_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1163 {
1164 nand_device_t *p;
1165 int retval;
1166
1167 if (argc != 1)
1168 {
1169 return ERROR_COMMAND_SYNTAX_ERROR;
1170 }
1171
1172 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1173 if (p)
1174 {
1175 if ((retval = nand_probe(p)) == ERROR_OK)
1176 {
1177 command_print(cmd_ctx, "NAND flash device '%s' found", p->device->name);
1178 }
1179 else if (retval == ERROR_NAND_OPERATION_FAILED)
1180 {
1181 command_print(cmd_ctx, "probing failed for NAND flash device");
1182 }
1183 else
1184 {
1185 command_print(cmd_ctx, "unknown error when probing NAND flash device");
1186 }
1187 }
1188 else
1189 {
1190 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1191 }
1192
1193 return ERROR_OK;
1194 }
1195
1196 int handle_nand_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1197 {
1198 nand_device_t *p;
1199 int retval;
1200
1201 if (argc != 3)
1202 {
1203 return ERROR_COMMAND_SYNTAX_ERROR;
1204
1205 }
1206
1207 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1208 if (p)
1209 {
1210 int first = strtoul(args[1], NULL, 0);
1211 int last = strtoul(args[2], NULL, 0);
1212
1213 if ((retval = nand_erase(p, first, last)) == ERROR_OK)
1214 {
1215 command_print(cmd_ctx, "successfully erased blocks %i to %i on NAND flash device '%s'", first, last, p->device->name);
1216 }
1217 else if (retval == ERROR_NAND_OPERATION_FAILED)
1218 {
1219 command_print(cmd_ctx, "erase failed");
1220 }
1221 else
1222 {
1223 command_print(cmd_ctx, "unknown error when erasing NAND flash device");
1224 }
1225 }
1226 else
1227 {
1228 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1229 }
1230
1231 return ERROR_OK;
1232 }
1233
1234 int handle_nand_check_bad_blocks_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1235 {
1236 nand_device_t *p;
1237 int retval;
1238 int first = -1;
1239 int last = -1;
1240
1241 if ((argc < 1) || (argc > 3) || (argc == 2))
1242 {
1243 return ERROR_COMMAND_SYNTAX_ERROR;
1244
1245 }
1246
1247 if (argc == 3)
1248 {
1249 first = strtoul(args[1], NULL, 0);
1250 last = strtoul(args[2], NULL, 0);
1251 }
1252
1253 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1254 if (p)
1255 {
1256 if ((retval = nand_build_bbt(p, first, last)) == ERROR_OK)
1257 {
1258 command_print(cmd_ctx, "checked NAND flash device for bad blocks, use \"nand info\" command to list blocks", p->device->name);
1259 }
1260 else if (retval == ERROR_NAND_OPERATION_FAILED)
1261 {
1262 command_print(cmd_ctx, "error when checking for bad blocks on NAND flash device");
1263 }
1264 else
1265 {
1266 command_print(cmd_ctx, "unknown error when checking for bad blocks on NAND flash device");
1267 }
1268 }
1269 else
1270 {
1271 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1272 }
1273
1274 return ERROR_OK;
1275 }
1276
1277 int handle_nand_copy_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1278 {
1279 nand_device_t *p;
1280
1281 if (argc != 4)
1282 {
1283 return ERROR_COMMAND_SYNTAX_ERROR;
1284
1285 }
1286
1287 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1288 if (p)
1289 {
1290
1291 }
1292 else
1293 {
1294 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1295 }
1296
1297 return ERROR_OK;
1298 }
1299
1300 int handle_nand_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1301 {
1302 u32 offset;
1303 u32 binary_size;
1304 u32 buf_cnt;
1305 enum oob_formats oob_format = NAND_OOB_NONE;
1306
1307 fileio_t fileio;
1308
1309 duration_t duration;
1310 char *duration_text;
1311
1312 nand_device_t *p;
1313
1314 if (argc < 3)
1315 {
1316 return ERROR_COMMAND_SYNTAX_ERROR;
1317
1318 }
1319
1320 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1321 if (p)
1322 {
1323 u8 *page = NULL;
1324 u32 page_size = 0;
1325 u8 *oob = NULL;
1326 u32 oob_size = 0;
1327 const int *eccpos = NULL;
1328
1329 offset = strtoul(args[2], NULL, 0);
1330
1331 if (argc > 3)
1332 {
1333 int i;
1334 for (i = 3; i < argc; i++)
1335 {
1336 if (!strcmp(args[i], "oob_raw"))
1337 oob_format |= NAND_OOB_RAW;
1338 else if (!strcmp(args[i], "oob_only"))
1339 oob_format |= NAND_OOB_RAW | NAND_OOB_ONLY;
1340 else if (!strcmp(args[i], "oob_softecc"))
1341 oob_format |= NAND_OOB_SW_ECC;
1342 else
1343 {
1344 command_print(cmd_ctx, "unknown option: %s", args[i]);
1345 return ERROR_COMMAND_SYNTAX_ERROR;
1346 }
1347 }
1348 }
1349
1350 duration_start_measure(&duration);
1351
1352 if (fileio_open(&fileio, args[1], FILEIO_READ, FILEIO_BINARY) != ERROR_OK)
1353 {
1354 return ERROR_OK;
1355 }
1356
1357 buf_cnt = binary_size = fileio.size;
1358
1359 if (!(oob_format & NAND_OOB_ONLY))
1360 {
1361 page_size = p->page_size;
1362 page = malloc(p->page_size);
1363 }
1364
1365 if (oob_format & (NAND_OOB_RAW | NAND_OOB_SW_ECC))
1366 {
1367 if (p->page_size == 512) {
1368 oob_size = 16;
1369 eccpos = nand_oob_16.eccpos;
1370 } else if (p->page_size == 2048) {
1371 oob_size = 64;
1372 eccpos = nand_oob_64.eccpos;
1373 }
1374 oob = malloc(oob_size);
1375 }
1376
1377 if (offset % p->page_size)
1378 {
1379 command_print(cmd_ctx, "only page size aligned offsets and sizes are supported");
1380 fileio_close(&fileio);
1381 free(oob);
1382 free(page);
1383 return ERROR_OK;
1384 }
1385
1386 while (buf_cnt > 0)
1387 {
1388 u32 size_read;
1389
1390 if (NULL != page)
1391 {
1392 fileio_read(&fileio, page_size, page, &size_read);
1393 buf_cnt -= size_read;
1394 if (size_read < page_size)
1395 {
1396 memset(page + size_read, 0xff, page_size - size_read);
1397 }
1398 }
1399
1400 if (oob_format & NAND_OOB_SW_ECC)
1401 {
1402 int i, j;
1403 u8 ecc[3];
1404 memset(oob, 0xff, oob_size);
1405 for (i = 0, j = 0; i < page_size; i += 256) {
1406 nand_calculate_ecc(p, page+i, ecc);
1407 oob[eccpos[j++]] = ecc[0];
1408 oob[eccpos[j++]] = ecc[1];
1409 oob[eccpos[j++]] = ecc[2];
1410 }
1411 }
1412 else if (NULL != oob)
1413 {
1414 fileio_read(&fileio, oob_size, oob, &size_read);
1415 buf_cnt -= size_read;
1416 if (size_read < oob_size)
1417 {
1418 memset(oob + size_read, 0xff, oob_size - size_read);
1419 }
1420 }
1421
1422 if (nand_write_page(p, offset / p->page_size, page, page_size, oob, oob_size) != ERROR_OK)
1423 {
1424 command_print(cmd_ctx, "failed writing file %s to NAND flash %s at offset 0x%8.8x",
1425 args[1], args[0], offset);
1426
1427 fileio_close(&fileio);
1428 free(oob);
1429 free(page);
1430
1431 return ERROR_OK;
1432 }
1433 offset += page_size;
1434 }
1435
1436 fileio_close(&fileio);
1437 free(oob);
1438 free(page);
1439 oob = NULL;
1440 page = NULL;
1441 duration_stop_measure(&duration, &duration_text);
1442 command_print(cmd_ctx, "wrote file %s to NAND flash %s up to offset 0x%8.8x in %s",
1443 args[1], args[0], offset, duration_text);
1444 free(duration_text);
1445 duration_text = NULL;
1446 }
1447 else
1448 {
1449 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1450 }
1451
1452 return ERROR_OK;
1453 }
1454
1455 int handle_nand_dump_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1456 {
1457 nand_device_t *p;
1458
1459 if (argc < 4)
1460 {
1461 return ERROR_COMMAND_SYNTAX_ERROR;
1462 }
1463
1464 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1465 if (p)
1466 {
1467 if (p->device)
1468 {
1469 fileio_t fileio;
1470 duration_t duration;
1471 char *duration_text;
1472 int retval;
1473
1474 u8 *page = NULL;
1475 u32 page_size = 0;
1476 u8 *oob = NULL;
1477 u32 oob_size = 0;
1478 u32 address = strtoul(args[2], NULL, 0);
1479 u32 size = strtoul(args[3], NULL, 0);
1480 u32 bytes_done = 0;
1481 enum oob_formats oob_format = NAND_OOB_NONE;
1482
1483 if (argc > 4)
1484 {
1485 int i;
1486 for (i = 4; i < argc; i++)
1487 {
1488 if (!strcmp(args[i], "oob_raw"))
1489 oob_format |= NAND_OOB_RAW;
1490 else if (!strcmp(args[i], "oob_only"))
1491 oob_format |= NAND_OOB_RAW | NAND_OOB_ONLY;
1492 else
1493 command_print(cmd_ctx, "unknown option: '%s'", args[i]);
1494 }
1495 }
1496
1497 if ((address % p->page_size) || (size % p->page_size))
1498 {
1499 command_print(cmd_ctx, "only page size aligned addresses and sizes are supported");
1500 return ERROR_OK;
1501 }
1502
1503 if (!(oob_format & NAND_OOB_ONLY))
1504 {
1505 page_size = p->page_size;
1506 page = malloc(p->page_size);
1507 }
1508
1509 if (oob_format & NAND_OOB_RAW)
1510 {
1511 if (p->page_size == 512)
1512 oob_size = 16;
1513 else if (p->page_size == 2048)
1514 oob_size = 64;
1515 oob = malloc(oob_size);
1516 }
1517
1518 if (fileio_open(&fileio, args[1], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
1519 {
1520 return ERROR_OK;
1521 }
1522
1523 duration_start_measure(&duration);
1524
1525 while (size > 0)
1526 {
1527 u32 size_written;
1528 if ((retval = nand_read_page(p, address / p->page_size, page, page_size, oob, oob_size)) != ERROR_OK)
1529 {
1530 command_print(cmd_ctx, "reading NAND flash page failed");
1531 free(page);
1532 free(oob);
1533 fileio_close(&fileio);
1534 return ERROR_OK;
1535 }
1536
1537 if (NULL != page)
1538 {
1539 fileio_write(&fileio, page_size, page, &size_written);
1540 bytes_done += page_size;
1541 }
1542
1543 if (NULL != oob)
1544 {
1545 fileio_write(&fileio, oob_size, oob, &size_written);
1546 bytes_done += oob_size;
1547 }
1548
1549 size -= p->page_size;
1550 address += p->page_size;
1551 }
1552
1553 free(page);
1554 page = NULL;
1555 free(oob);
1556 oob = NULL;
1557 fileio_close(&fileio);
1558
1559 duration_stop_measure(&duration, &duration_text);
1560 command_print(cmd_ctx, "dumped %"PRIi64" byte in %s", fileio.size, duration_text);
1561 free(duration_text);
1562 duration_text = NULL;
1563 }
1564 else
1565 {
1566 command_print(cmd_ctx, "#%i: not probed");
1567 }
1568 }
1569 else
1570 {
1571 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1572 }
1573
1574 return ERROR_OK;
1575 }
1576
1577 int handle_nand_raw_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1578 {
1579 nand_device_t *p;
1580
1581 if ((argc < 1) || (argc > 2))
1582 {
1583 return ERROR_COMMAND_SYNTAX_ERROR;
1584 }
1585
1586 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1587 if (p)
1588 {
1589 if (p->device)
1590 {
1591 if (argc == 2)
1592 {
1593 if (strcmp("enable", args[1]) == 0)
1594 {
1595 p->use_raw = 1;
1596 }
1597 else if (strcmp("disable", args[1]) == 0)
1598 {
1599 p->use_raw = 0;
1600 }
1601 else
1602 {
1603 return ERROR_COMMAND_SYNTAX_ERROR;
1604 }
1605 }
1606
1607 command_print(cmd_ctx, "raw access is %s", (p->use_raw) ? "enabled" : "disabled");
1608 }
1609 else
1610 {
1611 command_print(cmd_ctx, "#%i: not probed");
1612 }
1613 }
1614 else
1615 {
1616 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1617 }
1618
1619 return ERROR_OK;
1620 }
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