2 /***************************************************************************
3 * Copyright (C) 2009 by Alexei Babich *
4 * Rezonans plc., Chelyabinsk, Russia *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
21 ***************************************************************************/
24 * Freescale iMX3* OpenOCD NAND Flash controller support.
26 * Many thanks to Ben Dooks for writing s3c24xx driver.
30 driver tested with STMicro NAND512W3A @imx31
31 tested "nand probe #", "nand erase # 0 #", "nand dump # file 0 #", "nand write # file 0"
32 get_next_halfword_from_sram_buffer() not tested
40 #include <target/target.h>
42 static const char target_not_halted_err_msg
[] =
43 "target must be halted to use mx3 NAND flash controller";
44 static const char data_block_size_err_msg
[] =
45 "minimal granularity is one half-word, %" PRId32
" is incorrect";
46 static const char sram_buffer_bounds_err_msg
[] =
47 "trying to access out of SRAM buffer bound (addr=0x%" PRIx32
")";
48 static const char get_status_register_err_msg
[] = "can't get NAND status";
49 static uint32_t in_sram_address
;
50 static unsigned char sign_of_sequental_byte_read
;
52 static int test_iomux_settings (struct target
* target
, uint32_t value
,
53 uint32_t mask
, const char *text
);
54 static int initialize_nf_controller (struct nand_device
*nand
);
55 static int get_next_byte_from_sram_buffer (struct target
* target
, uint8_t * value
);
56 static int get_next_halfword_from_sram_buffer (struct target
* target
,
58 static int poll_for_complete_op (struct target
* target
, const char *text
);
59 static int validate_target_state (struct nand_device
*nand
);
60 static int do_data_output (struct nand_device
*nand
);
62 static int imx31_command (struct nand_device
*nand
, uint8_t command
);
63 static int imx31_address (struct nand_device
*nand
, uint8_t address
);
64 static int imx31_controller_ready (struct nand_device
*nand
, int tout
);
66 NAND_DEVICE_COMMAND_HANDLER(imx31_nand_device_command
)
68 struct mx3_nf_controller
*mx3_nf_info
;
69 mx3_nf_info
= malloc (sizeof (struct mx3_nf_controller
));
70 if (mx3_nf_info
== NULL
)
72 LOG_ERROR ("no memory for nand controller");
76 nand
->controller_priv
= mx3_nf_info
;
78 mx3_nf_info
->target
= get_target (CMD_ARGV
[1]);
79 if (mx3_nf_info
->target
== NULL
)
81 LOG_ERROR ("target '%s' not defined", CMD_ARGV
[1]);
86 LOG_ERROR ("use \"nand device imx31 target noecc|hwecc\"");
90 * check hwecc requirements
94 hwecc_needed
= strcmp (CMD_ARGV
[2], "hwecc");
95 if (hwecc_needed
== 0)
97 mx3_nf_info
->flags
.hw_ecc_enabled
= 1;
101 mx3_nf_info
->flags
.hw_ecc_enabled
= 0;
105 mx3_nf_info
->optype
= MX3_NF_DATAOUT_PAGE
;
106 mx3_nf_info
->fin
= MX3_NF_FIN_NONE
;
107 mx3_nf_info
->flags
.target_little_endian
=
108 (mx3_nf_info
->target
->endianness
== TARGET_LITTLE_ENDIAN
);
110 * testing host endianess
114 if (*(char *) &x
== 1)
116 mx3_nf_info
->flags
.host_little_endian
= 1;
120 mx3_nf_info
->flags
.host_little_endian
= 0;
126 static int imx31_init (struct nand_device
*nand
)
128 struct mx3_nf_controller
*mx3_nf_info
= nand
->controller_priv
;
129 struct target
*target
= mx3_nf_info
->target
;
133 * validate target state
135 int validate_target_result
;
136 validate_target_result
= validate_target_state(nand
);
137 if (validate_target_result
!= ERROR_OK
)
139 return validate_target_result
;
144 uint16_t buffsize_register_content
;
145 target_read_u16 (target
, MX3_NF_BUFSIZ
, &buffsize_register_content
);
146 mx3_nf_info
->flags
.one_kb_sram
= !(buffsize_register_content
& 0x000f);
150 uint32_t pcsr_register_content
;
151 target_read_u32 (target
, MX3_PCSR
, &pcsr_register_content
);
152 if (!nand
->bus_width
)
155 (pcsr_register_content
& 0x80000000) ? 16 : 8;
159 pcsr_register_content
|=
160 ((nand
->bus_width
== 16) ? 0x80000000 : 0x00000000);
161 target_write_u32 (target
, MX3_PCSR
, pcsr_register_content
);
164 if (!nand
->page_size
)
167 (pcsr_register_content
& 0x40000000) ? 2048 : 512;
171 pcsr_register_content
|=
172 ((nand
->page_size
== 2048) ? 0x40000000 : 0x00000000);
173 target_write_u32 (target
, MX3_PCSR
, pcsr_register_content
);
175 if (mx3_nf_info
->flags
.one_kb_sram
&& (nand
->page_size
== 2048))
178 ("NAND controller have only 1 kb SRAM, so pagesize 2048 is incompatible with it");
183 uint32_t cgr_register_content
;
184 target_read_u32 (target
, MX3_CCM_CGR2
, &cgr_register_content
);
185 if (!(cgr_register_content
& 0x00000300))
187 LOG_ERROR ("clock gating to EMI disabled");
193 uint32_t gpr_register_content
;
194 target_read_u32 (target
, MX3_GPR
, &gpr_register_content
);
195 if (gpr_register_content
& 0x00000060)
197 LOG_ERROR ("pins mode overrided by GPR");
204 * testing IOMUX settings; must be in "functional-mode output and
205 * functional-mode input" mode
208 test_iomux
= ERROR_OK
;
210 test_iomux_settings (target
, 0x43fac0c0, 0x7f7f7f00, "d0,d1,d2");
212 test_iomux_settings (target
, 0x43fac0c4, 0x7f7f7f7f, "d3,d4,d5,d6");
214 test_iomux_settings (target
, 0x43fac0c8, 0x0000007f, "d7");
215 if (nand
->bus_width
== 16)
218 test_iomux_settings (target
, 0x43fac0c8, 0x7f7f7f00,
221 test_iomux_settings (target
, 0x43fac0cc, 0x7f7f7f7f,
224 test_iomux_settings (target
, 0x43fac0d0, 0x0000007f, "d15");
227 test_iomux_settings (target
, 0x43fac0d0, 0x7f7f7f00,
230 test_iomux_settings (target
, 0x43fac0d4, 0x7f7f7f7f,
231 "nfwe,nfre,nfale,nfcle");
232 if (test_iomux
!= ERROR_OK
)
238 initialize_nf_controller (nand
);
242 uint16_t nand_status_content
;
244 retval
|= imx31_command (nand
, NAND_CMD_STATUS
);
245 retval
|= imx31_address (nand
, 0x00);
246 retval
|= do_data_output (nand
);
247 if (retval
!= ERROR_OK
)
249 LOG_ERROR (get_status_register_err_msg
);
252 target_read_u16 (target
, MX3_NF_MAIN_BUFFER0
, &nand_status_content
);
253 if (!(nand_status_content
& 0x0080))
256 * is host-big-endian correctly ??
258 LOG_INFO ("NAND read-only");
259 mx3_nf_info
->flags
.nand_readonly
= 1;
263 mx3_nf_info
->flags
.nand_readonly
= 0;
269 static int imx31_read_data (struct nand_device
*nand
, void *data
)
271 struct mx3_nf_controller
*mx3_nf_info
= nand
->controller_priv
;
272 struct target
*target
= mx3_nf_info
->target
;
275 * validate target state
277 int validate_target_result
;
278 validate_target_result
= validate_target_state (nand
);
279 if (validate_target_result
!= ERROR_OK
)
281 return validate_target_result
;
287 * get data from nand chip
289 int try_data_output_from_nand_chip
;
290 try_data_output_from_nand_chip
= do_data_output (nand
);
291 if (try_data_output_from_nand_chip
!= ERROR_OK
)
293 return try_data_output_from_nand_chip
;
297 if (nand
->bus_width
== 16)
299 get_next_halfword_from_sram_buffer (target
, data
);
303 get_next_byte_from_sram_buffer (target
, data
);
309 static int imx31_write_data (struct nand_device
*nand
, uint16_t data
)
311 LOG_ERROR ("write_data() not implemented");
312 return ERROR_NAND_OPERATION_FAILED
;
315 static int imx31_nand_ready (struct nand_device
*nand
, int timeout
)
317 return imx31_controller_ready (nand
, timeout
);
320 static int imx31_reset (struct nand_device
*nand
)
323 * validate target state
325 int validate_target_result
;
326 validate_target_result
= validate_target_state (nand
);
327 if (validate_target_result
!= ERROR_OK
)
329 return validate_target_result
;
331 initialize_nf_controller (nand
);
335 static int imx31_command (struct nand_device
*nand
, uint8_t command
)
337 struct mx3_nf_controller
*mx3_nf_info
= nand
->controller_priv
;
338 struct target
*target
= mx3_nf_info
->target
;
341 * validate target state
343 int validate_target_result
;
344 validate_target_result
= validate_target_state (nand
);
345 if (validate_target_result
!= ERROR_OK
)
347 return validate_target_result
;
353 case NAND_CMD_READOOB
:
354 command
= NAND_CMD_READ0
;
355 in_sram_address
= MX3_NF_SPARE_BUFFER0
; /* set read point for
357 * read_block_data() to
362 command
= NAND_CMD_READ0
;
364 * offset == one half of page size
367 MX3_NF_MAIN_BUFFER0
+ (nand
->page_size
>> 1);
369 in_sram_address
= MX3_NF_MAIN_BUFFER0
;
372 target_write_u16 (target
, MX3_NF_FCMD
, command
);
374 * start command input operation (set MX3_NF_BIT_OP_DONE==0)
376 target_write_u16 (target
, MX3_NF_CFG2
, MX3_NF_BIT_OP_FCI
);
379 poll_result
= poll_for_complete_op (target
, "command");
380 if (poll_result
!= ERROR_OK
)
386 * reset cursor to begin of the buffer
388 sign_of_sequental_byte_read
= 0;
391 case NAND_CMD_READID
:
392 mx3_nf_info
->optype
= MX3_NF_DATAOUT_NANDID
;
393 mx3_nf_info
->fin
= MX3_NF_FIN_DATAOUT
;
395 case NAND_CMD_STATUS
:
396 mx3_nf_info
->optype
= MX3_NF_DATAOUT_NANDSTATUS
;
397 mx3_nf_info
->fin
= MX3_NF_FIN_DATAOUT
;
400 mx3_nf_info
->fin
= MX3_NF_FIN_DATAOUT
;
401 mx3_nf_info
->optype
= MX3_NF_DATAOUT_PAGE
;
404 mx3_nf_info
->optype
= MX3_NF_DATAOUT_PAGE
;
409 static int imx31_address (struct nand_device
*nand
, uint8_t address
)
411 struct mx3_nf_controller
*mx3_nf_info
= nand
->controller_priv
;
412 struct target
*target
= mx3_nf_info
->target
;
415 * validate target state
417 int validate_target_result
;
418 validate_target_result
= validate_target_state (nand
);
419 if (validate_target_result
!= ERROR_OK
)
421 return validate_target_result
;
425 target_write_u16 (target
, MX3_NF_FADDR
, address
);
427 * start address input operation (set MX3_NF_BIT_OP_DONE==0)
429 target_write_u16 (target
, MX3_NF_CFG2
, MX3_NF_BIT_OP_FAI
);
432 poll_result
= poll_for_complete_op (target
, "address");
433 if (poll_result
!= ERROR_OK
)
441 static int imx31_controller_ready (struct nand_device
*nand
, int tout
)
443 uint16_t poll_complete_status
;
444 struct mx3_nf_controller
*mx3_nf_info
= nand
->controller_priv
;
445 struct target
*target
= mx3_nf_info
->target
;
449 * validate target state
451 int validate_target_result
;
452 validate_target_result
= validate_target_state (nand
);
453 if (validate_target_result
!= ERROR_OK
)
455 return validate_target_result
;
461 target_read_u16 (target
, MX3_NF_CFG2
, &poll_complete_status
);
462 if (poll_complete_status
& MX3_NF_BIT_OP_DONE
)
472 static int imx31_write_page (struct nand_device
*nand
, uint32_t page
,
473 uint8_t * data
, uint32_t data_size
, uint8_t * oob
,
476 struct mx3_nf_controller
*mx3_nf_info
= nand
->controller_priv
;
477 struct target
*target
= mx3_nf_info
->target
;
481 LOG_ERROR (data_block_size_err_msg
, data_size
);
482 return ERROR_NAND_OPERATION_FAILED
;
486 LOG_ERROR (data_block_size_err_msg
, oob_size
);
487 return ERROR_NAND_OPERATION_FAILED
;
491 LOG_ERROR ("nothing to program");
492 return ERROR_NAND_OPERATION_FAILED
;
496 * validate target state
499 retval
= validate_target_state (nand
);
500 if (retval
!= ERROR_OK
)
506 int retval
= ERROR_OK
;
507 retval
|= imx31_command(nand
, NAND_CMD_SEQIN
);
508 retval
|= imx31_address(nand
, 0x00);
509 retval
|= imx31_address(nand
, page
& 0xff);
510 retval
|= imx31_address(nand
, (page
>> 8) & 0xff);
511 if (nand
->address_cycles
>= 4)
513 retval
|= imx31_address (nand
, (page
>> 16) & 0xff);
514 if (nand
->address_cycles
>= 5)
516 retval
|= imx31_address (nand
, (page
>> 24) & 0xff);
519 target_write_buffer (target
, MX3_NF_MAIN_BUFFER0
, data_size
, data
);
522 if (mx3_nf_info
->flags
.hw_ecc_enabled
)
525 * part of spare block will be overrided by hardware
529 ("part of spare block will be overrided by hardware ECC generator");
531 target_write_buffer (target
, MX3_NF_SPARE_BUFFER0
, oob_size
,
535 * start data input operation (set MX3_NF_BIT_OP_DONE==0)
537 target_write_u16 (target
, MX3_NF_CFG2
, MX3_NF_BIT_OP_FDI
);
540 poll_result
= poll_for_complete_op (target
, "data input");
541 if (poll_result
!= ERROR_OK
)
546 retval
|= imx31_command (nand
, NAND_CMD_PAGEPROG
);
547 if (retval
!= ERROR_OK
)
553 * check status register
556 uint16_t nand_status_content
;
558 retval
|= imx31_command(nand
, NAND_CMD_STATUS
);
559 retval
|= imx31_address(nand
, 0x00);
560 retval
|= do_data_output(nand
);
561 if (retval
!= ERROR_OK
)
563 LOG_ERROR (get_status_register_err_msg
);
566 target_read_u16 (target
, MX3_NF_MAIN_BUFFER0
, &nand_status_content
);
567 if (nand_status_content
& 0x0001)
570 * is host-big-endian correctly ??
572 return ERROR_NAND_OPERATION_FAILED
;
579 static int imx31_read_page (struct nand_device
*nand
, uint32_t page
,
580 uint8_t * data
, uint32_t data_size
, uint8_t * oob
,
583 struct mx3_nf_controller
*mx3_nf_info
= nand
->controller_priv
;
584 struct target
*target
= mx3_nf_info
->target
;
588 LOG_ERROR (data_block_size_err_msg
, data_size
);
589 return ERROR_NAND_OPERATION_FAILED
;
593 LOG_ERROR (data_block_size_err_msg
, oob_size
);
594 return ERROR_NAND_OPERATION_FAILED
;
599 * validate target state
602 retval
= validate_target_state(nand
);
603 if (retval
!= ERROR_OK
)
609 int retval
= ERROR_OK
;
610 retval
|= imx31_command(nand
, NAND_CMD_READ0
);
611 retval
|= imx31_address(nand
, 0x00);
612 retval
|= imx31_address(nand
, page
& 0xff);
613 retval
|= imx31_address(nand
, (page
>> 8) & 0xff);
614 if (nand
->address_cycles
>= 4)
616 retval
|= imx31_address(nand
, (page
>> 16) & 0xff);
617 if (nand
->address_cycles
>= 5)
619 retval
|= imx31_address(nand
, (page
>> 24) & 0xff);
620 retval
|= imx31_command(nand
, NAND_CMD_READSTART
);
623 retval
|= do_data_output (nand
);
624 if (retval
!= ERROR_OK
)
631 target_read_buffer (target
, MX3_NF_MAIN_BUFFER0
, data_size
,
636 target_read_buffer (target
, MX3_NF_SPARE_BUFFER0
, oob_size
,
643 static int test_iomux_settings (struct target
* target
, uint32_t address
,
644 uint32_t mask
, const char *text
)
646 uint32_t register_content
;
647 target_read_u32 (target
, address
, ®ister_content
);
648 if ((register_content
& mask
) != (0x12121212 & mask
))
650 LOG_ERROR ("IOMUX for {%s} is bad", text
);
656 static int initialize_nf_controller (struct nand_device
*nand
)
658 struct mx3_nf_controller
*mx3_nf_info
= nand
->controller_priv
;
659 struct target
*target
= mx3_nf_info
->target
;
661 * resets NAND flash controller in zero time ? I dont know.
663 target_write_u16 (target
, MX3_NF_CFG1
, MX3_NF_BIT_RESET_EN
);
666 work_mode
= MX3_NF_BIT_INT_DIS
; /* disable interrupt */
667 if (target
->endianness
== TARGET_BIG_ENDIAN
)
669 work_mode
|= MX3_NF_BIT_BE_EN
;
671 if (mx3_nf_info
->flags
.hw_ecc_enabled
)
673 work_mode
|= MX3_NF_BIT_ECC_EN
;
675 target_write_u16 (target
, MX3_NF_CFG1
, work_mode
);
678 * unlock SRAM buffer for write; 2 mean "Unlock", other values means "Lock"
680 target_write_u16 (target
, MX3_NF_BUFCFG
, 2);
683 target_read_u16 (target
, MX3_NF_FWP
, &temp
);
684 if ((temp
& 0x0007) == 1)
686 LOG_ERROR ("NAND flash is tight-locked, reset needed");
692 * unlock NAND flash for write
694 target_write_u16 (target
, MX3_NF_FWP
, 4);
695 target_write_u16 (target
, MX3_NF_LOCKSTART
, 0x0000);
696 target_write_u16 (target
, MX3_NF_LOCKEND
, 0xFFFF);
698 * 0x0000 means that first SRAM buffer @0xB800_0000 will be used
700 target_write_u16 (target
, MX3_NF_BUFADDR
, 0x0000);
702 * address of SRAM buffer
704 in_sram_address
= MX3_NF_MAIN_BUFFER0
;
705 sign_of_sequental_byte_read
= 0;
709 static int get_next_byte_from_sram_buffer (struct target
* target
, uint8_t * value
)
711 static uint8_t even_byte
= 0;
715 if (sign_of_sequental_byte_read
== 0)
719 if (in_sram_address
> MX3_NF_LAST_BUFFER_ADDR
)
721 LOG_ERROR (sram_buffer_bounds_err_msg
, in_sram_address
);
723 sign_of_sequental_byte_read
= 0;
725 return ERROR_NAND_OPERATION_FAILED
;
730 target_read_u16 (target
, in_sram_address
, &temp
);
735 in_sram_address
+= 2;
739 *value
= temp
& 0xff;
743 sign_of_sequental_byte_read
= 1;
747 static int get_next_halfword_from_sram_buffer (struct target
* target
,
750 if (in_sram_address
> MX3_NF_LAST_BUFFER_ADDR
)
752 LOG_ERROR (sram_buffer_bounds_err_msg
, in_sram_address
);
754 return ERROR_NAND_OPERATION_FAILED
;
758 target_read_u16 (target
, in_sram_address
, value
);
759 in_sram_address
+= 2;
764 static int poll_for_complete_op (struct target
* target
, const char *text
)
766 uint16_t poll_complete_status
;
767 for (int poll_cycle_count
= 0; poll_cycle_count
< 100; poll_cycle_count
++)
770 target_read_u16 (target
, MX3_NF_CFG2
, &poll_complete_status
);
771 if (poll_complete_status
& MX3_NF_BIT_OP_DONE
)
776 if (!(poll_complete_status
& MX3_NF_BIT_OP_DONE
))
778 LOG_ERROR ("%s sending timeout", text
);
779 return ERROR_NAND_OPERATION_FAILED
;
784 static int validate_target_state (struct nand_device
*nand
)
786 struct mx3_nf_controller
*mx3_nf_info
= nand
->controller_priv
;
787 struct target
*target
= mx3_nf_info
->target
;
789 if (target
->state
!= TARGET_HALTED
)
791 LOG_ERROR (target_not_halted_err_msg
);
792 return ERROR_NAND_OPERATION_FAILED
;
795 if (mx3_nf_info
->flags
.target_little_endian
!=
796 (target
->endianness
== TARGET_LITTLE_ENDIAN
))
799 * endianness changed after NAND controller probed
801 return ERROR_NAND_OPERATION_FAILED
;
806 static int do_data_output (struct nand_device
*nand
)
808 struct mx3_nf_controller
*mx3_nf_info
= nand
->controller_priv
;
809 struct target
*target
= mx3_nf_info
->target
;
810 switch (mx3_nf_info
->fin
)
812 case MX3_NF_FIN_DATAOUT
:
814 * start data output operation (set MX3_NF_BIT_OP_DONE==0)
816 target_write_u16 (target
, MX3_NF_CFG2
,
817 MX3_NF_BIT_DATAOUT_TYPE (mx3_nf_info
->
821 poll_result
= poll_for_complete_op (target
, "data output");
822 if (poll_result
!= ERROR_OK
)
827 mx3_nf_info
->fin
= MX3_NF_FIN_NONE
;
831 if ((mx3_nf_info
->optype
== MX3_NF_DATAOUT_PAGE
)
832 && mx3_nf_info
->flags
.hw_ecc_enabled
)
835 target_read_u16 (target
, MX3_NF_ECCSTATUS
, &ecc_status
);
836 switch (ecc_status
& 0x000c)
840 ("main area readed with 1 (correctable) error");
844 ("main area readed with more than 1 (incorrectable) error");
845 return ERROR_NAND_OPERATION_FAILED
;
848 switch (ecc_status
& 0x0003)
852 ("spare area readed with 1 (correctable) error");
856 ("main area readed with more than 1 (incorrectable) error");
857 return ERROR_NAND_OPERATION_FAILED
;
862 case MX3_NF_FIN_NONE
:
868 struct nand_flash_controller imx31_nand_flash_controller
= {
870 .nand_device_command
= &imx31_nand_device_command
,
872 .reset
= &imx31_reset
,
873 .command
= &imx31_command
,
874 .address
= &imx31_address
,
875 .write_data
= &imx31_write_data
,
876 .read_data
= &imx31_read_data
,
877 .write_page
= &imx31_write_page
,
878 .read_page
= &imx31_read_page
,
879 .controller_ready
= &imx31_controller_ready
,
880 .nand_ready
= &imx31_nand_ready
,
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