1 // SPDX-License-Identifier: GPL-2.0-or-later
3 /***************************************************************************
4 * Copyright (C) 2009 by Alexei Babich *
5 * Rezonans plc., Chelyabinsk, Russia *
8 * Copyright (C) 2010 by Gaetan CARLIER *
9 * Trump s.a., Belgium *
11 * Copyright (C) 2011 by Erik Ahlen *
12 * Avalon Innovation, Sweden *
13 ***************************************************************************/
16 * Freescale iMX OpenOCD NAND Flash controller support.
17 * based on Freescale iMX2* and iMX3* OpenOCD NAND Flash controller support.
21 * driver tested with Samsung K9F2G08UXA and Numonyx/ST NAND02G-B2D @mxc
22 * tested "nand probe #", "nand erase # 0 #", "nand dump # file 0 #",
23 * "nand write # file 0", "nand verify"
25 * get_next_halfword_from_sram_buffer() not tested
26 * !! all function only tested with 2k page nand device; mxc_write_page
27 * writes the 4 MAIN_BUFFER's and is not compatible with < 2k page
28 * !! oob must be be used due to NFS bug
29 * !! oob must be 64 bytes per 2KiB page
37 #include <target/target.h>
41 #define nfc_is_v1() (mxc_nf_info->mxc_version == MXC_VERSION_MX27 || \
42 mxc_nf_info->mxc_version == MXC_VERSION_MX31)
43 #define nfc_is_v2() (mxc_nf_info->mxc_version == MXC_VERSION_MX25 || \
44 mxc_nf_info->mxc_version == MXC_VERSION_MX35)
46 /* This permits to print (in LOG_INFO) how much bytes
47 * has been written after a page read or write.
48 * This is useful when OpenOCD is used with a graphical
49 * front-end to estimate progression of the global read/write
51 #undef _MXC_PRINT_STAT
52 /* #define _MXC_PRINT_STAT */
54 static const char target_not_halted_err_msg
[] =
55 "target must be halted to use mxc NAND flash controller";
56 static const char data_block_size_err_msg
[] =
57 "minimal granularity is one half-word, %" PRIu32
" is incorrect";
58 static const char sram_buffer_bounds_err_msg
[] =
59 "trying to access out of SRAM buffer bound (addr=0x%" PRIx32
")";
60 static const char get_status_register_err_msg
[] = "can't get NAND status";
61 static uint32_t in_sram_address
;
62 static unsigned char sign_of_sequental_byte_read
;
64 static uint32_t align_address_v2(struct nand_device
*nand
, uint32_t addr
);
65 static int initialize_nf_controller(struct nand_device
*nand
);
66 static int get_next_byte_from_sram_buffer(struct nand_device
*nand
, uint8_t *value
);
67 static int get_next_halfword_from_sram_buffer(struct nand_device
*nand
, uint16_t *value
);
68 static int poll_for_complete_op(struct nand_device
*nand
, const char *text
);
69 static int validate_target_state(struct nand_device
*nand
);
70 static int do_data_output(struct nand_device
*nand
);
72 static int mxc_command(struct nand_device
*nand
, uint8_t command
);
73 static int mxc_address(struct nand_device
*nand
, uint8_t address
);
75 NAND_DEVICE_COMMAND_HANDLER(mxc_nand_device_command
)
77 struct mxc_nf_controller
*mxc_nf_info
;
80 mxc_nf_info
= malloc(sizeof(struct mxc_nf_controller
));
82 LOG_ERROR("no memory for nand controller");
85 nand
->controller_priv
= mxc_nf_info
;
88 LOG_ERROR("use \"nand device mxc target mx25|mx27|mx31|mx35 noecc|hwecc [biswap]\"");
95 if (strcmp(CMD_ARGV
[2], "mx25") == 0) {
96 mxc_nf_info
->mxc_version
= MXC_VERSION_MX25
;
97 mxc_nf_info
->mxc_base_addr
= 0xBB000000;
98 mxc_nf_info
->mxc_regs_addr
= mxc_nf_info
->mxc_base_addr
+ 0x1E00;
99 } else if (strcmp(CMD_ARGV
[2], "mx27") == 0) {
100 mxc_nf_info
->mxc_version
= MXC_VERSION_MX27
;
101 mxc_nf_info
->mxc_base_addr
= 0xD8000000;
102 mxc_nf_info
->mxc_regs_addr
= mxc_nf_info
->mxc_base_addr
+ 0x0E00;
103 } else if (strcmp(CMD_ARGV
[2], "mx31") == 0) {
104 mxc_nf_info
->mxc_version
= MXC_VERSION_MX31
;
105 mxc_nf_info
->mxc_base_addr
= 0xB8000000;
106 mxc_nf_info
->mxc_regs_addr
= mxc_nf_info
->mxc_base_addr
+ 0x0E00;
107 } else if (strcmp(CMD_ARGV
[2], "mx35") == 0) {
108 mxc_nf_info
->mxc_version
= MXC_VERSION_MX35
;
109 mxc_nf_info
->mxc_base_addr
= 0xBB000000;
110 mxc_nf_info
->mxc_regs_addr
= mxc_nf_info
->mxc_base_addr
+ 0x1E00;
114 * check hwecc requirements
116 hwecc_needed
= strcmp(CMD_ARGV
[3], "hwecc");
117 if (hwecc_needed
== 0)
118 mxc_nf_info
->flags
.hw_ecc_enabled
= 1;
120 mxc_nf_info
->flags
.hw_ecc_enabled
= 0;
122 mxc_nf_info
->optype
= MXC_NF_DATAOUT_PAGE
;
123 mxc_nf_info
->fin
= MXC_NF_FIN_NONE
;
124 mxc_nf_info
->flags
.target_little_endian
=
125 (nand
->target
->endianness
== TARGET_LITTLE_ENDIAN
);
128 * should factory bad block indicator be swapped
129 * as a workaround for how the nfc handles pages.
131 if (CMD_ARGC
> 4 && strcmp(CMD_ARGV
[4], "biswap") == 0) {
132 LOG_DEBUG("BI-swap enabled");
133 mxc_nf_info
->flags
.biswap_enabled
= 1;
139 COMMAND_HANDLER(handle_mxc_biswap_command
)
141 struct nand_device
*nand
= NULL
;
142 struct mxc_nf_controller
*mxc_nf_info
= NULL
;
144 if (CMD_ARGC
< 1 || CMD_ARGC
> 2)
145 return ERROR_COMMAND_SYNTAX_ERROR
;
147 int retval
= CALL_COMMAND_HANDLER(nand_command_get_device
, 0, &nand
);
148 if (retval
!= ERROR_OK
) {
149 command_print(CMD
, "invalid nand device number or name: %s", CMD_ARGV
[0]);
150 return ERROR_COMMAND_ARGUMENT_INVALID
;
153 mxc_nf_info
= nand
->controller_priv
;
155 if (strcmp(CMD_ARGV
[1], "enable") == 0)
156 mxc_nf_info
->flags
.biswap_enabled
= true;
158 mxc_nf_info
->flags
.biswap_enabled
= false;
160 if (mxc_nf_info
->flags
.biswap_enabled
)
161 command_print(CMD
, "BI-swapping enabled on %s", nand
->name
);
163 command_print(CMD
, "BI-swapping disabled on %s", nand
->name
);
168 static const struct command_registration mxc_sub_command_handlers
[] = {
171 .mode
= COMMAND_EXEC
,
172 .handler
= handle_mxc_biswap_command
,
173 .help
= "Turns on/off bad block information swapping from main area, "
174 "without parameter query status.",
175 .usage
= "bank_id ['enable'|'disable']",
177 COMMAND_REGISTRATION_DONE
180 static const struct command_registration mxc_nand_command_handler
[] = {
184 .help
= "MXC NAND flash controller commands",
185 .chain
= mxc_sub_command_handlers
,
188 COMMAND_REGISTRATION_DONE
191 static int mxc_init(struct nand_device
*nand
)
193 struct mxc_nf_controller
*mxc_nf_info
= nand
->controller_priv
;
194 struct target
*target
= nand
->target
;
196 int validate_target_result
;
197 uint16_t buffsize_register_content
;
198 uint32_t sreg_content
;
199 uint32_t sreg
= MX2_FMCR
;
200 uint32_t sel_16bit
= MX2_FMCR_NF_16BIT_SEL
;
201 uint32_t sel_fms
= MX2_FMCR_NF_FMS
;
203 uint16_t nand_status_content
;
205 * validate target state
207 validate_target_result
= validate_target_state(nand
);
208 if (validate_target_result
!= ERROR_OK
)
209 return validate_target_result
;
212 target_read_u16(target
, MXC_NF_BUFSIZ
, &buffsize_register_content
);
213 mxc_nf_info
->flags
.one_kb_sram
= !(buffsize_register_content
& 0x000f);
215 mxc_nf_info
->flags
.one_kb_sram
= 0;
217 if (mxc_nf_info
->mxc_version
== MXC_VERSION_MX31
) {
219 sel_16bit
= MX3_PCSR_NF_16BIT_SEL
;
220 sel_fms
= MX3_PCSR_NF_FMS
;
221 } else if (mxc_nf_info
->mxc_version
== MXC_VERSION_MX25
) {
223 sel_16bit
= MX25_RCSR_NF_16BIT_SEL
;
224 sel_fms
= MX25_RCSR_NF_FMS
;
225 } else if (mxc_nf_info
->mxc_version
== MXC_VERSION_MX35
) {
227 sel_16bit
= MX35_RCSR_NF_16BIT_SEL
;
228 sel_fms
= MX35_RCSR_NF_FMS
;
231 target_read_u32(target
, sreg
, &sreg_content
);
232 if (!nand
->bus_width
) {
233 /* bus_width not yet defined. Read it from MXC_FMCR */
234 nand
->bus_width
= (sreg_content
& sel_16bit
) ? 16 : 8;
236 /* bus_width forced in soft. Sync it to MXC_FMCR */
237 sreg_content
|= ((nand
->bus_width
== 16) ? sel_16bit
: 0x00000000);
238 target_write_u32(target
, sreg
, sreg_content
);
240 if (nand
->bus_width
== 16)
241 LOG_DEBUG("MXC_NF : bus is 16-bit width");
243 LOG_DEBUG("MXC_NF : bus is 8-bit width");
245 if (!nand
->page_size
)
246 nand
->page_size
= (sreg_content
& sel_fms
) ? 2048 : 512;
248 sreg_content
|= ((nand
->page_size
== 2048) ? sel_fms
: 0x00000000);
249 target_write_u32(target
, sreg
, sreg_content
);
251 if (mxc_nf_info
->flags
.one_kb_sram
&& (nand
->page_size
== 2048)) {
252 LOG_ERROR("NAND controller have only 1 kb SRAM, so "
253 "pagesize 2048 is incompatible with it");
255 LOG_DEBUG("MXC_NF : NAND controller can handle pagesize of 2048");
257 if (nfc_is_v2() && sreg_content
& MX35_RCSR_NF_4K
)
258 LOG_ERROR("MXC driver does not have support for 4k pagesize.");
260 initialize_nf_controller(nand
);
263 retval
|= mxc_command(nand
, NAND_CMD_STATUS
);
264 retval
|= mxc_address(nand
, 0x00);
265 retval
|= do_data_output(nand
);
266 if (retval
!= ERROR_OK
) {
267 LOG_ERROR(get_status_register_err_msg
);
270 target_read_u16(target
, MXC_NF_MAIN_BUFFER0
, &nand_status_content
);
271 if (!(nand_status_content
& 0x0080)) {
272 LOG_INFO("NAND read-only");
273 mxc_nf_info
->flags
.nand_readonly
= 1;
275 mxc_nf_info
->flags
.nand_readonly
= 0;
279 static int mxc_read_data(struct nand_device
*nand
, void *data
)
281 int validate_target_result
;
282 int try_data_output_from_nand_chip
;
284 * validate target state
286 validate_target_result
= validate_target_state(nand
);
287 if (validate_target_result
!= ERROR_OK
)
288 return validate_target_result
;
291 * get data from nand chip
293 try_data_output_from_nand_chip
= do_data_output(nand
);
294 if (try_data_output_from_nand_chip
!= ERROR_OK
) {
295 LOG_ERROR("mxc_read_data : read data failed : '%x'",
296 try_data_output_from_nand_chip
);
297 return try_data_output_from_nand_chip
;
300 if (nand
->bus_width
== 16)
301 get_next_halfword_from_sram_buffer(nand
, data
);
303 get_next_byte_from_sram_buffer(nand
, data
);
308 static int mxc_write_data(struct nand_device
*nand
, uint16_t data
)
310 LOG_ERROR("write_data() not implemented");
311 return ERROR_NAND_OPERATION_FAILED
;
314 static int mxc_reset(struct nand_device
*nand
)
317 * validate target state
319 int validate_target_result
;
320 validate_target_result
= validate_target_state(nand
);
321 if (validate_target_result
!= ERROR_OK
)
322 return validate_target_result
;
323 initialize_nf_controller(nand
);
327 static int mxc_command(struct nand_device
*nand
, uint8_t command
)
329 struct mxc_nf_controller
*mxc_nf_info
= nand
->controller_priv
;
330 struct target
*target
= nand
->target
;
331 int validate_target_result
;
334 * validate target state
336 validate_target_result
= validate_target_state(nand
);
337 if (validate_target_result
!= ERROR_OK
)
338 return validate_target_result
;
341 case NAND_CMD_READOOB
:
342 command
= NAND_CMD_READ0
;
343 /* set read point for data_read() and read_block_data() to
344 * spare area in SRAM buffer
347 in_sram_address
= MXC_NF_V1_SPARE_BUFFER0
;
349 in_sram_address
= MXC_NF_V2_SPARE_BUFFER0
;
352 command
= NAND_CMD_READ0
;
354 * offset == one half of page size
356 in_sram_address
= MXC_NF_MAIN_BUFFER0
+ (nand
->page_size
>> 1);
359 in_sram_address
= MXC_NF_MAIN_BUFFER0
;
363 target_write_u16(target
, MXC_NF_FCMD
, command
);
365 * start command input operation (set MXC_NF_BIT_OP_DONE==0)
367 target_write_u16(target
, MXC_NF_CFG2
, MXC_NF_BIT_OP_FCI
);
368 poll_result
= poll_for_complete_op(nand
, "command");
369 if (poll_result
!= ERROR_OK
)
372 * reset cursor to begin of the buffer
374 sign_of_sequental_byte_read
= 0;
375 /* Handle special read command and adjust NF_CFG2(FDO) */
377 case NAND_CMD_READID
:
378 mxc_nf_info
->optype
= MXC_NF_DATAOUT_NANDID
;
379 mxc_nf_info
->fin
= MXC_NF_FIN_DATAOUT
;
381 case NAND_CMD_STATUS
:
382 mxc_nf_info
->optype
= MXC_NF_DATAOUT_NANDSTATUS
;
383 mxc_nf_info
->fin
= MXC_NF_FIN_DATAOUT
;
384 target_write_u16 (target
, MXC_NF_BUFADDR
, 0);
388 mxc_nf_info
->fin
= MXC_NF_FIN_DATAOUT
;
389 mxc_nf_info
->optype
= MXC_NF_DATAOUT_PAGE
;
392 /* Other command use the default 'One page data out' FDO */
393 mxc_nf_info
->optype
= MXC_NF_DATAOUT_PAGE
;
399 static int mxc_address(struct nand_device
*nand
, uint8_t address
)
401 struct mxc_nf_controller
*mxc_nf_info
= nand
->controller_priv
;
402 struct target
*target
= nand
->target
;
403 int validate_target_result
;
406 * validate target state
408 validate_target_result
= validate_target_state(nand
);
409 if (validate_target_result
!= ERROR_OK
)
410 return validate_target_result
;
412 target_write_u16(target
, MXC_NF_FADDR
, address
);
414 * start address input operation (set MXC_NF_BIT_OP_DONE==0)
416 target_write_u16(target
, MXC_NF_CFG2
, MXC_NF_BIT_OP_FAI
);
417 poll_result
= poll_for_complete_op(nand
, "address");
418 if (poll_result
!= ERROR_OK
)
424 static int mxc_nand_ready(struct nand_device
*nand
, int tout
)
426 struct mxc_nf_controller
*mxc_nf_info
= nand
->controller_priv
;
427 struct target
*target
= nand
->target
;
428 uint16_t poll_complete_status
;
429 int validate_target_result
;
432 * validate target state
434 validate_target_result
= validate_target_state(nand
);
435 if (validate_target_result
!= ERROR_OK
)
436 return validate_target_result
;
439 target_read_u16(target
, MXC_NF_CFG2
, &poll_complete_status
);
440 if (poll_complete_status
& MXC_NF_BIT_OP_DONE
)
444 } while (tout
-- > 0);
448 static int mxc_write_page(struct nand_device
*nand
, uint32_t page
,
449 uint8_t *data
, uint32_t data_size
,
450 uint8_t *oob
, uint32_t oob_size
)
452 struct mxc_nf_controller
*mxc_nf_info
= nand
->controller_priv
;
453 struct target
*target
= nand
->target
;
455 uint16_t nand_status_content
;
456 uint16_t swap1
, swap2
, new_swap1
;
461 LOG_ERROR(data_block_size_err_msg
, data_size
);
462 return ERROR_NAND_OPERATION_FAILED
;
465 LOG_ERROR(data_block_size_err_msg
, oob_size
);
466 return ERROR_NAND_OPERATION_FAILED
;
469 LOG_ERROR("nothing to program");
470 return ERROR_NAND_OPERATION_FAILED
;
474 * validate target state
476 retval
= validate_target_state(nand
);
477 if (retval
!= ERROR_OK
)
480 in_sram_address
= MXC_NF_MAIN_BUFFER0
;
481 sign_of_sequental_byte_read
= 0;
483 retval
|= mxc_command(nand
, NAND_CMD_SEQIN
);
484 retval
|= mxc_address(nand
, 0); /* col */
485 retval
|= mxc_address(nand
, 0); /* col */
486 retval
|= mxc_address(nand
, page
& 0xff); /* page address */
487 retval
|= mxc_address(nand
, (page
>> 8) & 0xff);/* page address */
488 retval
|= mxc_address(nand
, (page
>> 16) & 0xff); /* page address */
490 target_write_buffer(target
, MXC_NF_MAIN_BUFFER0
, data_size
, data
);
492 if (mxc_nf_info
->flags
.hw_ecc_enabled
) {
494 * part of spare block will be overridden by hardware
497 LOG_DEBUG("part of spare block will be overridden "
498 "by hardware ECC generator");
501 target_write_buffer(target
, MXC_NF_V1_SPARE_BUFFER0
, oob_size
, oob
);
503 uint32_t addr
= MXC_NF_V2_SPARE_BUFFER0
;
504 while (oob_size
> 0) {
505 uint8_t len
= MIN(oob_size
, MXC_NF_SPARE_BUFFER_LEN
);
506 target_write_buffer(target
, addr
, len
, oob
);
507 addr
= align_address_v2(nand
, addr
+ len
);
514 if (nand
->page_size
> 512 && mxc_nf_info
->flags
.biswap_enabled
) {
515 /* BI-swap - work-around of i.MX NFC for NAND device with page == 2kb*/
516 target_read_u16(target
, MXC_NF_MAIN_BUFFER3
+ 464, &swap1
);
518 LOG_ERROR("Due to NFC Bug, oob is not correctly implemented in mxc driver");
519 return ERROR_NAND_OPERATION_FAILED
;
521 swap2
= 0xffff; /* Spare buffer unused forced to 0xffff */
522 new_swap1
= (swap1
& 0xFF00) | (swap2
>> 8);
523 swap2
= (swap1
<< 8) | (swap2
& 0xFF);
524 target_write_u16(target
, MXC_NF_MAIN_BUFFER3
+ 464, new_swap1
);
526 target_write_u16(target
, MXC_NF_V1_SPARE_BUFFER3
+ 4, swap2
);
528 target_write_u16(target
, MXC_NF_V2_SPARE_BUFFER3
, swap2
);
532 * start data input operation (set MXC_NF_BIT_OP_DONE==0)
534 if (nfc_is_v1() && nand
->page_size
> 512)
539 for (uint8_t i
= 0; i
< bufs
; ++i
) {
540 target_write_u16(target
, MXC_NF_BUFADDR
, i
);
541 target_write_u16(target
, MXC_NF_CFG2
, MXC_NF_BIT_OP_FDI
);
542 poll_result
= poll_for_complete_op(nand
, "data input");
543 if (poll_result
!= ERROR_OK
)
547 retval
|= mxc_command(nand
, NAND_CMD_PAGEPROG
);
548 if (retval
!= ERROR_OK
)
552 * check status register
555 retval
|= mxc_command(nand
, NAND_CMD_STATUS
);
556 target_write_u16 (target
, MXC_NF_BUFADDR
, 0);
557 mxc_nf_info
->optype
= MXC_NF_DATAOUT_NANDSTATUS
;
558 mxc_nf_info
->fin
= MXC_NF_FIN_DATAOUT
;
559 retval
|= do_data_output(nand
);
560 if (retval
!= ERROR_OK
) {
561 LOG_ERROR(get_status_register_err_msg
);
564 target_read_u16(target
, MXC_NF_MAIN_BUFFER0
, &nand_status_content
);
565 if (nand_status_content
& 0x0001) {
567 * page not correctly written
569 return ERROR_NAND_OPERATION_FAILED
;
571 #ifdef _MXC_PRINT_STAT
572 LOG_INFO("%d bytes newly written", data_size
);
577 static int mxc_read_page(struct nand_device
*nand
, uint32_t page
,
578 uint8_t *data
, uint32_t data_size
,
579 uint8_t *oob
, uint32_t oob_size
)
581 struct mxc_nf_controller
*mxc_nf_info
= nand
->controller_priv
;
582 struct target
*target
= nand
->target
;
585 uint16_t swap1
, swap2
, new_swap1
;
588 LOG_ERROR(data_block_size_err_msg
, data_size
);
589 return ERROR_NAND_OPERATION_FAILED
;
592 LOG_ERROR(data_block_size_err_msg
, oob_size
);
593 return ERROR_NAND_OPERATION_FAILED
;
597 * validate target state
599 retval
= validate_target_state(nand
);
600 if (retval
!= ERROR_OK
)
602 /* Reset address_cycles before mxc_command ?? */
603 retval
= mxc_command(nand
, NAND_CMD_READ0
);
604 if (retval
!= ERROR_OK
)
606 retval
= mxc_address(nand
, 0); /* col */
607 if (retval
!= ERROR_OK
)
609 retval
= mxc_address(nand
, 0); /* col */
610 if (retval
!= ERROR_OK
)
612 retval
= mxc_address(nand
, page
& 0xff);/* page address */
613 if (retval
!= ERROR_OK
)
615 retval
= mxc_address(nand
, (page
>> 8) & 0xff); /* page address */
616 if (retval
!= ERROR_OK
)
618 retval
= mxc_address(nand
, (page
>> 16) & 0xff);/* page address */
619 if (retval
!= ERROR_OK
)
621 retval
= mxc_command(nand
, NAND_CMD_READSTART
);
622 if (retval
!= ERROR_OK
)
625 if (nfc_is_v1() && nand
->page_size
> 512)
630 for (uint8_t i
= 0; i
< bufs
; ++i
) {
631 target_write_u16(target
, MXC_NF_BUFADDR
, i
);
632 mxc_nf_info
->fin
= MXC_NF_FIN_DATAOUT
;
633 retval
= do_data_output(nand
);
634 if (retval
!= ERROR_OK
) {
635 LOG_ERROR("MXC_NF : Error reading page %d", i
);
640 if (nand
->page_size
> 512 && mxc_nf_info
->flags
.biswap_enabled
) {
641 uint32_t spare_buffer3
;
642 /* BI-swap - work-around of mxc NFC for NAND device with page == 2k */
643 target_read_u16(target
, MXC_NF_MAIN_BUFFER3
+ 464, &swap1
);
645 spare_buffer3
= MXC_NF_V1_SPARE_BUFFER3
+ 4;
647 spare_buffer3
= MXC_NF_V2_SPARE_BUFFER3
;
648 target_read_u16(target
, spare_buffer3
, &swap2
);
649 new_swap1
= (swap1
& 0xFF00) | (swap2
>> 8);
650 swap2
= (swap1
<< 8) | (swap2
& 0xFF);
651 target_write_u16(target
, MXC_NF_MAIN_BUFFER3
+ 464, new_swap1
);
652 target_write_u16(target
, spare_buffer3
, swap2
);
656 target_read_buffer(target
, MXC_NF_MAIN_BUFFER0
, data_size
, data
);
659 target_read_buffer(target
, MXC_NF_V1_SPARE_BUFFER0
, oob_size
, oob
);
661 uint32_t addr
= MXC_NF_V2_SPARE_BUFFER0
;
662 while (oob_size
> 0) {
663 uint8_t len
= MIN(oob_size
, MXC_NF_SPARE_BUFFER_LEN
);
664 target_read_buffer(target
, addr
, len
, oob
);
665 addr
= align_address_v2(nand
, addr
+ len
);
672 #ifdef _MXC_PRINT_STAT
674 /* When Operation Status is read (when page is erased),
675 * this function is used but data_size is null.
677 LOG_INFO("%d bytes newly read", data_size
);
683 static uint32_t align_address_v2(struct nand_device
*nand
, uint32_t addr
)
685 struct mxc_nf_controller
*mxc_nf_info
= nand
->controller_priv
;
687 if (addr
> MXC_NF_V2_SPARE_BUFFER0
&&
688 (addr
& 0x1F) == MXC_NF_SPARE_BUFFER_LEN
)
689 ret
+= MXC_NF_SPARE_BUFFER_MAX
- MXC_NF_SPARE_BUFFER_LEN
;
690 else if (addr
>= (mxc_nf_info
->mxc_base_addr
+ (uint32_t)nand
->page_size
))
691 ret
= MXC_NF_V2_SPARE_BUFFER0
;
695 static int initialize_nf_controller(struct nand_device
*nand
)
697 struct mxc_nf_controller
*mxc_nf_info
= nand
->controller_priv
;
698 struct target
*target
= nand
->target
;
699 uint16_t work_mode
= 0;
702 * resets NAND flash controller in zero time ? I don't know.
704 target_write_u16(target
, MXC_NF_CFG1
, MXC_NF_BIT_RESET_EN
);
705 if (mxc_nf_info
->mxc_version
== MXC_VERSION_MX27
)
706 work_mode
= MXC_NF_BIT_INT_DIS
; /* disable interrupt */
708 if (target
->endianness
== TARGET_BIG_ENDIAN
) {
709 LOG_DEBUG("MXC_NF : work in Big Endian mode");
710 work_mode
|= MXC_NF_BIT_BE_EN
;
712 LOG_DEBUG("MXC_NF : work in Little Endian mode");
713 if (mxc_nf_info
->flags
.hw_ecc_enabled
) {
714 LOG_DEBUG("MXC_NF : work with ECC mode");
715 work_mode
|= MXC_NF_BIT_ECC_EN
;
717 LOG_DEBUG("MXC_NF : work without ECC mode");
719 target_write_u16(target
, MXC_NF_V2_SPAS
, OOB_SIZE
/ 2);
720 if (nand
->page_size
) {
721 uint16_t pages_per_block
= nand
->erase_size
/ nand
->page_size
;
722 work_mode
|= MXC_NF_V2_CFG1_PPB(ffs(pages_per_block
) - 6);
724 work_mode
|= MXC_NF_BIT_ECC_4BIT
;
726 target_write_u16(target
, MXC_NF_CFG1
, work_mode
);
729 * unlock SRAM buffer for write; 2 mean "Unlock", other values means "Lock"
731 target_write_u16(target
, MXC_NF_BUFCFG
, 2);
732 target_read_u16(target
, MXC_NF_FWP
, &temp
);
733 if ((temp
& 0x0007) == 1) {
734 LOG_ERROR("NAND flash is tight-locked, reset needed");
739 * unlock NAND flash for write
742 target_write_u16(target
, MXC_NF_V1_UNLOCKSTART
, 0x0000);
743 target_write_u16(target
, MXC_NF_V1_UNLOCKEND
, 0xFFFF);
745 target_write_u16(target
, MXC_NF_V2_UNLOCKSTART0
, 0x0000);
746 target_write_u16(target
, MXC_NF_V2_UNLOCKSTART1
, 0x0000);
747 target_write_u16(target
, MXC_NF_V2_UNLOCKSTART2
, 0x0000);
748 target_write_u16(target
, MXC_NF_V2_UNLOCKSTART3
, 0x0000);
749 target_write_u16(target
, MXC_NF_V2_UNLOCKEND0
, 0xFFFF);
750 target_write_u16(target
, MXC_NF_V2_UNLOCKEND1
, 0xFFFF);
751 target_write_u16(target
, MXC_NF_V2_UNLOCKEND2
, 0xFFFF);
752 target_write_u16(target
, MXC_NF_V2_UNLOCKEND3
, 0xFFFF);
754 target_write_u16(target
, MXC_NF_FWP
, 4);
757 * 0x0000 means that first SRAM buffer @base_addr will be used
759 target_write_u16(target
, MXC_NF_BUFADDR
, 0x0000);
761 * address of SRAM buffer
763 in_sram_address
= MXC_NF_MAIN_BUFFER0
;
764 sign_of_sequental_byte_read
= 0;
768 static int get_next_byte_from_sram_buffer(struct nand_device
*nand
, uint8_t *value
)
770 struct mxc_nf_controller
*mxc_nf_info
= nand
->controller_priv
;
771 struct target
*target
= nand
->target
;
772 static uint8_t even_byte
;
777 if (sign_of_sequental_byte_read
== 0)
780 if (in_sram_address
> (nfc_is_v1() ? MXC_NF_V1_LAST_BUFFADDR
: MXC_NF_V2_LAST_BUFFADDR
)) {
781 LOG_ERROR(sram_buffer_bounds_err_msg
, in_sram_address
);
783 sign_of_sequental_byte_read
= 0;
785 return ERROR_NAND_OPERATION_FAILED
;
788 in_sram_address
= align_address_v2(nand
, in_sram_address
);
790 target_read_u16(target
, in_sram_address
, &temp
);
794 in_sram_address
+= 2;
796 *value
= temp
& 0xff;
800 sign_of_sequental_byte_read
= 1;
804 static int get_next_halfword_from_sram_buffer(struct nand_device
*nand
, uint16_t *value
)
806 struct mxc_nf_controller
*mxc_nf_info
= nand
->controller_priv
;
807 struct target
*target
= nand
->target
;
809 if (in_sram_address
> (nfc_is_v1() ? MXC_NF_V1_LAST_BUFFADDR
: MXC_NF_V2_LAST_BUFFADDR
)) {
810 LOG_ERROR(sram_buffer_bounds_err_msg
, in_sram_address
);
812 return ERROR_NAND_OPERATION_FAILED
;
815 in_sram_address
= align_address_v2(nand
, in_sram_address
);
817 target_read_u16(target
, in_sram_address
, value
);
818 in_sram_address
+= 2;
823 static int poll_for_complete_op(struct nand_device
*nand
, const char *text
)
825 if (mxc_nand_ready(nand
, 1000) == -1) {
826 LOG_ERROR("%s sending timeout", text
);
827 return ERROR_NAND_OPERATION_FAILED
;
832 static int validate_target_state(struct nand_device
*nand
)
834 struct mxc_nf_controller
*mxc_nf_info
= nand
->controller_priv
;
835 struct target
*target
= nand
->target
;
837 if (target
->state
!= TARGET_HALTED
) {
838 LOG_ERROR(target_not_halted_err_msg
);
839 return ERROR_NAND_OPERATION_FAILED
;
842 if (mxc_nf_info
->flags
.target_little_endian
!=
843 (target
->endianness
== TARGET_LITTLE_ENDIAN
)) {
845 * endianness changed after NAND controller probed
847 return ERROR_NAND_OPERATION_FAILED
;
852 static int ecc_status_v1(struct nand_device
*nand
)
854 struct mxc_nf_controller
*mxc_nf_info
= nand
->controller_priv
;
855 struct target
*target
= nand
->target
;
858 target_read_u16(target
, MXC_NF_ECCSTATUS
, &ecc_status
);
859 switch (ecc_status
& 0x000c) {
861 LOG_INFO("main area read with 1 (correctable) error");
864 LOG_INFO("main area read with more than 1 (incorrectable) error");
865 return ERROR_NAND_OPERATION_FAILED
;
867 switch (ecc_status
& 0x0003) {
869 LOG_INFO("spare area read with 1 (correctable) error");
872 LOG_INFO("main area read with more than 1 (incorrectable) error");
873 return ERROR_NAND_OPERATION_FAILED
;
878 static int ecc_status_v2(struct nand_device
*nand
)
880 struct mxc_nf_controller
*mxc_nf_info
= nand
->controller_priv
;
881 struct target
*target
= nand
->target
;
886 no_subpages
= nand
->page_size
>> 9;
888 target_read_u16(target
, MXC_NF_ECCSTATUS
, &ecc_status
);
890 err
= ecc_status
& 0xF;
892 LOG_INFO("UnCorrectable RS-ECC Error");
893 return ERROR_NAND_OPERATION_FAILED
;
895 LOG_INFO("%d Symbol Correctable RS-ECC Error", err
);
897 } while (--no_subpages
);
901 static int do_data_output(struct nand_device
*nand
)
903 struct mxc_nf_controller
*mxc_nf_info
= nand
->controller_priv
;
904 struct target
*target
= nand
->target
;
906 switch (mxc_nf_info
->fin
) {
907 case MXC_NF_FIN_DATAOUT
:
909 * start data output operation (set MXC_NF_BIT_OP_DONE==0)
911 target_write_u16(target
, MXC_NF_CFG2
, MXC_NF_BIT_DATAOUT_TYPE(mxc_nf_info
->optype
));
912 poll_result
= poll_for_complete_op(nand
, "data output");
913 if (poll_result
!= ERROR_OK
)
916 mxc_nf_info
->fin
= MXC_NF_FIN_NONE
;
920 if (mxc_nf_info
->optype
== MXC_NF_DATAOUT_PAGE
&& mxc_nf_info
->flags
.hw_ecc_enabled
) {
923 ecc_status
= ecc_status_v1(nand
);
925 ecc_status
= ecc_status_v2(nand
);
926 if (ecc_status
!= ERROR_OK
)
930 case MXC_NF_FIN_NONE
:
936 struct nand_flash_controller mxc_nand_flash_controller
= {
938 .nand_device_command
= &mxc_nand_device_command
,
939 .commands
= mxc_nand_command_handler
,
942 .command
= &mxc_command
,
943 .address
= &mxc_address
,
944 .write_data
= &mxc_write_data
,
945 .read_data
= &mxc_read_data
,
946 .write_page
= &mxc_write_page
,
947 .read_page
= &mxc_read_page
,
948 .nand_ready
= &mxc_nand_ready
,
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