1 /***************************************************************************
2 * Copyright (C) 2009 by Duane Ellis *
3 * openocd@duaneellis.com *
5 * Copyright (C) 2010 by Olaf Lüke (at91sam3s* support) *
6 * olaf@uni-paderborn.de *
8 * Copyright (C) 2011 by Olivier Schonken (at91sam3x* support) * *
10 * This program is free software; you can redistribute it and/or modify *
11 * it under the terms of the GNU General public License as published by *
12 * the Free Software Foundation; either version 2 of the License, or *
13 * (at your option) any later version. *
15 * This program is distributed in the hope that it will be useful, *
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
17 * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the *
18 * GNU General public License for more details. *
20 * You should have received a copy of the GNU General public License *
21 * along with this program; if not, write to the *
22 * Free Software Foundation, Inc., *
23 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
24 ****************************************************************************/
26 /* Some of the the lower level code was based on code supplied by
27 * ATMEL under this copyright. */
29 /* BEGIN ATMEL COPYRIGHT */
30 /* ----------------------------------------------------------------------------
31 * ATMEL Microcontroller Software Support
32 * ----------------------------------------------------------------------------
33 * Copyright (c) 2009, Atmel Corporation
35 * All rights reserved.
37 * Redistribution and use in source and binary forms, with or without
38 * modification, are permitted provided that the following conditions are met:
40 * - Redistributions of source code must retain the above copyright notice,
41 * this list of conditions and the disclaimer below.
43 * Atmel's name may not be used to endorse or promote products derived from
44 * this software without specific prior written permission.
46 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
47 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
48 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
49 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
50 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
51 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
52 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
53 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
54 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
55 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
56 * ----------------------------------------------------------------------------
58 /* END ATMEL COPYRIGHT */
65 #include <helper/time_support.h>
67 #define REG_NAME_WIDTH (12)
69 /* at91sam3u series (has one or two flash banks) */
70 #define FLASH_BANK0_BASE_U 0x00080000
71 #define FLASH_BANK1_BASE_U 0x00100000
73 /* at91sam3s series (has always one flash bank) */
74 #define FLASH_BANK_BASE_S 0x00400000
76 /* at91sam3n series (has always one flash bank) */
77 #define FLASH_BANK_BASE_N 0x00400000
79 /* at91sam3a/x series has two flash banks*/
80 #define FLASH_BANK0_BASE_AX 0x00080000
81 /*Bank 1 of the at91sam3a/x series starts at 0x00080000 + half flash size*/
82 #define FLASH_BANK1_BASE_256K_AX 0x000A0000
83 #define FLASH_BANK1_BASE_512K_AX 0x000C0000
85 #define AT91C_EFC_FCMD_GETD (0x0) /* (EFC) Get Flash Descriptor */
86 #define AT91C_EFC_FCMD_WP (0x1) /* (EFC) Write Page */
87 #define AT91C_EFC_FCMD_WPL (0x2) /* (EFC) Write Page and Lock */
88 #define AT91C_EFC_FCMD_EWP (0x3) /* (EFC) Erase Page and Write Page */
89 #define AT91C_EFC_FCMD_EWPL (0x4) /* (EFC) Erase Page and Write Page
91 #define AT91C_EFC_FCMD_EA (0x5) /* (EFC) Erase All */
92 /* cmd6 is not present int he at91sam3u4/2/1 data sheet table 17-2 */
93 /* #define AT91C_EFC_FCMD_EPL (0x6) // (EFC) Erase plane? */
94 /* cmd7 is not present int he at91sam3u4/2/1 data sheet table 17-2 */
95 /* #define AT91C_EFC_FCMD_EPA (0x7) // (EFC) Erase pages? */
96 #define AT91C_EFC_FCMD_SLB (0x8) /* (EFC) Set Lock Bit */
97 #define AT91C_EFC_FCMD_CLB (0x9) /* (EFC) Clear Lock Bit */
98 #define AT91C_EFC_FCMD_GLB (0xA) /* (EFC) Get Lock Bit */
99 #define AT91C_EFC_FCMD_SFB (0xB) /* (EFC) Set Fuse Bit */
100 #define AT91C_EFC_FCMD_CFB (0xC) /* (EFC) Clear Fuse Bit */
101 #define AT91C_EFC_FCMD_GFB (0xD) /* (EFC) Get Fuse Bit */
102 #define AT91C_EFC_FCMD_STUI (0xE) /* (EFC) Start Read Unique ID */
103 #define AT91C_EFC_FCMD_SPUI (0xF) /* (EFC) Stop Read Unique ID */
105 #define offset_EFC_FMR 0
106 #define offset_EFC_FCR 4
107 #define offset_EFC_FSR 8
108 #define offset_EFC_FRR 12
110 extern struct flash_driver at91sam3_flash
;
112 static float _tomhz(uint32_t freq_hz
)
116 f
= ((float)(freq_hz
)) / 1000000.0;
120 /* How the chip is configured. */
122 uint32_t unique_id
[4];
126 uint32_t mainosc_freq
;
136 #define SAM3_CHIPID_CIDR (0x400E0740)
137 uint32_t CHIPID_CIDR
;
138 #define SAM3_CHIPID_CIDR2 (0x400E0940) /*SAM3X and SAM3A cidr at this address*/
139 uint32_t CHIPID_CIDR2
;
140 #define SAM3_CHIPID_EXID (0x400E0744)
141 uint32_t CHIPID_EXID
;
142 #define SAM3_CHIPID_EXID2 (0x400E0944) /*SAM3X and SAM3A cidr at this address*/
143 uint32_t CHIPID_EXID2
;
146 #define SAM3_PMC_BASE (0x400E0400)
147 #define SAM3_PMC_SCSR (SAM3_PMC_BASE + 0x0008)
149 #define SAM3_PMC_PCSR (SAM3_PMC_BASE + 0x0018)
151 #define SAM3_CKGR_UCKR (SAM3_PMC_BASE + 0x001c)
153 #define SAM3_CKGR_MOR (SAM3_PMC_BASE + 0x0020)
155 #define SAM3_CKGR_MCFR (SAM3_PMC_BASE + 0x0024)
157 #define SAM3_CKGR_PLLAR (SAM3_PMC_BASE + 0x0028)
159 #define SAM3_PMC_MCKR (SAM3_PMC_BASE + 0x0030)
161 #define SAM3_PMC_PCK0 (SAM3_PMC_BASE + 0x0040)
163 #define SAM3_PMC_PCK1 (SAM3_PMC_BASE + 0x0044)
165 #define SAM3_PMC_PCK2 (SAM3_PMC_BASE + 0x0048)
167 #define SAM3_PMC_SR (SAM3_PMC_BASE + 0x0068)
169 #define SAM3_PMC_IMR (SAM3_PMC_BASE + 0x006c)
171 #define SAM3_PMC_FSMR (SAM3_PMC_BASE + 0x0070)
173 #define SAM3_PMC_FSPR (SAM3_PMC_BASE + 0x0074)
178 * The AT91SAM3N data sheet 04-Oct-2010, AT91SAM3U data sheet 22-Aug-2011
179 * and AT91SAM3S data sheet 09-Feb-2011 state that for flash writes
180 * the flash wait state (FWS) should be set to 6. It seems like that the
181 * cause of the problem is not the flash itself, but the flash write
182 * buffer. Ie the wait states have to be set before writing into the
184 * Tested and confirmed with SAM3N and SAM3U
187 struct sam3_bank_private
{
189 /* DANGER: THERE ARE DRAGONS HERE.. */
190 /* NOTE: If you add more 'ghost' pointers */
191 /* be aware that you must *manually* update */
192 /* these pointers in the function sam3_GetDetails() */
193 /* See the comment "Here there be dragons" */
195 /* so we can find the chip we belong to */
196 struct sam3_chip
*pChip
;
197 /* so we can find the orginal bank pointer */
198 struct flash_bank
*pBank
;
199 unsigned bank_number
;
200 uint32_t controller_address
;
201 uint32_t base_address
;
202 uint32_t flash_wait_states
;
206 unsigned sector_size
;
210 struct sam3_chip_details
{
211 /* THERE ARE DRAGONS HERE.. */
212 /* note: If you add pointers here */
213 /* becareful about them as they */
214 /* may need to be updated inside */
215 /* the function: "sam3_GetDetails() */
216 /* which copy/overwrites the */
217 /* 'runtime' copy of this structure */
218 uint32_t chipid_cidr
;
222 #define SAM3_N_NVM_BITS 3
223 unsigned gpnvm
[SAM3_N_NVM_BITS
];
224 unsigned total_flash_size
;
225 unsigned total_sram_size
;
227 #define SAM3_MAX_FLASH_BANKS 2
228 /* these are "initialized" from the global const data */
229 struct sam3_bank_private bank
[SAM3_MAX_FLASH_BANKS
];
233 struct sam3_chip
*next
;
236 /* this is "initialized" from the global const structure */
237 struct sam3_chip_details details
;
238 struct target
*target
;
243 struct sam3_reg_list
{
244 uint32_t address
; size_t struct_offset
; const char *name
;
245 void (*explain_func
)(struct sam3_chip
*pInfo
);
248 static struct sam3_chip
*all_sam3_chips
;
250 static struct sam3_chip
*get_current_sam3(struct command_context
*cmd_ctx
)
253 static struct sam3_chip
*p
;
255 t
= get_current_target(cmd_ctx
);
257 command_print(cmd_ctx
, "No current target?");
263 /* this should not happen */
264 /* the command is not registered until the chip is created? */
265 command_print(cmd_ctx
, "No SAM3 chips exist?");
274 command_print(cmd_ctx
, "Cannot find SAM3 chip?");
278 /* these are used to *initialize* the "pChip->details" structure. */
279 static const struct sam3_chip_details all_sam3_details
[] = {
280 /* Start at91sam3u* series */
282 .chipid_cidr
= 0x28100960,
283 .name
= "at91sam3u4e",
284 .total_flash_size
= 256 * 1024,
285 .total_sram_size
= 52 * 1024,
289 /* System boots at address 0x0 */
290 /* gpnvm[1] = selects boot code */
291 /* if gpnvm[1] == 0 */
292 /* boot is via "SAMBA" (rom) */
294 /* boot is via FLASH */
295 /* Selection is via gpnvm[2] */
298 /* NOTE: banks 0 & 1 switch places */
299 /* if gpnvm[2] == 0 */
300 /* Bank0 is the boot rom */
302 /* Bank1 is the boot rom */
311 .base_address
= FLASH_BANK0_BASE_U
,
312 .controller_address
= 0x400e0800,
313 .flash_wait_states
= 6, /* workaround silicon bug */
315 .size_bytes
= 128 * 1024,
327 .base_address
= FLASH_BANK1_BASE_U
,
328 .controller_address
= 0x400e0a00,
329 .flash_wait_states
= 6, /* workaround silicon bug */
331 .size_bytes
= 128 * 1024,
340 .chipid_cidr
= 0x281a0760,
341 .name
= "at91sam3u2e",
342 .total_flash_size
= 128 * 1024,
343 .total_sram_size
= 36 * 1024,
347 /* System boots at address 0x0 */
348 /* gpnvm[1] = selects boot code */
349 /* if gpnvm[1] == 0 */
350 /* boot is via "SAMBA" (rom) */
352 /* boot is via FLASH */
353 /* Selection is via gpnvm[2] */
362 .base_address
= FLASH_BANK0_BASE_U
,
363 .controller_address
= 0x400e0800,
364 .flash_wait_states
= 6, /* workaround silicon bug */
366 .size_bytes
= 128 * 1024,
380 .chipid_cidr
= 0x28190560,
381 .name
= "at91sam3u1e",
382 .total_flash_size
= 64 * 1024,
383 .total_sram_size
= 20 * 1024,
387 /* System boots at address 0x0 */
388 /* gpnvm[1] = selects boot code */
389 /* if gpnvm[1] == 0 */
390 /* boot is via "SAMBA" (rom) */
392 /* boot is via FLASH */
393 /* Selection is via gpnvm[2] */
404 .base_address
= FLASH_BANK0_BASE_U
,
405 .controller_address
= 0x400e0800,
406 .flash_wait_states
= 6, /* workaround silicon bug */
408 .size_bytes
= 64 * 1024,
424 .chipid_cidr
= 0x28000960,
425 .name
= "at91sam3u4c",
426 .total_flash_size
= 256 * 1024,
427 .total_sram_size
= 52 * 1024,
431 /* System boots at address 0x0 */
432 /* gpnvm[1] = selects boot code */
433 /* if gpnvm[1] == 0 */
434 /* boot is via "SAMBA" (rom) */
436 /* boot is via FLASH */
437 /* Selection is via gpnvm[2] */
440 /* NOTE: banks 0 & 1 switch places */
441 /* if gpnvm[2] == 0 */
442 /* Bank0 is the boot rom */
444 /* Bank1 is the boot rom */
453 .base_address
= FLASH_BANK0_BASE_U
,
454 .controller_address
= 0x400e0800,
455 .flash_wait_states
= 6, /* workaround silicon bug */
457 .size_bytes
= 128 * 1024,
468 .base_address
= FLASH_BANK1_BASE_U
,
469 .controller_address
= 0x400e0a00,
470 .flash_wait_states
= 6, /* workaround silicon bug */
472 .size_bytes
= 128 * 1024,
481 .chipid_cidr
= 0x280a0760,
482 .name
= "at91sam3u2c",
483 .total_flash_size
= 128 * 1024,
484 .total_sram_size
= 36 * 1024,
488 /* System boots at address 0x0 */
489 /* gpnvm[1] = selects boot code */
490 /* if gpnvm[1] == 0 */
491 /* boot is via "SAMBA" (rom) */
493 /* boot is via FLASH */
494 /* Selection is via gpnvm[2] */
503 .base_address
= FLASH_BANK0_BASE_U
,
504 .controller_address
= 0x400e0800,
505 .flash_wait_states
= 6, /* workaround silicon bug */
507 .size_bytes
= 128 * 1024,
521 .chipid_cidr
= 0x28090560,
522 .name
= "at91sam3u1c",
523 .total_flash_size
= 64 * 1024,
524 .total_sram_size
= 20 * 1024,
528 /* System boots at address 0x0 */
529 /* gpnvm[1] = selects boot code */
530 /* if gpnvm[1] == 0 */
531 /* boot is via "SAMBA" (rom) */
533 /* boot is via FLASH */
534 /* Selection is via gpnvm[2] */
545 .base_address
= FLASH_BANK0_BASE_U
,
546 .controller_address
= 0x400e0800,
547 .flash_wait_states
= 6, /* workaround silicon bug */
549 .size_bytes
= 64 * 1024,
564 /* Start at91sam3s* series */
566 /* Note: The preliminary at91sam3s datasheet says on page 302 */
567 /* that the flash controller is at address 0x400E0800. */
568 /* This is _not_ the case, the controller resides at address 0x400e0a0. */
570 .chipid_cidr
= 0x28A00960,
571 .name
= "at91sam3s4c",
572 .total_flash_size
= 256 * 1024,
573 .total_sram_size
= 48 * 1024,
583 .base_address
= FLASH_BANK_BASE_S
,
584 .controller_address
= 0x400e0a00,
585 .flash_wait_states
= 6, /* workaround silicon bug */
587 .size_bytes
= 256 * 1024,
589 .sector_size
= 16384,
603 .chipid_cidr
= 0x28900960,
604 .name
= "at91sam3s4b",
605 .total_flash_size
= 256 * 1024,
606 .total_sram_size
= 48 * 1024,
616 .base_address
= FLASH_BANK_BASE_S
,
617 .controller_address
= 0x400e0a00,
618 .flash_wait_states
= 6, /* workaround silicon bug */
620 .size_bytes
= 256 * 1024,
622 .sector_size
= 16384,
635 .chipid_cidr
= 0x28800960,
636 .name
= "at91sam3s4a",
637 .total_flash_size
= 256 * 1024,
638 .total_sram_size
= 48 * 1024,
648 .base_address
= FLASH_BANK_BASE_S
,
649 .controller_address
= 0x400e0a00,
650 .flash_wait_states
= 6, /* workaround silicon bug */
652 .size_bytes
= 256 * 1024,
654 .sector_size
= 16384,
667 .chipid_cidr
= 0x28AA0760,
668 .name
= "at91sam3s2c",
669 .total_flash_size
= 128 * 1024,
670 .total_sram_size
= 32 * 1024,
680 .base_address
= FLASH_BANK_BASE_S
,
681 .controller_address
= 0x400e0a00,
682 .flash_wait_states
= 6, /* workaround silicon bug */
684 .size_bytes
= 128 * 1024,
686 .sector_size
= 16384,
699 .chipid_cidr
= 0x289A0760,
700 .name
= "at91sam3s2b",
701 .total_flash_size
= 128 * 1024,
702 .total_sram_size
= 32 * 1024,
712 .base_address
= FLASH_BANK_BASE_S
,
713 .controller_address
= 0x400e0a00,
714 .flash_wait_states
= 6, /* workaround silicon bug */
716 .size_bytes
= 128 * 1024,
718 .sector_size
= 16384,
731 .chipid_cidr
= 0x288A0760,
732 .name
= "at91sam3s2a",
733 .total_flash_size
= 128 * 1024,
734 .total_sram_size
= 32 * 1024,
744 .base_address
= FLASH_BANK_BASE_S
,
745 .controller_address
= 0x400e0a00,
746 .flash_wait_states
= 6, /* workaround silicon bug */
748 .size_bytes
= 128 * 1024,
750 .sector_size
= 16384,
763 .chipid_cidr
= 0x28A90560,
764 .name
= "at91sam3s1c",
765 .total_flash_size
= 64 * 1024,
766 .total_sram_size
= 16 * 1024,
776 .base_address
= FLASH_BANK_BASE_S
,
777 .controller_address
= 0x400e0a00,
778 .flash_wait_states
= 6, /* workaround silicon bug */
780 .size_bytes
= 64 * 1024,
782 .sector_size
= 16384,
795 .chipid_cidr
= 0x28990560,
796 .name
= "at91sam3s1b",
797 .total_flash_size
= 64 * 1024,
798 .total_sram_size
= 16 * 1024,
808 .base_address
= FLASH_BANK_BASE_S
,
809 .controller_address
= 0x400e0a00,
810 .flash_wait_states
= 6, /* workaround silicon bug */
812 .size_bytes
= 64 * 1024,
814 .sector_size
= 16384,
827 .chipid_cidr
= 0x28890560,
828 .name
= "at91sam3s1a",
829 .total_flash_size
= 64 * 1024,
830 .total_sram_size
= 16 * 1024,
840 .base_address
= FLASH_BANK_BASE_S
,
841 .controller_address
= 0x400e0a00,
842 .flash_wait_states
= 6, /* workaround silicon bug */
844 .size_bytes
= 64 * 1024,
846 .sector_size
= 16384,
859 /* Start at91sam3n* series */
861 .chipid_cidr
= 0x29540960,
862 .name
= "at91sam3n4c",
863 .total_flash_size
= 256 * 1024,
864 .total_sram_size
= 24 * 1024,
868 /* System boots at address 0x0 */
869 /* gpnvm[1] = selects boot code */
870 /* if gpnvm[1] == 0 */
871 /* boot is via "SAMBA" (rom) */
873 /* boot is via FLASH */
874 /* Selection is via gpnvm[2] */
877 /* NOTE: banks 0 & 1 switch places */
878 /* if gpnvm[2] == 0 */
879 /* Bank0 is the boot rom */
881 /* Bank1 is the boot rom */
890 .base_address
= FLASH_BANK_BASE_N
,
891 .controller_address
= 0x400e0A00,
892 .flash_wait_states
= 6, /* workaround silicon bug */
894 .size_bytes
= 256 * 1024,
896 .sector_size
= 16384,
910 .chipid_cidr
= 0x29440960,
911 .name
= "at91sam3n4b",
912 .total_flash_size
= 256 * 1024,
913 .total_sram_size
= 24 * 1024,
917 /* System boots at address 0x0 */
918 /* gpnvm[1] = selects boot code */
919 /* if gpnvm[1] == 0 */
920 /* boot is via "SAMBA" (rom) */
922 /* boot is via FLASH */
923 /* Selection is via gpnvm[2] */
926 /* NOTE: banks 0 & 1 switch places */
927 /* if gpnvm[2] == 0 */
928 /* Bank0 is the boot rom */
930 /* Bank1 is the boot rom */
939 .base_address
= FLASH_BANK_BASE_N
,
940 .controller_address
= 0x400e0A00,
941 .flash_wait_states
= 6, /* workaround silicon bug */
943 .size_bytes
= 256 * 1024,
945 .sector_size
= 16384,
959 .chipid_cidr
= 0x29340960,
960 .name
= "at91sam3n4a",
961 .total_flash_size
= 256 * 1024,
962 .total_sram_size
= 24 * 1024,
966 /* System boots at address 0x0 */
967 /* gpnvm[1] = selects boot code */
968 /* if gpnvm[1] == 0 */
969 /* boot is via "SAMBA" (rom) */
971 /* boot is via FLASH */
972 /* Selection is via gpnvm[2] */
975 /* NOTE: banks 0 & 1 switch places */
976 /* if gpnvm[2] == 0 */
977 /* Bank0 is the boot rom */
979 /* Bank1 is the boot rom */
988 .base_address
= FLASH_BANK_BASE_N
,
989 .controller_address
= 0x400e0A00,
990 .flash_wait_states
= 6, /* workaround silicon bug */
992 .size_bytes
= 256 * 1024,
994 .sector_size
= 16384,
1008 .chipid_cidr
= 0x29590760,
1009 .name
= "at91sam3n2c",
1010 .total_flash_size
= 128 * 1024,
1011 .total_sram_size
= 16 * 1024,
1015 /* System boots at address 0x0 */
1016 /* gpnvm[1] = selects boot code */
1017 /* if gpnvm[1] == 0 */
1018 /* boot is via "SAMBA" (rom) */
1020 /* boot is via FLASH */
1021 /* Selection is via gpnvm[2] */
1024 /* NOTE: banks 0 & 1 switch places */
1025 /* if gpnvm[2] == 0 */
1026 /* Bank0 is the boot rom */
1028 /* Bank1 is the boot rom */
1037 .base_address
= FLASH_BANK_BASE_N
,
1038 .controller_address
= 0x400e0A00,
1039 .flash_wait_states
= 6, /* workaround silicon bug */
1041 .size_bytes
= 128 * 1024,
1043 .sector_size
= 16384,
1057 .chipid_cidr
= 0x29490760,
1058 .name
= "at91sam3n2b",
1059 .total_flash_size
= 128 * 1024,
1060 .total_sram_size
= 16 * 1024,
1064 /* System boots at address 0x0 */
1065 /* gpnvm[1] = selects boot code */
1066 /* if gpnvm[1] == 0 */
1067 /* boot is via "SAMBA" (rom) */
1069 /* boot is via FLASH */
1070 /* Selection is via gpnvm[2] */
1073 /* NOTE: banks 0 & 1 switch places */
1074 /* if gpnvm[2] == 0 */
1075 /* Bank0 is the boot rom */
1077 /* Bank1 is the boot rom */
1086 .base_address
= FLASH_BANK_BASE_N
,
1087 .controller_address
= 0x400e0A00,
1088 .flash_wait_states
= 6, /* workaround silicon bug */
1090 .size_bytes
= 128 * 1024,
1092 .sector_size
= 16384,
1106 .chipid_cidr
= 0x29390760,
1107 .name
= "at91sam3n2a",
1108 .total_flash_size
= 128 * 1024,
1109 .total_sram_size
= 16 * 1024,
1113 /* System boots at address 0x0 */
1114 /* gpnvm[1] = selects boot code */
1115 /* if gpnvm[1] == 0 */
1116 /* boot is via "SAMBA" (rom) */
1118 /* boot is via FLASH */
1119 /* Selection is via gpnvm[2] */
1122 /* NOTE: banks 0 & 1 switch places */
1123 /* if gpnvm[2] == 0 */
1124 /* Bank0 is the boot rom */
1126 /* Bank1 is the boot rom */
1135 .base_address
= FLASH_BANK_BASE_N
,
1136 .controller_address
= 0x400e0A00,
1137 .flash_wait_states
= 6, /* workaround silicon bug */
1139 .size_bytes
= 128 * 1024,
1141 .sector_size
= 16384,
1155 .chipid_cidr
= 0x29580560,
1156 .name
= "at91sam3n1c",
1157 .total_flash_size
= 64 * 1024,
1158 .total_sram_size
= 8 * 1024,
1162 /* System boots at address 0x0 */
1163 /* gpnvm[1] = selects boot code */
1164 /* if gpnvm[1] == 0 */
1165 /* boot is via "SAMBA" (rom) */
1167 /* boot is via FLASH */
1168 /* Selection is via gpnvm[2] */
1171 /* NOTE: banks 0 & 1 switch places */
1172 /* if gpnvm[2] == 0 */
1173 /* Bank0 is the boot rom */
1175 /* Bank1 is the boot rom */
1184 .base_address
= FLASH_BANK_BASE_N
,
1185 .controller_address
= 0x400e0A00,
1186 .flash_wait_states
= 6, /* workaround silicon bug */
1188 .size_bytes
= 64 * 1024,
1190 .sector_size
= 16384,
1204 .chipid_cidr
= 0x29480560,
1205 .name
= "at91sam3n1b",
1206 .total_flash_size
= 64 * 1024,
1207 .total_sram_size
= 8 * 1024,
1211 /* System boots at address 0x0 */
1212 /* gpnvm[1] = selects boot code */
1213 /* if gpnvm[1] == 0 */
1214 /* boot is via "SAMBA" (rom) */
1216 /* boot is via FLASH */
1217 /* Selection is via gpnvm[2] */
1220 /* NOTE: banks 0 & 1 switch places */
1221 /* if gpnvm[2] == 0 */
1222 /* Bank0 is the boot rom */
1224 /* Bank1 is the boot rom */
1233 .base_address
= FLASH_BANK_BASE_N
,
1234 .controller_address
= 0x400e0A00,
1235 .flash_wait_states
= 6, /* workaround silicon bug */
1237 .size_bytes
= 64 * 1024,
1239 .sector_size
= 16384,
1253 .chipid_cidr
= 0x29380560,
1254 .name
= "at91sam3n1a",
1255 .total_flash_size
= 64 * 1024,
1256 .total_sram_size
= 8 * 1024,
1260 /* System boots at address 0x0 */
1261 /* gpnvm[1] = selects boot code */
1262 /* if gpnvm[1] == 0 */
1263 /* boot is via "SAMBA" (rom) */
1265 /* boot is via FLASH */
1266 /* Selection is via gpnvm[2] */
1269 /* NOTE: banks 0 & 1 switch places */
1270 /* if gpnvm[2] == 0 */
1271 /* Bank0 is the boot rom */
1273 /* Bank1 is the boot rom */
1282 .base_address
= FLASH_BANK_BASE_N
,
1283 .controller_address
= 0x400e0A00,
1284 .flash_wait_states
= 6, /* workaround silicon bug */
1286 .size_bytes
= 64 * 1024,
1288 .sector_size
= 16384,
1301 /* Start at91sam3a series*/
1302 /* System boots at address 0x0 */
1303 /* gpnvm[1] = selects boot code */
1304 /* if gpnvm[1] == 0 */
1305 /* boot is via "SAMBA" (rom) */
1307 /* boot is via FLASH */
1308 /* Selection is via gpnvm[2] */
1311 /* NOTE: banks 0 & 1 switch places */
1312 /* if gpnvm[2] == 0 */
1313 /* Bank0 is the boot rom */
1315 /* Bank1 is the boot rom */
1319 .chipid_cidr
= 0x283E0A60,
1320 .name
= "at91sam3a8c",
1321 .total_flash_size
= 512 * 1024,
1322 .total_sram_size
= 96 * 1024,
1332 .base_address
= FLASH_BANK0_BASE_AX
,
1333 .controller_address
= 0x400e0a00,
1334 .flash_wait_states
= 6, /* workaround silicon bug */
1336 .size_bytes
= 256 * 1024,
1338 .sector_size
= 16384,
1347 .base_address
= FLASH_BANK1_BASE_512K_AX
,
1348 .controller_address
= 0x400e0c00,
1349 .flash_wait_states
= 6, /* workaround silicon bug */
1351 .size_bytes
= 256 * 1024,
1353 .sector_size
= 16384,
1360 .chipid_cidr
= 0x283B0960,
1361 .name
= "at91sam3a4c",
1362 .total_flash_size
= 256 * 1024,
1363 .total_sram_size
= 64 * 1024,
1373 .base_address
= FLASH_BANK0_BASE_AX
,
1374 .controller_address
= 0x400e0a00,
1375 .flash_wait_states
= 6, /* workaround silicon bug */
1377 .size_bytes
= 128 * 1024,
1379 .sector_size
= 16384,
1388 .base_address
= FLASH_BANK1_BASE_256K_AX
,
1389 .controller_address
= 0x400e0c00,
1390 .flash_wait_states
= 6, /* workaround silicon bug */
1392 .size_bytes
= 128 * 1024,
1394 .sector_size
= 16384,
1401 /* Start at91sam3x* series */
1402 /* System boots at address 0x0 */
1403 /* gpnvm[1] = selects boot code */
1404 /* if gpnvm[1] == 0 */
1405 /* boot is via "SAMBA" (rom) */
1407 /* boot is via FLASH */
1408 /* Selection is via gpnvm[2] */
1411 /* NOTE: banks 0 & 1 switch places */
1412 /* if gpnvm[2] == 0 */
1413 /* Bank0 is the boot rom */
1415 /* Bank1 is the boot rom */
1418 .chipid_cidr
= 0x286E0A20,
1419 .name
= "at91sam3x8h",
1420 .total_flash_size
= 512 * 1024,
1421 .total_sram_size
= 96 * 1024,
1431 .base_address
= FLASH_BANK0_BASE_AX
,
1432 .controller_address
= 0x400e0a00,
1433 .flash_wait_states
= 6, /* workaround silicon bug */
1435 .size_bytes
= 256 * 1024,
1437 .sector_size
= 16384,
1446 .base_address
= FLASH_BANK1_BASE_512K_AX
,
1447 .controller_address
= 0x400e0c00,
1448 .flash_wait_states
= 6, /* workaround silicon bug */
1450 .size_bytes
= 256 * 1024,
1452 .sector_size
= 16384,
1459 .chipid_cidr
= 0x285E0A60,
1460 .name
= "at91sam3x8e",
1461 .total_flash_size
= 512 * 1024,
1462 .total_sram_size
= 96 * 1024,
1472 .base_address
= FLASH_BANK0_BASE_AX
,
1473 .controller_address
= 0x400e0a00,
1474 .flash_wait_states
= 6, /* workaround silicon bug */
1476 .size_bytes
= 256 * 1024,
1478 .sector_size
= 16384,
1487 .base_address
= FLASH_BANK1_BASE_512K_AX
,
1488 .controller_address
= 0x400e0c00,
1489 .flash_wait_states
= 6, /* workaround silicon bug */
1491 .size_bytes
= 256 * 1024,
1493 .sector_size
= 16384,
1500 .chipid_cidr
= 0x284E0A60,
1501 .name
= "at91sam3x8c",
1502 .total_flash_size
= 512 * 1024,
1503 .total_sram_size
= 96 * 1024,
1513 .base_address
= FLASH_BANK0_BASE_AX
,
1514 .controller_address
= 0x400e0a00,
1515 .flash_wait_states
= 6, /* workaround silicon bug */
1517 .size_bytes
= 256 * 1024,
1519 .sector_size
= 16384,
1528 .base_address
= FLASH_BANK1_BASE_512K_AX
,
1529 .controller_address
= 0x400e0c00,
1530 .flash_wait_states
= 6, /* workaround silicon bug */
1532 .size_bytes
= 256 * 1024,
1534 .sector_size
= 16384,
1541 .chipid_cidr
= 0x285B0960,
1542 .name
= "at91sam3x4e",
1543 .total_flash_size
= 256 * 1024,
1544 .total_sram_size
= 64 * 1024,
1554 .base_address
= FLASH_BANK0_BASE_AX
,
1555 .controller_address
= 0x400e0a00,
1556 .flash_wait_states
= 6, /* workaround silicon bug */
1558 .size_bytes
= 128 * 1024,
1560 .sector_size
= 16384,
1569 .base_address
= FLASH_BANK1_BASE_256K_AX
,
1570 .controller_address
= 0x400e0c00,
1571 .flash_wait_states
= 6, /* workaround silicon bug */
1573 .size_bytes
= 128 * 1024,
1575 .sector_size
= 16384,
1582 .chipid_cidr
= 0x284B0960,
1583 .name
= "at91sam3x4c",
1584 .total_flash_size
= 256 * 1024,
1585 .total_sram_size
= 64 * 1024,
1595 .base_address
= FLASH_BANK0_BASE_AX
,
1596 .controller_address
= 0x400e0a00,
1597 .flash_wait_states
= 6, /* workaround silicon bug */
1599 .size_bytes
= 128 * 1024,
1601 .sector_size
= 16384,
1610 .base_address
= FLASH_BANK1_BASE_256K_AX
,
1611 .controller_address
= 0x400e0c00,
1612 .flash_wait_states
= 6, /* workaround silicon bug */
1614 .size_bytes
= 128 * 1024,
1616 .sector_size
= 16384,
1630 /***********************************************************************
1631 **********************************************************************
1632 **********************************************************************
1633 **********************************************************************
1634 **********************************************************************
1635 **********************************************************************/
1636 /* *ATMEL* style code - from the SAM3 driver code */
1639 * Get the current status of the EEFC and
1640 * the value of some status bits (LOCKE, PROGE).
1641 * @param pPrivate - info about the bank
1642 * @param v - result goes here
1644 static int EFC_GetStatus(struct sam3_bank_private
*pPrivate
, uint32_t *v
)
1647 r
= target_read_u32(pPrivate
->pChip
->target
,
1648 pPrivate
->controller_address
+ offset_EFC_FSR
,
1650 LOG_DEBUG("Status: 0x%08x (lockerror: %d, cmderror: %d, ready: %d)",
1652 ((unsigned int)((*v
>> 2) & 1)),
1653 ((unsigned int)((*v
>> 1) & 1)),
1654 ((unsigned int)((*v
>> 0) & 1)));
1660 * Get the result of the last executed command.
1661 * @param pPrivate - info about the bank
1662 * @param v - result goes here
1664 static int EFC_GetResult(struct sam3_bank_private
*pPrivate
, uint32_t *v
)
1668 r
= target_read_u32(pPrivate
->pChip
->target
,
1669 pPrivate
->controller_address
+ offset_EFC_FRR
,
1673 LOG_DEBUG("Result: 0x%08x", ((unsigned int)(rv
)));
1677 static int EFC_StartCommand(struct sam3_bank_private
*pPrivate
,
1678 unsigned command
, unsigned argument
)
1687 /* Check command & argument */
1690 case AT91C_EFC_FCMD_WP
:
1691 case AT91C_EFC_FCMD_WPL
:
1692 case AT91C_EFC_FCMD_EWP
:
1693 case AT91C_EFC_FCMD_EWPL
:
1694 /* case AT91C_EFC_FCMD_EPL: */
1695 /* case AT91C_EFC_FCMD_EPA: */
1696 case AT91C_EFC_FCMD_SLB
:
1697 case AT91C_EFC_FCMD_CLB
:
1698 n
= (pPrivate
->size_bytes
/ pPrivate
->page_size
);
1700 LOG_ERROR("*BUG*: Embedded flash has only %u pages", (unsigned)(n
));
1703 case AT91C_EFC_FCMD_SFB
:
1704 case AT91C_EFC_FCMD_CFB
:
1705 if (argument
>= pPrivate
->pChip
->details
.n_gpnvms
) {
1706 LOG_ERROR("*BUG*: Embedded flash has only %d GPNVMs",
1707 pPrivate
->pChip
->details
.n_gpnvms
);
1711 case AT91C_EFC_FCMD_GETD
:
1712 case AT91C_EFC_FCMD_EA
:
1713 case AT91C_EFC_FCMD_GLB
:
1714 case AT91C_EFC_FCMD_GFB
:
1715 case AT91C_EFC_FCMD_STUI
:
1716 case AT91C_EFC_FCMD_SPUI
:
1718 LOG_ERROR("Argument is meaningless for cmd: %d", command
);
1721 LOG_ERROR("Unknown command %d", command
);
1725 if (command
== AT91C_EFC_FCMD_SPUI
) {
1726 /* this is a very special situation. */
1727 /* Situation (1) - error/retry - see below */
1728 /* And we are being called recursively */
1729 /* Situation (2) - normal, finished reading unique id */
1731 /* it should be "ready" */
1732 EFC_GetStatus(pPrivate
, &v
);
1734 /* then it is ready */
1738 /* we have done this before */
1739 /* the controller is not responding. */
1740 LOG_ERROR("flash controller(%d) is not ready! Error",
1741 pPrivate
->bank_number
);
1745 LOG_ERROR("Flash controller(%d) is not ready, attempting reset",
1746 pPrivate
->bank_number
);
1747 /* we do that by issuing the *STOP* command */
1748 EFC_StartCommand(pPrivate
, AT91C_EFC_FCMD_SPUI
, 0);
1749 /* above is recursive, and further recursion is blocked by */
1750 /* if (command == AT91C_EFC_FCMD_SPUI) above */
1756 v
= (0x5A << 24) | (argument
<< 8) | command
;
1757 LOG_DEBUG("Command: 0x%08x", ((unsigned int)(v
)));
1758 r
= target_write_u32(pPrivate
->pBank
->target
,
1759 pPrivate
->controller_address
+ offset_EFC_FCR
, v
);
1761 LOG_DEBUG("Error Write failed");
1766 * Performs the given command and wait until its completion (or an error).
1767 * @param pPrivate - info about the bank
1768 * @param command - Command to perform.
1769 * @param argument - Optional command argument.
1770 * @param status - put command status bits here
1772 static int EFC_PerformCommand(struct sam3_bank_private
*pPrivate
,
1780 long long ms_now
, ms_end
;
1786 r
= EFC_StartCommand(pPrivate
, command
, argument
);
1790 ms_end
= 500 + timeval_ms();
1793 r
= EFC_GetStatus(pPrivate
, &v
);
1796 ms_now
= timeval_ms();
1797 if (ms_now
> ms_end
) {
1799 LOG_ERROR("Command timeout");
1802 } while ((v
& 1) == 0);
1806 *status
= (v
& 0x6);
1812 * Read the unique ID.
1813 * @param pPrivate - info about the bank
1814 * The unique ID is stored in the 'pPrivate' structure.
1816 static int FLASHD_ReadUniqueID(struct sam3_bank_private
*pPrivate
)
1822 pPrivate
->pChip
->cfg
.unique_id
[0] = 0;
1823 pPrivate
->pChip
->cfg
.unique_id
[1] = 0;
1824 pPrivate
->pChip
->cfg
.unique_id
[2] = 0;
1825 pPrivate
->pChip
->cfg
.unique_id
[3] = 0;
1828 r
= EFC_StartCommand(pPrivate
, AT91C_EFC_FCMD_STUI
, 0);
1832 for (x
= 0; x
< 4; x
++) {
1833 r
= target_read_u32(pPrivate
->pChip
->target
,
1834 pPrivate
->pBank
->base
+ (x
* 4),
1838 pPrivate
->pChip
->cfg
.unique_id
[x
] = v
;
1841 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_SPUI
, 0, NULL
);
1842 LOG_DEBUG("End: R=%d, id = 0x%08x, 0x%08x, 0x%08x, 0x%08x",
1844 (unsigned int)(pPrivate
->pChip
->cfg
.unique_id
[0]),
1845 (unsigned int)(pPrivate
->pChip
->cfg
.unique_id
[1]),
1846 (unsigned int)(pPrivate
->pChip
->cfg
.unique_id
[2]),
1847 (unsigned int)(pPrivate
->pChip
->cfg
.unique_id
[3]));
1853 * Erases the entire flash.
1854 * @param pPrivate - the info about the bank.
1856 static int FLASHD_EraseEntireBank(struct sam3_bank_private
*pPrivate
)
1859 return EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_EA
, 0, NULL
);
1863 * Gets current GPNVM state.
1864 * @param pPrivate - info about the bank.
1865 * @param gpnvm - GPNVM bit index.
1866 * @param puthere - result stored here.
1868 /* ------------------------------------------------------------------------------ */
1869 static int FLASHD_GetGPNVM(struct sam3_bank_private
*pPrivate
, unsigned gpnvm
, unsigned *puthere
)
1875 if (pPrivate
->bank_number
!= 0) {
1876 LOG_ERROR("GPNVM only works with Bank0");
1880 if (gpnvm
>= pPrivate
->pChip
->details
.n_gpnvms
) {
1881 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1882 gpnvm
, pPrivate
->pChip
->details
.n_gpnvms
);
1886 /* Get GPNVMs status */
1887 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_GFB
, 0, NULL
);
1888 if (r
!= ERROR_OK
) {
1889 LOG_ERROR("Failed");
1893 r
= EFC_GetResult(pPrivate
, &v
);
1896 /* Check if GPNVM is set */
1897 /* get the bit and make it a 0/1 */
1898 *puthere
= (v
>> gpnvm
) & 1;
1905 * Clears the selected GPNVM bit.
1906 * @param pPrivate info about the bank
1907 * @param gpnvm GPNVM index.
1908 * @returns 0 if successful; otherwise returns an error code.
1910 static int FLASHD_ClrGPNVM(struct sam3_bank_private
*pPrivate
, unsigned gpnvm
)
1916 if (pPrivate
->bank_number
!= 0) {
1917 LOG_ERROR("GPNVM only works with Bank0");
1921 if (gpnvm
>= pPrivate
->pChip
->details
.n_gpnvms
) {
1922 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1923 gpnvm
, pPrivate
->pChip
->details
.n_gpnvms
);
1927 r
= FLASHD_GetGPNVM(pPrivate
, gpnvm
, &v
);
1928 if (r
!= ERROR_OK
) {
1929 LOG_DEBUG("Failed: %d", r
);
1932 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_CFB
, gpnvm
, NULL
);
1933 LOG_DEBUG("End: %d", r
);
1938 * Sets the selected GPNVM bit.
1939 * @param pPrivate info about the bank
1940 * @param gpnvm GPNVM index.
1942 static int FLASHD_SetGPNVM(struct sam3_bank_private
*pPrivate
, unsigned gpnvm
)
1947 if (pPrivate
->bank_number
!= 0) {
1948 LOG_ERROR("GPNVM only works with Bank0");
1952 if (gpnvm
>= pPrivate
->pChip
->details
.n_gpnvms
) {
1953 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1954 gpnvm
, pPrivate
->pChip
->details
.n_gpnvms
);
1958 r
= FLASHD_GetGPNVM(pPrivate
, gpnvm
, &v
);
1966 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_SFB
, gpnvm
, NULL
);
1972 * Returns a bit field (at most 64) of locked regions within a page.
1973 * @param pPrivate info about the bank
1974 * @param v where to store locked bits
1976 static int FLASHD_GetLockBits(struct sam3_bank_private
*pPrivate
, uint32_t *v
)
1980 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_GLB
, 0, NULL
);
1982 r
= EFC_GetResult(pPrivate
, v
);
1983 LOG_DEBUG("End: %d", r
);
1988 * Unlocks all the regions in the given address range.
1989 * @param pPrivate info about the bank
1990 * @param start_sector first sector to unlock
1991 * @param end_sector last (inclusive) to unlock
1994 static int FLASHD_Unlock(struct sam3_bank_private
*pPrivate
,
1995 unsigned start_sector
,
1996 unsigned end_sector
)
2001 uint32_t pages_per_sector
;
2003 pages_per_sector
= pPrivate
->sector_size
/ pPrivate
->page_size
;
2005 /* Unlock all pages */
2006 while (start_sector
<= end_sector
) {
2007 pg
= start_sector
* pages_per_sector
;
2009 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_CLB
, pg
, &status
);
2020 * @param pPrivate - info about the bank
2021 * @param start_sector - first sector to lock
2022 * @param end_sector - last sector (inclusive) to lock
2024 static int FLASHD_Lock(struct sam3_bank_private
*pPrivate
,
2025 unsigned start_sector
,
2026 unsigned end_sector
)
2030 uint32_t pages_per_sector
;
2033 pages_per_sector
= pPrivate
->sector_size
/ pPrivate
->page_size
;
2035 /* Lock all pages */
2036 while (start_sector
<= end_sector
) {
2037 pg
= start_sector
* pages_per_sector
;
2039 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_SLB
, pg
, &status
);
2047 /****** END SAM3 CODE ********/
2049 /* begin helpful debug code */
2050 /* print the fieldname, the field value, in dec & hex, and return field value */
2051 static uint32_t sam3_reg_fieldname(struct sam3_chip
*pChip
,
2052 const char *regname
,
2061 /* extract the field */
2063 v
= v
& ((1 << width
)-1);
2072 /* show the basics */
2073 LOG_USER_N("\t%*s: %*d [0x%0*x] ",
2074 REG_NAME_WIDTH
, regname
,
2080 static const char _unknown
[] = "unknown";
2081 static const char *const eproc_names
[] = {
2085 "cortex-m3", /* 3 */
2087 "arm926ejs", /* 5 */
2100 #define nvpsize2 nvpsize /* these two tables are identical */
2101 static const char *const nvpsize
[] = {
2104 "16K bytes", /* 2 */
2105 "32K bytes", /* 3 */
2107 "64K bytes", /* 5 */
2109 "128K bytes", /* 7 */
2111 "256K bytes", /* 9 */
2112 "512K bytes", /* 10 */
2114 "1024K bytes", /* 12 */
2116 "2048K bytes", /* 14 */
2120 static const char *const sramsize
[] = {
2121 "48K Bytes", /* 0 */
2125 "112K Bytes", /* 4 */
2127 "80K Bytes", /* 6 */
2128 "160K Bytes", /* 7 */
2130 "16K Bytes", /* 9 */
2131 "32K Bytes", /* 10 */
2132 "64K Bytes", /* 11 */
2133 "128K Bytes", /* 12 */
2134 "256K Bytes", /* 13 */
2135 "96K Bytes", /* 14 */
2136 "512K Bytes", /* 15 */
2140 static const struct archnames
{ unsigned value
; const char *name
; } archnames
[] = {
2141 { 0x19, "AT91SAM9xx Series" },
2142 { 0x29, "AT91SAM9XExx Series" },
2143 { 0x34, "AT91x34 Series" },
2144 { 0x37, "CAP7 Series" },
2145 { 0x39, "CAP9 Series" },
2146 { 0x3B, "CAP11 Series" },
2147 { 0x40, "AT91x40 Series" },
2148 { 0x42, "AT91x42 Series" },
2149 { 0x55, "AT91x55 Series" },
2150 { 0x60, "AT91SAM7Axx Series" },
2151 { 0x61, "AT91SAM7AQxx Series" },
2152 { 0x63, "AT91x63 Series" },
2153 { 0x70, "AT91SAM7Sxx Series" },
2154 { 0x71, "AT91SAM7XCxx Series" },
2155 { 0x72, "AT91SAM7SExx Series" },
2156 { 0x73, "AT91SAM7Lxx Series" },
2157 { 0x75, "AT91SAM7Xxx Series" },
2158 { 0x76, "AT91SAM7SLxx Series" },
2159 { 0x80, "ATSAM3UxC Series (100-pin version)" },
2160 { 0x81, "ATSAM3UxE Series (144-pin version)" },
2161 { 0x83, "ATSAM3AxC Series (100-pin version)" },
2162 { 0x84, "ATSAM3XxC Series (100-pin version)" },
2163 { 0x85, "ATSAM3XxE Series (144-pin version)" },
2164 { 0x86, "ATSAM3XxG Series (208/217-pin version)" },
2165 { 0x88, "ATSAM3SxA Series (48-pin version)" },
2166 { 0x89, "ATSAM3SxB Series (64-pin version)" },
2167 { 0x8A, "ATSAM3SxC Series (100-pin version)" },
2168 { 0x92, "AT91x92 Series" },
2169 { 0x93, "ATSAM3NxA Series (48-pin version)" },
2170 { 0x94, "ATSAM3NxB Series (64-pin version)" },
2171 { 0x95, "ATSAM3NxC Series (100-pin version)" },
2172 { 0x98, "ATSAM3SDxA Series (48-pin version)" },
2173 { 0x99, "ATSAM3SDxB Series (64-pin version)" },
2174 { 0x9A, "ATSAM3SDxC Series (100-pin version)" },
2175 { 0xA5, "ATSAM5A" },
2176 { 0xF0, "AT75Cxx Series" },
2180 static const char *const nvptype
[] = {
2182 "romless or onchip flash", /* 1 */
2183 "embedded flash memory",/* 2 */
2184 "rom(nvpsiz) + embedded flash (nvpsiz2)", /* 3 */
2185 "sram emulating flash", /* 4 */
2191 static const char *_yes_or_no(uint32_t v
)
2199 static const char *const _rc_freq
[] = {
2200 "4 MHz", "8 MHz", "12 MHz", "reserved"
2203 static void sam3_explain_ckgr_mor(struct sam3_chip
*pChip
)
2208 v
= sam3_reg_fieldname(pChip
, "MOSCXTEN", pChip
->cfg
.CKGR_MOR
, 0, 1);
2209 LOG_USER("(main xtal enabled: %s)", _yes_or_no(v
));
2210 v
= sam3_reg_fieldname(pChip
, "MOSCXTBY", pChip
->cfg
.CKGR_MOR
, 1, 1);
2211 LOG_USER("(main osc bypass: %s)", _yes_or_no(v
));
2212 rcen
= sam3_reg_fieldname(pChip
, "MOSCRCEN", pChip
->cfg
.CKGR_MOR
, 3, 1);
2213 LOG_USER("(onchip RC-OSC enabled: %s)", _yes_or_no(rcen
));
2214 v
= sam3_reg_fieldname(pChip
, "MOSCRCF", pChip
->cfg
.CKGR_MOR
, 4, 3);
2215 LOG_USER("(onchip RC-OSC freq: %s)", _rc_freq
[v
]);
2217 pChip
->cfg
.rc_freq
= 0;
2221 pChip
->cfg
.rc_freq
= 0;
2224 pChip
->cfg
.rc_freq
= 4 * 1000 * 1000;
2227 pChip
->cfg
.rc_freq
= 8 * 1000 * 1000;
2230 pChip
->cfg
.rc_freq
= 12 * 1000 * 1000;
2235 v
= sam3_reg_fieldname(pChip
, "MOSCXTST", pChip
->cfg
.CKGR_MOR
, 8, 8);
2236 LOG_USER("(startup clks, time= %f uSecs)",
2237 ((float)(v
* 1000000)) / ((float)(pChip
->cfg
.slow_freq
)));
2238 v
= sam3_reg_fieldname(pChip
, "MOSCSEL", pChip
->cfg
.CKGR_MOR
, 24, 1);
2239 LOG_USER("(mainosc source: %s)",
2240 v
? "external xtal" : "internal RC");
2242 v
= sam3_reg_fieldname(pChip
, "CFDEN", pChip
->cfg
.CKGR_MOR
, 25, 1);
2243 LOG_USER("(clock failure enabled: %s)",
2247 static void sam3_explain_chipid_cidr(struct sam3_chip
*pChip
)
2253 sam3_reg_fieldname(pChip
, "Version", pChip
->cfg
.CHIPID_CIDR
, 0, 5);
2256 v
= sam3_reg_fieldname(pChip
, "EPROC", pChip
->cfg
.CHIPID_CIDR
, 5, 3);
2257 LOG_USER("%s", eproc_names
[v
]);
2259 v
= sam3_reg_fieldname(pChip
, "NVPSIZE", pChip
->cfg
.CHIPID_CIDR
, 8, 4);
2260 LOG_USER("%s", nvpsize
[v
]);
2262 v
= sam3_reg_fieldname(pChip
, "NVPSIZE2", pChip
->cfg
.CHIPID_CIDR
, 12, 4);
2263 LOG_USER("%s", nvpsize2
[v
]);
2265 v
= sam3_reg_fieldname(pChip
, "SRAMSIZE", pChip
->cfg
.CHIPID_CIDR
, 16, 4);
2266 LOG_USER("%s", sramsize
[v
]);
2268 v
= sam3_reg_fieldname(pChip
, "ARCH", pChip
->cfg
.CHIPID_CIDR
, 20, 8);
2270 for (x
= 0; archnames
[x
].name
; x
++) {
2271 if (v
== archnames
[x
].value
) {
2272 cp
= archnames
[x
].name
;
2279 v
= sam3_reg_fieldname(pChip
, "NVPTYP", pChip
->cfg
.CHIPID_CIDR
, 28, 3);
2280 LOG_USER("%s", nvptype
[v
]);
2282 v
= sam3_reg_fieldname(pChip
, "EXTID", pChip
->cfg
.CHIPID_CIDR
, 31, 1);
2283 LOG_USER("(exists: %s)", _yes_or_no(v
));
2286 static void sam3_explain_ckgr_mcfr(struct sam3_chip
*pChip
)
2290 v
= sam3_reg_fieldname(pChip
, "MAINFRDY", pChip
->cfg
.CKGR_MCFR
, 16, 1);
2291 LOG_USER("(main ready: %s)", _yes_or_no(v
));
2293 v
= sam3_reg_fieldname(pChip
, "MAINF", pChip
->cfg
.CKGR_MCFR
, 0, 16);
2295 v
= (v
* pChip
->cfg
.slow_freq
) / 16;
2296 pChip
->cfg
.mainosc_freq
= v
;
2298 LOG_USER("(%3.03f Mhz (%d.%03dkhz slowclk)",
2300 pChip
->cfg
.slow_freq
/ 1000,
2301 pChip
->cfg
.slow_freq
% 1000);
2304 static void sam3_explain_ckgr_plla(struct sam3_chip
*pChip
)
2306 uint32_t mula
, diva
;
2308 diva
= sam3_reg_fieldname(pChip
, "DIVA", pChip
->cfg
.CKGR_PLLAR
, 0, 8);
2310 mula
= sam3_reg_fieldname(pChip
, "MULA", pChip
->cfg
.CKGR_PLLAR
, 16, 11);
2312 pChip
->cfg
.plla_freq
= 0;
2314 LOG_USER("\tPLLA Freq: (Disabled,mula = 0)");
2316 LOG_USER("\tPLLA Freq: (Disabled,diva = 0)");
2317 else if (diva
== 1) {
2318 pChip
->cfg
.plla_freq
= (pChip
->cfg
.mainosc_freq
* (mula
+ 1));
2319 LOG_USER("\tPLLA Freq: %3.03f MHz",
2320 _tomhz(pChip
->cfg
.plla_freq
));
2324 static void sam3_explain_mckr(struct sam3_chip
*pChip
)
2326 uint32_t css
, pres
, fin
= 0;
2328 const char *cp
= NULL
;
2330 css
= sam3_reg_fieldname(pChip
, "CSS", pChip
->cfg
.PMC_MCKR
, 0, 2);
2333 fin
= pChip
->cfg
.slow_freq
;
2337 fin
= pChip
->cfg
.mainosc_freq
;
2341 fin
= pChip
->cfg
.plla_freq
;
2345 if (pChip
->cfg
.CKGR_UCKR
& (1 << 16)) {
2346 fin
= 480 * 1000 * 1000;
2350 cp
= "upll (*ERROR* UPLL is disabled)";
2358 LOG_USER("%s (%3.03f Mhz)",
2361 pres
= sam3_reg_fieldname(pChip
, "PRES", pChip
->cfg
.PMC_MCKR
, 4, 3);
2362 switch (pres
& 0x07) {
2365 cp
= "selected clock";
2399 LOG_USER("(%s)", cp
);
2401 /* sam3 has a *SINGLE* clock - */
2402 /* other at91 series parts have divisors for these. */
2403 pChip
->cfg
.cpu_freq
= fin
;
2404 pChip
->cfg
.mclk_freq
= fin
;
2405 pChip
->cfg
.fclk_freq
= fin
;
2406 LOG_USER("\t\tResult CPU Freq: %3.03f",
2411 static struct sam3_chip
*target2sam3(struct target
*pTarget
)
2413 struct sam3_chip
*pChip
;
2415 if (pTarget
== NULL
)
2418 pChip
= all_sam3_chips
;
2420 if (pChip
->target
== pTarget
)
2421 break; /* return below */
2423 pChip
= pChip
->next
;
2429 static uint32_t *sam3_get_reg_ptr(struct sam3_cfg
*pCfg
, const struct sam3_reg_list
*pList
)
2431 /* this function exists to help */
2432 /* keep funky offsetof() errors */
2433 /* and casting from causing bugs */
2435 /* By using prototypes - we can detect what would */
2436 /* be casting errors. */
2438 return (uint32_t *)(void *)(((char *)(pCfg
)) + pList
->struct_offset
);
2442 #define SAM3_ENTRY(NAME, FUNC) { .address = SAM3_ ## NAME, .struct_offset = offsetof( \
2444 NAME), # NAME, FUNC }
2445 static const struct sam3_reg_list sam3_all_regs
[] = {
2446 SAM3_ENTRY(CKGR_MOR
, sam3_explain_ckgr_mor
),
2447 SAM3_ENTRY(CKGR_MCFR
, sam3_explain_ckgr_mcfr
),
2448 SAM3_ENTRY(CKGR_PLLAR
, sam3_explain_ckgr_plla
),
2449 SAM3_ENTRY(CKGR_UCKR
, NULL
),
2450 SAM3_ENTRY(PMC_FSMR
, NULL
),
2451 SAM3_ENTRY(PMC_FSPR
, NULL
),
2452 SAM3_ENTRY(PMC_IMR
, NULL
),
2453 SAM3_ENTRY(PMC_MCKR
, sam3_explain_mckr
),
2454 SAM3_ENTRY(PMC_PCK0
, NULL
),
2455 SAM3_ENTRY(PMC_PCK1
, NULL
),
2456 SAM3_ENTRY(PMC_PCK2
, NULL
),
2457 SAM3_ENTRY(PMC_PCSR
, NULL
),
2458 SAM3_ENTRY(PMC_SCSR
, NULL
),
2459 SAM3_ENTRY(PMC_SR
, NULL
),
2460 SAM3_ENTRY(CHIPID_CIDR
, sam3_explain_chipid_cidr
),
2461 SAM3_ENTRY(CHIPID_CIDR2
, sam3_explain_chipid_cidr
),
2462 SAM3_ENTRY(CHIPID_EXID
, NULL
),
2463 SAM3_ENTRY(CHIPID_EXID2
, NULL
),
2464 /* TERMINATE THE LIST */
2469 static struct sam3_bank_private
*get_sam3_bank_private(struct flash_bank
*bank
)
2471 return (struct sam3_bank_private
*)(bank
->driver_priv
);
2475 * Given a pointer to where it goes in the structure,
2476 * determine the register name, address from the all registers table.
2478 static const struct sam3_reg_list
*sam3_GetReg(struct sam3_chip
*pChip
, uint32_t *goes_here
)
2480 const struct sam3_reg_list
*pReg
;
2482 pReg
= &(sam3_all_regs
[0]);
2483 while (pReg
->name
) {
2484 uint32_t *pPossible
;
2486 /* calculate where this one go.. */
2487 /* it is "possibly" this register. */
2489 pPossible
= ((uint32_t *)(void *)(((char *)(&(pChip
->cfg
))) + pReg
->struct_offset
));
2491 /* well? Is it this register */
2492 if (pPossible
== goes_here
) {
2500 /* This is *TOTAL*PANIC* - we are totally screwed. */
2501 LOG_ERROR("INVALID SAM3 REGISTER");
2505 static int sam3_ReadThisReg(struct sam3_chip
*pChip
, uint32_t *goes_here
)
2507 const struct sam3_reg_list
*pReg
;
2510 pReg
= sam3_GetReg(pChip
, goes_here
);
2514 r
= target_read_u32(pChip
->target
, pReg
->address
, goes_here
);
2515 if (r
!= ERROR_OK
) {
2516 LOG_ERROR("Cannot read SAM3 register: %s @ 0x%08x, Err: %d",
2517 pReg
->name
, (unsigned)(pReg
->address
), r
);
2522 static int sam3_ReadAllRegs(struct sam3_chip
*pChip
)
2525 const struct sam3_reg_list
*pReg
;
2527 pReg
= &(sam3_all_regs
[0]);
2528 while (pReg
->name
) {
2529 r
= sam3_ReadThisReg(pChip
,
2530 sam3_get_reg_ptr(&(pChip
->cfg
), pReg
));
2531 if (r
!= ERROR_OK
) {
2532 LOG_ERROR("Cannot read SAM3 registere: %s @ 0x%08x, Error: %d",
2533 pReg
->name
, ((unsigned)(pReg
->address
)), r
);
2539 /* Chip identification register
2541 * Unfortunately, the chip identification register is not at
2542 * a constant address across all of the SAM3 series'. As a
2543 * consequence, a simple heuristic is used to find where it's
2546 * If the contents at the first address is zero, then we know
2547 * that the second address is where the chip id register is.
2548 * We can deduce this because for those SAM's that have the
2549 * chip id @ 0x400e0940, the first address, 0x400e0740, is
2550 * located in the memory map of the Power Management Controller
2551 * (PMC). Furthermore, the address is not used by the PMC.
2552 * So when read, the memory controller returns zero.*/
2553 if (pChip
->cfg
.CHIPID_CIDR
== 0) {
2554 /*Put the correct CIDR and EXID values in the pChip structure */
2555 pChip
->cfg
.CHIPID_CIDR
= pChip
->cfg
.CHIPID_CIDR2
;
2556 pChip
->cfg
.CHIPID_EXID
= pChip
->cfg
.CHIPID_EXID2
;
2561 static int sam3_GetInfo(struct sam3_chip
*pChip
)
2563 const struct sam3_reg_list
*pReg
;
2566 pReg
= &(sam3_all_regs
[0]);
2567 while (pReg
->name
) {
2568 /* display all regs */
2569 LOG_DEBUG("Start: %s", pReg
->name
);
2570 regval
= *sam3_get_reg_ptr(&(pChip
->cfg
), pReg
);
2571 LOG_USER("%*s: [0x%08x] -> 0x%08x",
2576 if (pReg
->explain_func
)
2577 (*(pReg
->explain_func
))(pChip
);
2578 LOG_DEBUG("End: %s", pReg
->name
);
2581 LOG_USER(" rc-osc: %3.03f MHz", _tomhz(pChip
->cfg
.rc_freq
));
2582 LOG_USER(" mainosc: %3.03f MHz", _tomhz(pChip
->cfg
.mainosc_freq
));
2583 LOG_USER(" plla: %3.03f MHz", _tomhz(pChip
->cfg
.plla_freq
));
2584 LOG_USER(" cpu-freq: %3.03f MHz", _tomhz(pChip
->cfg
.cpu_freq
));
2585 LOG_USER("mclk-freq: %3.03f MHz", _tomhz(pChip
->cfg
.mclk_freq
));
2587 LOG_USER(" UniqueId: 0x%08x 0x%08x 0x%08x 0x%08x",
2588 pChip
->cfg
.unique_id
[0],
2589 pChip
->cfg
.unique_id
[1],
2590 pChip
->cfg
.unique_id
[2],
2591 pChip
->cfg
.unique_id
[3]);
2596 static int sam3_erase_check(struct flash_bank
*bank
)
2601 if (bank
->target
->state
!= TARGET_HALTED
) {
2602 LOG_ERROR("Target not halted");
2603 return ERROR_TARGET_NOT_HALTED
;
2605 if (0 == bank
->num_sectors
) {
2606 LOG_ERROR("Target: not supported/not probed");
2610 LOG_INFO("sam3 - supports auto-erase, erase_check ignored");
2611 for (x
= 0; x
< bank
->num_sectors
; x
++)
2612 bank
->sectors
[x
].is_erased
= 1;
2618 static int sam3_protect_check(struct flash_bank
*bank
)
2623 struct sam3_bank_private
*pPrivate
;
2626 if (bank
->target
->state
!= TARGET_HALTED
) {
2627 LOG_ERROR("Target not halted");
2628 return ERROR_TARGET_NOT_HALTED
;
2631 pPrivate
= get_sam3_bank_private(bank
);
2633 LOG_ERROR("no private for this bank?");
2636 if (!(pPrivate
->probed
))
2637 return ERROR_FLASH_BANK_NOT_PROBED
;
2639 r
= FLASHD_GetLockBits(pPrivate
, &v
);
2640 if (r
!= ERROR_OK
) {
2641 LOG_DEBUG("Failed: %d", r
);
2645 for (x
= 0; x
< pPrivate
->nsectors
; x
++)
2646 bank
->sectors
[x
].is_protected
= (!!(v
& (1 << x
)));
2651 FLASH_BANK_COMMAND_HANDLER(sam3_flash_bank_command
)
2653 struct sam3_chip
*pChip
;
2655 pChip
= all_sam3_chips
;
2657 /* is this an existing chip? */
2659 if (pChip
->target
== bank
->target
)
2661 pChip
= pChip
->next
;
2665 /* this is a *NEW* chip */
2666 pChip
= calloc(1, sizeof(struct sam3_chip
));
2668 LOG_ERROR("NO RAM!");
2671 pChip
->target
= bank
->target
;
2672 /* insert at head */
2673 pChip
->next
= all_sam3_chips
;
2674 all_sam3_chips
= pChip
;
2675 pChip
->target
= bank
->target
;
2676 /* assumption is this runs at 32khz */
2677 pChip
->cfg
.slow_freq
= 32768;
2681 switch (bank
->base
) {
2683 LOG_ERROR("Address 0x%08x invalid bank address (try 0x%08x or 0x%08x "
2684 "[at91sam3u series] or 0x%08x [at91sam3s series] or "
2685 "0x%08x [at91sam3n series] or 0x%08x or 0x%08x or 0x%08x[at91sam3ax series] )",
2686 ((unsigned int)(bank
->base
)),
2687 ((unsigned int)(FLASH_BANK0_BASE_U
)),
2688 ((unsigned int)(FLASH_BANK1_BASE_U
)),
2689 ((unsigned int)(FLASH_BANK_BASE_S
)),
2690 ((unsigned int)(FLASH_BANK_BASE_N
)),
2691 ((unsigned int)(FLASH_BANK0_BASE_AX
)),
2692 ((unsigned int)(FLASH_BANK1_BASE_256K_AX
)),
2693 ((unsigned int)(FLASH_BANK1_BASE_512K_AX
)));
2697 /* at91sam3s and at91sam3n series only has bank 0*/
2698 /* at91sam3u and at91sam3ax series has the same address for bank 0*/
2699 case FLASH_BANK_BASE_S
:
2700 case FLASH_BANK0_BASE_U
:
2701 bank
->driver_priv
= &(pChip
->details
.bank
[0]);
2702 bank
->bank_number
= 0;
2703 pChip
->details
.bank
[0].pChip
= pChip
;
2704 pChip
->details
.bank
[0].pBank
= bank
;
2707 /* Bank 1 of at91sam3u or at91sam3ax series */
2708 case FLASH_BANK1_BASE_U
:
2709 case FLASH_BANK1_BASE_256K_AX
:
2710 case FLASH_BANK1_BASE_512K_AX
:
2711 bank
->driver_priv
= &(pChip
->details
.bank
[1]);
2712 bank
->bank_number
= 1;
2713 pChip
->details
.bank
[1].pChip
= pChip
;
2714 pChip
->details
.bank
[1].pBank
= bank
;
2718 /* we initialize after probing. */
2722 static int sam3_GetDetails(struct sam3_bank_private
*pPrivate
)
2724 const struct sam3_chip_details
*pDetails
;
2725 struct sam3_chip
*pChip
;
2726 struct flash_bank
*saved_banks
[SAM3_MAX_FLASH_BANKS
];
2730 pDetails
= all_sam3_details
;
2731 while (pDetails
->name
) {
2732 /* Compare cidr without version bits */
2733 if (pDetails
->chipid_cidr
== (pPrivate
->pChip
->cfg
.CHIPID_CIDR
& 0xFFFFFFE0))
2738 if (pDetails
->name
== NULL
) {
2739 LOG_ERROR("SAM3 ChipID 0x%08x not found in table (perhaps you can ID this chip?)",
2740 (unsigned int)(pPrivate
->pChip
->cfg
.CHIPID_CIDR
));
2741 /* Help the victim, print details about the chip */
2742 LOG_INFO("SAM3 CHIPID_CIDR: 0x%08x decodes as follows",
2743 pPrivate
->pChip
->cfg
.CHIPID_CIDR
);
2744 sam3_explain_chipid_cidr(pPrivate
->pChip
);
2748 /* DANGER: THERE ARE DRAGONS HERE */
2750 /* get our pChip - it is going */
2751 /* to be over-written shortly */
2752 pChip
= pPrivate
->pChip
;
2754 /* Note that, in reality: */
2756 /* pPrivate = &(pChip->details.bank[0]) */
2757 /* or pPrivate = &(pChip->details.bank[1]) */
2760 /* save the "bank" pointers */
2761 for (x
= 0; x
< SAM3_MAX_FLASH_BANKS
; x
++)
2762 saved_banks
[x
] = pChip
->details
.bank
[x
].pBank
;
2764 /* Overwrite the "details" structure. */
2765 memcpy(&(pPrivate
->pChip
->details
),
2767 sizeof(pPrivate
->pChip
->details
));
2769 /* now fix the ghosted pointers */
2770 for (x
= 0; x
< SAM3_MAX_FLASH_BANKS
; x
++) {
2771 pChip
->details
.bank
[x
].pChip
= pChip
;
2772 pChip
->details
.bank
[x
].pBank
= saved_banks
[x
];
2775 /* update the *BANK*SIZE* */
2781 static int _sam3_probe(struct flash_bank
*bank
, int noise
)
2785 struct sam3_bank_private
*pPrivate
;
2788 LOG_DEBUG("Begin: Bank: %d, Noise: %d", bank
->bank_number
, noise
);
2789 if (bank
->target
->state
!= TARGET_HALTED
) {
2790 LOG_ERROR("Target not halted");
2791 return ERROR_TARGET_NOT_HALTED
;
2794 pPrivate
= get_sam3_bank_private(bank
);
2796 LOG_ERROR("Invalid/unknown bank number");
2800 r
= sam3_ReadAllRegs(pPrivate
->pChip
);
2805 if (pPrivate
->pChip
->probed
)
2806 r
= sam3_GetInfo(pPrivate
->pChip
);
2808 r
= sam3_GetDetails(pPrivate
);
2812 /* update the flash bank size */
2813 for (x
= 0; x
< SAM3_MAX_FLASH_BANKS
; x
++) {
2814 if (bank
->base
== pPrivate
->pChip
->details
.bank
[x
].base_address
) {
2815 bank
->size
= pPrivate
->pChip
->details
.bank
[x
].size_bytes
;
2820 if (bank
->sectors
== NULL
) {
2821 bank
->sectors
= calloc(pPrivate
->nsectors
, (sizeof((bank
->sectors
)[0])));
2822 if (bank
->sectors
== NULL
) {
2823 LOG_ERROR("No memory!");
2826 bank
->num_sectors
= pPrivate
->nsectors
;
2828 for (x
= 0; ((int)(x
)) < bank
->num_sectors
; x
++) {
2829 bank
->sectors
[x
].size
= pPrivate
->sector_size
;
2830 bank
->sectors
[x
].offset
= x
* (pPrivate
->sector_size
);
2831 /* mark as unknown */
2832 bank
->sectors
[x
].is_erased
= -1;
2833 bank
->sectors
[x
].is_protected
= -1;
2837 pPrivate
->probed
= 1;
2839 r
= sam3_protect_check(bank
);
2843 LOG_DEBUG("Bank = %d, nbanks = %d",
2844 pPrivate
->bank_number
, pPrivate
->pChip
->details
.n_banks
);
2845 if ((pPrivate
->bank_number
+ 1) == pPrivate
->pChip
->details
.n_banks
) {
2846 /* read unique id, */
2847 /* it appears to be associated with the *last* flash bank. */
2848 FLASHD_ReadUniqueID(pPrivate
);
2854 static int sam3_probe(struct flash_bank
*bank
)
2856 return _sam3_probe(bank
, 1);
2859 static int sam3_auto_probe(struct flash_bank
*bank
)
2861 return _sam3_probe(bank
, 0);
2864 static int sam3_erase(struct flash_bank
*bank
, int first
, int last
)
2866 struct sam3_bank_private
*pPrivate
;
2870 if (bank
->target
->state
!= TARGET_HALTED
) {
2871 LOG_ERROR("Target not halted");
2872 return ERROR_TARGET_NOT_HALTED
;
2875 r
= sam3_auto_probe(bank
);
2876 if (r
!= ERROR_OK
) {
2877 LOG_DEBUG("Here,r=%d", r
);
2881 pPrivate
= get_sam3_bank_private(bank
);
2882 if (!(pPrivate
->probed
))
2883 return ERROR_FLASH_BANK_NOT_PROBED
;
2885 if ((first
== 0) && ((last
+ 1) == ((int)(pPrivate
->nsectors
)))) {
2888 return FLASHD_EraseEntireBank(pPrivate
);
2890 LOG_INFO("sam3 auto-erases while programing (request ignored)");
2894 static int sam3_protect(struct flash_bank
*bank
, int set
, int first
, int last
)
2896 struct sam3_bank_private
*pPrivate
;
2900 if (bank
->target
->state
!= TARGET_HALTED
) {
2901 LOG_ERROR("Target not halted");
2902 return ERROR_TARGET_NOT_HALTED
;
2905 pPrivate
= get_sam3_bank_private(bank
);
2906 if (!(pPrivate
->probed
))
2907 return ERROR_FLASH_BANK_NOT_PROBED
;
2910 r
= FLASHD_Lock(pPrivate
, (unsigned)(first
), (unsigned)(last
));
2912 r
= FLASHD_Unlock(pPrivate
, (unsigned)(first
), (unsigned)(last
));
2913 LOG_DEBUG("End: r=%d", r
);
2919 static int sam3_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
2921 if (bank
->target
->state
!= TARGET_HALTED
) {
2922 LOG_ERROR("Target not halted");
2923 return ERROR_TARGET_NOT_HALTED
;
2929 static int sam3_page_read(struct sam3_bank_private
*pPrivate
, unsigned pagenum
, uint8_t *buf
)
2934 adr
= pagenum
* pPrivate
->page_size
;
2935 adr
+= adr
+ pPrivate
->base_address
;
2937 r
= target_read_memory(pPrivate
->pChip
->target
,
2939 4, /* THIS*MUST*BE* in 32bit values */
2940 pPrivate
->page_size
/ 4,
2943 LOG_ERROR("SAM3: Flash program failed to read page phys address: 0x%08x",
2944 (unsigned int)(adr
));
2948 /* The code below is basically this: */
2950 /* arm-none-eabi-gcc -mthumb -mcpu = cortex-m3 -O9 -S ./foobar.c -o foobar.s */
2952 /* Only the *CPU* can write to the flash buffer. */
2953 /* the DAP cannot... so - we download this 28byte thing */
2954 /* Run the algorithm - (below) */
2955 /* to program the device */
2957 /* ======================================== */
2958 /* #include <stdint.h> */
2961 /* uint32_t *dst; */
2962 /* const uint32_t *src; */
2964 /* volatile uint32_t *base; */
2969 /* uint32_t sam3_function(struct foo *p) */
2971 /* volatile uint32_t *v; */
2973 /* const uint32_t *s; */
2988 /* v[ 1 ] = p->cmd; */
2991 /* } while (!(r&1)) */
2995 /* ======================================== */
2997 static const uint8_t
2998 sam3_page_write_opcodes
[] = {
2999 /* 24 0000 0446 mov r4, r0 */
3001 /* 25 0002 6168 ldr r1, [r4, #4] */
3003 /* 26 0004 0068 ldr r0, [r0, #0] */
3005 /* 27 0006 A268 ldr r2, [r4, #8] */
3007 /* 28 @ lr needed for prologue */
3009 /* 30 0008 51F8043B ldr r3, [r1], #4 */
3010 0x51, 0xf8, 0x04, 0x3b,
3011 /* 31 000c 12F1FF32 adds r2, r2, #-1 */
3012 0x12, 0xf1, 0xff, 0x32,
3013 /* 32 0010 40F8043B str r3, [r0], #4 */
3014 0x40, 0xf8, 0x04, 0x3b,
3015 /* 33 0014 F8D1 bne .L2 */
3017 /* 34 0016 E268 ldr r2, [r4, #12] */
3019 /* 35 0018 2369 ldr r3, [r4, #16] */
3021 /* 36 001a 5360 str r3, [r2, #4] */
3023 /* 37 001c 0832 adds r2, r2, #8 */
3026 /* 39 001e 1068 ldr r0, [r2, #0] */
3028 /* 40 0020 10F0010F tst r0, #1 */
3029 0x10, 0xf0, 0x01, 0x0f,
3030 /* 41 0024 FBD0 beq .L4 */
3032 0x00, 0xBE /* bkpt #0 */
3035 static int sam3_page_write(struct sam3_bank_private
*pPrivate
, unsigned pagenum
, uint8_t *buf
)
3039 uint32_t fmr
; /* EEFC Flash Mode Register */
3042 adr
= pagenum
* pPrivate
->page_size
;
3043 adr
+= (adr
+ pPrivate
->base_address
);
3045 /* Get flash mode register value */
3046 r
= target_read_u32(pPrivate
->pChip
->target
, pPrivate
->controller_address
, &fmr
);
3048 LOG_DEBUG("Error Read failed: read flash mode register");
3050 /* Clear flash wait state field */
3053 /* set FWS (flash wait states) field in the FMR (flash mode register) */
3054 fmr
|= (pPrivate
->flash_wait_states
<< 8);
3056 LOG_DEBUG("Flash Mode: 0x%08x", ((unsigned int)(fmr
)));
3057 r
= target_write_u32(pPrivate
->pBank
->target
, pPrivate
->controller_address
, fmr
);
3059 LOG_DEBUG("Error Write failed: set flash mode register");
3061 LOG_DEBUG("Wr Page %u @ phys address: 0x%08x", pagenum
, (unsigned int)(adr
));
3062 r
= target_write_memory(pPrivate
->pChip
->target
,
3064 4, /* THIS*MUST*BE* in 32bit values */
3065 pPrivate
->page_size
/ 4,
3067 if (r
!= ERROR_OK
) {
3068 LOG_ERROR("SAM3: Failed to write (buffer) page at phys address 0x%08x",
3069 (unsigned int)(adr
));
3073 r
= EFC_PerformCommand(pPrivate
,
3074 /* send Erase & Write Page */
3080 LOG_ERROR("SAM3: Error performing Erase & Write page @ phys address 0x%08x",
3081 (unsigned int)(adr
));
3082 if (status
& (1 << 2)) {
3083 LOG_ERROR("SAM3: Page @ Phys address 0x%08x is locked", (unsigned int)(adr
));
3086 if (status
& (1 << 1)) {
3087 LOG_ERROR("SAM3: Flash Command error @phys address 0x%08x", (unsigned int)(adr
));
3093 static int sam3_write(struct flash_bank
*bank
,
3102 unsigned page_offset
;
3103 struct sam3_bank_private
*pPrivate
;
3104 uint8_t *pagebuffer
;
3106 /* incase we bail further below, set this to null */
3109 /* ignore dumb requests */
3115 if (bank
->target
->state
!= TARGET_HALTED
) {
3116 LOG_ERROR("Target not halted");
3117 r
= ERROR_TARGET_NOT_HALTED
;
3121 pPrivate
= get_sam3_bank_private(bank
);
3122 if (!(pPrivate
->probed
)) {
3123 r
= ERROR_FLASH_BANK_NOT_PROBED
;
3127 if ((offset
+ count
) > pPrivate
->size_bytes
) {
3128 LOG_ERROR("Flash write error - past end of bank");
3129 LOG_ERROR(" offset: 0x%08x, count 0x%08x, BankEnd: 0x%08x",
3130 (unsigned int)(offset
),
3131 (unsigned int)(count
),
3132 (unsigned int)(pPrivate
->size_bytes
));
3137 pagebuffer
= malloc(pPrivate
->page_size
);
3139 LOG_ERROR("No memory for %d Byte page buffer", (int)(pPrivate
->page_size
));
3144 /* what page do we start & end in? */
3145 page_cur
= offset
/ pPrivate
->page_size
;
3146 page_end
= (offset
+ count
- 1) / pPrivate
->page_size
;
3148 LOG_DEBUG("Offset: 0x%08x, Count: 0x%08x", (unsigned int)(offset
), (unsigned int)(count
));
3149 LOG_DEBUG("Page start: %d, Page End: %d", (int)(page_cur
), (int)(page_end
));
3151 /* Special case: all one page */
3154 /* (1) non-aligned start */
3155 /* (2) body pages */
3156 /* (3) non-aligned end. */
3158 /* Handle special case - all one page. */
3159 if (page_cur
== page_end
) {
3160 LOG_DEBUG("Special case, all in one page");
3161 r
= sam3_page_read(pPrivate
, page_cur
, pagebuffer
);
3165 page_offset
= (offset
& (pPrivate
->page_size
-1));
3166 memcpy(pagebuffer
+ page_offset
,
3170 r
= sam3_page_write(pPrivate
, page_cur
, pagebuffer
);
3177 /* non-aligned start */
3178 page_offset
= offset
& (pPrivate
->page_size
- 1);
3180 LOG_DEBUG("Not-Aligned start");
3181 /* read the partial */
3182 r
= sam3_page_read(pPrivate
, page_cur
, pagebuffer
);
3186 /* over-write with new data */
3187 n
= (pPrivate
->page_size
- page_offset
);
3188 memcpy(pagebuffer
+ page_offset
,
3192 r
= sam3_page_write(pPrivate
, page_cur
, pagebuffer
);
3202 /* By checking that offset is correct here, we also
3203 fix a clang warning */
3204 assert(offset
% pPrivate
->page_size
== 0);
3206 /* intermediate large pages */
3207 /* also - the final *terminal* */
3208 /* if that terminal page is a full page */
3209 LOG_DEBUG("Full Page Loop: cur=%d, end=%d, count = 0x%08x",
3210 (int)page_cur
, (int)page_end
, (unsigned int)(count
));
3212 while ((page_cur
< page_end
) &&
3213 (count
>= pPrivate
->page_size
)) {
3214 r
= sam3_page_write(pPrivate
, page_cur
, buffer
);
3217 count
-= pPrivate
->page_size
;
3218 buffer
+= pPrivate
->page_size
;
3222 /* terminal partial page? */
3224 LOG_DEBUG("Terminal partial page, count = 0x%08x", (unsigned int)(count
));
3225 /* we have a partial page */
3226 r
= sam3_page_read(pPrivate
, page_cur
, pagebuffer
);
3229 /* data goes at start */
3230 memcpy(pagebuffer
, buffer
, count
);
3231 r
= sam3_page_write(pPrivate
, page_cur
, pagebuffer
);
3244 COMMAND_HANDLER(sam3_handle_info_command
)
3246 struct sam3_chip
*pChip
;
3247 pChip
= get_current_sam3(CMD_CTX
);
3254 /* bank0 must exist before we can do anything */
3255 if (pChip
->details
.bank
[0].pBank
== NULL
) {
3258 command_print(CMD_CTX
,
3259 "Please define bank %d via command: flash bank %s ... ",
3261 at91sam3_flash
.name
);
3265 /* if bank 0 is not probed, then probe it */
3266 if (!(pChip
->details
.bank
[0].probed
)) {
3267 r
= sam3_auto_probe(pChip
->details
.bank
[0].pBank
);
3271 /* above guarantees the "chip details" structure is valid */
3272 /* and thus, bank private areas are valid */
3273 /* and we have a SAM3 chip, what a concept! */
3275 /* auto-probe other banks, 0 done above */
3276 for (x
= 1; x
< SAM3_MAX_FLASH_BANKS
; x
++) {
3277 /* skip banks not present */
3278 if (!(pChip
->details
.bank
[x
].present
))
3281 if (pChip
->details
.bank
[x
].pBank
== NULL
)
3284 if (pChip
->details
.bank
[x
].probed
)
3287 r
= sam3_auto_probe(pChip
->details
.bank
[x
].pBank
);
3292 r
= sam3_GetInfo(pChip
);
3293 if (r
!= ERROR_OK
) {
3294 LOG_DEBUG("Sam3Info, Failed %d", r
);
3301 COMMAND_HANDLER(sam3_handle_gpnvm_command
)
3305 struct sam3_chip
*pChip
;
3307 pChip
= get_current_sam3(CMD_CTX
);
3311 if (pChip
->target
->state
!= TARGET_HALTED
) {
3312 LOG_ERROR("sam3 - target not halted");
3313 return ERROR_TARGET_NOT_HALTED
;
3316 if (pChip
->details
.bank
[0].pBank
== NULL
) {
3317 command_print(CMD_CTX
, "Bank0 must be defined first via: flash bank %s ...",
3318 at91sam3_flash
.name
);
3321 if (!pChip
->details
.bank
[0].probed
) {
3322 r
= sam3_auto_probe(pChip
->details
.bank
[0].pBank
);
3329 return ERROR_COMMAND_SYNTAX_ERROR
;
3338 if ((0 == strcmp(CMD_ARGV
[0], "show")) && (0 == strcmp(CMD_ARGV
[1], "all")))
3342 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], v32
);
3348 if (0 == strcmp("show", CMD_ARGV
[0])) {
3352 for (x
= 0; x
< pChip
->details
.n_gpnvms
; x
++) {
3353 r
= FLASHD_GetGPNVM(&(pChip
->details
.bank
[0]), x
, &v
);
3356 command_print(CMD_CTX
, "sam3-gpnvm%u: %u", x
, v
);
3360 if ((who
>= 0) && (((unsigned)(who
)) < pChip
->details
.n_gpnvms
)) {
3361 r
= FLASHD_GetGPNVM(&(pChip
->details
.bank
[0]), who
, &v
);
3362 command_print(CMD_CTX
, "sam3-gpnvm%u: %u", who
, v
);
3365 command_print(CMD_CTX
, "sam3-gpnvm invalid GPNVM: %u", who
);
3366 return ERROR_COMMAND_SYNTAX_ERROR
;
3371 command_print(CMD_CTX
, "Missing GPNVM number");
3372 return ERROR_COMMAND_SYNTAX_ERROR
;
3375 if (0 == strcmp("set", CMD_ARGV
[0]))
3376 r
= FLASHD_SetGPNVM(&(pChip
->details
.bank
[0]), who
);
3377 else if ((0 == strcmp("clr", CMD_ARGV
[0])) ||
3378 (0 == strcmp("clear", CMD_ARGV
[0]))) /* quietly accept both */
3379 r
= FLASHD_ClrGPNVM(&(pChip
->details
.bank
[0]), who
);
3381 command_print(CMD_CTX
, "Unknown command: %s", CMD_ARGV
[0]);
3382 r
= ERROR_COMMAND_SYNTAX_ERROR
;
3387 COMMAND_HANDLER(sam3_handle_slowclk_command
)
3389 struct sam3_chip
*pChip
;
3391 pChip
= get_current_sam3(CMD_CTX
);
3403 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], v
);
3405 /* absurd slow clock of 200Khz? */
3406 command_print(CMD_CTX
, "Absurd/illegal slow clock freq: %d\n", (int)(v
));
3407 return ERROR_COMMAND_SYNTAX_ERROR
;
3409 pChip
->cfg
.slow_freq
= v
;
3414 command_print(CMD_CTX
, "Too many parameters");
3415 return ERROR_COMMAND_SYNTAX_ERROR
;
3418 command_print(CMD_CTX
, "Slowclk freq: %d.%03dkhz",
3419 (int)(pChip
->cfg
.slow_freq
/ 1000),
3420 (int)(pChip
->cfg
.slow_freq
% 1000));
3424 static const struct command_registration at91sam3_exec_command_handlers
[] = {
3427 .handler
= sam3_handle_gpnvm_command
,
3428 .mode
= COMMAND_EXEC
,
3429 .usage
= "[('clr'|'set'|'show') bitnum]",
3430 .help
= "Without arguments, shows all bits in the gpnvm "
3431 "register. Otherwise, clears, sets, or shows one "
3432 "General Purpose Non-Volatile Memory (gpnvm) bit.",
3436 .handler
= sam3_handle_info_command
,
3437 .mode
= COMMAND_EXEC
,
3438 .help
= "Print information about the current at91sam3 chip"
3439 "and its flash configuration.",
3443 .handler
= sam3_handle_slowclk_command
,
3444 .mode
= COMMAND_EXEC
,
3445 .usage
= "[clock_hz]",
3446 .help
= "Display or set the slowclock frequency "
3447 "(default 32768 Hz).",
3449 COMMAND_REGISTRATION_DONE
3451 static const struct command_registration at91sam3_command_handlers
[] = {
3454 .mode
= COMMAND_ANY
,
3455 .help
= "at91sam3 flash command group",
3457 .chain
= at91sam3_exec_command_handlers
,
3459 COMMAND_REGISTRATION_DONE
3462 struct flash_driver at91sam3_flash
= {
3464 .commands
= at91sam3_command_handlers
,
3465 .flash_bank_command
= sam3_flash_bank_command
,
3466 .erase
= sam3_erase
,
3467 .protect
= sam3_protect
,
3468 .write
= sam3_write
,
3469 .read
= default_flash_read
,
3470 .probe
= sam3_probe
,
3471 .auto_probe
= sam3_auto_probe
,
3472 .erase_check
= sam3_erase_check
,
3473 .protect_check
= sam3_protect_check
,
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