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jtag: linuxgpiod: drop extra parenthesis
[openocd.git] / src / flash / nor / at91sam3.c
1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-Source-Code)
2
3 /*
4 * Copyright (C) 2009 by Duane Ellis <openocd@duaneellis.com>
5 *
6 * at91sam3s* support
7 * Copyright (C) 2010 by Olaf Lüke <olaf@uni-paderborn.de>
8 * Copyright (C) 2011 by Olivier Schonken and Jim Norris
9 *
10 * Some of the lower level code was based on code supplied by
11 * ATMEL under BSD-Source-Code License and this copyright.
12 * ATMEL Microcontroller Software Support
13 * Copyright (c) 2009, Atmel Corporation. All rights reserved.
14 */
15
16 #ifdef HAVE_CONFIG_H
17 #include "config.h"
18 #endif
19
20 #include "imp.h"
21 #include <helper/time_support.h>
22
23 #define REG_NAME_WIDTH (12)
24
25 /* at91sam3u series (has one or two flash banks) */
26 #define FLASH_BANK0_BASE_U 0x00080000
27 #define FLASH_BANK1_BASE_U 0x00100000
28
29 /* at91sam3s series (has always one flash bank) */
30 #define FLASH_BANK_BASE_S 0x00400000
31
32 /* at91sam3sd series (has always two flash banks) */
33 #define FLASH_BANK0_BASE_SD FLASH_BANK_BASE_S
34 #define FLASH_BANK1_BASE_512K_SD (FLASH_BANK0_BASE_SD+(512*1024/2))
35
36
37 /* at91sam3n series (has always one flash bank) */
38 #define FLASH_BANK_BASE_N 0x00400000
39
40 /* at91sam3a/x series has two flash banks*/
41 #define FLASH_BANK0_BASE_AX 0x00080000
42 /*Bank 1 of the at91sam3a/x series starts at 0x00080000 + half flash size*/
43 #define FLASH_BANK1_BASE_256K_AX 0x000A0000
44 #define FLASH_BANK1_BASE_512K_AX 0x000C0000
45
46 #define AT91C_EFC_FCMD_GETD (0x0) /* (EFC) Get Flash Descriptor */
47 #define AT91C_EFC_FCMD_WP (0x1) /* (EFC) Write Page */
48 #define AT91C_EFC_FCMD_WPL (0x2) /* (EFC) Write Page and Lock */
49 #define AT91C_EFC_FCMD_EWP (0x3) /* (EFC) Erase Page and Write Page */
50 #define AT91C_EFC_FCMD_EWPL (0x4) /* (EFC) Erase Page and Write Page then Lock */
51 #define AT91C_EFC_FCMD_EA (0x5) /* (EFC) Erase All */
52 /* cmd6 is not present in the at91sam3u4/2/1 data sheet table 17-2 */
53 /* #define AT91C_EFC_FCMD_EPL (0x6) // (EFC) Erase plane? */
54 /* cmd7 is not present in the at91sam3u4/2/1 data sheet table 17-2 */
55 /* #define AT91C_EFC_FCMD_EPA (0x7) // (EFC) Erase pages? */
56 #define AT91C_EFC_FCMD_SLB (0x8) /* (EFC) Set Lock Bit */
57 #define AT91C_EFC_FCMD_CLB (0x9) /* (EFC) Clear Lock Bit */
58 #define AT91C_EFC_FCMD_GLB (0xA) /* (EFC) Get Lock Bit */
59 #define AT91C_EFC_FCMD_SFB (0xB) /* (EFC) Set Fuse Bit */
60 #define AT91C_EFC_FCMD_CFB (0xC) /* (EFC) Clear Fuse Bit */
61 #define AT91C_EFC_FCMD_GFB (0xD) /* (EFC) Get Fuse Bit */
62 #define AT91C_EFC_FCMD_STUI (0xE) /* (EFC) Start Read Unique ID */
63 #define AT91C_EFC_FCMD_SPUI (0xF) /* (EFC) Stop Read Unique ID */
64
65 #define OFFSET_EFC_FMR 0
66 #define OFFSET_EFC_FCR 4
67 #define OFFSET_EFC_FSR 8
68 #define OFFSET_EFC_FRR 12
69
70 extern const struct flash_driver at91sam3_flash;
71
72 static float _tomhz(uint32_t freq_hz)
73 {
74 float f;
75
76 f = ((float)(freq_hz)) / 1000000.0;
77 return f;
78 }
79
80 /* How the chip is configured. */
81 struct sam3_cfg {
82 uint32_t unique_id[4];
83
84 uint32_t slow_freq;
85 uint32_t rc_freq;
86 uint32_t mainosc_freq;
87 uint32_t plla_freq;
88 uint32_t mclk_freq;
89 uint32_t cpu_freq;
90 uint32_t fclk_freq;
91 uint32_t pclk0_freq;
92 uint32_t pclk1_freq;
93 uint32_t pclk2_freq;
94
95
96 #define SAM3_CHIPID_CIDR (0x400E0740)
97 uint32_t CHIPID_CIDR;
98 #define SAM3_CHIPID_CIDR2 (0x400E0940) /*SAM3X and SAM3A cidr at this address*/
99 uint32_t CHIPID_CIDR2;
100 #define SAM3_CHIPID_EXID (0x400E0744)
101 uint32_t CHIPID_EXID;
102 #define SAM3_CHIPID_EXID2 (0x400E0944) /*SAM3X and SAM3A cidr at this address*/
103 uint32_t CHIPID_EXID2;
104
105
106 #define SAM3_PMC_BASE (0x400E0400)
107 #define SAM3_PMC_SCSR (SAM3_PMC_BASE + 0x0008)
108 uint32_t PMC_SCSR;
109 #define SAM3_PMC_PCSR (SAM3_PMC_BASE + 0x0018)
110 uint32_t PMC_PCSR;
111 #define SAM3_CKGR_UCKR (SAM3_PMC_BASE + 0x001c)
112 uint32_t CKGR_UCKR;
113 #define SAM3_CKGR_MOR (SAM3_PMC_BASE + 0x0020)
114 uint32_t CKGR_MOR;
115 #define SAM3_CKGR_MCFR (SAM3_PMC_BASE + 0x0024)
116 uint32_t CKGR_MCFR;
117 #define SAM3_CKGR_PLLAR (SAM3_PMC_BASE + 0x0028)
118 uint32_t CKGR_PLLAR;
119 #define SAM3_PMC_MCKR (SAM3_PMC_BASE + 0x0030)
120 uint32_t PMC_MCKR;
121 #define SAM3_PMC_PCK0 (SAM3_PMC_BASE + 0x0040)
122 uint32_t PMC_PCK0;
123 #define SAM3_PMC_PCK1 (SAM3_PMC_BASE + 0x0044)
124 uint32_t PMC_PCK1;
125 #define SAM3_PMC_PCK2 (SAM3_PMC_BASE + 0x0048)
126 uint32_t PMC_PCK2;
127 #define SAM3_PMC_SR (SAM3_PMC_BASE + 0x0068)
128 uint32_t PMC_SR;
129 #define SAM3_PMC_IMR (SAM3_PMC_BASE + 0x006c)
130 uint32_t PMC_IMR;
131 #define SAM3_PMC_FSMR (SAM3_PMC_BASE + 0x0070)
132 uint32_t PMC_FSMR;
133 #define SAM3_PMC_FSPR (SAM3_PMC_BASE + 0x0074)
134 uint32_t PMC_FSPR;
135 };
136
137 /*
138 * The AT91SAM3N data sheet 04-Oct-2010, AT91SAM3U data sheet 22-Aug-2011
139 * and AT91SAM3S data sheet 09-Feb-2011 state that for flash writes
140 * the flash wait state (FWS) should be set to 6. It seems like that the
141 * cause of the problem is not the flash itself, but the flash write
142 * buffer. Ie the wait states have to be set before writing into the
143 * buffer.
144 * Tested and confirmed with SAM3N and SAM3U
145 */
146
147 struct sam3_bank_private {
148 bool probed;
149 /* DANGER: THERE ARE DRAGONS HERE.. */
150 /* NOTE: If you add more 'ghost' pointers */
151 /* be aware that you must *manually* update */
152 /* these pointers in the function sam3_get_details() */
153 /* See the comment "Here there be dragons" */
154
155 /* so we can find the chip we belong to */
156 struct sam3_chip *chip;
157 /* so we can find the original bank pointer */
158 struct flash_bank *bank;
159 unsigned bank_number;
160 uint32_t controller_address;
161 uint32_t base_address;
162 uint32_t flash_wait_states;
163 bool present;
164 unsigned size_bytes;
165 unsigned nsectors;
166 unsigned sector_size;
167 unsigned page_size;
168 };
169
170 struct sam3_chip_details {
171 /* THERE ARE DRAGONS HERE.. */
172 /* note: If you add pointers here */
173 /* be careful about them as they */
174 /* may need to be updated inside */
175 /* the function: "sam3_get_details() */
176 /* which copy/overwrites the */
177 /* 'runtime' copy of this structure */
178 uint32_t chipid_cidr;
179 const char *name;
180
181 unsigned n_gpnvms;
182 #define SAM3_N_NVM_BITS 3
183 unsigned gpnvm[SAM3_N_NVM_BITS];
184 unsigned total_flash_size;
185 unsigned total_sram_size;
186 unsigned n_banks;
187 #define SAM3_MAX_FLASH_BANKS 2
188 /* these are "initialized" from the global const data */
189 struct sam3_bank_private bank[SAM3_MAX_FLASH_BANKS];
190 };
191
192 struct sam3_chip {
193 struct sam3_chip *next;
194 bool probed;
195
196 /* this is "initialized" from the global const structure */
197 struct sam3_chip_details details;
198 struct target *target;
199 struct sam3_cfg cfg;
200 };
201
202
203 struct sam3_reg_list {
204 uint32_t address; size_t struct_offset; const char *name;
205 void (*explain_func)(struct sam3_chip *chip);
206 };
207
208 static struct sam3_chip *all_sam3_chips;
209
210 static struct sam3_chip *get_current_sam3(struct command_invocation *cmd)
211 {
212 struct target *t;
213 static struct sam3_chip *p;
214
215 t = get_current_target(cmd->ctx);
216 if (!t) {
217 command_print_sameline(cmd, "No current target?\n");
218 return NULL;
219 }
220
221 p = all_sam3_chips;
222 if (!p) {
223 /* this should not happen */
224 /* the command is not registered until the chip is created? */
225 command_print_sameline(cmd, "No SAM3 chips exist?\n");
226 return NULL;
227 }
228
229 while (p) {
230 if (p->target == t)
231 return p;
232 p = p->next;
233 }
234 command_print_sameline(cmd, "Cannot find SAM3 chip?\n");
235 return NULL;
236 }
237
238 /* these are used to *initialize* the "chip->details" structure. */
239 static const struct sam3_chip_details all_sam3_details[] = {
240 /* Start at91sam3u* series */
241 {
242 .chipid_cidr = 0x28100960,
243 .name = "at91sam3u4e",
244 .total_flash_size = 256 * 1024,
245 .total_sram_size = 52 * 1024,
246 .n_gpnvms = 3,
247 .n_banks = 2,
248
249 /* System boots at address 0x0 */
250 /* gpnvm[1] = selects boot code */
251 /* if gpnvm[1] == 0 */
252 /* boot is via "SAMBA" (rom) */
253 /* else */
254 /* boot is via FLASH */
255 /* Selection is via gpnvm[2] */
256 /* endif */
257 /* */
258 /* NOTE: banks 0 & 1 switch places */
259 /* if gpnvm[2] == 0 */
260 /* Bank0 is the boot rom */
261 /* else */
262 /* Bank1 is the boot rom */
263 /* endif */
264 /* .bank[0] = { */
265 {
266 {
267 .probed = false,
268 .chip = NULL,
269 .bank = NULL,
270 .bank_number = 0,
271 .base_address = FLASH_BANK0_BASE_U,
272 .controller_address = 0x400e0800,
273 .flash_wait_states = 6, /* workaround silicon bug */
274 .present = 1,
275 .size_bytes = 128 * 1024,
276 .nsectors = 16,
277 .sector_size = 8192,
278 .page_size = 256,
279 },
280
281 /* .bank[1] = { */
282 {
283 .probed = false,
284 .chip = NULL,
285 .bank = NULL,
286 .bank_number = 1,
287 .base_address = FLASH_BANK1_BASE_U,
288 .controller_address = 0x400e0a00,
289 .flash_wait_states = 6, /* workaround silicon bug */
290 .present = 1,
291 .size_bytes = 128 * 1024,
292 .nsectors = 16,
293 .sector_size = 8192,
294 .page_size = 256,
295 },
296 },
297 },
298
299 {
300 .chipid_cidr = 0x281a0760,
301 .name = "at91sam3u2e",
302 .total_flash_size = 128 * 1024,
303 .total_sram_size = 36 * 1024,
304 .n_gpnvms = 2,
305 .n_banks = 1,
306
307 /* System boots at address 0x0 */
308 /* gpnvm[1] = selects boot code */
309 /* if gpnvm[1] == 0 */
310 /* boot is via "SAMBA" (rom) */
311 /* else */
312 /* boot is via FLASH */
313 /* Selection is via gpnvm[2] */
314 /* endif */
315 /* .bank[0] = { */
316 {
317 {
318 .probed = false,
319 .chip = NULL,
320 .bank = NULL,
321 .bank_number = 0,
322 .base_address = FLASH_BANK0_BASE_U,
323 .controller_address = 0x400e0800,
324 .flash_wait_states = 6, /* workaround silicon bug */
325 .present = 1,
326 .size_bytes = 128 * 1024,
327 .nsectors = 16,
328 .sector_size = 8192,
329 .page_size = 256,
330 },
331 /* .bank[1] = { */
332 {
333 .present = 0,
334 .probed = false,
335 .bank_number = 1,
336 },
337 },
338 },
339 {
340 .chipid_cidr = 0x28190560,
341 .name = "at91sam3u1e",
342 .total_flash_size = 64 * 1024,
343 .total_sram_size = 20 * 1024,
344 .n_gpnvms = 2,
345 .n_banks = 1,
346
347 /* System boots at address 0x0 */
348 /* gpnvm[1] = selects boot code */
349 /* if gpnvm[1] == 0 */
350 /* boot is via "SAMBA" (rom) */
351 /* else */
352 /* boot is via FLASH */
353 /* Selection is via gpnvm[2] */
354 /* endif */
355 /* */
356
357 /* .bank[0] = { */
358 {
359 {
360 .probed = false,
361 .chip = NULL,
362 .bank = NULL,
363 .bank_number = 0,
364 .base_address = FLASH_BANK0_BASE_U,
365 .controller_address = 0x400e0800,
366 .flash_wait_states = 6, /* workaround silicon bug */
367 .present = 1,
368 .size_bytes = 64 * 1024,
369 .nsectors = 8,
370 .sector_size = 8192,
371 .page_size = 256,
372 },
373
374 /* .bank[1] = { */
375 {
376 .present = 0,
377 .probed = false,
378 .bank_number = 1,
379 },
380 },
381 },
382
383 {
384 .chipid_cidr = 0x28000960,
385 .name = "at91sam3u4c",
386 .total_flash_size = 256 * 1024,
387 .total_sram_size = 52 * 1024,
388 .n_gpnvms = 3,
389 .n_banks = 2,
390
391 /* System boots at address 0x0 */
392 /* gpnvm[1] = selects boot code */
393 /* if gpnvm[1] == 0 */
394 /* boot is via "SAMBA" (rom) */
395 /* else */
396 /* boot is via FLASH */
397 /* Selection is via gpnvm[2] */
398 /* endif */
399 /* */
400 /* NOTE: banks 0 & 1 switch places */
401 /* if gpnvm[2] == 0 */
402 /* Bank0 is the boot rom */
403 /* else */
404 /* Bank1 is the boot rom */
405 /* endif */
406 {
407 {
408 /* .bank[0] = { */
409 .probed = false,
410 .chip = NULL,
411 .bank = NULL,
412 .bank_number = 0,
413 .base_address = FLASH_BANK0_BASE_U,
414 .controller_address = 0x400e0800,
415 .flash_wait_states = 6, /* workaround silicon bug */
416 .present = 1,
417 .size_bytes = 128 * 1024,
418 .nsectors = 16,
419 .sector_size = 8192,
420 .page_size = 256,
421 },
422 /* .bank[1] = { */
423 {
424 .probed = false,
425 .chip = NULL,
426 .bank = NULL,
427 .bank_number = 1,
428 .base_address = FLASH_BANK1_BASE_U,
429 .controller_address = 0x400e0a00,
430 .flash_wait_states = 6, /* workaround silicon bug */
431 .present = 1,
432 .size_bytes = 128 * 1024,
433 .nsectors = 16,
434 .sector_size = 8192,
435 .page_size = 256,
436 },
437 },
438 },
439
440 {
441 .chipid_cidr = 0x280a0760,
442 .name = "at91sam3u2c",
443 .total_flash_size = 128 * 1024,
444 .total_sram_size = 36 * 1024,
445 .n_gpnvms = 2,
446 .n_banks = 1,
447
448 /* System boots at address 0x0 */
449 /* gpnvm[1] = selects boot code */
450 /* if gpnvm[1] == 0 */
451 /* boot is via "SAMBA" (rom) */
452 /* else */
453 /* boot is via FLASH */
454 /* Selection is via gpnvm[2] */
455 /* endif */
456 {
457 /* .bank[0] = { */
458 {
459 .probed = false,
460 .chip = NULL,
461 .bank = NULL,
462 .bank_number = 0,
463 .base_address = FLASH_BANK0_BASE_U,
464 .controller_address = 0x400e0800,
465 .flash_wait_states = 6, /* workaround silicon bug */
466 .present = 1,
467 .size_bytes = 128 * 1024,
468 .nsectors = 16,
469 .sector_size = 8192,
470 .page_size = 256,
471 },
472 /* .bank[1] = { */
473 {
474 .present = 0,
475 .probed = false,
476 .bank_number = 1,
477 },
478 },
479 },
480 {
481 .chipid_cidr = 0x28090560,
482 .name = "at91sam3u1c",
483 .total_flash_size = 64 * 1024,
484 .total_sram_size = 20 * 1024,
485 .n_gpnvms = 2,
486 .n_banks = 1,
487
488 /* System boots at address 0x0 */
489 /* gpnvm[1] = selects boot code */
490 /* if gpnvm[1] == 0 */
491 /* boot is via "SAMBA" (rom) */
492 /* else */
493 /* boot is via FLASH */
494 /* Selection is via gpnvm[2] */
495 /* endif */
496 /* */
497
498 {
499 /* .bank[0] = { */
500 {
501 .probed = false,
502 .chip = NULL,
503 .bank = NULL,
504 .bank_number = 0,
505 .base_address = FLASH_BANK0_BASE_U,
506 .controller_address = 0x400e0800,
507 .flash_wait_states = 6, /* workaround silicon bug */
508 .present = 1,
509 .size_bytes = 64 * 1024,
510 .nsectors = 8,
511 .sector_size = 8192,
512 .page_size = 256,
513 },
514 /* .bank[1] = { */
515 {
516 .present = 0,
517 .probed = false,
518 .bank_number = 1,
519
520 },
521 },
522 },
523
524 /* Start at91sam3s* series */
525
526 /* Note: The preliminary at91sam3s datasheet says on page 302 */
527 /* that the flash controller is at address 0x400E0800. */
528 /* This is _not_ the case, the controller resides at address 0x400e0a00. */
529 {
530 .chipid_cidr = 0x28A00960,
531 .name = "at91sam3s4c",
532 .total_flash_size = 256 * 1024,
533 .total_sram_size = 48 * 1024,
534 .n_gpnvms = 2,
535 .n_banks = 1,
536 {
537 /* .bank[0] = { */
538 {
539 .probed = false,
540 .chip = NULL,
541 .bank = NULL,
542 .bank_number = 0,
543 .base_address = FLASH_BANK_BASE_S,
544 .controller_address = 0x400e0a00,
545 .flash_wait_states = 6, /* workaround silicon bug */
546 .present = 1,
547 .size_bytes = 256 * 1024,
548 .nsectors = 16,
549 .sector_size = 16384,
550 .page_size = 256,
551 },
552 /* .bank[1] = { */
553 {
554 .present = 0,
555 .probed = false,
556 .bank_number = 1,
557
558 },
559 },
560 },
561
562 {
563 .chipid_cidr = 0x28900960,
564 .name = "at91sam3s4b",
565 .total_flash_size = 256 * 1024,
566 .total_sram_size = 48 * 1024,
567 .n_gpnvms = 2,
568 .n_banks = 1,
569 {
570 /* .bank[0] = { */
571 {
572 .probed = false,
573 .chip = NULL,
574 .bank = NULL,
575 .bank_number = 0,
576 .base_address = FLASH_BANK_BASE_S,
577 .controller_address = 0x400e0a00,
578 .flash_wait_states = 6, /* workaround silicon bug */
579 .present = 1,
580 .size_bytes = 256 * 1024,
581 .nsectors = 16,
582 .sector_size = 16384,
583 .page_size = 256,
584 },
585 /* .bank[1] = { */
586 {
587 .present = 0,
588 .probed = false,
589 .bank_number = 1,
590
591 },
592 },
593 },
594 {
595 .chipid_cidr = 0x28800960,
596 .name = "at91sam3s4a",
597 .total_flash_size = 256 * 1024,
598 .total_sram_size = 48 * 1024,
599 .n_gpnvms = 2,
600 .n_banks = 1,
601 {
602 /* .bank[0] = { */
603 {
604 .probed = false,
605 .chip = NULL,
606 .bank = NULL,
607 .bank_number = 0,
608 .base_address = FLASH_BANK_BASE_S,
609 .controller_address = 0x400e0a00,
610 .flash_wait_states = 6, /* workaround silicon bug */
611 .present = 1,
612 .size_bytes = 256 * 1024,
613 .nsectors = 16,
614 .sector_size = 16384,
615 .page_size = 256,
616 },
617 /* .bank[1] = { */
618 {
619 .present = 0,
620 .probed = false,
621 .bank_number = 1,
622
623 },
624 },
625 },
626 {
627 .chipid_cidr = 0x28AA0760,
628 .name = "at91sam3s2c",
629 .total_flash_size = 128 * 1024,
630 .total_sram_size = 32 * 1024,
631 .n_gpnvms = 2,
632 .n_banks = 1,
633 {
634 /* .bank[0] = { */
635 {
636 .probed = false,
637 .chip = NULL,
638 .bank = NULL,
639 .bank_number = 0,
640 .base_address = FLASH_BANK_BASE_S,
641 .controller_address = 0x400e0a00,
642 .flash_wait_states = 6, /* workaround silicon bug */
643 .present = 1,
644 .size_bytes = 128 * 1024,
645 .nsectors = 8,
646 .sector_size = 16384,
647 .page_size = 256,
648 },
649 /* .bank[1] = { */
650 {
651 .present = 0,
652 .probed = false,
653 .bank_number = 1,
654
655 },
656 },
657 },
658 {
659 .chipid_cidr = 0x289A0760,
660 .name = "at91sam3s2b",
661 .total_flash_size = 128 * 1024,
662 .total_sram_size = 32 * 1024,
663 .n_gpnvms = 2,
664 .n_banks = 1,
665 {
666 /* .bank[0] = { */
667 {
668 .probed = false,
669 .chip = NULL,
670 .bank = NULL,
671 .bank_number = 0,
672 .base_address = FLASH_BANK_BASE_S,
673 .controller_address = 0x400e0a00,
674 .flash_wait_states = 6, /* workaround silicon bug */
675 .present = 1,
676 .size_bytes = 128 * 1024,
677 .nsectors = 8,
678 .sector_size = 16384,
679 .page_size = 256,
680 },
681 /* .bank[1] = { */
682 {
683 .present = 0,
684 .probed = false,
685 .bank_number = 1,
686
687 },
688 },
689 },
690 {
691 .chipid_cidr = 0x298B0A60,
692 .name = "at91sam3sd8a",
693 .total_flash_size = 512 * 1024,
694 .total_sram_size = 64 * 1024,
695 .n_gpnvms = 3,
696 .n_banks = 2,
697 {
698 /* .bank[0] = { */
699 {
700 .probed = false,
701 .chip = NULL,
702 .bank = NULL,
703 .bank_number = 0,
704 .base_address = FLASH_BANK0_BASE_SD,
705 .controller_address = 0x400e0a00,
706 .flash_wait_states = 6, /* workaround silicon bug */
707 .present = 1,
708 .size_bytes = 256 * 1024,
709 .nsectors = 16,
710 .sector_size = 32768,
711 .page_size = 256,
712 },
713 /* .bank[1] = { */
714 {
715 .probed = false,
716 .chip = NULL,
717 .bank = NULL,
718 .bank_number = 1,
719 .base_address = FLASH_BANK1_BASE_512K_SD,
720 .controller_address = 0x400e0a00,
721 .flash_wait_states = 6, /* workaround silicon bug */
722 .present = 1,
723 .size_bytes = 256 * 1024,
724 .nsectors = 16,
725 .sector_size = 32768,
726 .page_size = 256,
727 },
728 },
729 },
730 {
731 .chipid_cidr = 0x299B0A60,
732 .name = "at91sam3sd8b",
733 .total_flash_size = 512 * 1024,
734 .total_sram_size = 64 * 1024,
735 .n_gpnvms = 3,
736 .n_banks = 2,
737 {
738 /* .bank[0] = { */
739 {
740 .probed = false,
741 .chip = NULL,
742 .bank = NULL,
743 .bank_number = 0,
744 .base_address = FLASH_BANK0_BASE_SD,
745 .controller_address = 0x400e0a00,
746 .flash_wait_states = 6, /* workaround silicon bug */
747 .present = 1,
748 .size_bytes = 256 * 1024,
749 .nsectors = 16,
750 .sector_size = 32768,
751 .page_size = 256,
752 },
753 /* .bank[1] = { */
754 {
755 .probed = false,
756 .chip = NULL,
757 .bank = NULL,
758 .bank_number = 1,
759 .base_address = FLASH_BANK1_BASE_512K_SD,
760 .controller_address = 0x400e0a00,
761 .flash_wait_states = 6, /* workaround silicon bug */
762 .present = 1,
763 .size_bytes = 256 * 1024,
764 .nsectors = 16,
765 .sector_size = 32768,
766 .page_size = 256,
767 },
768 },
769 },
770 {
771 .chipid_cidr = 0x29ab0a60,
772 .name = "at91sam3sd8c",
773 .total_flash_size = 512 * 1024,
774 .total_sram_size = 64 * 1024,
775 .n_gpnvms = 3,
776 .n_banks = 2,
777 {
778 /* .bank[0] = { */
779 {
780 .probed = false,
781 .chip = NULL,
782 .bank = NULL,
783 .bank_number = 0,
784 .base_address = FLASH_BANK0_BASE_SD,
785 .controller_address = 0x400e0a00,
786 .flash_wait_states = 6, /* workaround silicon bug */
787 .present = 1,
788 .size_bytes = 256 * 1024,
789 .nsectors = 16,
790 .sector_size = 32768,
791 .page_size = 256,
792 },
793 /* .bank[1] = { */
794 {
795 .probed = false,
796 .chip = NULL,
797 .bank = NULL,
798 .bank_number = 1,
799 .base_address = FLASH_BANK1_BASE_512K_SD,
800 .controller_address = 0x400e0a00,
801 .flash_wait_states = 6, /* workaround silicon bug */
802 .present = 1,
803 .size_bytes = 256 * 1024,
804 .nsectors = 16,
805 .sector_size = 32768,
806 .page_size = 256,
807 },
808 },
809 },
810 {
811 .chipid_cidr = 0x288A0760,
812 .name = "at91sam3s2a",
813 .total_flash_size = 128 * 1024,
814 .total_sram_size = 32 * 1024,
815 .n_gpnvms = 2,
816 .n_banks = 1,
817 {
818 /* .bank[0] = { */
819 {
820 .probed = false,
821 .chip = NULL,
822 .bank = NULL,
823 .bank_number = 0,
824 .base_address = FLASH_BANK_BASE_S,
825 .controller_address = 0x400e0a00,
826 .flash_wait_states = 6, /* workaround silicon bug */
827 .present = 1,
828 .size_bytes = 128 * 1024,
829 .nsectors = 8,
830 .sector_size = 16384,
831 .page_size = 256,
832 },
833 /* .bank[1] = { */
834 {
835 .present = 0,
836 .probed = false,
837 .bank_number = 1,
838
839 },
840 },
841 },
842 {
843 .chipid_cidr = 0x28A90560,
844 .name = "at91sam3s1c",
845 .total_flash_size = 64 * 1024,
846 .total_sram_size = 16 * 1024,
847 .n_gpnvms = 2,
848 .n_banks = 1,
849 {
850 /* .bank[0] = { */
851 {
852 .probed = false,
853 .chip = NULL,
854 .bank = NULL,
855 .bank_number = 0,
856 .base_address = FLASH_BANK_BASE_S,
857 .controller_address = 0x400e0a00,
858 .flash_wait_states = 6, /* workaround silicon bug */
859 .present = 1,
860 .size_bytes = 64 * 1024,
861 .nsectors = 4,
862 .sector_size = 16384,
863 .page_size = 256,
864 },
865 /* .bank[1] = { */
866 {
867 .present = 0,
868 .probed = false,
869 .bank_number = 1,
870
871 },
872 },
873 },
874 {
875 .chipid_cidr = 0x28990560,
876 .name = "at91sam3s1b",
877 .total_flash_size = 64 * 1024,
878 .total_sram_size = 16 * 1024,
879 .n_gpnvms = 2,
880 .n_banks = 1,
881 {
882 /* .bank[0] = { */
883 {
884 .probed = false,
885 .chip = NULL,
886 .bank = NULL,
887 .bank_number = 0,
888 .base_address = FLASH_BANK_BASE_S,
889 .controller_address = 0x400e0a00,
890 .flash_wait_states = 6, /* workaround silicon bug */
891 .present = 1,
892 .size_bytes = 64 * 1024,
893 .nsectors = 4,
894 .sector_size = 16384,
895 .page_size = 256,
896 },
897 /* .bank[1] = { */
898 {
899 .present = 0,
900 .probed = false,
901 .bank_number = 1,
902
903 },
904 },
905 },
906 {
907 .chipid_cidr = 0x28890560,
908 .name = "at91sam3s1a",
909 .total_flash_size = 64 * 1024,
910 .total_sram_size = 16 * 1024,
911 .n_gpnvms = 2,
912 .n_banks = 1,
913 {
914 /* .bank[0] = { */
915 {
916 .probed = false,
917 .chip = NULL,
918 .bank = NULL,
919 .bank_number = 0,
920 .base_address = FLASH_BANK_BASE_S,
921 .controller_address = 0x400e0a00,
922 .flash_wait_states = 6, /* workaround silicon bug */
923 .present = 1,
924 .size_bytes = 64 * 1024,
925 .nsectors = 4,
926 .sector_size = 16384,
927 .page_size = 256,
928 },
929 /* .bank[1] = { */
930 {
931 .present = 0,
932 .probed = false,
933 .bank_number = 1,
934
935 },
936 },
937 },
938 {
939 .chipid_cidr = 0x288B0A60,
940 .name = "at91sam3s8a",
941 .total_flash_size = 256 * 2048,
942 .total_sram_size = 64 * 1024,
943 .n_gpnvms = 2,
944 .n_banks = 1,
945 {
946 /* .bank[0] = { */
947 {
948 .probed = false,
949 .chip = NULL,
950 .bank = NULL,
951 .bank_number = 0,
952 .base_address = FLASH_BANK_BASE_S,
953 .controller_address = 0x400e0a00,
954 .flash_wait_states = 6, /* workaround silicon bug */
955 .present = 1,
956 .size_bytes = 256 * 2048,
957 .nsectors = 16,
958 .sector_size = 32768,
959 .page_size = 256,
960 },
961 /* .bank[1] = { */
962 {
963 .present = 0,
964 .probed = false,
965 .bank_number = 1,
966
967 },
968 },
969 },
970 {
971 .chipid_cidr = 0x289B0A60,
972 .name = "at91sam3s8b",
973 .total_flash_size = 256 * 2048,
974 .total_sram_size = 64 * 1024,
975 .n_gpnvms = 2,
976 .n_banks = 1,
977 {
978 /* .bank[0] = { */
979 {
980 .probed = false,
981 .chip = NULL,
982 .bank = NULL,
983 .bank_number = 0,
984 .base_address = FLASH_BANK_BASE_S,
985 .controller_address = 0x400e0a00,
986 .flash_wait_states = 6, /* workaround silicon bug */
987 .present = 1,
988 .size_bytes = 256 * 2048,
989 .nsectors = 16,
990 .sector_size = 32768,
991 .page_size = 256,
992 },
993 /* .bank[1] = { */
994 {
995 .present = 0,
996 .probed = false,
997 .bank_number = 1,
998
999 },
1000 },
1001 },
1002 {
1003 .chipid_cidr = 0x28AB0A60,
1004 .name = "at91sam3s8c",
1005 .total_flash_size = 256 * 2048,
1006 .total_sram_size = 64 * 1024,
1007 .n_gpnvms = 2,
1008 .n_banks = 1,
1009 {
1010 /* .bank[0] = { */
1011 {
1012 .probed = false,
1013 .chip = NULL,
1014 .bank = NULL,
1015 .bank_number = 0,
1016 .base_address = FLASH_BANK_BASE_S,
1017 .controller_address = 0x400e0a00,
1018 .flash_wait_states = 6, /* workaround silicon bug */
1019 .present = 1,
1020 .size_bytes = 256 * 2048,
1021 .nsectors = 16,
1022 .sector_size = 32768,
1023 .page_size = 256,
1024 },
1025 /* .bank[1] = { */
1026 {
1027 .present = 0,
1028 .probed = false,
1029 .bank_number = 1,
1030
1031 },
1032 },
1033 },
1034
1035 /* Start at91sam3n* series */
1036 {
1037 .chipid_cidr = 0x29540960,
1038 .name = "at91sam3n4c",
1039 .total_flash_size = 256 * 1024,
1040 .total_sram_size = 24 * 1024,
1041 .n_gpnvms = 3,
1042 .n_banks = 1,
1043
1044 /* System boots at address 0x0 */
1045 /* gpnvm[1] = selects boot code */
1046 /* if gpnvm[1] == 0 */
1047 /* boot is via "SAMBA" (rom) */
1048 /* else */
1049 /* boot is via FLASH */
1050 /* Selection is via gpnvm[2] */
1051 /* endif */
1052 /* */
1053 /* NOTE: banks 0 & 1 switch places */
1054 /* if gpnvm[2] == 0 */
1055 /* Bank0 is the boot rom */
1056 /* else */
1057 /* Bank1 is the boot rom */
1058 /* endif */
1059 /* .bank[0] = { */
1060 {
1061 {
1062 .probed = false,
1063 .chip = NULL,
1064 .bank = NULL,
1065 .bank_number = 0,
1066 .base_address = FLASH_BANK_BASE_N,
1067 .controller_address = 0x400e0A00,
1068 .flash_wait_states = 6, /* workaround silicon bug */
1069 .present = 1,
1070 .size_bytes = 256 * 1024,
1071 .nsectors = 16,
1072 .sector_size = 16384,
1073 .page_size = 256,
1074 },
1075
1076 /* .bank[1] = { */
1077 {
1078 .present = 0,
1079 .probed = false,
1080 .bank_number = 1,
1081 },
1082 },
1083 },
1084
1085 {
1086 .chipid_cidr = 0x29440960,
1087 .name = "at91sam3n4b",
1088 .total_flash_size = 256 * 1024,
1089 .total_sram_size = 24 * 1024,
1090 .n_gpnvms = 3,
1091 .n_banks = 1,
1092
1093 /* System boots at address 0x0 */
1094 /* gpnvm[1] = selects boot code */
1095 /* if gpnvm[1] == 0 */
1096 /* boot is via "SAMBA" (rom) */
1097 /* else */
1098 /* boot is via FLASH */
1099 /* Selection is via gpnvm[2] */
1100 /* endif */
1101 /* */
1102 /* NOTE: banks 0 & 1 switch places */
1103 /* if gpnvm[2] == 0 */
1104 /* Bank0 is the boot rom */
1105 /* else */
1106 /* Bank1 is the boot rom */
1107 /* endif */
1108 /* .bank[0] = { */
1109 {
1110 {
1111 .probed = false,
1112 .chip = NULL,
1113 .bank = NULL,
1114 .bank_number = 0,
1115 .base_address = FLASH_BANK_BASE_N,
1116 .controller_address = 0x400e0A00,
1117 .flash_wait_states = 6, /* workaround silicon bug */
1118 .present = 1,
1119 .size_bytes = 256 * 1024,
1120 .nsectors = 16,
1121 .sector_size = 16384,
1122 .page_size = 256,
1123 },
1124
1125 /* .bank[1] = { */
1126 {
1127 .present = 0,
1128 .probed = false,
1129 .bank_number = 1,
1130 },
1131 },
1132 },
1133
1134 {
1135 .chipid_cidr = 0x29340960,
1136 .name = "at91sam3n4a",
1137 .total_flash_size = 256 * 1024,
1138 .total_sram_size = 24 * 1024,
1139 .n_gpnvms = 3,
1140 .n_banks = 1,
1141
1142 /* System boots at address 0x0 */
1143 /* gpnvm[1] = selects boot code */
1144 /* if gpnvm[1] == 0 */
1145 /* boot is via "SAMBA" (rom) */
1146 /* else */
1147 /* boot is via FLASH */
1148 /* Selection is via gpnvm[2] */
1149 /* endif */
1150 /* */
1151 /* NOTE: banks 0 & 1 switch places */
1152 /* if gpnvm[2] == 0 */
1153 /* Bank0 is the boot rom */
1154 /* else */
1155 /* Bank1 is the boot rom */
1156 /* endif */
1157 /* .bank[0] = { */
1158 {
1159 {
1160 .probed = false,
1161 .chip = NULL,
1162 .bank = NULL,
1163 .bank_number = 0,
1164 .base_address = FLASH_BANK_BASE_N,
1165 .controller_address = 0x400e0A00,
1166 .flash_wait_states = 6, /* workaround silicon bug */
1167 .present = 1,
1168 .size_bytes = 256 * 1024,
1169 .nsectors = 16,
1170 .sector_size = 16384,
1171 .page_size = 256,
1172 },
1173
1174 /* .bank[1] = { */
1175 {
1176 .present = 0,
1177 .probed = false,
1178 .bank_number = 1,
1179 },
1180 },
1181 },
1182
1183 {
1184 .chipid_cidr = 0x29590760,
1185 .name = "at91sam3n2c",
1186 .total_flash_size = 128 * 1024,
1187 .total_sram_size = 16 * 1024,
1188 .n_gpnvms = 3,
1189 .n_banks = 1,
1190
1191 /* System boots at address 0x0 */
1192 /* gpnvm[1] = selects boot code */
1193 /* if gpnvm[1] == 0 */
1194 /* boot is via "SAMBA" (rom) */
1195 /* else */
1196 /* boot is via FLASH */
1197 /* Selection is via gpnvm[2] */
1198 /* endif */
1199 /* */
1200 /* NOTE: banks 0 & 1 switch places */
1201 /* if gpnvm[2] == 0 */
1202 /* Bank0 is the boot rom */
1203 /* else */
1204 /* Bank1 is the boot rom */
1205 /* endif */
1206 /* .bank[0] = { */
1207 {
1208 {
1209 .probed = false,
1210 .chip = NULL,
1211 .bank = NULL,
1212 .bank_number = 0,
1213 .base_address = FLASH_BANK_BASE_N,
1214 .controller_address = 0x400e0A00,
1215 .flash_wait_states = 6, /* workaround silicon bug */
1216 .present = 1,
1217 .size_bytes = 128 * 1024,
1218 .nsectors = 8,
1219 .sector_size = 16384,
1220 .page_size = 256,
1221 },
1222
1223 /* .bank[1] = { */
1224 {
1225 .present = 0,
1226 .probed = false,
1227 .bank_number = 1,
1228 },
1229 },
1230 },
1231
1232 {
1233 .chipid_cidr = 0x29490760,
1234 .name = "at91sam3n2b",
1235 .total_flash_size = 128 * 1024,
1236 .total_sram_size = 16 * 1024,
1237 .n_gpnvms = 3,
1238 .n_banks = 1,
1239
1240 /* System boots at address 0x0 */
1241 /* gpnvm[1] = selects boot code */
1242 /* if gpnvm[1] == 0 */
1243 /* boot is via "SAMBA" (rom) */
1244 /* else */
1245 /* boot is via FLASH */
1246 /* Selection is via gpnvm[2] */
1247 /* endif */
1248 /* */
1249 /* NOTE: banks 0 & 1 switch places */
1250 /* if gpnvm[2] == 0 */
1251 /* Bank0 is the boot rom */
1252 /* else */
1253 /* Bank1 is the boot rom */
1254 /* endif */
1255 /* .bank[0] = { */
1256 {
1257 {
1258 .probed = false,
1259 .chip = NULL,
1260 .bank = NULL,
1261 .bank_number = 0,
1262 .base_address = FLASH_BANK_BASE_N,
1263 .controller_address = 0x400e0A00,
1264 .flash_wait_states = 6, /* workaround silicon bug */
1265 .present = 1,
1266 .size_bytes = 128 * 1024,
1267 .nsectors = 8,
1268 .sector_size = 16384,
1269 .page_size = 256,
1270 },
1271
1272 /* .bank[1] = { */
1273 {
1274 .present = 0,
1275 .probed = false,
1276 .bank_number = 1,
1277 },
1278 },
1279 },
1280
1281 {
1282 .chipid_cidr = 0x29390760,
1283 .name = "at91sam3n2a",
1284 .total_flash_size = 128 * 1024,
1285 .total_sram_size = 16 * 1024,
1286 .n_gpnvms = 3,
1287 .n_banks = 1,
1288
1289 /* System boots at address 0x0 */
1290 /* gpnvm[1] = selects boot code */
1291 /* if gpnvm[1] == 0 */
1292 /* boot is via "SAMBA" (rom) */
1293 /* else */
1294 /* boot is via FLASH */
1295 /* Selection is via gpnvm[2] */
1296 /* endif */
1297 /* */
1298 /* NOTE: banks 0 & 1 switch places */
1299 /* if gpnvm[2] == 0 */
1300 /* Bank0 is the boot rom */
1301 /* else */
1302 /* Bank1 is the boot rom */
1303 /* endif */
1304 /* .bank[0] = { */
1305 {
1306 {
1307 .probed = false,
1308 .chip = NULL,
1309 .bank = NULL,
1310 .bank_number = 0,
1311 .base_address = FLASH_BANK_BASE_N,
1312 .controller_address = 0x400e0A00,
1313 .flash_wait_states = 6, /* workaround silicon bug */
1314 .present = 1,
1315 .size_bytes = 128 * 1024,
1316 .nsectors = 8,
1317 .sector_size = 16384,
1318 .page_size = 256,
1319 },
1320
1321 /* .bank[1] = { */
1322 {
1323 .present = 0,
1324 .probed = false,
1325 .bank_number = 1,
1326 },
1327 },
1328 },
1329
1330 {
1331 .chipid_cidr = 0x29580560,
1332 .name = "at91sam3n1c",
1333 .total_flash_size = 64 * 1024,
1334 .total_sram_size = 8 * 1024,
1335 .n_gpnvms = 3,
1336 .n_banks = 1,
1337
1338 /* System boots at address 0x0 */
1339 /* gpnvm[1] = selects boot code */
1340 /* if gpnvm[1] == 0 */
1341 /* boot is via "SAMBA" (rom) */
1342 /* else */
1343 /* boot is via FLASH */
1344 /* Selection is via gpnvm[2] */
1345 /* endif */
1346 /* */
1347 /* NOTE: banks 0 & 1 switch places */
1348 /* if gpnvm[2] == 0 */
1349 /* Bank0 is the boot rom */
1350 /* else */
1351 /* Bank1 is the boot rom */
1352 /* endif */
1353 /* .bank[0] = { */
1354 {
1355 {
1356 .probed = false,
1357 .chip = NULL,
1358 .bank = NULL,
1359 .bank_number = 0,
1360 .base_address = FLASH_BANK_BASE_N,
1361 .controller_address = 0x400e0A00,
1362 .flash_wait_states = 6, /* workaround silicon bug */
1363 .present = 1,
1364 .size_bytes = 64 * 1024,
1365 .nsectors = 4,
1366 .sector_size = 16384,
1367 .page_size = 256,
1368 },
1369
1370 /* .bank[1] = { */
1371 {
1372 .present = 0,
1373 .probed = false,
1374 .bank_number = 1,
1375 },
1376 },
1377 },
1378
1379 {
1380 .chipid_cidr = 0x29480560,
1381 .name = "at91sam3n1b",
1382 .total_flash_size = 64 * 1024,
1383 .total_sram_size = 8 * 1024,
1384 .n_gpnvms = 3,
1385 .n_banks = 1,
1386
1387 /* System boots at address 0x0 */
1388 /* gpnvm[1] = selects boot code */
1389 /* if gpnvm[1] == 0 */
1390 /* boot is via "SAMBA" (rom) */
1391 /* else */
1392 /* boot is via FLASH */
1393 /* Selection is via gpnvm[2] */
1394 /* endif */
1395 /* */
1396 /* NOTE: banks 0 & 1 switch places */
1397 /* if gpnvm[2] == 0 */
1398 /* Bank0 is the boot rom */
1399 /* else */
1400 /* Bank1 is the boot rom */
1401 /* endif */
1402 /* .bank[0] = { */
1403 {
1404 {
1405 .probed = false,
1406 .chip = NULL,
1407 .bank = NULL,
1408 .bank_number = 0,
1409 .base_address = FLASH_BANK_BASE_N,
1410 .controller_address = 0x400e0A00,
1411 .flash_wait_states = 6, /* workaround silicon bug */
1412 .present = 1,
1413 .size_bytes = 64 * 1024,
1414 .nsectors = 4,
1415 .sector_size = 16384,
1416 .page_size = 256,
1417 },
1418
1419 /* .bank[1] = { */
1420 {
1421 .present = 0,
1422 .probed = false,
1423 .bank_number = 1,
1424 },
1425 },
1426 },
1427
1428 {
1429 .chipid_cidr = 0x29380560,
1430 .name = "at91sam3n1a",
1431 .total_flash_size = 64 * 1024,
1432 .total_sram_size = 8 * 1024,
1433 .n_gpnvms = 3,
1434 .n_banks = 1,
1435
1436 /* System boots at address 0x0 */
1437 /* gpnvm[1] = selects boot code */
1438 /* if gpnvm[1] == 0 */
1439 /* boot is via "SAMBA" (rom) */
1440 /* else */
1441 /* boot is via FLASH */
1442 /* Selection is via gpnvm[2] */
1443 /* endif */
1444 /* */
1445 /* NOTE: banks 0 & 1 switch places */
1446 /* if gpnvm[2] == 0 */
1447 /* Bank0 is the boot rom */
1448 /* else */
1449 /* Bank1 is the boot rom */
1450 /* endif */
1451 /* .bank[0] = { */
1452 {
1453 {
1454 .probed = false,
1455 .chip = NULL,
1456 .bank = NULL,
1457 .bank_number = 0,
1458 .base_address = FLASH_BANK_BASE_N,
1459 .controller_address = 0x400e0A00,
1460 .flash_wait_states = 6, /* workaround silicon bug */
1461 .present = 1,
1462 .size_bytes = 64 * 1024,
1463 .nsectors = 4,
1464 .sector_size = 16384,
1465 .page_size = 256,
1466 },
1467
1468 /* .bank[1] = { */
1469 {
1470 .present = 0,
1471 .probed = false,
1472 .bank_number = 1,
1473 },
1474 },
1475 },
1476
1477 {
1478 .chipid_cidr = 0x29480360,
1479 .name = "at91sam3n0b",
1480 .total_flash_size = 32 * 1024,
1481 .total_sram_size = 8 * 1024,
1482 .n_gpnvms = 3,
1483 .n_banks = 1,
1484
1485 /* .bank[0] = { */
1486 {
1487 {
1488 .probed = false,
1489 .chip = NULL,
1490 .bank = NULL,
1491 .bank_number = 0,
1492 .base_address = FLASH_BANK_BASE_N,
1493 .controller_address = 0x400e0A00,
1494 .flash_wait_states = 6, /* workaround silicon bug */
1495 .present = 1,
1496 .size_bytes = 32 * 1024,
1497 .nsectors = 2,
1498 .sector_size = 16384,
1499 .page_size = 256,
1500 },
1501
1502 /* .bank[1] = { */
1503 {
1504 .present = 0,
1505 .probed = false,
1506 .bank_number = 1,
1507 },
1508 },
1509 },
1510
1511 {
1512 .chipid_cidr = 0x29380360,
1513 .name = "at91sam3n0a",
1514 .total_flash_size = 32 * 1024,
1515 .total_sram_size = 8 * 1024,
1516 .n_gpnvms = 3,
1517 .n_banks = 1,
1518
1519 /* .bank[0] = { */
1520 {
1521 {
1522 .probed = false,
1523 .chip = NULL,
1524 .bank = NULL,
1525 .bank_number = 0,
1526 .base_address = FLASH_BANK_BASE_N,
1527 .controller_address = 0x400e0A00,
1528 .flash_wait_states = 6, /* workaround silicon bug */
1529 .present = 1,
1530 .size_bytes = 32 * 1024,
1531 .nsectors = 2,
1532 .sector_size = 16384,
1533 .page_size = 256,
1534 },
1535
1536 /* .bank[1] = { */
1537 {
1538 .present = 0,
1539 .probed = false,
1540 .bank_number = 1,
1541 },
1542 },
1543 },
1544
1545 {
1546 .chipid_cidr = 0x29450260,
1547 .name = "at91sam3n00b",
1548 .total_flash_size = 16 * 1024,
1549 .total_sram_size = 4 * 1024,
1550 .n_gpnvms = 3,
1551 .n_banks = 1,
1552
1553 /* .bank[0] = { */
1554 {
1555 {
1556 .probed = false,
1557 .chip = NULL,
1558 .bank = NULL,
1559 .bank_number = 0,
1560 .base_address = FLASH_BANK_BASE_N,
1561 .controller_address = 0x400e0A00,
1562 .flash_wait_states = 6, /* workaround silicon bug */
1563 .present = 1,
1564 .size_bytes = 16 * 1024,
1565 .nsectors = 1,
1566 .sector_size = 16384,
1567 .page_size = 256,
1568 },
1569
1570 /* .bank[1] = { */
1571 {
1572 .present = 0,
1573 .probed = false,
1574 .bank_number = 1,
1575 },
1576 },
1577 },
1578
1579 {
1580 .chipid_cidr = 0x29350260,
1581 .name = "at91sam3n00a",
1582 .total_flash_size = 16 * 1024,
1583 .total_sram_size = 4 * 1024,
1584 .n_gpnvms = 3,
1585 .n_banks = 1,
1586
1587 /* .bank[0] = { */
1588 {
1589 {
1590 .probed = false,
1591 .chip = NULL,
1592 .bank = NULL,
1593 .bank_number = 0,
1594 .base_address = FLASH_BANK_BASE_N,
1595 .controller_address = 0x400e0A00,
1596 .flash_wait_states = 6, /* workaround silicon bug */
1597 .present = 1,
1598 .size_bytes = 16 * 1024,
1599 .nsectors = 1,
1600 .sector_size = 16384,
1601 .page_size = 256,
1602 },
1603
1604 /* .bank[1] = { */
1605 {
1606 .present = 0,
1607 .probed = false,
1608 .bank_number = 1,
1609 },
1610 },
1611 },
1612
1613
1614 /* Start at91sam3a series*/
1615 /* System boots at address 0x0 */
1616 /* gpnvm[1] = selects boot code */
1617 /* if gpnvm[1] == 0 */
1618 /* boot is via "SAMBA" (rom) */
1619 /* else */
1620 /* boot is via FLASH */
1621 /* Selection is via gpnvm[2] */
1622 /* endif */
1623 /* */
1624 /* NOTE: banks 0 & 1 switch places */
1625 /* if gpnvm[2] == 0 */
1626 /* Bank0 is the boot rom */
1627 /* else */
1628 /* Bank1 is the boot rom */
1629 /* endif */
1630
1631 {
1632 .chipid_cidr = 0x283E0A60,
1633 .name = "at91sam3a8c",
1634 .total_flash_size = 512 * 1024,
1635 .total_sram_size = 96 * 1024,
1636 .n_gpnvms = 3,
1637 .n_banks = 2,
1638 {
1639 /* .bank[0] = { */
1640 {
1641 .probed = false,
1642 .chip = NULL,
1643 .bank = NULL,
1644 .bank_number = 0,
1645 .base_address = FLASH_BANK0_BASE_AX,
1646 .controller_address = 0x400e0a00,
1647 .flash_wait_states = 6, /* workaround silicon bug */
1648 .present = 1,
1649 .size_bytes = 256 * 1024,
1650 .nsectors = 16,
1651 .sector_size = 16384,
1652 .page_size = 256,
1653 },
1654 /* .bank[1] = { */
1655 {
1656 .probed = false,
1657 .chip = NULL,
1658 .bank = NULL,
1659 .bank_number = 1,
1660 .base_address = FLASH_BANK1_BASE_512K_AX,
1661 .controller_address = 0x400e0c00,
1662 .flash_wait_states = 6, /* workaround silicon bug */
1663 .present = 1,
1664 .size_bytes = 256 * 1024,
1665 .nsectors = 16,
1666 .sector_size = 16384,
1667 .page_size = 256,
1668
1669 },
1670 },
1671 },
1672 {
1673 .chipid_cidr = 0x283B0960,
1674 .name = "at91sam3a4c",
1675 .total_flash_size = 256 * 1024,
1676 .total_sram_size = 64 * 1024,
1677 .n_gpnvms = 3,
1678 .n_banks = 2,
1679 {
1680 /* .bank[0] = { */
1681 {
1682 .probed = false,
1683 .chip = NULL,
1684 .bank = NULL,
1685 .bank_number = 0,
1686 .base_address = FLASH_BANK0_BASE_AX,
1687 .controller_address = 0x400e0a00,
1688 .flash_wait_states = 6, /* workaround silicon bug */
1689 .present = 1,
1690 .size_bytes = 128 * 1024,
1691 .nsectors = 8,
1692 .sector_size = 16384,
1693 .page_size = 256,
1694 },
1695 /* .bank[1] = { */
1696 {
1697 .probed = false,
1698 .chip = NULL,
1699 .bank = NULL,
1700 .bank_number = 1,
1701 .base_address = FLASH_BANK1_BASE_256K_AX,
1702 .controller_address = 0x400e0c00,
1703 .flash_wait_states = 6, /* workaround silicon bug */
1704 .present = 1,
1705 .size_bytes = 128 * 1024,
1706 .nsectors = 8,
1707 .sector_size = 16384,
1708 .page_size = 256,
1709
1710 },
1711 },
1712 },
1713
1714 /* Start at91sam3x* series */
1715 /* System boots at address 0x0 */
1716 /* gpnvm[1] = selects boot code */
1717 /* if gpnvm[1] == 0 */
1718 /* boot is via "SAMBA" (rom) */
1719 /* else */
1720 /* boot is via FLASH */
1721 /* Selection is via gpnvm[2] */
1722 /* endif */
1723 /* */
1724 /* NOTE: banks 0 & 1 switch places */
1725 /* if gpnvm[2] == 0 */
1726 /* Bank0 is the boot rom */
1727 /* else */
1728 /* Bank1 is the boot rom */
1729 /* endif */
1730 /*at91sam3x8h - ES has an incorrect CIDR of 0x286E0A20*/
1731 {
1732 .chipid_cidr = 0x286E0A20,
1733 .name = "at91sam3x8h - ES",
1734 .total_flash_size = 512 * 1024,
1735 .total_sram_size = 96 * 1024,
1736 .n_gpnvms = 3,
1737 .n_banks = 2,
1738 {
1739 /* .bank[0] = { */
1740 {
1741 .probed = false,
1742 .chip = NULL,
1743 .bank = NULL,
1744 .bank_number = 0,
1745 .base_address = FLASH_BANK0_BASE_AX,
1746 .controller_address = 0x400e0a00,
1747 .flash_wait_states = 6, /* workaround silicon bug */
1748 .present = 1,
1749 .size_bytes = 256 * 1024,
1750 .nsectors = 16,
1751 .sector_size = 16384,
1752 .page_size = 256,
1753 },
1754 /* .bank[1] = { */
1755 {
1756 .probed = false,
1757 .chip = NULL,
1758 .bank = NULL,
1759 .bank_number = 1,
1760 .base_address = FLASH_BANK1_BASE_512K_AX,
1761 .controller_address = 0x400e0c00,
1762 .flash_wait_states = 6, /* workaround silicon bug */
1763 .present = 1,
1764 .size_bytes = 256 * 1024,
1765 .nsectors = 16,
1766 .sector_size = 16384,
1767 .page_size = 256,
1768
1769 },
1770 },
1771 },
1772 /*at91sam3x8h - ES2 and up uses the correct CIDR of 0x286E0A60*/
1773 {
1774 .chipid_cidr = 0x286E0A60,
1775 .name = "at91sam3x8h",
1776 .total_flash_size = 512 * 1024,
1777 .total_sram_size = 96 * 1024,
1778 .n_gpnvms = 3,
1779 .n_banks = 2,
1780 {
1781 /* .bank[0] = { */
1782 {
1783 .probed = false,
1784 .chip = NULL,
1785 .bank = NULL,
1786 .bank_number = 0,
1787 .base_address = FLASH_BANK0_BASE_AX,
1788 .controller_address = 0x400e0a00,
1789 .flash_wait_states = 6, /* workaround silicon bug */
1790 .present = 1,
1791 .size_bytes = 256 * 1024,
1792 .nsectors = 16,
1793 .sector_size = 16384,
1794 .page_size = 256,
1795 },
1796 /* .bank[1] = { */
1797 {
1798 .probed = false,
1799 .chip = NULL,
1800 .bank = NULL,
1801 .bank_number = 1,
1802 .base_address = FLASH_BANK1_BASE_512K_AX,
1803 .controller_address = 0x400e0c00,
1804 .flash_wait_states = 6, /* workaround silicon bug */
1805 .present = 1,
1806 .size_bytes = 256 * 1024,
1807 .nsectors = 16,
1808 .sector_size = 16384,
1809 .page_size = 256,
1810
1811 },
1812 },
1813 },
1814 {
1815 .chipid_cidr = 0x285E0A60,
1816 .name = "at91sam3x8e",
1817 .total_flash_size = 512 * 1024,
1818 .total_sram_size = 96 * 1024,
1819 .n_gpnvms = 3,
1820 .n_banks = 2,
1821 {
1822 /* .bank[0] = { */
1823 {
1824 .probed = false,
1825 .chip = NULL,
1826 .bank = NULL,
1827 .bank_number = 0,
1828 .base_address = FLASH_BANK0_BASE_AX,
1829 .controller_address = 0x400e0a00,
1830 .flash_wait_states = 6, /* workaround silicon bug */
1831 .present = 1,
1832 .size_bytes = 256 * 1024,
1833 .nsectors = 16,
1834 .sector_size = 16384,
1835 .page_size = 256,
1836 },
1837 /* .bank[1] = { */
1838 {
1839 .probed = false,
1840 .chip = NULL,
1841 .bank = NULL,
1842 .bank_number = 1,
1843 .base_address = FLASH_BANK1_BASE_512K_AX,
1844 .controller_address = 0x400e0c00,
1845 .flash_wait_states = 6, /* workaround silicon bug */
1846 .present = 1,
1847 .size_bytes = 256 * 1024,
1848 .nsectors = 16,
1849 .sector_size = 16384,
1850 .page_size = 256,
1851
1852 },
1853 },
1854 },
1855 {
1856 .chipid_cidr = 0x284E0A60,
1857 .name = "at91sam3x8c",
1858 .total_flash_size = 512 * 1024,
1859 .total_sram_size = 96 * 1024,
1860 .n_gpnvms = 3,
1861 .n_banks = 2,
1862 {
1863 /* .bank[0] = { */
1864 {
1865 .probed = false,
1866 .chip = NULL,
1867 .bank = NULL,
1868 .bank_number = 0,
1869 .base_address = FLASH_BANK0_BASE_AX,
1870 .controller_address = 0x400e0a00,
1871 .flash_wait_states = 6, /* workaround silicon bug */
1872 .present = 1,
1873 .size_bytes = 256 * 1024,
1874 .nsectors = 16,
1875 .sector_size = 16384,
1876 .page_size = 256,
1877 },
1878 /* .bank[1] = { */
1879 {
1880 .probed = false,
1881 .chip = NULL,
1882 .bank = NULL,
1883 .bank_number = 1,
1884 .base_address = FLASH_BANK1_BASE_512K_AX,
1885 .controller_address = 0x400e0c00,
1886 .flash_wait_states = 6, /* workaround silicon bug */
1887 .present = 1,
1888 .size_bytes = 256 * 1024,
1889 .nsectors = 16,
1890 .sector_size = 16384,
1891 .page_size = 256,
1892
1893 },
1894 },
1895 },
1896 {
1897 .chipid_cidr = 0x285B0960,
1898 .name = "at91sam3x4e",
1899 .total_flash_size = 256 * 1024,
1900 .total_sram_size = 64 * 1024,
1901 .n_gpnvms = 3,
1902 .n_banks = 2,
1903 {
1904 /* .bank[0] = { */
1905 {
1906 .probed = false,
1907 .chip = NULL,
1908 .bank = NULL,
1909 .bank_number = 0,
1910 .base_address = FLASH_BANK0_BASE_AX,
1911 .controller_address = 0x400e0a00,
1912 .flash_wait_states = 6, /* workaround silicon bug */
1913 .present = 1,
1914 .size_bytes = 128 * 1024,
1915 .nsectors = 8,
1916 .sector_size = 16384,
1917 .page_size = 256,
1918 },
1919 /* .bank[1] = { */
1920 {
1921 .probed = false,
1922 .chip = NULL,
1923 .bank = NULL,
1924 .bank_number = 1,
1925 .base_address = FLASH_BANK1_BASE_256K_AX,
1926 .controller_address = 0x400e0c00,
1927 .flash_wait_states = 6, /* workaround silicon bug */
1928 .present = 1,
1929 .size_bytes = 128 * 1024,
1930 .nsectors = 8,
1931 .sector_size = 16384,
1932 .page_size = 256,
1933
1934 },
1935 },
1936 },
1937 {
1938 .chipid_cidr = 0x284B0960,
1939 .name = "at91sam3x4c",
1940 .total_flash_size = 256 * 1024,
1941 .total_sram_size = 64 * 1024,
1942 .n_gpnvms = 3,
1943 .n_banks = 2,
1944 {
1945 /* .bank[0] = { */
1946 {
1947 .probed = false,
1948 .chip = NULL,
1949 .bank = NULL,
1950 .bank_number = 0,
1951 .base_address = FLASH_BANK0_BASE_AX,
1952 .controller_address = 0x400e0a00,
1953 .flash_wait_states = 6, /* workaround silicon bug */
1954 .present = 1,
1955 .size_bytes = 128 * 1024,
1956 .nsectors = 8,
1957 .sector_size = 16384,
1958 .page_size = 256,
1959 },
1960 /* .bank[1] = { */
1961 {
1962 .probed = false,
1963 .chip = NULL,
1964 .bank = NULL,
1965 .bank_number = 1,
1966 .base_address = FLASH_BANK1_BASE_256K_AX,
1967 .controller_address = 0x400e0c00,
1968 .flash_wait_states = 6, /* workaround silicon bug */
1969 .present = 1,
1970 .size_bytes = 128 * 1024,
1971 .nsectors = 8,
1972 .sector_size = 16384,
1973 .page_size = 256,
1974
1975 },
1976 },
1977 },
1978 /* terminate */
1979 {
1980 .chipid_cidr = 0,
1981 .name = NULL,
1982 }
1983 };
1984
1985 /* Globals above */
1986 /***********************************************************************
1987 **********************************************************************
1988 **********************************************************************
1989 **********************************************************************
1990 **********************************************************************
1991 **********************************************************************/
1992 /* *ATMEL* style code - from the SAM3 driver code */
1993
1994 /**
1995 * Get the current status of the EEFC and
1996 * the value of some status bits (LOCKE, PROGE).
1997 * @param private - info about the bank
1998 * @param v - result goes here
1999 */
2000 static int efc_get_status(struct sam3_bank_private *private, uint32_t *v)
2001 {
2002 int r;
2003 r = target_read_u32(private->chip->target,
2004 private->controller_address + OFFSET_EFC_FSR,
2005 v);
2006 LOG_DEBUG("Status: 0x%08x (lockerror: %d, cmderror: %d, ready: %d)",
2007 (unsigned int)(*v),
2008 ((unsigned int)((*v >> 2) & 1)),
2009 ((unsigned int)((*v >> 1) & 1)),
2010 ((unsigned int)((*v >> 0) & 1)));
2011
2012 return r;
2013 }
2014
2015 /**
2016 * Get the result of the last executed command.
2017 * @param private - info about the bank
2018 * @param v - result goes here
2019 */
2020 static int efc_get_result(struct sam3_bank_private *private, uint32_t *v)
2021 {
2022 int r;
2023 uint32_t rv;
2024 r = target_read_u32(private->chip->target,
2025 private->controller_address + OFFSET_EFC_FRR,
2026 &rv);
2027 if (v)
2028 *v = rv;
2029 LOG_DEBUG("Result: 0x%08x", ((unsigned int)(rv)));
2030 return r;
2031 }
2032
2033 static int efc_start_command(struct sam3_bank_private *private,
2034 unsigned command, unsigned argument)
2035 {
2036 uint32_t n, v;
2037 int r;
2038 int retry;
2039
2040 retry = 0;
2041 do_retry:
2042
2043 /* Check command & argument */
2044 switch (command) {
2045
2046 case AT91C_EFC_FCMD_WP:
2047 case AT91C_EFC_FCMD_WPL:
2048 case AT91C_EFC_FCMD_EWP:
2049 case AT91C_EFC_FCMD_EWPL:
2050 /* case AT91C_EFC_FCMD_EPL: */
2051 /* case AT91C_EFC_FCMD_EPA: */
2052 case AT91C_EFC_FCMD_SLB:
2053 case AT91C_EFC_FCMD_CLB:
2054 n = (private->size_bytes / private->page_size);
2055 if (argument >= n)
2056 LOG_ERROR("*BUG*: Embedded flash has only %u pages", (unsigned)(n));
2057 break;
2058
2059 case AT91C_EFC_FCMD_SFB:
2060 case AT91C_EFC_FCMD_CFB:
2061 if (argument >= private->chip->details.n_gpnvms) {
2062 LOG_ERROR("*BUG*: Embedded flash has only %d GPNVMs",
2063 private->chip->details.n_gpnvms);
2064 }
2065 break;
2066
2067 case AT91C_EFC_FCMD_GETD:
2068 case AT91C_EFC_FCMD_EA:
2069 case AT91C_EFC_FCMD_GLB:
2070 case AT91C_EFC_FCMD_GFB:
2071 case AT91C_EFC_FCMD_STUI:
2072 case AT91C_EFC_FCMD_SPUI:
2073 if (argument != 0)
2074 LOG_ERROR("Argument is meaningless for cmd: %d", command);
2075 break;
2076 default:
2077 LOG_ERROR("Unknown command %d", command);
2078 break;
2079 }
2080
2081 if (command == AT91C_EFC_FCMD_SPUI) {
2082 /* this is a very special situation. */
2083 /* Situation (1) - error/retry - see below */
2084 /* And we are being called recursively */
2085 /* Situation (2) - normal, finished reading unique id */
2086 } else {
2087 /* it should be "ready" */
2088 efc_get_status(private, &v);
2089 if (v & 1) {
2090 /* then it is ready */
2091 /* we go on */
2092 } else {
2093 if (retry) {
2094 /* we have done this before */
2095 /* the controller is not responding. */
2096 LOG_ERROR("flash controller(%d) is not ready! Error",
2097 private->bank_number);
2098 return ERROR_FAIL;
2099 } else {
2100 retry++;
2101 LOG_ERROR("Flash controller(%d) is not ready, attempting reset",
2102 private->bank_number);
2103 /* we do that by issuing the *STOP* command */
2104 efc_start_command(private, AT91C_EFC_FCMD_SPUI, 0);
2105 /* above is recursive, and further recursion is blocked by */
2106 /* if (command == AT91C_EFC_FCMD_SPUI) above */
2107 goto do_retry;
2108 }
2109 }
2110 }
2111
2112 v = (0x5A << 24) | (argument << 8) | command;
2113 LOG_DEBUG("Command: 0x%08x", ((unsigned int)(v)));
2114 r = target_write_u32(private->bank->target,
2115 private->controller_address + OFFSET_EFC_FCR, v);
2116 if (r != ERROR_OK)
2117 LOG_DEBUG("Error Write failed");
2118 return r;
2119 }
2120
2121 /**
2122 * Performs the given command and wait until its completion (or an error).
2123 * @param private - info about the bank
2124 * @param command - Command to perform.
2125 * @param argument - Optional command argument.
2126 * @param status - put command status bits here
2127 */
2128 static int efc_perform_command(struct sam3_bank_private *private,
2129 unsigned command,
2130 unsigned argument,
2131 uint32_t *status)
2132 {
2133
2134 int r;
2135 uint32_t v;
2136 int64_t ms_now, ms_end;
2137
2138 /* default */
2139 if (status)
2140 *status = 0;
2141
2142 r = efc_start_command(private, command, argument);
2143 if (r != ERROR_OK)
2144 return r;
2145
2146 ms_end = 500 + timeval_ms();
2147
2148 do {
2149 r = efc_get_status(private, &v);
2150 if (r != ERROR_OK)
2151 return r;
2152 ms_now = timeval_ms();
2153 if (ms_now > ms_end) {
2154 /* error */
2155 LOG_ERROR("Command timeout");
2156 return ERROR_FAIL;
2157 }
2158 } while ((v & 1) == 0);
2159
2160 /* error bits.. */
2161 if (status)
2162 *status = (v & 0x6);
2163 return ERROR_OK;
2164
2165 }
2166
2167 /**
2168 * Read the unique ID.
2169 * @param private - info about the bank
2170 * The unique ID is stored in the 'private' structure.
2171 */
2172 static int flashd_read_uid(struct sam3_bank_private *private)
2173 {
2174 int r;
2175 uint32_t v;
2176 int x;
2177 /* assume 0 */
2178 private->chip->cfg.unique_id[0] = 0;
2179 private->chip->cfg.unique_id[1] = 0;
2180 private->chip->cfg.unique_id[2] = 0;
2181 private->chip->cfg.unique_id[3] = 0;
2182
2183 LOG_DEBUG("Begin");
2184 r = efc_start_command(private, AT91C_EFC_FCMD_STUI, 0);
2185 if (r < 0)
2186 return r;
2187
2188 for (x = 0; x < 4; x++) {
2189 r = target_read_u32(private->chip->target,
2190 private->bank->base + (x * 4),
2191 &v);
2192 if (r < 0)
2193 return r;
2194 private->chip->cfg.unique_id[x] = v;
2195 }
2196
2197 r = efc_perform_command(private, AT91C_EFC_FCMD_SPUI, 0, NULL);
2198 LOG_DEBUG("End: R=%d, id = 0x%08x, 0x%08x, 0x%08x, 0x%08x",
2199 r,
2200 (unsigned int)(private->chip->cfg.unique_id[0]),
2201 (unsigned int)(private->chip->cfg.unique_id[1]),
2202 (unsigned int)(private->chip->cfg.unique_id[2]),
2203 (unsigned int)(private->chip->cfg.unique_id[3]));
2204 return r;
2205
2206 }
2207
2208 /**
2209 * Erases the entire flash.
2210 * @param private - the info about the bank.
2211 */
2212 static int flashd_erase_entire_bank(struct sam3_bank_private *private)
2213 {
2214 LOG_DEBUG("Here");
2215 return efc_perform_command(private, AT91C_EFC_FCMD_EA, 0, NULL);
2216 }
2217
2218 /**
2219 * Gets current GPNVM state.
2220 * @param private - info about the bank.
2221 * @param gpnvm - GPNVM bit index.
2222 * @param puthere - result stored here.
2223 */
2224 /* ------------------------------------------------------------------------------ */
2225 static int flashd_get_gpnvm(struct sam3_bank_private *private, unsigned gpnvm, unsigned *puthere)
2226 {
2227 uint32_t v;
2228 int r;
2229
2230 LOG_DEBUG("Here");
2231 if (private->bank_number != 0) {
2232 LOG_ERROR("GPNVM only works with Bank0");
2233 return ERROR_FAIL;
2234 }
2235
2236 if (gpnvm >= private->chip->details.n_gpnvms) {
2237 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
2238 gpnvm, private->chip->details.n_gpnvms);
2239 return ERROR_FAIL;
2240 }
2241
2242 /* Get GPNVMs status */
2243 r = efc_perform_command(private, AT91C_EFC_FCMD_GFB, 0, NULL);
2244 if (r != ERROR_OK) {
2245 LOG_ERROR("Failed");
2246 return r;
2247 }
2248
2249 r = efc_get_result(private, &v);
2250
2251 if (puthere) {
2252 /* Check if GPNVM is set */
2253 /* get the bit and make it a 0/1 */
2254 *puthere = (v >> gpnvm) & 1;
2255 }
2256
2257 return r;
2258 }
2259
2260 /**
2261 * Clears the selected GPNVM bit.
2262 * @param private info about the bank
2263 * @param gpnvm GPNVM index.
2264 * @returns 0 if successful; otherwise returns an error code.
2265 */
2266 static int flashd_clr_gpnvm(struct sam3_bank_private *private, unsigned gpnvm)
2267 {
2268 int r;
2269 unsigned v;
2270
2271 LOG_DEBUG("Here");
2272 if (private->bank_number != 0) {
2273 LOG_ERROR("GPNVM only works with Bank0");
2274 return ERROR_FAIL;
2275 }
2276
2277 if (gpnvm >= private->chip->details.n_gpnvms) {
2278 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
2279 gpnvm, private->chip->details.n_gpnvms);
2280 return ERROR_FAIL;
2281 }
2282
2283 r = flashd_get_gpnvm(private, gpnvm, &v);
2284 if (r != ERROR_OK) {
2285 LOG_DEBUG("Failed: %d", r);
2286 return r;
2287 }
2288 r = efc_perform_command(private, AT91C_EFC_FCMD_CFB, gpnvm, NULL);
2289 LOG_DEBUG("End: %d", r);
2290 return r;
2291 }
2292
2293 /**
2294 * Sets the selected GPNVM bit.
2295 * @param private info about the bank
2296 * @param gpnvm GPNVM index.
2297 */
2298 static int flashd_set_gpnvm(struct sam3_bank_private *private, unsigned gpnvm)
2299 {
2300 int r;
2301 unsigned v;
2302
2303 if (private->bank_number != 0) {
2304 LOG_ERROR("GPNVM only works with Bank0");
2305 return ERROR_FAIL;
2306 }
2307
2308 if (gpnvm >= private->chip->details.n_gpnvms) {
2309 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
2310 gpnvm, private->chip->details.n_gpnvms);
2311 return ERROR_FAIL;
2312 }
2313
2314 r = flashd_get_gpnvm(private, gpnvm, &v);
2315 if (r != ERROR_OK)
2316 return r;
2317 if (v) {
2318 /* already set */
2319 r = ERROR_OK;
2320 } else {
2321 /* set it */
2322 r = efc_perform_command(private, AT91C_EFC_FCMD_SFB, gpnvm, NULL);
2323 }
2324 return r;
2325 }
2326
2327 /**
2328 * Returns a bit field (at most 64) of locked regions within a page.
2329 * @param private info about the bank
2330 * @param v where to store locked bits
2331 */
2332 static int flashd_get_lock_bits(struct sam3_bank_private *private, uint32_t *v)
2333 {
2334 int r;
2335 LOG_DEBUG("Here");
2336 r = efc_perform_command(private, AT91C_EFC_FCMD_GLB, 0, NULL);
2337 if (r == ERROR_OK)
2338 r = efc_get_result(private, v);
2339 LOG_DEBUG("End: %d", r);
2340 return r;
2341 }
2342
2343 /**
2344 * Unlocks all the regions in the given address range.
2345 * @param private info about the bank
2346 * @param start_sector first sector to unlock
2347 * @param end_sector last (inclusive) to unlock
2348 */
2349
2350 static int flashd_unlock(struct sam3_bank_private *private,
2351 unsigned start_sector,
2352 unsigned end_sector)
2353 {
2354 int r;
2355 uint32_t status;
2356 uint32_t pg;
2357 uint32_t pages_per_sector;
2358
2359 pages_per_sector = private->sector_size / private->page_size;
2360
2361 /* Unlock all pages */
2362 while (start_sector <= end_sector) {
2363 pg = start_sector * pages_per_sector;
2364
2365 r = efc_perform_command(private, AT91C_EFC_FCMD_CLB, pg, &status);
2366 if (r != ERROR_OK)
2367 return r;
2368 start_sector++;
2369 }
2370
2371 return ERROR_OK;
2372 }
2373
2374 /**
2375 * Locks regions
2376 * @param private - info about the bank
2377 * @param start_sector - first sector to lock
2378 * @param end_sector - last sector (inclusive) to lock
2379 */
2380 static int flashd_lock(struct sam3_bank_private *private,
2381 unsigned start_sector,
2382 unsigned end_sector)
2383 {
2384 uint32_t status;
2385 uint32_t pg;
2386 uint32_t pages_per_sector;
2387 int r;
2388
2389 pages_per_sector = private->sector_size / private->page_size;
2390
2391 /* Lock all pages */
2392 while (start_sector <= end_sector) {
2393 pg = start_sector * pages_per_sector;
2394
2395 r = efc_perform_command(private, AT91C_EFC_FCMD_SLB, pg, &status);
2396 if (r != ERROR_OK)
2397 return r;
2398 start_sector++;
2399 }
2400 return ERROR_OK;
2401 }
2402
2403 /****** END SAM3 CODE ********/
2404
2405 /* begin helpful debug code */
2406 /* print the fieldname, the field value, in dec & hex, and return field value */
2407 static uint32_t sam3_reg_fieldname(struct sam3_chip *chip,
2408 const char *regname,
2409 uint32_t value,
2410 unsigned shift,
2411 unsigned width)
2412 {
2413 uint32_t v;
2414 int hwidth, dwidth;
2415
2416
2417 /* extract the field */
2418 v = value >> shift;
2419 v = v & ((1 << width)-1);
2420 if (width <= 16) {
2421 hwidth = 4;
2422 dwidth = 5;
2423 } else {
2424 hwidth = 8;
2425 dwidth = 12;
2426 }
2427
2428 /* show the basics */
2429 LOG_USER_N("\t%*s: %*" PRIu32 " [0x%0*" PRIx32 "] ",
2430 REG_NAME_WIDTH, regname,
2431 dwidth, v,
2432 hwidth, v);
2433 return v;
2434 }
2435
2436 static const char _unknown[] = "unknown";
2437 static const char *const eproc_names[] = {
2438 _unknown, /* 0 */
2439 "arm946es", /* 1 */
2440 "arm7tdmi", /* 2 */
2441 "Cortex-M3", /* 3 */
2442 "arm920t", /* 4 */
2443 "arm926ejs", /* 5 */
2444 _unknown, /* 6 */
2445 _unknown, /* 7 */
2446 _unknown, /* 8 */
2447 _unknown, /* 9 */
2448 _unknown, /* 10 */
2449 _unknown, /* 11 */
2450 _unknown, /* 12 */
2451 _unknown, /* 13 */
2452 _unknown, /* 14 */
2453 _unknown, /* 15 */
2454 };
2455
2456 #define nvpsize2 nvpsize /* these two tables are identical */
2457 static const char *const nvpsize[] = {
2458 "none", /* 0 */
2459 "8K bytes", /* 1 */
2460 "16K bytes", /* 2 */
2461 "32K bytes", /* 3 */
2462 _unknown, /* 4 */
2463 "64K bytes", /* 5 */
2464 _unknown, /* 6 */
2465 "128K bytes", /* 7 */
2466 _unknown, /* 8 */
2467 "256K bytes", /* 9 */
2468 "512K bytes", /* 10 */
2469 _unknown, /* 11 */
2470 "1024K bytes", /* 12 */
2471 _unknown, /* 13 */
2472 "2048K bytes", /* 14 */
2473 _unknown, /* 15 */
2474 };
2475
2476 static const char *const sramsize[] = {
2477 "48K Bytes", /* 0 */
2478 "1K Bytes", /* 1 */
2479 "2K Bytes", /* 2 */
2480 "6K Bytes", /* 3 */
2481 "112K Bytes", /* 4 */
2482 "4K Bytes", /* 5 */
2483 "80K Bytes", /* 6 */
2484 "160K Bytes", /* 7 */
2485 "8K Bytes", /* 8 */
2486 "16K Bytes", /* 9 */
2487 "32K Bytes", /* 10 */
2488 "64K Bytes", /* 11 */
2489 "128K Bytes", /* 12 */
2490 "256K Bytes", /* 13 */
2491 "96K Bytes", /* 14 */
2492 "512K Bytes", /* 15 */
2493
2494 };
2495
2496 static const struct archnames { unsigned value; const char *name; } archnames[] = {
2497 { 0x19, "AT91SAM9xx Series" },
2498 { 0x29, "AT91SAM9XExx Series" },
2499 { 0x34, "AT91x34 Series" },
2500 { 0x37, "CAP7 Series" },
2501 { 0x39, "CAP9 Series" },
2502 { 0x3B, "CAP11 Series" },
2503 { 0x40, "AT91x40 Series" },
2504 { 0x42, "AT91x42 Series" },
2505 { 0x55, "AT91x55 Series" },
2506 { 0x60, "AT91SAM7Axx Series" },
2507 { 0x61, "AT91SAM7AQxx Series" },
2508 { 0x63, "AT91x63 Series" },
2509 { 0x70, "AT91SAM7Sxx Series" },
2510 { 0x71, "AT91SAM7XCxx Series" },
2511 { 0x72, "AT91SAM7SExx Series" },
2512 { 0x73, "AT91SAM7Lxx Series" },
2513 { 0x75, "AT91SAM7Xxx Series" },
2514 { 0x76, "AT91SAM7SLxx Series" },
2515 { 0x80, "ATSAM3UxC Series (100-pin version)" },
2516 { 0x81, "ATSAM3UxE Series (144-pin version)" },
2517 { 0x83, "ATSAM3AxC Series (100-pin version)" },
2518 { 0x84, "ATSAM3XxC Series (100-pin version)" },
2519 { 0x85, "ATSAM3XxE Series (144-pin version)" },
2520 { 0x86, "ATSAM3XxG Series (208/217-pin version)" },
2521 { 0x88, "ATSAM3SxA Series (48-pin version)" },
2522 { 0x89, "ATSAM3SxB Series (64-pin version)" },
2523 { 0x8A, "ATSAM3SxC Series (100-pin version)" },
2524 { 0x92, "AT91x92 Series" },
2525 { 0x93, "ATSAM3NxA Series (48-pin version)" },
2526 { 0x94, "ATSAM3NxB Series (64-pin version)" },
2527 { 0x95, "ATSAM3NxC Series (100-pin version)" },
2528 { 0x98, "ATSAM3SDxA Series (48-pin version)" },
2529 { 0x99, "ATSAM3SDxB Series (64-pin version)" },
2530 { 0x9A, "ATSAM3SDxC Series (100-pin version)" },
2531 { 0xA5, "ATSAM5A" },
2532 { 0xF0, "AT75Cxx Series" },
2533 { -1, NULL },
2534 };
2535
2536 static const char *const nvptype[] = {
2537 "rom", /* 0 */
2538 "romless or onchip flash", /* 1 */
2539 "embedded flash memory",/* 2 */
2540 "rom(nvpsiz) + embedded flash (nvpsiz2)", /* 3 */
2541 "sram emulating flash", /* 4 */
2542 _unknown, /* 5 */
2543 _unknown, /* 6 */
2544 _unknown, /* 7 */
2545 };
2546
2547 static const char *_yes_or_no(uint32_t v)
2548 {
2549 if (v)
2550 return "YES";
2551 else
2552 return "NO";
2553 }
2554
2555 static const char *const _rc_freq[] = {
2556 "4 MHz", "8 MHz", "12 MHz", "reserved"
2557 };
2558
2559 static void sam3_explain_ckgr_mor(struct sam3_chip *chip)
2560 {
2561 uint32_t v;
2562 uint32_t rcen;
2563
2564 v = sam3_reg_fieldname(chip, "MOSCXTEN", chip->cfg.CKGR_MOR, 0, 1);
2565 LOG_USER("(main xtal enabled: %s)", _yes_or_no(v));
2566 v = sam3_reg_fieldname(chip, "MOSCXTBY", chip->cfg.CKGR_MOR, 1, 1);
2567 LOG_USER("(main osc bypass: %s)", _yes_or_no(v));
2568 rcen = sam3_reg_fieldname(chip, "MOSCRCEN", chip->cfg.CKGR_MOR, 3, 1);
2569 LOG_USER("(onchip RC-OSC enabled: %s)", _yes_or_no(rcen));
2570 v = sam3_reg_fieldname(chip, "MOSCRCF", chip->cfg.CKGR_MOR, 4, 3);
2571 LOG_USER("(onchip RC-OSC freq: %s)", _rc_freq[v]);
2572
2573 chip->cfg.rc_freq = 0;
2574 if (rcen) {
2575 switch (v) {
2576 default:
2577 chip->cfg.rc_freq = 0;
2578 break;
2579 case 0:
2580 chip->cfg.rc_freq = 4 * 1000 * 1000;
2581 break;
2582 case 1:
2583 chip->cfg.rc_freq = 8 * 1000 * 1000;
2584 break;
2585 case 2:
2586 chip->cfg.rc_freq = 12 * 1000 * 1000;
2587 break;
2588 }
2589 }
2590
2591 v = sam3_reg_fieldname(chip, "MOSCXTST", chip->cfg.CKGR_MOR, 8, 8);
2592 LOG_USER("(startup clks, time= %f uSecs)",
2593 ((float)(v * 1000000)) / ((float)(chip->cfg.slow_freq)));
2594 v = sam3_reg_fieldname(chip, "MOSCSEL", chip->cfg.CKGR_MOR, 24, 1);
2595 LOG_USER("(mainosc source: %s)",
2596 v ? "external xtal" : "internal RC");
2597
2598 v = sam3_reg_fieldname(chip, "CFDEN", chip->cfg.CKGR_MOR, 25, 1);
2599 LOG_USER("(clock failure enabled: %s)",
2600 _yes_or_no(v));
2601 }
2602
2603 static void sam3_explain_chipid_cidr(struct sam3_chip *chip)
2604 {
2605 int x;
2606 uint32_t v;
2607 const char *cp;
2608
2609 sam3_reg_fieldname(chip, "Version", chip->cfg.CHIPID_CIDR, 0, 5);
2610 LOG_USER_N("\n");
2611
2612 v = sam3_reg_fieldname(chip, "EPROC", chip->cfg.CHIPID_CIDR, 5, 3);
2613 LOG_USER("%s", eproc_names[v]);
2614
2615 v = sam3_reg_fieldname(chip, "NVPSIZE", chip->cfg.CHIPID_CIDR, 8, 4);
2616 LOG_USER("%s", nvpsize[v]);
2617
2618 v = sam3_reg_fieldname(chip, "NVPSIZE2", chip->cfg.CHIPID_CIDR, 12, 4);
2619 LOG_USER("%s", nvpsize2[v]);
2620
2621 v = sam3_reg_fieldname(chip, "SRAMSIZE", chip->cfg.CHIPID_CIDR, 16, 4);
2622 LOG_USER("%s", sramsize[v]);
2623
2624 v = sam3_reg_fieldname(chip, "ARCH", chip->cfg.CHIPID_CIDR, 20, 8);
2625 cp = _unknown;
2626 for (x = 0; archnames[x].name; x++) {
2627 if (v == archnames[x].value) {
2628 cp = archnames[x].name;
2629 break;
2630 }
2631 }
2632
2633 LOG_USER("%s", cp);
2634
2635 v = sam3_reg_fieldname(chip, "NVPTYP", chip->cfg.CHIPID_CIDR, 28, 3);
2636 LOG_USER("%s", nvptype[v]);
2637
2638 v = sam3_reg_fieldname(chip, "EXTID", chip->cfg.CHIPID_CIDR, 31, 1);
2639 LOG_USER("(exists: %s)", _yes_or_no(v));
2640 }
2641
2642 static void sam3_explain_ckgr_mcfr(struct sam3_chip *chip)
2643 {
2644 uint32_t v;
2645
2646 v = sam3_reg_fieldname(chip, "MAINFRDY", chip->cfg.CKGR_MCFR, 16, 1);
2647 LOG_USER("(main ready: %s)", _yes_or_no(v));
2648
2649 v = sam3_reg_fieldname(chip, "MAINF", chip->cfg.CKGR_MCFR, 0, 16);
2650
2651 v = (v * chip->cfg.slow_freq) / 16;
2652 chip->cfg.mainosc_freq = v;
2653
2654 LOG_USER("(%3.03f Mhz (%" PRIu32 ".%03" PRIu32 "khz slowclk)",
2655 _tomhz(v),
2656 (uint32_t)(chip->cfg.slow_freq / 1000),
2657 (uint32_t)(chip->cfg.slow_freq % 1000));
2658 }
2659
2660 static void sam3_explain_ckgr_plla(struct sam3_chip *chip)
2661 {
2662 uint32_t mula, diva;
2663
2664 diva = sam3_reg_fieldname(chip, "DIVA", chip->cfg.CKGR_PLLAR, 0, 8);
2665 LOG_USER_N("\n");
2666 mula = sam3_reg_fieldname(chip, "MULA", chip->cfg.CKGR_PLLAR, 16, 11);
2667 LOG_USER_N("\n");
2668 chip->cfg.plla_freq = 0;
2669 if (mula == 0)
2670 LOG_USER("\tPLLA Freq: (Disabled,mula = 0)");
2671 else if (diva == 0)
2672 LOG_USER("\tPLLA Freq: (Disabled,diva = 0)");
2673 else if (diva >= 1) {
2674 chip->cfg.plla_freq = (chip->cfg.mainosc_freq * (mula + 1) / diva);
2675 LOG_USER("\tPLLA Freq: %3.03f MHz",
2676 _tomhz(chip->cfg.plla_freq));
2677 }
2678 }
2679
2680 static void sam3_explain_mckr(struct sam3_chip *chip)
2681 {
2682 uint32_t css, pres, fin = 0;
2683 int pdiv = 0;
2684 const char *cp = NULL;
2685
2686 css = sam3_reg_fieldname(chip, "CSS", chip->cfg.PMC_MCKR, 0, 2);
2687 switch (css & 3) {
2688 case 0:
2689 fin = chip->cfg.slow_freq;
2690 cp = "slowclk";
2691 break;
2692 case 1:
2693 fin = chip->cfg.mainosc_freq;
2694 cp = "mainosc";
2695 break;
2696 case 2:
2697 fin = chip->cfg.plla_freq;
2698 cp = "plla";
2699 break;
2700 case 3:
2701 if (chip->cfg.CKGR_UCKR & (1 << 16)) {
2702 fin = 480 * 1000 * 1000;
2703 cp = "upll";
2704 } else {
2705 fin = 0;
2706 cp = "upll (*ERROR* UPLL is disabled)";
2707 }
2708 break;
2709 default:
2710 assert(0);
2711 break;
2712 }
2713
2714 LOG_USER("%s (%3.03f Mhz)",
2715 cp,
2716 _tomhz(fin));
2717 pres = sam3_reg_fieldname(chip, "PRES", chip->cfg.PMC_MCKR, 4, 3);
2718 switch (pres & 0x07) {
2719 case 0:
2720 pdiv = 1;
2721 cp = "selected clock";
2722 break;
2723 case 1:
2724 pdiv = 2;
2725 cp = "clock/2";
2726 break;
2727 case 2:
2728 pdiv = 4;
2729 cp = "clock/4";
2730 break;
2731 case 3:
2732 pdiv = 8;
2733 cp = "clock/8";
2734 break;
2735 case 4:
2736 pdiv = 16;
2737 cp = "clock/16";
2738 break;
2739 case 5:
2740 pdiv = 32;
2741 cp = "clock/32";
2742 break;
2743 case 6:
2744 pdiv = 64;
2745 cp = "clock/64";
2746 break;
2747 case 7:
2748 pdiv = 6;
2749 cp = "clock/6";
2750 break;
2751 default:
2752 assert(0);
2753 break;
2754 }
2755 LOG_USER("(%s)", cp);
2756 fin = fin / pdiv;
2757 /* sam3 has a *SINGLE* clock - */
2758 /* other at91 series parts have divisors for these. */
2759 chip->cfg.cpu_freq = fin;
2760 chip->cfg.mclk_freq = fin;
2761 chip->cfg.fclk_freq = fin;
2762 LOG_USER("\t\tResult CPU Freq: %3.03f",
2763 _tomhz(fin));
2764 }
2765
2766 #if 0
2767 static struct sam3_chip *target2sam3(struct target *target)
2768 {
2769 struct sam3_chip *chip;
2770
2771 if (!target)
2772 return NULL;
2773
2774 chip = all_sam3_chips;
2775 while (chip) {
2776 if (chip->target == target)
2777 break; /* return below */
2778 else
2779 chip = chip->next;
2780 }
2781 return chip;
2782 }
2783 #endif
2784
2785 static uint32_t *sam3_get_reg_ptr(struct sam3_cfg *cfg, const struct sam3_reg_list *list)
2786 {
2787 /* this function exists to help */
2788 /* keep funky offsetof() errors */
2789 /* and casting from causing bugs */
2790
2791 /* By using prototypes - we can detect what would */
2792 /* be casting errors. */
2793
2794 return (uint32_t *)(void *)(((char *)(cfg)) + list->struct_offset);
2795 }
2796
2797
2798 #define SAM3_ENTRY(NAME, FUNC) { .address = SAM3_ ## NAME, .struct_offset = offsetof( \
2799 struct sam3_cfg, \
2800 NAME), # NAME, FUNC }
2801 static const struct sam3_reg_list sam3_all_regs[] = {
2802 SAM3_ENTRY(CKGR_MOR, sam3_explain_ckgr_mor),
2803 SAM3_ENTRY(CKGR_MCFR, sam3_explain_ckgr_mcfr),
2804 SAM3_ENTRY(CKGR_PLLAR, sam3_explain_ckgr_plla),
2805 SAM3_ENTRY(CKGR_UCKR, NULL),
2806 SAM3_ENTRY(PMC_FSMR, NULL),
2807 SAM3_ENTRY(PMC_FSPR, NULL),
2808 SAM3_ENTRY(PMC_IMR, NULL),
2809 SAM3_ENTRY(PMC_MCKR, sam3_explain_mckr),
2810 SAM3_ENTRY(PMC_PCK0, NULL),
2811 SAM3_ENTRY(PMC_PCK1, NULL),
2812 SAM3_ENTRY(PMC_PCK2, NULL),
2813 SAM3_ENTRY(PMC_PCSR, NULL),
2814 SAM3_ENTRY(PMC_SCSR, NULL),
2815 SAM3_ENTRY(PMC_SR, NULL),
2816 SAM3_ENTRY(CHIPID_CIDR, sam3_explain_chipid_cidr),
2817 SAM3_ENTRY(CHIPID_CIDR2, sam3_explain_chipid_cidr),
2818 SAM3_ENTRY(CHIPID_EXID, NULL),
2819 SAM3_ENTRY(CHIPID_EXID2, NULL),
2820 /* TERMINATE THE LIST */
2821 { .name = NULL }
2822 };
2823 #undef SAM3_ENTRY
2824
2825 static struct sam3_bank_private *get_sam3_bank_private(struct flash_bank *bank)
2826 {
2827 return bank->driver_priv;
2828 }
2829
2830 /**
2831 * Given a pointer to where it goes in the structure,
2832 * determine the register name, address from the all registers table.
2833 */
2834 static const struct sam3_reg_list *sam3_get_reg(struct sam3_chip *chip, uint32_t *goes_here)
2835 {
2836 const struct sam3_reg_list *reg;
2837
2838 reg = &(sam3_all_regs[0]);
2839 while (reg->name) {
2840 uint32_t *possible;
2841
2842 /* calculate where this one go.. */
2843 /* it is "possibly" this register. */
2844
2845 possible = ((uint32_t *)(void *)(((char *)(&(chip->cfg))) + reg->struct_offset));
2846
2847 /* well? Is it this register */
2848 if (possible == goes_here) {
2849 /* Jump for joy! */
2850 return reg;
2851 }
2852
2853 /* next... */
2854 reg++;
2855 }
2856 /* This is *TOTAL*PANIC* - we are totally screwed. */
2857 LOG_ERROR("INVALID SAM3 REGISTER");
2858 return NULL;
2859 }
2860
2861 static int sam3_read_this_reg(struct sam3_chip *chip, uint32_t *goes_here)
2862 {
2863 const struct sam3_reg_list *reg;
2864 int r;
2865
2866 reg = sam3_get_reg(chip, goes_here);
2867 if (!reg)
2868 return ERROR_FAIL;
2869
2870 r = target_read_u32(chip->target, reg->address, goes_here);
2871 if (r != ERROR_OK) {
2872 LOG_ERROR("Cannot read SAM3 register: %s @ 0x%08x, Err: %d",
2873 reg->name, (unsigned)(reg->address), r);
2874 }
2875 return r;
2876 }
2877
2878 static int sam3_read_all_regs(struct sam3_chip *chip)
2879 {
2880 int r;
2881 const struct sam3_reg_list *reg;
2882
2883 reg = &(sam3_all_regs[0]);
2884 while (reg->name) {
2885 r = sam3_read_this_reg(chip,
2886 sam3_get_reg_ptr(&(chip->cfg), reg));
2887 if (r != ERROR_OK) {
2888 LOG_ERROR("Cannot read SAM3 register: %s @ 0x%08x, Error: %d",
2889 reg->name, ((unsigned)(reg->address)), r);
2890 return r;
2891 }
2892 reg++;
2893 }
2894
2895 /* Chip identification register
2896 *
2897 * Unfortunately, the chip identification register is not at
2898 * a constant address across all of the SAM3 series'. As a
2899 * consequence, a simple heuristic is used to find where it's
2900 * at...
2901 *
2902 * If the contents at the first address is zero, then we know
2903 * that the second address is where the chip id register is.
2904 * We can deduce this because for those SAM's that have the
2905 * chip id @ 0x400e0940, the first address, 0x400e0740, is
2906 * located in the memory map of the Power Management Controller
2907 * (PMC). Furthermore, the address is not used by the PMC.
2908 * So when read, the memory controller returns zero.*/
2909 if (chip->cfg.CHIPID_CIDR == 0) {
2910 /*Put the correct CIDR and EXID values in the chip structure */
2911 chip->cfg.CHIPID_CIDR = chip->cfg.CHIPID_CIDR2;
2912 chip->cfg.CHIPID_EXID = chip->cfg.CHIPID_EXID2;
2913 }
2914 return ERROR_OK;
2915 }
2916
2917 static int sam3_get_info(struct sam3_chip *chip)
2918 {
2919 const struct sam3_reg_list *reg;
2920 uint32_t regval;
2921
2922 reg = &(sam3_all_regs[0]);
2923 while (reg->name) {
2924 /* display all regs */
2925 LOG_DEBUG("Start: %s", reg->name);
2926 regval = *sam3_get_reg_ptr(&(chip->cfg), reg);
2927 LOG_USER("%*s: [0x%08" PRIx32 "] -> 0x%08" PRIx32,
2928 REG_NAME_WIDTH,
2929 reg->name,
2930 reg->address,
2931 regval);
2932 if (reg->explain_func)
2933 (*(reg->explain_func))(chip);
2934 LOG_DEBUG("End: %s", reg->name);
2935 reg++;
2936 }
2937 LOG_USER(" rc-osc: %3.03f MHz", _tomhz(chip->cfg.rc_freq));
2938 LOG_USER(" mainosc: %3.03f MHz", _tomhz(chip->cfg.mainosc_freq));
2939 LOG_USER(" plla: %3.03f MHz", _tomhz(chip->cfg.plla_freq));
2940 LOG_USER(" cpu-freq: %3.03f MHz", _tomhz(chip->cfg.cpu_freq));
2941 LOG_USER("mclk-freq: %3.03f MHz", _tomhz(chip->cfg.mclk_freq));
2942
2943 LOG_USER(" UniqueId: 0x%08" PRIx32 " 0x%08" PRIx32 " 0x%08" PRIx32 " 0x%08" PRIx32,
2944 chip->cfg.unique_id[0],
2945 chip->cfg.unique_id[1],
2946 chip->cfg.unique_id[2],
2947 chip->cfg.unique_id[3]);
2948
2949 return ERROR_OK;
2950 }
2951
2952 static int sam3_protect_check(struct flash_bank *bank)
2953 {
2954 int r;
2955 uint32_t v = 0;
2956 unsigned x;
2957 struct sam3_bank_private *private;
2958
2959 LOG_DEBUG("Begin");
2960 if (bank->target->state != TARGET_HALTED) {
2961 LOG_ERROR("Target not halted");
2962 return ERROR_TARGET_NOT_HALTED;
2963 }
2964
2965 private = get_sam3_bank_private(bank);
2966 if (!private) {
2967 LOG_ERROR("no private for this bank?");
2968 return ERROR_FAIL;
2969 }
2970 if (!(private->probed))
2971 return ERROR_FLASH_BANK_NOT_PROBED;
2972
2973 r = flashd_get_lock_bits(private, &v);
2974 if (r != ERROR_OK) {
2975 LOG_DEBUG("Failed: %d", r);
2976 return r;
2977 }
2978
2979 for (x = 0; x < private->nsectors; x++)
2980 bank->sectors[x].is_protected = (!!(v & (1 << x)));
2981 LOG_DEBUG("Done");
2982 return ERROR_OK;
2983 }
2984
2985 FLASH_BANK_COMMAND_HANDLER(sam3_flash_bank_command)
2986 {
2987 struct sam3_chip *chip;
2988
2989 chip = all_sam3_chips;
2990
2991 /* is this an existing chip? */
2992 while (chip) {
2993 if (chip->target == bank->target)
2994 break;
2995 chip = chip->next;
2996 }
2997
2998 if (!chip) {
2999 /* this is a *NEW* chip */
3000 chip = calloc(1, sizeof(struct sam3_chip));
3001 if (!chip) {
3002 LOG_ERROR("NO RAM!");
3003 return ERROR_FAIL;
3004 }
3005 chip->target = bank->target;
3006 /* insert at head */
3007 chip->next = all_sam3_chips;
3008 all_sam3_chips = chip;
3009 chip->target = bank->target;
3010 /* assumption is this runs at 32khz */
3011 chip->cfg.slow_freq = 32768;
3012 chip->probed = false;
3013 }
3014
3015 switch (bank->base) {
3016 default:
3017 LOG_ERROR("Address 0x%08x invalid bank address (try 0x%08x or 0x%08x "
3018 "[at91sam3u series] or 0x%08x [at91sam3s series] or "
3019 "0x%08x [at91sam3n series] or 0x%08x or 0x%08x or 0x%08x[at91sam3ax series] )",
3020 ((unsigned int)(bank->base)),
3021 ((unsigned int)(FLASH_BANK0_BASE_U)),
3022 ((unsigned int)(FLASH_BANK1_BASE_U)),
3023 ((unsigned int)(FLASH_BANK_BASE_S)),
3024 ((unsigned int)(FLASH_BANK_BASE_N)),
3025 ((unsigned int)(FLASH_BANK0_BASE_AX)),
3026 ((unsigned int)(FLASH_BANK1_BASE_256K_AX)),
3027 ((unsigned int)(FLASH_BANK1_BASE_512K_AX)));
3028 return ERROR_FAIL;
3029
3030 /* at91sam3s and at91sam3n series only has bank 0*/
3031 /* at91sam3u and at91sam3ax series has the same address for bank 0*/
3032 case FLASH_BANK_BASE_S:
3033 case FLASH_BANK0_BASE_U:
3034 bank->driver_priv = &(chip->details.bank[0]);
3035 bank->bank_number = 0;
3036 chip->details.bank[0].chip = chip;
3037 chip->details.bank[0].bank = bank;
3038 break;
3039
3040 /* Bank 1 of at91sam3u or at91sam3ax series */
3041 case FLASH_BANK1_BASE_U:
3042 case FLASH_BANK1_BASE_256K_AX:
3043 case FLASH_BANK1_BASE_512K_AX:
3044 bank->driver_priv = &(chip->details.bank[1]);
3045 bank->bank_number = 1;
3046 chip->details.bank[1].chip = chip;
3047 chip->details.bank[1].bank = bank;
3048 break;
3049 }
3050
3051 /* we initialize after probing. */
3052 return ERROR_OK;
3053 }
3054
3055 /**
3056 * Remove all chips from the internal list without distinguishing which one
3057 * is owned by this bank. This simplification works only for one shot
3058 * deallocation like current flash_free_all_banks()
3059 */
3060 static void sam3_free_driver_priv(struct flash_bank *bank)
3061 {
3062 struct sam3_chip *chip = all_sam3_chips;
3063 while (chip) {
3064 struct sam3_chip *next = chip->next;
3065 free(chip);
3066 chip = next;
3067 }
3068 all_sam3_chips = NULL;
3069 }
3070
3071 static int sam3_get_details(struct sam3_bank_private *private)
3072 {
3073 const struct sam3_chip_details *details;
3074 struct sam3_chip *chip;
3075 struct flash_bank *saved_banks[SAM3_MAX_FLASH_BANKS];
3076 unsigned x;
3077
3078 LOG_DEBUG("Begin");
3079 details = all_sam3_details;
3080 while (details->name) {
3081 /* Compare cidr without version bits */
3082 if (((details->chipid_cidr ^ private->chip->cfg.CHIPID_CIDR) & 0xFFFFFFE0) == 0)
3083 break;
3084 else
3085 details++;
3086 }
3087 if (!details->name) {
3088 LOG_ERROR("SAM3 ChipID 0x%08x not found in table (perhaps you can ID this chip?)",
3089 (unsigned int)(private->chip->cfg.CHIPID_CIDR));
3090 /* Help the victim, print details about the chip */
3091 LOG_INFO("SAM3 CHIPID_CIDR: 0x%08" PRIx32 " decodes as follows",
3092 private->chip->cfg.CHIPID_CIDR);
3093 sam3_explain_chipid_cidr(private->chip);
3094 return ERROR_FAIL;
3095 }
3096
3097 /* DANGER: THERE ARE DRAGONS HERE */
3098
3099 /* get our chip - it is going */
3100 /* to be over-written shortly */
3101 chip = private->chip;
3102
3103 /* Note that, in reality: */
3104 /* */
3105 /* private = &(chip->details.bank[0]) */
3106 /* or private = &(chip->details.bank[1]) */
3107 /* */
3108
3109 /* save the "bank" pointers */
3110 for (x = 0; x < SAM3_MAX_FLASH_BANKS; x++)
3111 saved_banks[x] = chip->details.bank[x].bank;
3112
3113 /* Overwrite the "details" structure. */
3114 memcpy(&(private->chip->details),
3115 details,
3116 sizeof(private->chip->details));
3117
3118 /* now fix the ghosted pointers */
3119 for (x = 0; x < SAM3_MAX_FLASH_BANKS; x++) {
3120 chip->details.bank[x].chip = chip;
3121 chip->details.bank[x].bank = saved_banks[x];
3122 }
3123
3124 /* update the *BANK*SIZE* */
3125
3126 LOG_DEBUG("End");
3127 return ERROR_OK;
3128 }
3129
3130 static int _sam3_probe(struct flash_bank *bank, int noise)
3131 {
3132 int r;
3133 struct sam3_bank_private *private;
3134
3135
3136 LOG_DEBUG("Begin: Bank: %u, Noise: %d", bank->bank_number, noise);
3137 if (bank->target->state != TARGET_HALTED) {
3138 LOG_ERROR("Target not halted");
3139 return ERROR_TARGET_NOT_HALTED;
3140 }
3141
3142 private = get_sam3_bank_private(bank);
3143 if (!private) {
3144 LOG_ERROR("Invalid/unknown bank number");
3145 return ERROR_FAIL;
3146 }
3147
3148 r = sam3_read_all_regs(private->chip);
3149 if (r != ERROR_OK)
3150 return r;
3151
3152 LOG_DEBUG("Here");
3153 if (private->chip->probed)
3154 r = sam3_get_info(private->chip);
3155 else
3156 r = sam3_get_details(private);
3157 if (r != ERROR_OK)
3158 return r;
3159
3160 /* update the flash bank size */
3161 for (unsigned int x = 0; x < SAM3_MAX_FLASH_BANKS; x++) {
3162 if (bank->base == private->chip->details.bank[x].base_address) {
3163 bank->size = private->chip->details.bank[x].size_bytes;
3164 break;
3165 }
3166 }
3167
3168 if (!bank->sectors) {
3169 bank->sectors = calloc(private->nsectors, (sizeof((bank->sectors)[0])));
3170 if (!bank->sectors) {
3171 LOG_ERROR("No memory!");
3172 return ERROR_FAIL;
3173 }
3174 bank->num_sectors = private->nsectors;
3175
3176 for (unsigned int x = 0; x < bank->num_sectors; x++) {
3177 bank->sectors[x].size = private->sector_size;
3178 bank->sectors[x].offset = x * (private->sector_size);
3179 /* mark as unknown */
3180 bank->sectors[x].is_erased = -1;
3181 bank->sectors[x].is_protected = -1;
3182 }
3183 }
3184
3185 private->probed = true;
3186
3187 r = sam3_protect_check(bank);
3188 if (r != ERROR_OK)
3189 return r;
3190
3191 LOG_DEBUG("Bank = %d, nbanks = %d",
3192 private->bank_number, private->chip->details.n_banks);
3193 if ((private->bank_number + 1) == private->chip->details.n_banks) {
3194 /* read unique id, */
3195 /* it appears to be associated with the *last* flash bank. */
3196 flashd_read_uid(private);
3197 }
3198
3199 return r;
3200 }
3201
3202 static int sam3_probe(struct flash_bank *bank)
3203 {
3204 return _sam3_probe(bank, 1);
3205 }
3206
3207 static int sam3_auto_probe(struct flash_bank *bank)
3208 {
3209 return _sam3_probe(bank, 0);
3210 }
3211
3212 static int sam3_erase(struct flash_bank *bank, unsigned int first,
3213 unsigned int last)
3214 {
3215 struct sam3_bank_private *private;
3216 int r;
3217
3218 LOG_DEBUG("Here");
3219 if (bank->target->state != TARGET_HALTED) {
3220 LOG_ERROR("Target not halted");
3221 return ERROR_TARGET_NOT_HALTED;
3222 }
3223
3224 r = sam3_auto_probe(bank);
3225 if (r != ERROR_OK) {
3226 LOG_DEBUG("Here,r=%d", r);
3227 return r;
3228 }
3229
3230 private = get_sam3_bank_private(bank);
3231 if (!(private->probed))
3232 return ERROR_FLASH_BANK_NOT_PROBED;
3233
3234 if ((first == 0) && ((last + 1) == private->nsectors)) {
3235 /* whole chip */
3236 LOG_DEBUG("Here");
3237 return flashd_erase_entire_bank(private);
3238 }
3239 LOG_INFO("sam3 auto-erases while programming (request ignored)");
3240 return ERROR_OK;
3241 }
3242
3243 static int sam3_protect(struct flash_bank *bank, int set, unsigned int first,
3244 unsigned int last)
3245 {
3246 struct sam3_bank_private *private;
3247 int r;
3248
3249 LOG_DEBUG("Here");
3250 if (bank->target->state != TARGET_HALTED) {
3251 LOG_ERROR("Target not halted");
3252 return ERROR_TARGET_NOT_HALTED;
3253 }
3254
3255 private = get_sam3_bank_private(bank);
3256 if (!(private->probed))
3257 return ERROR_FLASH_BANK_NOT_PROBED;
3258
3259 if (set)
3260 r = flashd_lock(private, first, last);
3261 else
3262 r = flashd_unlock(private, first, last);
3263 LOG_DEBUG("End: r=%d", r);
3264
3265 return r;
3266
3267 }
3268
3269 static int sam3_page_read(struct sam3_bank_private *private, unsigned pagenum, uint8_t *buf)
3270 {
3271 uint32_t adr;
3272 int r;
3273
3274 adr = pagenum * private->page_size;
3275 adr += private->base_address;
3276
3277 r = target_read_memory(private->chip->target,
3278 adr,
3279 4, /* THIS*MUST*BE* in 32bit values */
3280 private->page_size / 4,
3281 buf);
3282 if (r != ERROR_OK)
3283 LOG_ERROR("SAM3: Flash program failed to read page phys address: 0x%08x",
3284 (unsigned int)(adr));
3285 return r;
3286 }
3287
3288 static int sam3_page_write(struct sam3_bank_private *private, unsigned pagenum, const uint8_t *buf)
3289 {
3290 uint32_t adr;
3291 uint32_t status;
3292 uint32_t fmr; /* EEFC Flash Mode Register */
3293 int r;
3294
3295 adr = pagenum * private->page_size;
3296 adr += private->base_address;
3297
3298 /* Get flash mode register value */
3299 r = target_read_u32(private->chip->target, private->controller_address, &fmr);
3300 if (r != ERROR_OK)
3301 LOG_DEBUG("Error Read failed: read flash mode register");
3302
3303 /* Clear flash wait state field */
3304 fmr &= 0xfffff0ff;
3305
3306 /* set FWS (flash wait states) field in the FMR (flash mode register) */
3307 fmr |= (private->flash_wait_states << 8);
3308
3309 LOG_DEBUG("Flash Mode: 0x%08x", ((unsigned int)(fmr)));
3310 r = target_write_u32(private->bank->target, private->controller_address, fmr);
3311 if (r != ERROR_OK)
3312 LOG_DEBUG("Error Write failed: set flash mode register");
3313
3314 LOG_DEBUG("Wr Page %u @ phys address: 0x%08x", pagenum, (unsigned int)(adr));
3315 r = target_write_memory(private->chip->target,
3316 adr,
3317 4, /* THIS*MUST*BE* in 32bit values */
3318 private->page_size / 4,
3319 buf);
3320 if (r != ERROR_OK) {
3321 LOG_ERROR("SAM3: Failed to write (buffer) page at phys address 0x%08x",
3322 (unsigned int)(adr));
3323 return r;
3324 }
3325
3326 r = efc_perform_command(private,
3327 /* send Erase & Write Page */
3328 AT91C_EFC_FCMD_EWP,
3329 pagenum,
3330 &status);
3331
3332 if (r != ERROR_OK)
3333 LOG_ERROR("SAM3: Error performing Erase & Write page @ phys address 0x%08x",
3334 (unsigned int)(adr));
3335 if (status & (1 << 2)) {
3336 LOG_ERROR("SAM3: Page @ Phys address 0x%08x is locked", (unsigned int)(adr));
3337 return ERROR_FAIL;
3338 }
3339 if (status & (1 << 1)) {
3340 LOG_ERROR("SAM3: Flash Command error @phys address 0x%08x", (unsigned int)(adr));
3341 return ERROR_FAIL;
3342 }
3343 return ERROR_OK;
3344 }
3345
3346 static int sam3_write(struct flash_bank *bank,
3347 const uint8_t *buffer,
3348 uint32_t offset,
3349 uint32_t count)
3350 {
3351 int n;
3352 unsigned page_cur;
3353 unsigned page_end;
3354 int r;
3355 unsigned page_offset;
3356 struct sam3_bank_private *private;
3357 uint8_t *pagebuffer;
3358
3359 /* in case we bail further below, set this to null */
3360 pagebuffer = NULL;
3361
3362 /* ignore dumb requests */
3363 if (count == 0) {
3364 r = ERROR_OK;
3365 goto done;
3366 }
3367
3368 if (bank->target->state != TARGET_HALTED) {
3369 LOG_ERROR("Target not halted");
3370 r = ERROR_TARGET_NOT_HALTED;
3371 goto done;
3372 }
3373
3374 private = get_sam3_bank_private(bank);
3375 if (!(private->probed)) {
3376 r = ERROR_FLASH_BANK_NOT_PROBED;
3377 goto done;
3378 }
3379
3380 if ((offset + count) > private->size_bytes) {
3381 LOG_ERROR("Flash write error - past end of bank");
3382 LOG_ERROR(" offset: 0x%08x, count 0x%08x, BankEnd: 0x%08x",
3383 (unsigned int)(offset),
3384 (unsigned int)(count),
3385 (unsigned int)(private->size_bytes));
3386 r = ERROR_FAIL;
3387 goto done;
3388 }
3389
3390 pagebuffer = malloc(private->page_size);
3391 if (!pagebuffer) {
3392 LOG_ERROR("No memory for %d Byte page buffer", (int)(private->page_size));
3393 r = ERROR_FAIL;
3394 goto done;
3395 }
3396
3397 /* what page do we start & end in? */
3398 page_cur = offset / private->page_size;
3399 page_end = (offset + count - 1) / private->page_size;
3400
3401 LOG_DEBUG("Offset: 0x%08x, Count: 0x%08x", (unsigned int)(offset), (unsigned int)(count));
3402 LOG_DEBUG("Page start: %d, Page End: %d", (int)(page_cur), (int)(page_end));
3403
3404 /* Special case: all one page */
3405 /* */
3406 /* Otherwise: */
3407 /* (1) non-aligned start */
3408 /* (2) body pages */
3409 /* (3) non-aligned end. */
3410
3411 /* Handle special case - all one page. */
3412 if (page_cur == page_end) {
3413 LOG_DEBUG("Special case, all in one page");
3414 r = sam3_page_read(private, page_cur, pagebuffer);
3415 if (r != ERROR_OK)
3416 goto done;
3417
3418 page_offset = (offset & (private->page_size-1));
3419 memcpy(pagebuffer + page_offset,
3420 buffer,
3421 count);
3422
3423 r = sam3_page_write(private, page_cur, pagebuffer);
3424 if (r != ERROR_OK)
3425 goto done;
3426 r = ERROR_OK;
3427 goto done;
3428 }
3429
3430 /* non-aligned start */
3431 page_offset = offset & (private->page_size - 1);
3432 if (page_offset) {
3433 LOG_DEBUG("Not-Aligned start");
3434 /* read the partial */
3435 r = sam3_page_read(private, page_cur, pagebuffer);
3436 if (r != ERROR_OK)
3437 goto done;
3438
3439 /* over-write with new data */
3440 n = (private->page_size - page_offset);
3441 memcpy(pagebuffer + page_offset,
3442 buffer,
3443 n);
3444
3445 r = sam3_page_write(private, page_cur, pagebuffer);
3446 if (r != ERROR_OK)
3447 goto done;
3448
3449 count -= n;
3450 offset += n;
3451 buffer += n;
3452 page_cur++;
3453 }
3454
3455 /* By checking that offset is correct here, we also
3456 fix a clang warning */
3457 assert(offset % private->page_size == 0);
3458
3459 /* intermediate large pages */
3460 /* also - the final *terminal* */
3461 /* if that terminal page is a full page */
3462 LOG_DEBUG("Full Page Loop: cur=%d, end=%d, count = 0x%08x",
3463 (int)page_cur, (int)page_end, (unsigned int)(count));
3464
3465 while ((page_cur < page_end) &&
3466 (count >= private->page_size)) {
3467 r = sam3_page_write(private, page_cur, buffer);
3468 if (r != ERROR_OK)
3469 goto done;
3470 count -= private->page_size;
3471 buffer += private->page_size;
3472 page_cur += 1;
3473 }
3474
3475 /* terminal partial page? */
3476 if (count) {
3477 LOG_DEBUG("Terminal partial page, count = 0x%08x", (unsigned int)(count));
3478 /* we have a partial page */
3479 r = sam3_page_read(private, page_cur, pagebuffer);
3480 if (r != ERROR_OK)
3481 goto done;
3482 /* data goes at start */
3483 memcpy(pagebuffer, buffer, count);
3484 r = sam3_page_write(private, page_cur, pagebuffer);
3485 if (r != ERROR_OK)
3486 goto done;
3487 }
3488 LOG_DEBUG("Done!");
3489 r = ERROR_OK;
3490 done:
3491 free(pagebuffer);
3492 return r;
3493 }
3494
3495 COMMAND_HANDLER(sam3_handle_info_command)
3496 {
3497 struct sam3_chip *chip;
3498 chip = get_current_sam3(CMD);
3499 if (!chip)
3500 return ERROR_OK;
3501
3502 unsigned x;
3503 int r;
3504
3505 /* bank0 must exist before we can do anything */
3506 if (!chip->details.bank[0].bank) {
3507 x = 0;
3508 need_define:
3509 command_print(CMD,
3510 "Please define bank %d via command: flash bank %s ... ",
3511 x,
3512 at91sam3_flash.name);
3513 return ERROR_FAIL;
3514 }
3515
3516 /* if bank 0 is not probed, then probe it */
3517 if (!(chip->details.bank[0].probed)) {
3518 r = sam3_auto_probe(chip->details.bank[0].bank);
3519 if (r != ERROR_OK)
3520 return ERROR_FAIL;
3521 }
3522 /* above guarantees the "chip details" structure is valid */
3523 /* and thus, bank private areas are valid */
3524 /* and we have a SAM3 chip, what a concept! */
3525
3526 /* auto-probe other banks, 0 done above */
3527 for (x = 1; x < SAM3_MAX_FLASH_BANKS; x++) {
3528 /* skip banks not present */
3529 if (!(chip->details.bank[x].present))
3530 continue;
3531
3532 if (!chip->details.bank[x].bank)
3533 goto need_define;
3534
3535 if (chip->details.bank[x].probed)
3536 continue;
3537
3538 r = sam3_auto_probe(chip->details.bank[x].bank);
3539 if (r != ERROR_OK)
3540 return r;
3541 }
3542
3543 r = sam3_get_info(chip);
3544 if (r != ERROR_OK) {
3545 LOG_DEBUG("Sam3Info, Failed %d", r);
3546 return r;
3547 }
3548
3549 return ERROR_OK;
3550 }
3551
3552 COMMAND_HANDLER(sam3_handle_gpnvm_command)
3553 {
3554 unsigned x, v;
3555 int r, who;
3556 struct sam3_chip *chip;
3557
3558 chip = get_current_sam3(CMD);
3559 if (!chip)
3560 return ERROR_OK;
3561
3562 if (chip->target->state != TARGET_HALTED) {
3563 LOG_ERROR("sam3 - target not halted");
3564 return ERROR_TARGET_NOT_HALTED;
3565 }
3566
3567 if (!chip->details.bank[0].bank) {
3568 command_print(CMD, "Bank0 must be defined first via: flash bank %s ...",
3569 at91sam3_flash.name);
3570 return ERROR_FAIL;
3571 }
3572 if (!chip->details.bank[0].probed) {
3573 r = sam3_auto_probe(chip->details.bank[0].bank);
3574 if (r != ERROR_OK)
3575 return r;
3576 }
3577
3578 switch (CMD_ARGC) {
3579 default:
3580 return ERROR_COMMAND_SYNTAX_ERROR;
3581 case 0:
3582 goto showall;
3583 case 1:
3584 who = -1;
3585 break;
3586 case 2:
3587 if ((strcmp(CMD_ARGV[0], "show") == 0) && (strcmp(CMD_ARGV[1], "all") == 0))
3588 who = -1;
3589 else {
3590 uint32_t v32;
3591 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], v32);
3592 who = v32;
3593 }
3594 break;
3595 }
3596
3597 if (strcmp("show", CMD_ARGV[0]) == 0) {
3598 if (who == -1) {
3599 showall:
3600 r = ERROR_OK;
3601 for (x = 0; x < chip->details.n_gpnvms; x++) {
3602 r = flashd_get_gpnvm(&(chip->details.bank[0]), x, &v);
3603 if (r != ERROR_OK)
3604 break;
3605 command_print(CMD, "sam3-gpnvm%u: %u", x, v);
3606 }
3607 return r;
3608 }
3609 if ((who >= 0) && (((unsigned)(who)) < chip->details.n_gpnvms)) {
3610 r = flashd_get_gpnvm(&(chip->details.bank[0]), who, &v);
3611 if (r == ERROR_OK)
3612 command_print(CMD, "sam3-gpnvm%u: %u", who, v);
3613 return r;
3614 } else {
3615 command_print(CMD, "sam3-gpnvm invalid GPNVM: %u", who);
3616 return ERROR_COMMAND_SYNTAX_ERROR;
3617 }
3618 }
3619
3620 if (who == -1) {
3621 command_print(CMD, "Missing GPNVM number");
3622 return ERROR_COMMAND_SYNTAX_ERROR;
3623 }
3624
3625 if (strcmp("set", CMD_ARGV[0]) == 0)
3626 r = flashd_set_gpnvm(&(chip->details.bank[0]), who);
3627 else if ((strcmp("clr", CMD_ARGV[0]) == 0) ||
3628 (strcmp("clear", CMD_ARGV[0]) == 0)) /* quietly accept both */
3629 r = flashd_clr_gpnvm(&(chip->details.bank[0]), who);
3630 else {
3631 command_print(CMD, "Unknown command: %s", CMD_ARGV[0]);
3632 r = ERROR_COMMAND_SYNTAX_ERROR;
3633 }
3634 return r;
3635 }
3636
3637 COMMAND_HANDLER(sam3_handle_slowclk_command)
3638 {
3639 struct sam3_chip *chip;
3640
3641 chip = get_current_sam3(CMD);
3642 if (!chip)
3643 return ERROR_OK;
3644
3645 switch (CMD_ARGC) {
3646 case 0:
3647 /* show */
3648 break;
3649 case 1:
3650 {
3651 /* set */
3652 uint32_t v;
3653 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], v);
3654 if (v > 200000) {
3655 /* absurd slow clock of 200Khz? */
3656 command_print(CMD, "Absurd/illegal slow clock freq: %d\n", (int)(v));
3657 return ERROR_COMMAND_SYNTAX_ERROR;
3658 }
3659 chip->cfg.slow_freq = v;
3660 break;
3661 }
3662 default:
3663 /* error */
3664 command_print(CMD, "Too many parameters");
3665 return ERROR_COMMAND_SYNTAX_ERROR;
3666 }
3667 command_print(CMD, "Slowclk freq: %d.%03dkhz",
3668 (int)(chip->cfg.slow_freq / 1000),
3669 (int)(chip->cfg.slow_freq % 1000));
3670 return ERROR_OK;
3671 }
3672
3673 static const struct command_registration at91sam3_exec_command_handlers[] = {
3674 {
3675 .name = "gpnvm",
3676 .handler = sam3_handle_gpnvm_command,
3677 .mode = COMMAND_EXEC,
3678 .usage = "[('clr'|'set'|'show') bitnum]",
3679 .help = "Without arguments, shows all bits in the gpnvm "
3680 "register. Otherwise, clears, sets, or shows one "
3681 "General Purpose Non-Volatile Memory (gpnvm) bit.",
3682 },
3683 {
3684 .name = "info",
3685 .handler = sam3_handle_info_command,
3686 .mode = COMMAND_EXEC,
3687 .help = "Print information about the current at91sam3 chip "
3688 "and its flash configuration.",
3689 .usage = "",
3690 },
3691 {
3692 .name = "slowclk",
3693 .handler = sam3_handle_slowclk_command,
3694 .mode = COMMAND_EXEC,
3695 .usage = "[clock_hz]",
3696 .help = "Display or set the slowclock frequency "
3697 "(default 32768 Hz).",
3698 },
3699 COMMAND_REGISTRATION_DONE
3700 };
3701 static const struct command_registration at91sam3_command_handlers[] = {
3702 {
3703 .name = "at91sam3",
3704 .mode = COMMAND_ANY,
3705 .help = "at91sam3 flash command group",
3706 .usage = "",
3707 .chain = at91sam3_exec_command_handlers,
3708 },
3709 COMMAND_REGISTRATION_DONE
3710 };
3711
3712 const struct flash_driver at91sam3_flash = {
3713 .name = "at91sam3",
3714 .commands = at91sam3_command_handlers,
3715 .flash_bank_command = sam3_flash_bank_command,
3716 .erase = sam3_erase,
3717 .protect = sam3_protect,
3718 .write = sam3_write,
3719 .read = default_flash_read,
3720 .probe = sam3_probe,
3721 .auto_probe = sam3_auto_probe,
3722 .erase_check = default_flash_blank_check,
3723 .protect_check = sam3_protect_check,
3724 .free_driver_priv = sam3_free_driver_priv,
3725 };
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