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jtag: linuxgpiod: drop extra parenthesis
[openocd.git] / src / flash / nor / at91sam4.c
1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-Source-Code)
2
3 /*
4 * Copyright (C) 2009 by Duane Ellis <openocd@duaneellis.com>
5 *
6 * at91sam3s* support
7 * Copyright (C) 2010 by Olaf Lüke <olaf@uni-paderborn.de>
8 *
9 * at91sam3x* & at91sam4 support
10 * Copyright (C) 2011 by Olivier Schonken, Jim Norris
11 *
12 * Some of the lower level code was based on code supplied by
13 * ATMEL under BSD-Source-Code License and this copyright.
14 * ATMEL Microcontroller Software Support
15 * Copyright (c) 2009, Atmel Corporation. All rights reserved.
16 */
17
18 #ifdef HAVE_CONFIG_H
19 #include "config.h"
20 #endif
21
22 #include "imp.h"
23 #include <helper/time_support.h>
24
25 #define REG_NAME_WIDTH (12)
26
27 /* at91sam4s/at91sam4e/at91sam4c series (has always one flash bank)*/
28 #define FLASH_BANK_BASE_S 0x00400000
29 #define FLASH_BANK_BASE_C 0x01000000
30
31 /* at91sam4sd series (two one flash banks), first bank address */
32 #define FLASH_BANK0_BASE_SD FLASH_BANK_BASE_S
33 /* at91sam4sd16x, second bank address */
34 #define FLASH_BANK1_BASE_1024K_SD (FLASH_BANK0_BASE_SD+(1024*1024/2))
35 /* at91sam4sd32x, second bank address */
36 #define FLASH_BANK1_BASE_2048K_SD (FLASH_BANK0_BASE_SD+(2048*1024/2))
37
38 /* at91sam4c32x, first and second bank address */
39 #define FLASH_BANK0_BASE_C32 FLASH_BANK_BASE_C
40 #define FLASH_BANK1_BASE_C32 (FLASH_BANK_BASE_C+(2048*1024/2))
41
42 #define AT91C_EFC_FCMD_GETD (0x0) /* (EFC) Get Flash Descriptor */
43 #define AT91C_EFC_FCMD_WP (0x1) /* (EFC) Write Page */
44 #define AT91C_EFC_FCMD_WPL (0x2) /* (EFC) Write Page and Lock */
45 #define AT91C_EFC_FCMD_EWP (0x3) /* (EFC) Erase Page and Write Page */
46 #define AT91C_EFC_FCMD_EWPL (0x4) /* (EFC) Erase Page and Write Page then Lock */
47 #define AT91C_EFC_FCMD_EA (0x5) /* (EFC) Erase All */
48 /* cmd6 is not present in the at91sam4u4/2/1 data sheet table 19-2 */
49 /* #define AT91C_EFC_FCMD_EPL (0x6) // (EFC) Erase plane? */
50 #define AT91C_EFC_FCMD_EPA (0x7) /* (EFC) Erase pages */
51 #define AT91C_EFC_FCMD_SLB (0x8) /* (EFC) Set Lock Bit */
52 #define AT91C_EFC_FCMD_CLB (0x9) /* (EFC) Clear Lock Bit */
53 #define AT91C_EFC_FCMD_GLB (0xA) /* (EFC) Get Lock Bit */
54 #define AT91C_EFC_FCMD_SFB (0xB) /* (EFC) Set Fuse Bit */
55 #define AT91C_EFC_FCMD_CFB (0xC) /* (EFC) Clear Fuse Bit */
56 #define AT91C_EFC_FCMD_GFB (0xD) /* (EFC) Get Fuse Bit */
57 #define AT91C_EFC_FCMD_STUI (0xE) /* (EFC) Start Read Unique ID */
58 #define AT91C_EFC_FCMD_SPUI (0xF) /* (EFC) Stop Read Unique ID */
59
60 #define OFFSET_EFC_FMR 0
61 #define OFFSET_EFC_FCR 4
62 #define OFFSET_EFC_FSR 8
63 #define OFFSET_EFC_FRR 12
64
65 static float _tomhz(uint32_t freq_hz)
66 {
67 float f;
68
69 f = ((float)(freq_hz)) / 1000000.0;
70 return f;
71 }
72
73 /* How the chip is configured. */
74 struct sam4_cfg {
75 uint32_t unique_id[4];
76
77 uint32_t slow_freq;
78 uint32_t rc_freq;
79 uint32_t mainosc_freq;
80 uint32_t plla_freq;
81 uint32_t mclk_freq;
82 uint32_t cpu_freq;
83 uint32_t fclk_freq;
84 uint32_t pclk0_freq;
85 uint32_t pclk1_freq;
86 uint32_t pclk2_freq;
87
88
89 #define SAM4_CHIPID_CIDR (0x400E0740)
90 uint32_t CHIPID_CIDR;
91 #define SAM4_CHIPID_EXID (0x400E0744)
92 uint32_t CHIPID_EXID;
93
94 #define SAM4_PMC_BASE (0x400E0400)
95 #define SAM4_PMC_SCSR (SAM4_PMC_BASE + 0x0008)
96 uint32_t PMC_SCSR;
97 #define SAM4_PMC_PCSR (SAM4_PMC_BASE + 0x0018)
98 uint32_t PMC_PCSR;
99 #define SAM4_CKGR_UCKR (SAM4_PMC_BASE + 0x001c)
100 uint32_t CKGR_UCKR;
101 #define SAM4_CKGR_MOR (SAM4_PMC_BASE + 0x0020)
102 uint32_t CKGR_MOR;
103 #define SAM4_CKGR_MCFR (SAM4_PMC_BASE + 0x0024)
104 uint32_t CKGR_MCFR;
105 #define SAM4_CKGR_PLLAR (SAM4_PMC_BASE + 0x0028)
106 uint32_t CKGR_PLLAR;
107 #define SAM4_PMC_MCKR (SAM4_PMC_BASE + 0x0030)
108 uint32_t PMC_MCKR;
109 #define SAM4_PMC_PCK0 (SAM4_PMC_BASE + 0x0040)
110 uint32_t PMC_PCK0;
111 #define SAM4_PMC_PCK1 (SAM4_PMC_BASE + 0x0044)
112 uint32_t PMC_PCK1;
113 #define SAM4_PMC_PCK2 (SAM4_PMC_BASE + 0x0048)
114 uint32_t PMC_PCK2;
115 #define SAM4_PMC_SR (SAM4_PMC_BASE + 0x0068)
116 uint32_t PMC_SR;
117 #define SAM4_PMC_IMR (SAM4_PMC_BASE + 0x006c)
118 uint32_t PMC_IMR;
119 #define SAM4_PMC_FSMR (SAM4_PMC_BASE + 0x0070)
120 uint32_t PMC_FSMR;
121 #define SAM4_PMC_FSPR (SAM4_PMC_BASE + 0x0074)
122 uint32_t PMC_FSPR;
123 };
124
125 struct sam4_bank_private {
126 bool probed;
127 /* DANGER: THERE ARE DRAGONS HERE.. */
128 /* NOTE: If you add more 'ghost' pointers */
129 /* be aware that you must *manually* update */
130 /* these pointers in the function sam4_get_details() */
131 /* See the comment "Here there be dragons" */
132
133 /* so we can find the chip we belong to */
134 struct sam4_chip *chip;
135 /* so we can find the original bank pointer */
136 struct flash_bank *bank;
137 unsigned bank_number;
138 uint32_t controller_address;
139 uint32_t base_address;
140 uint32_t flash_wait_states;
141 bool present;
142 unsigned size_bytes;
143 unsigned nsectors;
144 unsigned sector_size;
145 unsigned page_size;
146 };
147
148 struct sam4_chip_details {
149 /* THERE ARE DRAGONS HERE.. */
150 /* note: If you add pointers here */
151 /* be careful about them as they */
152 /* may need to be updated inside */
153 /* the function: "sam4_get_details() */
154 /* which copy/overwrites the */
155 /* 'runtime' copy of this structure */
156 uint32_t chipid_cidr;
157 const char *name;
158
159 unsigned n_gpnvms;
160 #define SAM4_N_NVM_BITS 3
161 unsigned gpnvm[SAM4_N_NVM_BITS];
162 unsigned total_flash_size;
163 unsigned total_sram_size;
164 unsigned n_banks;
165 #define SAM4_MAX_FLASH_BANKS 2
166 /* these are "initialized" from the global const data */
167 struct sam4_bank_private bank[SAM4_MAX_FLASH_BANKS];
168 };
169
170 struct sam4_chip {
171 struct sam4_chip *next;
172 bool probed;
173
174 /* this is "initialized" from the global const structure */
175 struct sam4_chip_details details;
176 struct target *target;
177 struct sam4_cfg cfg;
178 };
179
180
181 struct sam4_reg_list {
182 uint32_t address; size_t struct_offset; const char *name;
183 void (*explain_func)(struct sam4_chip *chip);
184 };
185
186 static struct sam4_chip *all_sam4_chips;
187
188 static struct sam4_chip *get_current_sam4(struct command_invocation *cmd)
189 {
190 struct target *t;
191 static struct sam4_chip *p;
192
193 t = get_current_target(cmd->ctx);
194 if (!t) {
195 command_print_sameline(cmd, "No current target?\n");
196 return NULL;
197 }
198
199 p = all_sam4_chips;
200 if (!p) {
201 /* this should not happen */
202 /* the command is not registered until the chip is created? */
203 command_print_sameline(cmd, "No SAM4 chips exist?\n");
204 return NULL;
205 }
206
207 while (p) {
208 if (p->target == t)
209 return p;
210 p = p->next;
211 }
212 command_print_sameline(cmd, "Cannot find SAM4 chip?\n");
213 return NULL;
214 }
215
216 /*The actual sector size of the SAM4S flash memory is 65536 bytes. 16 sectors for a 1024KB device*/
217 /*The lockregions are 8KB per lock region, with a 1024KB device having 128 lock regions. */
218 /*For the best results, nsectors are thus set to the amount of lock regions, and the sector_size*/
219 /*set to the lock region size. Page erases are used to erase 8KB sections when programming*/
220
221 /* these are used to *initialize* the "chip->details" structure. */
222 static const struct sam4_chip_details all_sam4_details[] = {
223 /* Start at91sam4c* series */
224 /* at91sam4c32e - LQFP144 */
225 {
226 .chipid_cidr = 0xA66D0EE0,
227 .name = "at91sam4c32e",
228 .total_flash_size = 2024 * 1024,
229 .total_sram_size = 256 * 1024,
230 .n_gpnvms = 3,
231 .n_banks = 2,
232 /* .bank[0] = { */
233 {
234 {
235 .probed = false,
236 .chip = NULL,
237 .bank = NULL,
238 .bank_number = 0,
239 .base_address = FLASH_BANK0_BASE_C32,
240 .controller_address = 0x400e0a00,
241 .flash_wait_states = 5,
242 .present = true,
243 .size_bytes = 1024 * 1024,
244 .nsectors = 128,
245 .sector_size = 8192,
246 .page_size = 512,
247 },
248 /* .bank[1] = { */
249 {
250 .probed = false,
251 .chip = NULL,
252 .bank = NULL,
253 .bank_number = 1,
254 .base_address = FLASH_BANK1_BASE_C32,
255 .controller_address = 0x400e0c00,
256 .flash_wait_states = 5,
257 .present = true,
258 .size_bytes = 1024 * 1024,
259 .nsectors = 128,
260 .sector_size = 8192,
261 .page_size = 512,
262 },
263 },
264 },
265 /* at91sam4c32c - LQFP100 */
266 {
267 .chipid_cidr = 0xA64D0EE0,
268 .name = "at91sam4c32c",
269 .total_flash_size = 2024 * 1024,
270 .total_sram_size = 256 * 1024,
271 .n_gpnvms = 3,
272 .n_banks = 2,
273 /* .bank[0] = { */
274 {
275 {
276 .probed = false,
277 .chip = NULL,
278 .bank = NULL,
279 .bank_number = 0,
280 .base_address = FLASH_BANK0_BASE_C32,
281 .controller_address = 0x400e0a00,
282 .flash_wait_states = 5,
283 .present = true,
284 .size_bytes = 1024 * 1024,
285 .nsectors = 128,
286 .sector_size = 8192,
287 .page_size = 512,
288 },
289 /* .bank[1] = { */
290 {
291 .probed = false,
292 .chip = NULL,
293 .bank = NULL,
294 .bank_number = 1,
295 .base_address = FLASH_BANK1_BASE_C32,
296 .controller_address = 0x400e0c00,
297 .flash_wait_states = 5,
298 .present = true,
299 .size_bytes = 1024 * 1024,
300 .nsectors = 128,
301 .sector_size = 8192,
302 .page_size = 512,
303 },
304 },
305 },
306 /* at91sam4c16c - LQFP100 */
307 {
308 .chipid_cidr = 0xA64C0CE0,
309 .name = "at91sam4c16c",
310 .total_flash_size = 1024 * 1024,
311 .total_sram_size = 128 * 1024,
312 .n_gpnvms = 2,
313 .n_banks = 1,
314 {
315 /* .bank[0] = {*/
316 {
317 .probed = false,
318 .chip = NULL,
319 .bank = NULL,
320 .bank_number = 0,
321 .base_address = FLASH_BANK_BASE_C,
322 .controller_address = 0x400e0a00,
323 .flash_wait_states = 5,
324 .present = true,
325 .size_bytes = 1024 * 1024,
326 .nsectors = 128,
327 .sector_size = 8192,
328 .page_size = 512,
329 },
330 /* .bank[1] = {*/
331 {
332 .present = false,
333 .probed = false,
334 .bank_number = 1,
335
336 },
337 },
338 },
339 /* at91sam4c8c - LQFP100 */
340 {
341 .chipid_cidr = 0xA64C0AE0,
342 .name = "at91sam4c8c",
343 .total_flash_size = 512 * 1024,
344 .total_sram_size = 128 * 1024,
345 .n_gpnvms = 2,
346 .n_banks = 1,
347 {
348 /* .bank[0] = {*/
349 {
350 .probed = false,
351 .chip = NULL,
352 .bank = NULL,
353 .bank_number = 0,
354 .base_address = FLASH_BANK_BASE_C,
355 .controller_address = 0x400e0a00,
356 .flash_wait_states = 5,
357 .present = true,
358 .size_bytes = 512 * 1024,
359 .nsectors = 64,
360 .sector_size = 8192,
361 .page_size = 512,
362 },
363 /* .bank[1] = {*/
364 {
365 .present = false,
366 .probed = false,
367 .bank_number = 1,
368
369 },
370 },
371 },
372 /* at91sam4c4c (rev B) - LQFP100 */
373 {
374 .chipid_cidr = 0xA64C0CE5,
375 .name = "at91sam4c4c",
376 .total_flash_size = 256 * 1024,
377 .total_sram_size = 128 * 1024,
378 .n_gpnvms = 2,
379 .n_banks = 1,
380 {
381 /* .bank[0] = {*/
382 {
383 .probed = false,
384 .chip = NULL,
385 .bank = NULL,
386 .bank_number = 0,
387 .base_address = FLASH_BANK_BASE_C,
388 .controller_address = 0x400e0a00,
389 .flash_wait_states = 5,
390 .present = true,
391 .size_bytes = 256 * 1024,
392 .nsectors = 32,
393 .sector_size = 8192,
394 .page_size = 512,
395 },
396 /* .bank[1] = {*/
397 {
398 .present = false,
399 .probed = false,
400 .bank_number = 1,
401
402 },
403 },
404 },
405
406 /* Start at91sam4e* series */
407 /*atsam4e16e - LQFP144/LFBGA144*/
408 {
409 .chipid_cidr = 0xA3CC0CE0,
410 .name = "at91sam4e16e",
411 .total_flash_size = 1024 * 1024,
412 .total_sram_size = 128 * 1024,
413 .n_gpnvms = 2,
414 .n_banks = 1,
415 {
416 /* .bank[0] = {*/
417 {
418 .probed = false,
419 .chip = NULL,
420 .bank = NULL,
421 .bank_number = 0,
422 .base_address = FLASH_BANK_BASE_S,
423 .controller_address = 0x400e0a00,
424 .flash_wait_states = 5,
425 .present = true,
426 .size_bytes = 1024 * 1024,
427 .nsectors = 128,
428 .sector_size = 8192,
429 .page_size = 512,
430 },
431 /* .bank[1] = {*/
432 {
433 .present = false,
434 .probed = false,
435 .bank_number = 1,
436
437 },
438 },
439 },
440
441 /* Start at91sam4n* series */
442 /*atsam4n8a - LQFP48/QFN48*/
443 {
444 .chipid_cidr = 0x293B0AE0,
445 .name = "at91sam4n8a",
446 .total_flash_size = 512 * 1024,
447 .total_sram_size = 64 * 1024,
448 .n_gpnvms = 2,
449 .n_banks = 1,
450 {
451 /* .bank[0] = {*/
452 {
453 .probed = false,
454 .chip = NULL,
455 .bank = NULL,
456 .bank_number = 0,
457 .base_address = FLASH_BANK_BASE_S,
458 .controller_address = 0x400e0a00,
459 .flash_wait_states = 5,
460 .present = true,
461 .size_bytes = 512 * 1024,
462 .nsectors = 64,
463 .sector_size = 8192,
464 .page_size = 512,
465 },
466 /* .bank[1] = {*/
467 {
468 .present = false,
469 .probed = false,
470 .bank_number = 1,
471
472 },
473 },
474 },
475 /*atsam4n8b - LQFP64/QFN64*/
476 {
477 .chipid_cidr = 0x294B0AE0,
478 .name = "at91sam4n8b",
479 .total_flash_size = 512 * 1024,
480 .total_sram_size = 64 * 1024,
481 .n_gpnvms = 2,
482 .n_banks = 1,
483 {
484 /* .bank[0] = {*/
485 {
486 .probed = false,
487 .chip = NULL,
488 .bank = NULL,
489 .bank_number = 0,
490 .base_address = FLASH_BANK_BASE_S,
491 .controller_address = 0x400e0a00,
492 .flash_wait_states = 5,
493 .present = true,
494 .size_bytes = 512 * 1024,
495 .nsectors = 64,
496 .sector_size = 8192,
497 .page_size = 512,
498 },
499 /* .bank[1] = {*/
500 {
501 .present = false,
502 .probed = false,
503 .bank_number = 1,
504
505 },
506 },
507 },
508 /*atsam4n8c - LQFP100/TFBGA100/VFBGA100*/
509 {
510 .chipid_cidr = 0x295B0AE0,
511 .name = "at91sam4n8c",
512 .total_flash_size = 512 * 1024,
513 .total_sram_size = 64 * 1024,
514 .n_gpnvms = 2,
515 .n_banks = 1,
516 {
517 /* .bank[0] = {*/
518 {
519 .probed = false,
520 .chip = NULL,
521 .bank = NULL,
522 .bank_number = 0,
523 .base_address = FLASH_BANK_BASE_S,
524 .controller_address = 0x400e0a00,
525 .flash_wait_states = 5,
526 .present = true,
527 .size_bytes = 512 * 1024,
528 .nsectors = 64,
529 .sector_size = 8192,
530 .page_size = 512,
531 },
532 /* .bank[1] = {*/
533 {
534 .present = false,
535 .probed = false,
536 .bank_number = 1,
537
538 },
539 },
540 },
541 /*atsam4n16b - LQFP64/QFN64*/
542 {
543 .chipid_cidr = 0x29460CE0,
544 .name = "at91sam4n16b",
545 .total_flash_size = 1024 * 1024,
546 .total_sram_size = 80 * 1024,
547 .n_gpnvms = 2,
548 .n_banks = 1,
549 {
550 /* .bank[0] = {*/
551 {
552 .probed = false,
553 .chip = NULL,
554 .bank = NULL,
555 .bank_number = 0,
556 .base_address = FLASH_BANK_BASE_S,
557 .controller_address = 0x400e0a00,
558 .flash_wait_states = 5,
559 .present = true,
560 .size_bytes = 1024 * 1024,
561 .nsectors = 128,
562 .sector_size = 8192,
563 .page_size = 512,
564 },
565 /* .bank[1] = {*/
566 {
567 .present = false,
568 .probed = false,
569 .bank_number = 1,
570
571 },
572 },
573 },
574 /*atsam4n16c - LQFP100/TFBGA100/VFBGA100*/
575 {
576 .chipid_cidr = 0x29560CE0,
577 .name = "at91sam4n16c",
578 .total_flash_size = 1024 * 1024,
579 .total_sram_size = 80 * 1024,
580 .n_gpnvms = 2,
581 .n_banks = 1,
582 {
583 /* .bank[0] = {*/
584 {
585 .probed = false,
586 .chip = NULL,
587 .bank = NULL,
588 .bank_number = 0,
589 .base_address = FLASH_BANK_BASE_S,
590 .controller_address = 0x400e0a00,
591 .flash_wait_states = 5,
592 .present = true,
593 .size_bytes = 1024 * 1024,
594 .nsectors = 128,
595 .sector_size = 8192,
596 .page_size = 512,
597 },
598 /* .bank[1] = {*/
599 {
600 .present = false,
601 .probed = false,
602 .bank_number = 1,
603
604 },
605 },
606 },
607
608 /* Start at91sam4s* series */
609 /*atsam4s16c - LQFP100/BGA100*/
610 {
611 .chipid_cidr = 0x28AC0CE0,
612 .name = "at91sam4s16c",
613 .total_flash_size = 1024 * 1024,
614 .total_sram_size = 128 * 1024,
615 .n_gpnvms = 2,
616 .n_banks = 1,
617 {
618 /* .bank[0] = {*/
619 {
620 .probed = false,
621 .chip = NULL,
622 .bank = NULL,
623 .bank_number = 0,
624 .base_address = FLASH_BANK_BASE_S,
625 .controller_address = 0x400e0a00,
626 .flash_wait_states = 5,
627 .present = true,
628 .size_bytes = 1024 * 1024,
629 .nsectors = 128,
630 .sector_size = 8192,
631 .page_size = 512,
632 },
633 /* .bank[1] = {*/
634 {
635 .present = false,
636 .probed = false,
637 .bank_number = 1,
638
639 },
640 },
641 },
642 /*at91sam4sa16c - TFBGA100/VFBGA100/LQFP100*/
643 {
644 .chipid_cidr = 0x28a70ce0,
645 .name = "at91sam4sa16c",
646 .total_flash_size = 1024 * 1024,
647 .total_sram_size = 160 * 1024,
648 .n_gpnvms = 2,
649 .n_banks = 1,
650
651 /* .bank[0] = { */
652 {
653 {
654 .probed = false,
655 .chip = NULL,
656 .bank = NULL,
657 .bank_number = 0,
658 .base_address = FLASH_BANK_BASE_S,
659 .controller_address = 0x400e0a00,
660 .flash_wait_states = 5,
661 .present = true,
662 .size_bytes = 1024 * 1024,
663 .nsectors = 128,
664 .sector_size = 8192,
665 .page_size = 512,
666 },
667 /* .bank[1] = {*/
668 {
669 .present = false,
670 .probed = false,
671 .bank_number = 1,
672
673 },
674 },
675 },
676 /*atsam4s16b - LQFP64/QFN64/WLCSP64*/
677 {
678 .chipid_cidr = 0x289C0CE0,
679 .name = "at91sam4s16b",
680 .total_flash_size = 1024 * 1024,
681 .total_sram_size = 128 * 1024,
682 .n_gpnvms = 2,
683 .n_banks = 1,
684 {
685 /* .bank[0] = {*/
686 {
687 .probed = false,
688 .chip = NULL,
689 .bank = NULL,
690 .bank_number = 0,
691 .base_address = FLASH_BANK_BASE_S,
692 .controller_address = 0x400e0a00,
693 .flash_wait_states = 5,
694 .present = true,
695 .size_bytes = 1024 * 1024,
696 .nsectors = 128,
697 .sector_size = 8192,
698 .page_size = 512,
699 },
700 /* .bank[1] = {*/
701 {
702 .present = false,
703 .probed = false,
704 .bank_number = 1,
705
706 },
707 },
708 },
709 /*atsam4sa16b - LQFP64/QFN64*/
710 {
711 .chipid_cidr = 0x28970CE0,
712 .name = "at91sam4sa16b",
713 .total_flash_size = 1024 * 1024,
714 .total_sram_size = 160 * 1024,
715 .n_gpnvms = 2,
716 .n_banks = 1,
717 {
718 /* .bank[0] = {*/
719 {
720 .probed = false,
721 .chip = NULL,
722 .bank = NULL,
723 .bank_number = 0,
724 .base_address = FLASH_BANK_BASE_S,
725 .controller_address = 0x400e0a00,
726 .flash_wait_states = 5,
727 .present = true,
728 .size_bytes = 1024 * 1024,
729 .nsectors = 128,
730 .sector_size = 8192,
731 .page_size = 512,
732 },
733 /* .bank[1] = {*/
734 {
735 .present = false,
736 .probed = false,
737 .bank_number = 1,
738
739 },
740 },
741 },
742 /*atsam4s16a - LQFP48/QFN48*/
743 {
744 .chipid_cidr = 0x288C0CE0,
745 .name = "at91sam4s16a",
746 .total_flash_size = 1024 * 1024,
747 .total_sram_size = 128 * 1024,
748 .n_gpnvms = 2,
749 .n_banks = 1,
750 {
751 /* .bank[0] = {*/
752 {
753 .probed = false,
754 .chip = NULL,
755 .bank = NULL,
756 .bank_number = 0,
757 .base_address = FLASH_BANK_BASE_S,
758 .controller_address = 0x400e0a00,
759 .flash_wait_states = 5,
760 .present = true,
761 .size_bytes = 1024 * 1024,
762 .nsectors = 128,
763 .sector_size = 8192,
764 .page_size = 512,
765 },
766 /* .bank[1] = {*/
767 {
768 .present = false,
769 .probed = false,
770 .bank_number = 1,
771
772 },
773 },
774 },
775 /*atsam4s8c - LQFP100/BGA100*/
776 {
777 .chipid_cidr = 0x28AC0AE0,
778 .name = "at91sam4s8c",
779 .total_flash_size = 512 * 1024,
780 .total_sram_size = 128 * 1024,
781 .n_gpnvms = 2,
782 .n_banks = 1,
783 {
784 /* .bank[0] = {*/
785 {
786 .probed = false,
787 .chip = NULL,
788 .bank = NULL,
789 .bank_number = 0,
790 .base_address = FLASH_BANK_BASE_S,
791 .controller_address = 0x400e0a00,
792 .flash_wait_states = 5,
793 .present = true,
794 .size_bytes = 512 * 1024,
795 .nsectors = 64,
796 .sector_size = 8192,
797 .page_size = 512,
798 },
799 /* .bank[1] = {*/
800 {
801 .present = false,
802 .probed = false,
803 .bank_number = 1,
804
805 },
806 },
807 },
808 /*atsam4s8b - LQFP64/QFN64/WLCSP64*/
809 {
810 .chipid_cidr = 0x289C0AE0,
811 .name = "at91sam4s8b",
812 .total_flash_size = 512 * 1024,
813 .total_sram_size = 128 * 1024,
814 .n_gpnvms = 2,
815 .n_banks = 1,
816 {
817 /* .bank[0] = {*/
818 {
819 .probed = false,
820 .chip = NULL,
821 .bank = NULL,
822 .bank_number = 0,
823 .base_address = FLASH_BANK_BASE_S,
824 .controller_address = 0x400e0a00,
825 .flash_wait_states = 5,
826 .present = true,
827 .size_bytes = 512 * 1024,
828 .nsectors = 64,
829 .sector_size = 8192,
830 .page_size = 512,
831 },
832 /* .bank[1] = {*/
833 {
834 .present = false,
835 .probed = false,
836 .bank_number = 1,
837
838 },
839 },
840 },
841 /*atsam4s8a - LQFP48/BGA48*/
842 {
843 .chipid_cidr = 0x288C0AE0,
844 .name = "at91sam4s8a",
845 .total_flash_size = 512 * 1024,
846 .total_sram_size = 128 * 1024,
847 .n_gpnvms = 2,
848 .n_banks = 1,
849 {
850 /* .bank[0] = {*/
851 {
852 .probed = false,
853 .chip = NULL,
854 .bank = NULL,
855 .bank_number = 0,
856 .base_address = FLASH_BANK_BASE_S,
857 .controller_address = 0x400e0a00,
858 .flash_wait_states = 5,
859 .present = true,
860 .size_bytes = 512 * 1024,
861 .nsectors = 64,
862 .sector_size = 8192,
863 .page_size = 512,
864 },
865 /* .bank[1] = {*/
866 {
867 .present = false,
868 .probed = false,
869 .bank_number = 1,
870
871 },
872 },
873 },
874
875 /*atsam4s4c - LQFP100/BGA100*/
876 {
877 .chipid_cidr = 0x28ab09e0,
878 .name = "at91sam4s4c",
879 .total_flash_size = 256 * 1024,
880 .total_sram_size = 64 * 1024,
881 .n_gpnvms = 2,
882 .n_banks = 1,
883 {
884 /* .bank[0] = {*/
885 {
886 .probed = false,
887 .chip = NULL,
888 .bank = NULL,
889 .bank_number = 0,
890 .base_address = FLASH_BANK_BASE_S,
891 .controller_address = 0x400e0a00,
892 .flash_wait_states = 5,
893 .present = true,
894 .size_bytes = 256 * 1024,
895 .nsectors = 32,
896 .sector_size = 8192,
897 .page_size = 512,
898 },
899 /* .bank[1] = {*/
900 {
901 .present = false,
902 .probed = false,
903 .bank_number = 1,
904
905 },
906 },
907 },
908
909 /*atsam4s4b - LQFP64/QFN64/WLCSP64*/
910 {
911 .chipid_cidr = 0x289b09e0,
912 .name = "at91sam4s4b",
913 .total_flash_size = 256 * 1024,
914 .total_sram_size = 64 * 1024,
915 .n_gpnvms = 2,
916 .n_banks = 1,
917 {
918 /* .bank[0] = {*/
919 {
920 .probed = false,
921 .chip = NULL,
922 .bank = NULL,
923 .bank_number = 0,
924 .base_address = FLASH_BANK_BASE_S,
925 .controller_address = 0x400e0a00,
926 .flash_wait_states = 5,
927 .present = true,
928 .size_bytes = 256 * 1024,
929 .nsectors = 32,
930 .sector_size = 8192,
931 .page_size = 512,
932 },
933 /* .bank[1] = {*/
934 {
935 .present = false,
936 .probed = false,
937 .bank_number = 1,
938
939 },
940 },
941 },
942
943 /*atsam4s4a - LQFP48/QFN48*/
944 {
945 .chipid_cidr = 0x288b09e0,
946 .name = "at91sam4s4a",
947 .total_flash_size = 256 * 1024,
948 .total_sram_size = 64 * 1024,
949 .n_gpnvms = 2,
950 .n_banks = 1,
951 {
952 /* .bank[0] = {*/
953 {
954 .probed = false,
955 .chip = NULL,
956 .bank = NULL,
957 .bank_number = 0,
958 .base_address = FLASH_BANK_BASE_S,
959 .controller_address = 0x400e0a00,
960 .flash_wait_states = 5,
961 .present = true,
962 .size_bytes = 256 * 1024,
963 .nsectors = 32,
964 .sector_size = 8192,
965 .page_size = 512,
966 },
967 /* .bank[1] = {*/
968 {
969 .present = false,
970 .probed = false,
971 .bank_number = 1,
972
973 },
974 },
975 },
976
977 /*atsam4s2c - LQFP100/BGA100*/
978 {
979 .chipid_cidr = 0x28ab07e0,
980 .name = "at91sam4s2c",
981 .total_flash_size = 128 * 1024,
982 .total_sram_size = 64 * 1024,
983 .n_gpnvms = 2,
984 .n_banks = 1,
985 {
986 /* .bank[0] = {*/
987 {
988 .probed = false,
989 .chip = NULL,
990 .bank = NULL,
991 .bank_number = 0,
992 .base_address = FLASH_BANK_BASE_S,
993 .controller_address = 0x400e0a00,
994 .flash_wait_states = 5,
995 .present = true,
996 .size_bytes = 128 * 1024,
997 .nsectors = 16,
998 .sector_size = 8192,
999 .page_size = 512,
1000 },
1001 /* .bank[1] = {*/
1002 {
1003 .present = false,
1004 .probed = false,
1005 .bank_number = 1,
1006
1007 },
1008 },
1009 },
1010
1011 /*atsam4s2b - LQPF64/QFN64/WLCSP64*/
1012 {
1013 .chipid_cidr = 0x289b07e0,
1014 .name = "at91sam4s2b",
1015 .total_flash_size = 128 * 1024,
1016 .total_sram_size = 64 * 1024,
1017 .n_gpnvms = 2,
1018 .n_banks = 1,
1019 {
1020 /* .bank[0] = {*/
1021 {
1022 .probed = false,
1023 .chip = NULL,
1024 .bank = NULL,
1025 .bank_number = 0,
1026 .base_address = FLASH_BANK_BASE_S,
1027 .controller_address = 0x400e0a00,
1028 .flash_wait_states = 5,
1029 .present = true,
1030 .size_bytes = 128 * 1024,
1031 .nsectors = 16,
1032 .sector_size = 8192,
1033 .page_size = 512,
1034 },
1035 /* .bank[1] = {*/
1036 {
1037 .present = false,
1038 .probed = false,
1039 .bank_number = 1,
1040
1041 },
1042 },
1043 },
1044
1045 /*atsam4s2a - LQFP48/QFN48*/
1046 {
1047 .chipid_cidr = 0x288b07e0,
1048 .name = "at91sam4s2a",
1049 .total_flash_size = 128 * 1024,
1050 .total_sram_size = 64 * 1024,
1051 .n_gpnvms = 2,
1052 .n_banks = 1,
1053 {
1054 /* .bank[0] = {*/
1055 {
1056 .probed = false,
1057 .chip = NULL,
1058 .bank = NULL,
1059 .bank_number = 0,
1060 .base_address = FLASH_BANK_BASE_S,
1061 .controller_address = 0x400e0a00,
1062 .flash_wait_states = 5,
1063 .present = true,
1064 .size_bytes = 128 * 1024,
1065 .nsectors = 16,
1066 .sector_size = 8192,
1067 .page_size = 512,
1068 },
1069 /* .bank[1] = {*/
1070 {
1071 .present = false,
1072 .probed = false,
1073 .bank_number = 1,
1074
1075 },
1076 },
1077 },
1078
1079 /*at91sam4sd32c - LQFP100/BGA100*/
1080 {
1081 .chipid_cidr = 0x29a70ee0,
1082 .name = "at91sam4sd32c",
1083 .total_flash_size = 2048 * 1024,
1084 .total_sram_size = 160 * 1024,
1085 .n_gpnvms = 3,
1086 .n_banks = 2,
1087
1088 /* .bank[0] = { */
1089 {
1090 {
1091 .probed = false,
1092 .chip = NULL,
1093 .bank = NULL,
1094 .bank_number = 0,
1095 .base_address = FLASH_BANK0_BASE_SD,
1096 .controller_address = 0x400e0a00,
1097 .flash_wait_states = 5,
1098 .present = true,
1099 .size_bytes = 1024 * 1024,
1100 .nsectors = 128,
1101 .sector_size = 8192,
1102 .page_size = 512,
1103 },
1104
1105 /* .bank[1] = { */
1106 {
1107 .probed = false,
1108 .chip = NULL,
1109 .bank = NULL,
1110 .bank_number = 1,
1111 .base_address = FLASH_BANK1_BASE_2048K_SD,
1112 .controller_address = 0x400e0c00,
1113 .flash_wait_states = 5,
1114 .present = true,
1115 .size_bytes = 1024 * 1024,
1116 .nsectors = 128,
1117 .sector_size = 8192,
1118 .page_size = 512,
1119 },
1120 },
1121 },
1122
1123 /*at91sam4sd32b - LQFP64/BGA64*/
1124 {
1125 .chipid_cidr = 0x29970ee0,
1126 .name = "at91sam4sd32b",
1127 .total_flash_size = 2048 * 1024,
1128 .total_sram_size = 160 * 1024,
1129 .n_gpnvms = 3,
1130 .n_banks = 2,
1131
1132 /* .bank[0] = { */
1133 {
1134 {
1135 .probed = false,
1136 .chip = NULL,
1137 .bank = NULL,
1138 .bank_number = 0,
1139 .base_address = FLASH_BANK0_BASE_SD,
1140 .controller_address = 0x400e0a00,
1141 .flash_wait_states = 5,
1142 .present = true,
1143 .size_bytes = 1024 * 1024,
1144 .nsectors = 128,
1145 .sector_size = 8192,
1146 .page_size = 512,
1147 },
1148
1149 /* .bank[1] = { */
1150 {
1151 .probed = false,
1152 .chip = NULL,
1153 .bank = NULL,
1154 .bank_number = 1,
1155 .base_address = FLASH_BANK1_BASE_2048K_SD,
1156 .controller_address = 0x400e0c00,
1157 .flash_wait_states = 5,
1158 .present = true,
1159 .size_bytes = 1024 * 1024,
1160 .nsectors = 128,
1161 .sector_size = 8192,
1162 .page_size = 512,
1163 },
1164 },
1165 },
1166
1167 /*at91sam4sd16c - LQFP100/BGA100*/
1168 {
1169 .chipid_cidr = 0x29a70ce0,
1170 .name = "at91sam4sd16c",
1171 .total_flash_size = 1024 * 1024,
1172 .total_sram_size = 160 * 1024,
1173 .n_gpnvms = 3,
1174 .n_banks = 2,
1175
1176 /* .bank[0] = { */
1177 {
1178 {
1179 .probed = false,
1180 .chip = NULL,
1181 .bank = NULL,
1182 .bank_number = 0,
1183 .base_address = FLASH_BANK0_BASE_SD,
1184 .controller_address = 0x400e0a00,
1185 .flash_wait_states = 5,
1186 .present = true,
1187 .size_bytes = 512 * 1024,
1188 .nsectors = 64,
1189 .sector_size = 8192,
1190 .page_size = 512,
1191 },
1192
1193 /* .bank[1] = { */
1194 {
1195 .probed = false,
1196 .chip = NULL,
1197 .bank = NULL,
1198 .bank_number = 1,
1199 .base_address = FLASH_BANK1_BASE_1024K_SD,
1200 .controller_address = 0x400e0c00,
1201 .flash_wait_states = 5,
1202 .present = true,
1203 .size_bytes = 512 * 1024,
1204 .nsectors = 64,
1205 .sector_size = 8192,
1206 .page_size = 512,
1207 },
1208 },
1209 },
1210
1211 /*at91sam4sd16b - LQFP64/BGA64*/
1212 {
1213 .chipid_cidr = 0x29970ce0,
1214 .name = "at91sam4sd16b",
1215 .total_flash_size = 1024 * 1024,
1216 .total_sram_size = 160 * 1024,
1217 .n_gpnvms = 3,
1218 .n_banks = 2,
1219
1220 /* .bank[0] = { */
1221 {
1222 {
1223 .probed = false,
1224 .chip = NULL,
1225 .bank = NULL,
1226 .bank_number = 0,
1227 .base_address = FLASH_BANK0_BASE_SD,
1228 .controller_address = 0x400e0a00,
1229 .flash_wait_states = 5,
1230 .present = true,
1231 .size_bytes = 512 * 1024,
1232 .nsectors = 64,
1233 .sector_size = 8192,
1234 .page_size = 512,
1235 },
1236
1237 /* .bank[1] = { */
1238 {
1239 .probed = false,
1240 .chip = NULL,
1241 .bank = NULL,
1242 .bank_number = 1,
1243 .base_address = FLASH_BANK1_BASE_1024K_SD,
1244 .controller_address = 0x400e0c00,
1245 .flash_wait_states = 5,
1246 .present = true,
1247 .size_bytes = 512 * 1024,
1248 .nsectors = 64,
1249 .sector_size = 8192,
1250 .page_size = 512,
1251 },
1252 },
1253 },
1254
1255 /* atsamg53n19 */
1256 {
1257 .chipid_cidr = 0x247e0ae0,
1258 .name = "atsamg53n19",
1259 .total_flash_size = 512 * 1024,
1260 .total_sram_size = 96 * 1024,
1261 .n_gpnvms = 2,
1262 .n_banks = 1,
1263
1264 /* .bank[0] = {*/
1265 {
1266 {
1267 .probed = false,
1268 .chip = NULL,
1269 .bank = NULL,
1270 .bank_number = 0,
1271 .base_address = FLASH_BANK_BASE_S,
1272 .controller_address = 0x400e0a00,
1273 .flash_wait_states = 5,
1274 .present = true,
1275 .size_bytes = 512 * 1024,
1276 .nsectors = 64,
1277 .sector_size = 8192,
1278 .page_size = 512,
1279 },
1280 /* .bank[1] = {*/
1281 {
1282 .present = false,
1283 .probed = false,
1284 .bank_number = 1,
1285
1286 },
1287 }
1288 },
1289
1290 /* atsamg55g19 Rev.A */
1291 {
1292 .chipid_cidr = 0x24470ae0,
1293 .name = "atsamg55g19",
1294 .total_flash_size = 512 * 1024,
1295 .total_sram_size = 160 * 1024,
1296 .n_gpnvms = 2,
1297 .n_banks = 1,
1298
1299 {
1300 /* .bank[0] = */
1301 {
1302 .probed = false,
1303 .chip = NULL,
1304 .bank = NULL,
1305 .bank_number = 0,
1306 .base_address = FLASH_BANK_BASE_S,
1307 .controller_address = 0x400e0a00,
1308 .flash_wait_states = 5,
1309 .present = true,
1310 .size_bytes = 512 * 1024,
1311 .nsectors = 64,
1312 .sector_size = 8192,
1313 .page_size = 512,
1314 },
1315 /* .bank[1] = */
1316 {
1317 .present = false,
1318 .probed = false,
1319 .bank_number = 1,
1320 },
1321 }
1322 },
1323
1324 /* atsamg55g19 Rev.B */
1325 {
1326 .chipid_cidr = 0x24470ae1,
1327 .name = "atsamg55g19b",
1328 .total_flash_size = 512 * 1024,
1329 .total_sram_size = 160 * 1024,
1330 .n_gpnvms = 2,
1331 .n_banks = 1,
1332
1333 {
1334 /* .bank[0] = */
1335 {
1336 .probed = false,
1337 .chip = NULL,
1338 .bank = NULL,
1339 .bank_number = 0,
1340 .base_address = FLASH_BANK_BASE_S,
1341 .controller_address = 0x400e0a00,
1342 .flash_wait_states = 5,
1343 .present = true,
1344 .size_bytes = 512 * 1024,
1345 .nsectors = 64,
1346 .sector_size = 8192,
1347 .page_size = 512,
1348 },
1349 /* .bank[1] = */
1350 {
1351 .present = false,
1352 .probed = false,
1353 .bank_number = 1,
1354 },
1355 }
1356 },
1357
1358 /* atsamg55j19 Rev.A */
1359 {
1360 .chipid_cidr = 0x24570ae0,
1361 .name = "atsamg55j19",
1362 .total_flash_size = 512 * 1024,
1363 .total_sram_size = 160 * 1024,
1364 .n_gpnvms = 2,
1365 .n_banks = 1,
1366
1367 {
1368 /* .bank[0] = */
1369 {
1370 .probed = false,
1371 .chip = NULL,
1372 .bank = NULL,
1373 .bank_number = 0,
1374 .base_address = FLASH_BANK_BASE_S,
1375 .controller_address = 0x400e0a00,
1376 .flash_wait_states = 5,
1377 .present = true,
1378 .size_bytes = 512 * 1024,
1379 .nsectors = 64,
1380 .sector_size = 8192,
1381 .page_size = 512,
1382 },
1383 /* .bank[1] = */
1384 {
1385 .present = false,
1386 .probed = false,
1387 .bank_number = 1,
1388 },
1389 }
1390 },
1391
1392 /* atsamg55j19 Rev.B */
1393 {
1394 .chipid_cidr = 0x24570ae1,
1395 .name = "atsamg55j19b",
1396 .total_flash_size = 512 * 1024,
1397 .total_sram_size = 160 * 1024,
1398 .n_gpnvms = 2,
1399 .n_banks = 1,
1400
1401 {
1402 /* .bank[0] = */
1403 {
1404 .probed = false,
1405 .chip = NULL,
1406 .bank = NULL,
1407 .bank_number = 0,
1408 .base_address = FLASH_BANK_BASE_S,
1409 .controller_address = 0x400e0a00,
1410 .flash_wait_states = 5,
1411 .present = true,
1412 .size_bytes = 512 * 1024,
1413 .nsectors = 64,
1414 .sector_size = 8192,
1415 .page_size = 512,
1416 },
1417 /* .bank[1] = */
1418 {
1419 .present = false,
1420 .probed = false,
1421 .bank_number = 1,
1422 },
1423 }
1424 },
1425
1426 /* terminate */
1427 {
1428 .chipid_cidr = 0,
1429 .name = NULL,
1430 }
1431 };
1432
1433 /* Globals above */
1434 /***********************************************************************
1435 **********************************************************************
1436 **********************************************************************
1437 **********************************************************************
1438 **********************************************************************
1439 **********************************************************************/
1440 /* *ATMEL* style code - from the SAM4 driver code */
1441
1442 /**
1443 * Get the current status of the EEFC and
1444 * the value of some status bits (LOCKE, PROGE).
1445 * @param private - info about the bank
1446 * @param v - result goes here
1447 */
1448 static int efc_get_status(struct sam4_bank_private *private, uint32_t *v)
1449 {
1450 int r;
1451 r = target_read_u32(private->chip->target,
1452 private->controller_address + OFFSET_EFC_FSR,
1453 v);
1454 LOG_DEBUG("Status: 0x%08x (lockerror: %d, cmderror: %d, ready: %d)",
1455 (unsigned int)(*v),
1456 ((unsigned int)((*v >> 2) & 1)),
1457 ((unsigned int)((*v >> 1) & 1)),
1458 ((unsigned int)((*v >> 0) & 1)));
1459
1460 return r;
1461 }
1462
1463 /**
1464 * Get the result of the last executed command.
1465 * @param private - info about the bank
1466 * @param v - result goes here
1467 */
1468 static int efc_get_result(struct sam4_bank_private *private, uint32_t *v)
1469 {
1470 int r;
1471 uint32_t rv;
1472 r = target_read_u32(private->chip->target,
1473 private->controller_address + OFFSET_EFC_FRR,
1474 &rv);
1475 if (v)
1476 *v = rv;
1477 LOG_DEBUG("Result: 0x%08x", ((unsigned int)(rv)));
1478 return r;
1479 }
1480
1481 static int efc_start_command(struct sam4_bank_private *private,
1482 unsigned command, unsigned argument)
1483 {
1484 uint32_t n, v;
1485 int r;
1486 int retry;
1487
1488 retry = 0;
1489 do_retry:
1490
1491 /* Check command & argument */
1492 switch (command) {
1493
1494 case AT91C_EFC_FCMD_WP:
1495 case AT91C_EFC_FCMD_WPL:
1496 case AT91C_EFC_FCMD_EWP:
1497 case AT91C_EFC_FCMD_EWPL:
1498 /* case AT91C_EFC_FCMD_EPL: */
1499 case AT91C_EFC_FCMD_EPA:
1500 case AT91C_EFC_FCMD_SLB:
1501 case AT91C_EFC_FCMD_CLB:
1502 n = (private->size_bytes / private->page_size);
1503 if (argument >= n)
1504 LOG_ERROR("*BUG*: Embedded flash has only %u pages", (unsigned)(n));
1505 break;
1506
1507 case AT91C_EFC_FCMD_SFB:
1508 case AT91C_EFC_FCMD_CFB:
1509 if (argument >= private->chip->details.n_gpnvms) {
1510 LOG_ERROR("*BUG*: Embedded flash has only %d GPNVMs",
1511 private->chip->details.n_gpnvms);
1512 }
1513 break;
1514
1515 case AT91C_EFC_FCMD_GETD:
1516 case AT91C_EFC_FCMD_EA:
1517 case AT91C_EFC_FCMD_GLB:
1518 case AT91C_EFC_FCMD_GFB:
1519 case AT91C_EFC_FCMD_STUI:
1520 case AT91C_EFC_FCMD_SPUI:
1521 if (argument != 0)
1522 LOG_ERROR("Argument is meaningless for cmd: %d", command);
1523 break;
1524 default:
1525 LOG_ERROR("Unknown command %d", command);
1526 break;
1527 }
1528
1529 if (command == AT91C_EFC_FCMD_SPUI) {
1530 /* this is a very special situation. */
1531 /* Situation (1) - error/retry - see below */
1532 /* And we are being called recursively */
1533 /* Situation (2) - normal, finished reading unique id */
1534 } else {
1535 /* it should be "ready" */
1536 efc_get_status(private, &v);
1537 if (v & 1) {
1538 /* then it is ready */
1539 /* we go on */
1540 } else {
1541 if (retry) {
1542 /* we have done this before */
1543 /* the controller is not responding. */
1544 LOG_ERROR("flash controller(%d) is not ready! Error",
1545 private->bank_number);
1546 return ERROR_FAIL;
1547 } else {
1548 retry++;
1549 LOG_ERROR("Flash controller(%d) is not ready, attempting reset",
1550 private->bank_number);
1551 /* we do that by issuing the *STOP* command */
1552 efc_start_command(private, AT91C_EFC_FCMD_SPUI, 0);
1553 /* above is recursive, and further recursion is blocked by */
1554 /* if (command == AT91C_EFC_FCMD_SPUI) above */
1555 goto do_retry;
1556 }
1557 }
1558 }
1559
1560 v = (0x5A << 24) | (argument << 8) | command;
1561 LOG_DEBUG("Command: 0x%08x", ((unsigned int)(v)));
1562 r = target_write_u32(private->bank->target,
1563 private->controller_address + OFFSET_EFC_FCR, v);
1564 if (r != ERROR_OK)
1565 LOG_DEBUG("Error Write failed");
1566 return r;
1567 }
1568
1569 /**
1570 * Performs the given command and wait until its completion (or an error).
1571 * @param private - info about the bank
1572 * @param command - Command to perform.
1573 * @param argument - Optional command argument.
1574 * @param status - put command status bits here
1575 */
1576 static int efc_perform_command(struct sam4_bank_private *private,
1577 unsigned command,
1578 unsigned argument,
1579 uint32_t *status)
1580 {
1581
1582 int r;
1583 uint32_t v;
1584 int64_t ms_now, ms_end;
1585
1586 /* default */
1587 if (status)
1588 *status = 0;
1589
1590 r = efc_start_command(private, command, argument);
1591 if (r != ERROR_OK)
1592 return r;
1593
1594 ms_end = 10000 + timeval_ms();
1595
1596 do {
1597 r = efc_get_status(private, &v);
1598 if (r != ERROR_OK)
1599 return r;
1600 ms_now = timeval_ms();
1601 if (ms_now > ms_end) {
1602 /* error */
1603 LOG_ERROR("Command timeout");
1604 return ERROR_FAIL;
1605 }
1606 } while ((v & 1) == 0);
1607
1608 /* error bits.. */
1609 if (status)
1610 *status = (v & 0x6);
1611 return ERROR_OK;
1612
1613 }
1614
1615 /**
1616 * Read the unique ID.
1617 * @param private - info about the bank
1618 * The unique ID is stored in the 'private' structure.
1619 */
1620 static int flashd_read_uid(struct sam4_bank_private *private)
1621 {
1622 int r;
1623 uint32_t v;
1624 int x;
1625 /* assume 0 */
1626 private->chip->cfg.unique_id[0] = 0;
1627 private->chip->cfg.unique_id[1] = 0;
1628 private->chip->cfg.unique_id[2] = 0;
1629 private->chip->cfg.unique_id[3] = 0;
1630
1631 LOG_DEBUG("Begin");
1632 r = efc_start_command(private, AT91C_EFC_FCMD_STUI, 0);
1633 if (r < 0)
1634 return r;
1635
1636 for (x = 0; x < 4; x++) {
1637 r = target_read_u32(private->chip->target,
1638 private->bank->base + (x * 4),
1639 &v);
1640 if (r < 0)
1641 return r;
1642 private->chip->cfg.unique_id[x] = v;
1643 }
1644
1645 r = efc_perform_command(private, AT91C_EFC_FCMD_SPUI, 0, NULL);
1646 LOG_DEBUG("End: R=%d, id = 0x%08x, 0x%08x, 0x%08x, 0x%08x",
1647 r,
1648 (unsigned int)(private->chip->cfg.unique_id[0]),
1649 (unsigned int)(private->chip->cfg.unique_id[1]),
1650 (unsigned int)(private->chip->cfg.unique_id[2]),
1651 (unsigned int)(private->chip->cfg.unique_id[3]));
1652 return r;
1653
1654 }
1655
1656 /**
1657 * Erases the entire flash.
1658 * @param private - the info about the bank.
1659 */
1660 static int flashd_erase_entire_bank(struct sam4_bank_private *private)
1661 {
1662 LOG_DEBUG("Here");
1663 return efc_perform_command(private, AT91C_EFC_FCMD_EA, 0, NULL);
1664 }
1665
1666 /**
1667 * Erases the entire flash.
1668 * @param private - the info about the bank.
1669 * @param first_page
1670 * @param num_pages
1671 * @param status
1672 */
1673 static int flashd_erase_pages(struct sam4_bank_private *private,
1674 int first_page,
1675 int num_pages,
1676 uint32_t *status)
1677 {
1678 LOG_DEBUG("Here");
1679 uint8_t erase_pages;
1680 switch (num_pages) {
1681 case 4:
1682 erase_pages = 0x00;
1683 break;
1684 case 8:
1685 erase_pages = 0x01;
1686 break;
1687 case 16:
1688 erase_pages = 0x02;
1689 break;
1690 case 32:
1691 erase_pages = 0x03;
1692 break;
1693 default:
1694 erase_pages = 0x00;
1695 break;
1696 }
1697
1698 /* AT91C_EFC_FCMD_EPA
1699 * According to the datasheet FARG[15:2] defines the page from which
1700 * the erase will start.This page must be modulo 4, 8, 16 or 32
1701 * according to the number of pages to erase. FARG[1:0] defines the
1702 * number of pages to be erased. Previously (firstpage << 2) was used
1703 * to conform to this, seems it should not be shifted...
1704 */
1705 return efc_perform_command(private,
1706 /* send Erase Page */
1707 AT91C_EFC_FCMD_EPA,
1708 (first_page) | erase_pages,
1709 status);
1710 }
1711
1712 /**
1713 * Gets current GPNVM state.
1714 * @param private - info about the bank.
1715 * @param gpnvm - GPNVM bit index.
1716 * @param puthere - result stored here.
1717 */
1718 /* ------------------------------------------------------------------------------ */
1719 static int flashd_get_gpnvm(struct sam4_bank_private *private, unsigned gpnvm, unsigned *puthere)
1720 {
1721 uint32_t v;
1722 int r;
1723
1724 LOG_DEBUG("Here");
1725 if (private->bank_number != 0) {
1726 LOG_ERROR("GPNVM only works with Bank0");
1727 return ERROR_FAIL;
1728 }
1729
1730 if (gpnvm >= private->chip->details.n_gpnvms) {
1731 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1732 gpnvm, private->chip->details.n_gpnvms);
1733 return ERROR_FAIL;
1734 }
1735
1736 /* Get GPNVMs status */
1737 r = efc_perform_command(private, AT91C_EFC_FCMD_GFB, 0, NULL);
1738 if (r != ERROR_OK) {
1739 LOG_ERROR("Failed");
1740 return r;
1741 }
1742
1743 r = efc_get_result(private, &v);
1744
1745 if (puthere) {
1746 /* Check if GPNVM is set */
1747 /* get the bit and make it a 0/1 */
1748 *puthere = (v >> gpnvm) & 1;
1749 }
1750
1751 return r;
1752 }
1753
1754 /**
1755 * Clears the selected GPNVM bit.
1756 * @param private info about the bank
1757 * @param gpnvm GPNVM index.
1758 * @returns 0 if successful; otherwise returns an error code.
1759 */
1760 static int flashd_clr_gpnvm(struct sam4_bank_private *private, unsigned gpnvm)
1761 {
1762 int r;
1763 unsigned v;
1764
1765 LOG_DEBUG("Here");
1766 if (private->bank_number != 0) {
1767 LOG_ERROR("GPNVM only works with Bank0");
1768 return ERROR_FAIL;
1769 }
1770
1771 if (gpnvm >= private->chip->details.n_gpnvms) {
1772 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1773 gpnvm, private->chip->details.n_gpnvms);
1774 return ERROR_FAIL;
1775 }
1776
1777 r = flashd_get_gpnvm(private, gpnvm, &v);
1778 if (r != ERROR_OK) {
1779 LOG_DEBUG("Failed: %d", r);
1780 return r;
1781 }
1782 r = efc_perform_command(private, AT91C_EFC_FCMD_CFB, gpnvm, NULL);
1783 LOG_DEBUG("End: %d", r);
1784 return r;
1785 }
1786
1787 /**
1788 * Sets the selected GPNVM bit.
1789 * @param private info about the bank
1790 * @param gpnvm GPNVM index.
1791 */
1792 static int flashd_set_gpnvm(struct sam4_bank_private *private, unsigned gpnvm)
1793 {
1794 int r;
1795 unsigned v;
1796
1797 if (private->bank_number != 0) {
1798 LOG_ERROR("GPNVM only works with Bank0");
1799 return ERROR_FAIL;
1800 }
1801
1802 if (gpnvm >= private->chip->details.n_gpnvms) {
1803 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1804 gpnvm, private->chip->details.n_gpnvms);
1805 return ERROR_FAIL;
1806 }
1807
1808 r = flashd_get_gpnvm(private, gpnvm, &v);
1809 if (r != ERROR_OK)
1810 return r;
1811 if (v) {
1812 /* already set */
1813 r = ERROR_OK;
1814 } else {
1815 /* set it */
1816 r = efc_perform_command(private, AT91C_EFC_FCMD_SFB, gpnvm, NULL);
1817 }
1818 return r;
1819 }
1820
1821 /**
1822 * Returns a bit field (at most 64) of locked regions within a page.
1823 * @param private info about the bank
1824 * @param v where to store locked bits
1825 */
1826 static int flashd_get_lock_bits(struct sam4_bank_private *private, uint32_t *v)
1827 {
1828 int r;
1829 LOG_DEBUG("Here");
1830 r = efc_perform_command(private, AT91C_EFC_FCMD_GLB, 0, NULL);
1831 if (r == ERROR_OK) {
1832 efc_get_result(private, v);
1833 efc_get_result(private, v);
1834 efc_get_result(private, v);
1835 r = efc_get_result(private, v);
1836 }
1837 LOG_DEBUG("End: %d", r);
1838 return r;
1839 }
1840
1841 /**
1842 * Unlocks all the regions in the given address range.
1843 * @param private info about the bank
1844 * @param start_sector first sector to unlock
1845 * @param end_sector last (inclusive) to unlock
1846 */
1847
1848 static int flashd_unlock(struct sam4_bank_private *private,
1849 unsigned start_sector,
1850 unsigned end_sector)
1851 {
1852 int r;
1853 uint32_t status;
1854 uint32_t pg;
1855 uint32_t pages_per_sector;
1856
1857 pages_per_sector = private->sector_size / private->page_size;
1858
1859 /* Unlock all pages */
1860 while (start_sector <= end_sector) {
1861 pg = start_sector * pages_per_sector;
1862
1863 r = efc_perform_command(private, AT91C_EFC_FCMD_CLB, pg, &status);
1864 if (r != ERROR_OK)
1865 return r;
1866 start_sector++;
1867 }
1868
1869 return ERROR_OK;
1870 }
1871
1872 /**
1873 * Locks regions
1874 * @param private - info about the bank
1875 * @param start_sector - first sector to lock
1876 * @param end_sector - last sector (inclusive) to lock
1877 */
1878 static int flashd_lock(struct sam4_bank_private *private,
1879 unsigned start_sector,
1880 unsigned end_sector)
1881 {
1882 uint32_t status;
1883 uint32_t pg;
1884 uint32_t pages_per_sector;
1885 int r;
1886
1887 pages_per_sector = private->sector_size / private->page_size;
1888
1889 /* Lock all pages */
1890 while (start_sector <= end_sector) {
1891 pg = start_sector * pages_per_sector;
1892
1893 r = efc_perform_command(private, AT91C_EFC_FCMD_SLB, pg, &status);
1894 if (r != ERROR_OK)
1895 return r;
1896 start_sector++;
1897 }
1898 return ERROR_OK;
1899 }
1900
1901 /****** END SAM4 CODE ********/
1902
1903 /* begin helpful debug code */
1904 /* print the fieldname, the field value, in dec & hex, and return field value */
1905 static uint32_t sam4_reg_fieldname(struct sam4_chip *chip,
1906 const char *regname,
1907 uint32_t value,
1908 unsigned shift,
1909 unsigned width)
1910 {
1911 uint32_t v;
1912 int hwidth, dwidth;
1913
1914
1915 /* extract the field */
1916 v = value >> shift;
1917 v = v & ((1 << width)-1);
1918 if (width <= 16) {
1919 hwidth = 4;
1920 dwidth = 5;
1921 } else {
1922 hwidth = 8;
1923 dwidth = 12;
1924 }
1925
1926 /* show the basics */
1927 LOG_USER_N("\t%*s: %*" PRIu32 " [0x%0*" PRIx32 "] ",
1928 REG_NAME_WIDTH, regname,
1929 dwidth, v,
1930 hwidth, v);
1931 return v;
1932 }
1933
1934 static const char _unknown[] = "unknown";
1935 static const char *const eproc_names[] = {
1936 "Cortex-M7", /* 0 */
1937 "arm946es", /* 1 */
1938 "arm7tdmi", /* 2 */
1939 "Cortex-M3", /* 3 */
1940 "arm920t", /* 4 */
1941 "arm926ejs", /* 5 */
1942 "Cortex-A5", /* 6 */
1943 "Cortex-M4", /* 7 */
1944 _unknown, /* 8 */
1945 _unknown, /* 9 */
1946 _unknown, /* 10 */
1947 _unknown, /* 11 */
1948 _unknown, /* 12 */
1949 _unknown, /* 13 */
1950 _unknown, /* 14 */
1951 _unknown, /* 15 */
1952 };
1953
1954 #define nvpsize2 nvpsize /* these two tables are identical */
1955 static const char *const nvpsize[] = {
1956 "none", /* 0 */
1957 "8K bytes", /* 1 */
1958 "16K bytes", /* 2 */
1959 "32K bytes", /* 3 */
1960 _unknown, /* 4 */
1961 "64K bytes", /* 5 */
1962 _unknown, /* 6 */
1963 "128K bytes", /* 7 */
1964 "160K bytes", /* 8 */
1965 "256K bytes", /* 9 */
1966 "512K bytes", /* 10 */
1967 _unknown, /* 11 */
1968 "1024K bytes", /* 12 */
1969 _unknown, /* 13 */
1970 "2048K bytes", /* 14 */
1971 _unknown, /* 15 */
1972 };
1973
1974 static const char *const sramsize[] = {
1975 "48K Bytes", /* 0 */
1976 "1K Bytes", /* 1 */
1977 "2K Bytes", /* 2 */
1978 "6K Bytes", /* 3 */
1979 "112K Bytes", /* 4 */
1980 "4K Bytes", /* 5 */
1981 "80K Bytes", /* 6 */
1982 "160K Bytes", /* 7 */
1983 "8K Bytes", /* 8 */
1984 "16K Bytes", /* 9 */
1985 "32K Bytes", /* 10 */
1986 "64K Bytes", /* 11 */
1987 "128K Bytes", /* 12 */
1988 "256K Bytes", /* 13 */
1989 "96K Bytes", /* 14 */
1990 "512K Bytes", /* 15 */
1991
1992 };
1993
1994 static const struct archnames { unsigned value; const char *name; } archnames[] = {
1995 { 0x19, "AT91SAM9xx Series" },
1996 { 0x29, "AT91SAM9XExx Series" },
1997 { 0x34, "AT91x34 Series" },
1998 { 0x37, "CAP7 Series" },
1999 { 0x39, "CAP9 Series" },
2000 { 0x3B, "CAP11 Series" },
2001 { 0x3C, "ATSAM4E" },
2002 { 0x40, "AT91x40 Series" },
2003 { 0x42, "AT91x42 Series" },
2004 { 0x43, "SAMG51 Series"
2005 },
2006 { 0x44, "SAMG55 Series (49-pin WLCSP)" },
2007 { 0x45, "SAMG55 Series (64-pin)" },
2008 { 0x47, "SAMG53 Series"
2009 },
2010 { 0x55, "AT91x55 Series" },
2011 { 0x60, "AT91SAM7Axx Series" },
2012 { 0x61, "AT91SAM7AQxx Series" },
2013 { 0x63, "AT91x63 Series" },
2014 { 0x64, "SAM4CxxC (100-pin version)" },
2015 { 0x66, "SAM4CxxE (144-pin version)" },
2016 { 0x70, "AT91SAM7Sxx Series" },
2017 { 0x71, "AT91SAM7XCxx Series" },
2018 { 0x72, "AT91SAM7SExx Series" },
2019 { 0x73, "AT91SAM7Lxx Series" },
2020 { 0x75, "AT91SAM7Xxx Series" },
2021 { 0x76, "AT91SAM7SLxx Series" },
2022 { 0x80, "ATSAM3UxC Series (100-pin version)" },
2023 { 0x81, "ATSAM3UxE Series (144-pin version)" },
2024 { 0x83, "ATSAM3A/SAM4A xC Series (100-pin version)"},
2025 { 0x84, "ATSAM3X/SAM4X xC Series (100-pin version)"},
2026 { 0x85, "ATSAM3X/SAM4X xE Series (144-pin version)"},
2027 { 0x86, "ATSAM3X/SAM4X xG Series (208/217-pin version)" },
2028 { 0x88, "ATSAM3S/SAM4S xA Series (48-pin version)" },
2029 { 0x89, "ATSAM3S/SAM4S xB Series (64-pin version)" },
2030 { 0x8A, "ATSAM3S/SAM4S xC Series (100-pin version)"},
2031 { 0x92, "AT91x92 Series" },
2032 { 0x93, "ATSAM3NxA Series (48-pin version)" },
2033 { 0x94, "ATSAM3NxB Series (64-pin version)" },
2034 { 0x95, "ATSAM3NxC Series (100-pin version)" },
2035 { 0x98, "ATSAM3SDxA Series (48-pin version)" },
2036 { 0x99, "ATSAM3SDxB Series (64-pin version)" },
2037 { 0x9A, "ATSAM3SDxC Series (100-pin version)" },
2038 { 0xA5, "ATSAM5A" },
2039 { 0xF0, "AT75Cxx Series" },
2040 { -1, NULL },
2041 };
2042
2043 static const char *const nvptype[] = {
2044 "rom", /* 0 */
2045 "romless or onchip flash", /* 1 */
2046 "embedded flash memory",/* 2 */
2047 "rom(nvpsiz) + embedded flash (nvpsiz2)", /* 3 */
2048 "sram emulating flash", /* 4 */
2049 _unknown, /* 5 */
2050 _unknown, /* 6 */
2051 _unknown, /* 7 */
2052 };
2053
2054 static const char *_yes_or_no(uint32_t v)
2055 {
2056 if (v)
2057 return "YES";
2058 else
2059 return "NO";
2060 }
2061
2062 static const char *const _rc_freq[] = {
2063 "4 MHz", "8 MHz", "12 MHz", "reserved"
2064 };
2065
2066 static void sam4_explain_ckgr_mor(struct sam4_chip *chip)
2067 {
2068 uint32_t v;
2069 uint32_t rcen;
2070
2071 v = sam4_reg_fieldname(chip, "MOSCXTEN", chip->cfg.CKGR_MOR, 0, 1);
2072 LOG_USER("(main xtal enabled: %s)", _yes_or_no(v));
2073 v = sam4_reg_fieldname(chip, "MOSCXTBY", chip->cfg.CKGR_MOR, 1, 1);
2074 LOG_USER("(main osc bypass: %s)", _yes_or_no(v));
2075 rcen = sam4_reg_fieldname(chip, "MOSCRCEN", chip->cfg.CKGR_MOR, 3, 1);
2076 LOG_USER("(onchip RC-OSC enabled: %s)", _yes_or_no(rcen));
2077 v = sam4_reg_fieldname(chip, "MOSCRCF", chip->cfg.CKGR_MOR, 4, 3);
2078 LOG_USER("(onchip RC-OSC freq: %s)", _rc_freq[v]);
2079
2080 chip->cfg.rc_freq = 0;
2081 if (rcen) {
2082 switch (v) {
2083 default:
2084 chip->cfg.rc_freq = 0;
2085 break;
2086 case 0:
2087 chip->cfg.rc_freq = 4 * 1000 * 1000;
2088 break;
2089 case 1:
2090 chip->cfg.rc_freq = 8 * 1000 * 1000;
2091 break;
2092 case 2:
2093 chip->cfg.rc_freq = 12 * 1000 * 1000;
2094 break;
2095 }
2096 }
2097
2098 v = sam4_reg_fieldname(chip, "MOSCXTST", chip->cfg.CKGR_MOR, 8, 8);
2099 LOG_USER("(startup clks, time= %f uSecs)",
2100 ((float)(v * 1000000)) / ((float)(chip->cfg.slow_freq)));
2101 v = sam4_reg_fieldname(chip, "MOSCSEL", chip->cfg.CKGR_MOR, 24, 1);
2102 LOG_USER("(mainosc source: %s)",
2103 v ? "external xtal" : "internal RC");
2104
2105 v = sam4_reg_fieldname(chip, "CFDEN", chip->cfg.CKGR_MOR, 25, 1);
2106 LOG_USER("(clock failure enabled: %s)",
2107 _yes_or_no(v));
2108 }
2109
2110 static void sam4_explain_chipid_cidr(struct sam4_chip *chip)
2111 {
2112 int x;
2113 uint32_t v;
2114 const char *cp;
2115
2116 sam4_reg_fieldname(chip, "Version", chip->cfg.CHIPID_CIDR, 0, 5);
2117 LOG_USER_N("\n");
2118
2119 v = sam4_reg_fieldname(chip, "EPROC", chip->cfg.CHIPID_CIDR, 5, 3);
2120 LOG_USER("%s", eproc_names[v]);
2121
2122 v = sam4_reg_fieldname(chip, "NVPSIZE", chip->cfg.CHIPID_CIDR, 8, 4);
2123 LOG_USER("%s", nvpsize[v]);
2124
2125 v = sam4_reg_fieldname(chip, "NVPSIZE2", chip->cfg.CHIPID_CIDR, 12, 4);
2126 LOG_USER("%s", nvpsize2[v]);
2127
2128 v = sam4_reg_fieldname(chip, "SRAMSIZE", chip->cfg.CHIPID_CIDR, 16, 4);
2129 LOG_USER("%s", sramsize[v]);
2130
2131 v = sam4_reg_fieldname(chip, "ARCH", chip->cfg.CHIPID_CIDR, 20, 8);
2132 cp = _unknown;
2133 for (x = 0; archnames[x].name; x++) {
2134 if (v == archnames[x].value) {
2135 cp = archnames[x].name;
2136 break;
2137 }
2138 }
2139
2140 LOG_USER("%s", cp);
2141
2142 v = sam4_reg_fieldname(chip, "NVPTYP", chip->cfg.CHIPID_CIDR, 28, 3);
2143 LOG_USER("%s", nvptype[v]);
2144
2145 v = sam4_reg_fieldname(chip, "EXTID", chip->cfg.CHIPID_CIDR, 31, 1);
2146 LOG_USER("(exists: %s)", _yes_or_no(v));
2147 }
2148
2149 static void sam4_explain_ckgr_mcfr(struct sam4_chip *chip)
2150 {
2151 uint32_t v;
2152
2153 v = sam4_reg_fieldname(chip, "MAINFRDY", chip->cfg.CKGR_MCFR, 16, 1);
2154 LOG_USER("(main ready: %s)", _yes_or_no(v));
2155
2156 v = sam4_reg_fieldname(chip, "MAINF", chip->cfg.CKGR_MCFR, 0, 16);
2157
2158 v = (v * chip->cfg.slow_freq) / 16;
2159 chip->cfg.mainosc_freq = v;
2160
2161 LOG_USER("(%3.03f Mhz (%" PRIu32 ".%03" PRIu32 "khz slowclk)",
2162 _tomhz(v),
2163 (uint32_t)(chip->cfg.slow_freq / 1000),
2164 (uint32_t)(chip->cfg.slow_freq % 1000));
2165 }
2166
2167 static void sam4_explain_ckgr_plla(struct sam4_chip *chip)
2168 {
2169 uint32_t mula, diva;
2170
2171 diva = sam4_reg_fieldname(chip, "DIVA", chip->cfg.CKGR_PLLAR, 0, 8);
2172 LOG_USER_N("\n");
2173 mula = sam4_reg_fieldname(chip, "MULA", chip->cfg.CKGR_PLLAR, 16, 11);
2174 LOG_USER_N("\n");
2175 chip->cfg.plla_freq = 0;
2176 if (mula == 0)
2177 LOG_USER("\tPLLA Freq: (Disabled,mula = 0)");
2178 else if (diva == 0)
2179 LOG_USER("\tPLLA Freq: (Disabled,diva = 0)");
2180 else if (diva >= 1) {
2181 chip->cfg.plla_freq = (chip->cfg.mainosc_freq * (mula + 1) / diva);
2182 LOG_USER("\tPLLA Freq: %3.03f MHz",
2183 _tomhz(chip->cfg.plla_freq));
2184 }
2185 }
2186
2187 static void sam4_explain_mckr(struct sam4_chip *chip)
2188 {
2189 uint32_t css, pres, fin = 0;
2190 int pdiv = 0;
2191 const char *cp = NULL;
2192
2193 css = sam4_reg_fieldname(chip, "CSS", chip->cfg.PMC_MCKR, 0, 2);
2194 switch (css & 3) {
2195 case 0:
2196 fin = chip->cfg.slow_freq;
2197 cp = "slowclk";
2198 break;
2199 case 1:
2200 fin = chip->cfg.mainosc_freq;
2201 cp = "mainosc";
2202 break;
2203 case 2:
2204 fin = chip->cfg.plla_freq;
2205 cp = "plla";
2206 break;
2207 case 3:
2208 if (chip->cfg.CKGR_UCKR & (1 << 16)) {
2209 fin = 480 * 1000 * 1000;
2210 cp = "upll";
2211 } else {
2212 fin = 0;
2213 cp = "upll (*ERROR* UPLL is disabled)";
2214 }
2215 break;
2216 default:
2217 assert(0);
2218 break;
2219 }
2220
2221 LOG_USER("%s (%3.03f Mhz)",
2222 cp,
2223 _tomhz(fin));
2224 pres = sam4_reg_fieldname(chip, "PRES", chip->cfg.PMC_MCKR, 4, 3);
2225 switch (pres & 0x07) {
2226 case 0:
2227 pdiv = 1;
2228 cp = "selected clock";
2229 break;
2230 case 1:
2231 pdiv = 2;
2232 cp = "clock/2";
2233 break;
2234 case 2:
2235 pdiv = 4;
2236 cp = "clock/4";
2237 break;
2238 case 3:
2239 pdiv = 8;
2240 cp = "clock/8";
2241 break;
2242 case 4:
2243 pdiv = 16;
2244 cp = "clock/16";
2245 break;
2246 case 5:
2247 pdiv = 32;
2248 cp = "clock/32";
2249 break;
2250 case 6:
2251 pdiv = 64;
2252 cp = "clock/64";
2253 break;
2254 case 7:
2255 pdiv = 6;
2256 cp = "clock/6";
2257 break;
2258 default:
2259 assert(0);
2260 break;
2261 }
2262 LOG_USER("(%s)", cp);
2263 fin = fin / pdiv;
2264 /* sam4 has a *SINGLE* clock - */
2265 /* other at91 series parts have divisors for these. */
2266 chip->cfg.cpu_freq = fin;
2267 chip->cfg.mclk_freq = fin;
2268 chip->cfg.fclk_freq = fin;
2269 LOG_USER("\t\tResult CPU Freq: %3.03f",
2270 _tomhz(fin));
2271 }
2272
2273 #if 0
2274 static struct sam4_chip *target2sam4(struct target *target)
2275 {
2276 struct sam4_chip *chip;
2277
2278 if (!target)
2279 return NULL;
2280
2281 chip = all_sam4_chips;
2282 while (chip) {
2283 if (chip->target == target)
2284 break; /* return below */
2285 else
2286 chip = chip->next;
2287 }
2288 return chip;
2289 }
2290 #endif
2291
2292 static uint32_t *sam4_get_reg_ptr(struct sam4_cfg *cfg, const struct sam4_reg_list *list)
2293 {
2294 /* this function exists to help */
2295 /* keep funky offsetof() errors */
2296 /* and casting from causing bugs */
2297
2298 /* By using prototypes - we can detect what would */
2299 /* be casting errors. */
2300
2301 return (uint32_t *)(void *)(((char *)(cfg)) + list->struct_offset);
2302 }
2303
2304
2305 #define SAM4_ENTRY(NAME, FUNC) { .address = SAM4_ ## NAME, .struct_offset = offsetof( \
2306 struct sam4_cfg, \
2307 NAME), # NAME, FUNC }
2308 static const struct sam4_reg_list sam4_all_regs[] = {
2309 SAM4_ENTRY(CKGR_MOR, sam4_explain_ckgr_mor),
2310 SAM4_ENTRY(CKGR_MCFR, sam4_explain_ckgr_mcfr),
2311 SAM4_ENTRY(CKGR_PLLAR, sam4_explain_ckgr_plla),
2312 SAM4_ENTRY(CKGR_UCKR, NULL),
2313 SAM4_ENTRY(PMC_FSMR, NULL),
2314 SAM4_ENTRY(PMC_FSPR, NULL),
2315 SAM4_ENTRY(PMC_IMR, NULL),
2316 SAM4_ENTRY(PMC_MCKR, sam4_explain_mckr),
2317 SAM4_ENTRY(PMC_PCK0, NULL),
2318 SAM4_ENTRY(PMC_PCK1, NULL),
2319 SAM4_ENTRY(PMC_PCK2, NULL),
2320 SAM4_ENTRY(PMC_PCSR, NULL),
2321 SAM4_ENTRY(PMC_SCSR, NULL),
2322 SAM4_ENTRY(PMC_SR, NULL),
2323 SAM4_ENTRY(CHIPID_CIDR, sam4_explain_chipid_cidr),
2324 SAM4_ENTRY(CHIPID_EXID, NULL),
2325 /* TERMINATE THE LIST */
2326 { .name = NULL }
2327 };
2328 #undef SAM4_ENTRY
2329
2330 static struct sam4_bank_private *get_sam4_bank_private(struct flash_bank *bank)
2331 {
2332 return bank->driver_priv;
2333 }
2334
2335 /**
2336 * Given a pointer to where it goes in the structure,
2337 * determine the register name, address from the all registers table.
2338 */
2339 static const struct sam4_reg_list *sam4_get_reg(struct sam4_chip *chip, uint32_t *goes_here)
2340 {
2341 const struct sam4_reg_list *reg;
2342
2343 reg = &(sam4_all_regs[0]);
2344 while (reg->name) {
2345 uint32_t *possible;
2346
2347 /* calculate where this one go.. */
2348 /* it is "possibly" this register. */
2349
2350 possible = ((uint32_t *)(void *)(((char *)(&(chip->cfg))) + reg->struct_offset));
2351
2352 /* well? Is it this register */
2353 if (possible == goes_here) {
2354 /* Jump for joy! */
2355 return reg;
2356 }
2357
2358 /* next... */
2359 reg++;
2360 }
2361 /* This is *TOTAL*PANIC* - we are totally screwed. */
2362 LOG_ERROR("INVALID SAM4 REGISTER");
2363 return NULL;
2364 }
2365
2366 static int sam4_read_this_reg(struct sam4_chip *chip, uint32_t *goes_here)
2367 {
2368 const struct sam4_reg_list *reg;
2369 int r;
2370
2371 reg = sam4_get_reg(chip, goes_here);
2372 if (!reg)
2373 return ERROR_FAIL;
2374
2375 r = target_read_u32(chip->target, reg->address, goes_here);
2376 if (r != ERROR_OK) {
2377 LOG_ERROR("Cannot read SAM4 register: %s @ 0x%08x, Err: %d",
2378 reg->name, (unsigned)(reg->address), r);
2379 }
2380 return r;
2381 }
2382
2383 static int sam4_read_all_regs(struct sam4_chip *chip)
2384 {
2385 int r;
2386 const struct sam4_reg_list *reg;
2387
2388 reg = &(sam4_all_regs[0]);
2389 while (reg->name) {
2390 r = sam4_read_this_reg(chip,
2391 sam4_get_reg_ptr(&(chip->cfg), reg));
2392 if (r != ERROR_OK) {
2393 LOG_ERROR("Cannot read SAM4 register: %s @ 0x%08x, Error: %d",
2394 reg->name, ((unsigned)(reg->address)), r);
2395 return r;
2396 }
2397 reg++;
2398 }
2399
2400 return ERROR_OK;
2401 }
2402
2403 static int sam4_get_info(struct sam4_chip *chip)
2404 {
2405 const struct sam4_reg_list *reg;
2406 uint32_t regval;
2407 int r;
2408
2409 r = sam4_read_all_regs(chip);
2410 if (r != ERROR_OK)
2411 return r;
2412
2413 reg = &(sam4_all_regs[0]);
2414 while (reg->name) {
2415 /* display all regs */
2416 LOG_DEBUG("Start: %s", reg->name);
2417 regval = *sam4_get_reg_ptr(&(chip->cfg), reg);
2418 LOG_USER("%*s: [0x%08" PRIx32 "] -> 0x%08" PRIx32,
2419 REG_NAME_WIDTH,
2420 reg->name,
2421 reg->address,
2422 regval);
2423 if (reg->explain_func)
2424 (*(reg->explain_func))(chip);
2425 LOG_DEBUG("End: %s", reg->name);
2426 reg++;
2427 }
2428 LOG_USER(" rc-osc: %3.03f MHz", _tomhz(chip->cfg.rc_freq));
2429 LOG_USER(" mainosc: %3.03f MHz", _tomhz(chip->cfg.mainosc_freq));
2430 LOG_USER(" plla: %3.03f MHz", _tomhz(chip->cfg.plla_freq));
2431 LOG_USER(" cpu-freq: %3.03f MHz", _tomhz(chip->cfg.cpu_freq));
2432 LOG_USER("mclk-freq: %3.03f MHz", _tomhz(chip->cfg.mclk_freq));
2433
2434 LOG_USER(" UniqueId: 0x%08" PRIx32 " 0x%08" PRIx32 " 0x%08" PRIx32 " 0x%08"PRIx32,
2435 chip->cfg.unique_id[0],
2436 chip->cfg.unique_id[1],
2437 chip->cfg.unique_id[2],
2438 chip->cfg.unique_id[3]);
2439
2440 return ERROR_OK;
2441 }
2442
2443 static int sam4_protect_check(struct flash_bank *bank)
2444 {
2445 int r;
2446 uint32_t v[4] = {0};
2447 unsigned x;
2448 struct sam4_bank_private *private;
2449
2450 LOG_DEBUG("Begin");
2451 if (bank->target->state != TARGET_HALTED) {
2452 LOG_ERROR("Target not halted");
2453 return ERROR_TARGET_NOT_HALTED;
2454 }
2455
2456 private = get_sam4_bank_private(bank);
2457 if (!private) {
2458 LOG_ERROR("no private for this bank?");
2459 return ERROR_FAIL;
2460 }
2461 if (!(private->probed))
2462 return ERROR_FLASH_BANK_NOT_PROBED;
2463
2464 r = flashd_get_lock_bits(private, v);
2465 if (r != ERROR_OK) {
2466 LOG_DEBUG("Failed: %d", r);
2467 return r;
2468 }
2469
2470 for (x = 0; x < private->nsectors; x++)
2471 bank->sectors[x].is_protected = (!!(v[x >> 5] & (1 << (x % 32))));
2472 LOG_DEBUG("Done");
2473 return ERROR_OK;
2474 }
2475
2476 FLASH_BANK_COMMAND_HANDLER(sam4_flash_bank_command)
2477 {
2478 struct sam4_chip *chip;
2479
2480 chip = all_sam4_chips;
2481
2482 /* is this an existing chip? */
2483 while (chip) {
2484 if (chip->target == bank->target)
2485 break;
2486 chip = chip->next;
2487 }
2488
2489 if (!chip) {
2490 /* this is a *NEW* chip */
2491 chip = calloc(1, sizeof(struct sam4_chip));
2492 if (!chip) {
2493 LOG_ERROR("NO RAM!");
2494 return ERROR_FAIL;
2495 }
2496 chip->target = bank->target;
2497 /* insert at head */
2498 chip->next = all_sam4_chips;
2499 all_sam4_chips = chip;
2500 chip->target = bank->target;
2501 /* assumption is this runs at 32khz */
2502 chip->cfg.slow_freq = 32768;
2503 chip->probed = false;
2504 }
2505
2506 switch (bank->base) {
2507 default:
2508 LOG_ERROR("Address 0x%08x invalid bank address (try 0x%08x"
2509 "[at91sam4s series] )",
2510 ((unsigned int)(bank->base)),
2511 ((unsigned int)(FLASH_BANK_BASE_S)));
2512 return ERROR_FAIL;
2513
2514 /* at91sam4s series only has bank 0*/
2515 /* at91sam4sd series has the same address for bank 0 (FLASH_BANK0_BASE_SD)*/
2516 case FLASH_BANK_BASE_S:
2517 case FLASH_BANK_BASE_C:
2518 bank->driver_priv = &(chip->details.bank[0]);
2519 bank->bank_number = 0;
2520 chip->details.bank[0].chip = chip;
2521 chip->details.bank[0].bank = bank;
2522 break;
2523
2524 /* Bank 1 of at91sam4sd/at91sam4c32 series */
2525 case FLASH_BANK1_BASE_1024K_SD:
2526 case FLASH_BANK1_BASE_2048K_SD:
2527 case FLASH_BANK1_BASE_C32:
2528 bank->driver_priv = &(chip->details.bank[1]);
2529 bank->bank_number = 1;
2530 chip->details.bank[1].chip = chip;
2531 chip->details.bank[1].bank = bank;
2532 break;
2533 }
2534
2535 /* we initialize after probing. */
2536 return ERROR_OK;
2537 }
2538
2539 /**
2540 * Remove all chips from the internal list without distinguishing which one
2541 * is owned by this bank. This simplification works only for one shot
2542 * deallocation like current flash_free_all_banks()
2543 */
2544 static void sam4_free_driver_priv(struct flash_bank *bank)
2545 {
2546 struct sam4_chip *chip = all_sam4_chips;
2547 while (chip) {
2548 struct sam4_chip *next = chip->next;
2549 free(chip);
2550 chip = next;
2551 }
2552 all_sam4_chips = NULL;
2553 }
2554
2555 static int sam4_get_details(struct sam4_bank_private *private)
2556 {
2557 const struct sam4_chip_details *details;
2558 struct sam4_chip *chip;
2559 struct flash_bank *saved_banks[SAM4_MAX_FLASH_BANKS];
2560 unsigned x;
2561
2562 LOG_DEBUG("Begin");
2563 details = all_sam4_details;
2564 while (details->name) {
2565 /* Compare cidr without version bits */
2566 if (details->chipid_cidr == (private->chip->cfg.CHIPID_CIDR & 0xFFFFFFE0))
2567 break;
2568 else
2569 details++;
2570 }
2571 if (!details->name) {
2572 LOG_ERROR("SAM4 ChipID 0x%08x not found in table (perhaps you can ID this chip?)",
2573 (unsigned int)(private->chip->cfg.CHIPID_CIDR));
2574 /* Help the victim, print details about the chip */
2575 LOG_INFO("SAM4 CHIPID_CIDR: 0x%08" PRIx32 " decodes as follows",
2576 private->chip->cfg.CHIPID_CIDR);
2577 sam4_explain_chipid_cidr(private->chip);
2578 return ERROR_FAIL;
2579 } else {
2580 LOG_DEBUG("SAM4 Found chip %s, CIDR 0x%08" PRIx32, details->name, details->chipid_cidr);
2581 }
2582
2583 /* DANGER: THERE ARE DRAGONS HERE */
2584
2585 /* get our chip - it is going */
2586 /* to be over-written shortly */
2587 chip = private->chip;
2588
2589 /* Note that, in reality: */
2590 /* */
2591 /* private = &(chip->details.bank[0]) */
2592 /* or private = &(chip->details.bank[1]) */
2593 /* */
2594
2595 /* save the "bank" pointers */
2596 for (x = 0; x < SAM4_MAX_FLASH_BANKS; x++)
2597 saved_banks[x] = chip->details.bank[x].bank;
2598
2599 /* Overwrite the "details" structure. */
2600 memcpy(&(private->chip->details),
2601 details,
2602 sizeof(private->chip->details));
2603
2604 /* now fix the ghosted pointers */
2605 for (x = 0; x < SAM4_MAX_FLASH_BANKS; x++) {
2606 chip->details.bank[x].chip = chip;
2607 chip->details.bank[x].bank = saved_banks[x];
2608 }
2609
2610 /* update the *BANK*SIZE* */
2611
2612 LOG_DEBUG("End");
2613 return ERROR_OK;
2614 }
2615
2616 static int sam4_info(struct flash_bank *bank, struct command_invocation *cmd)
2617 {
2618 struct sam4_bank_private *private;
2619 int k = bank->size / 1024;
2620
2621 private = get_sam4_bank_private(bank);
2622 if (!private)
2623 return ERROR_FAIL;
2624
2625 command_print_sameline(cmd, "%s bank %d: %d kB at " TARGET_ADDR_FMT,
2626 private->chip->details.name,
2627 private->bank_number,
2628 k,
2629 bank->base);
2630
2631 return ERROR_OK;
2632 }
2633
2634 static int sam4_probe(struct flash_bank *bank)
2635 {
2636 int r;
2637 struct sam4_bank_private *private;
2638
2639
2640 LOG_DEBUG("Begin: Bank: %u", bank->bank_number);
2641 if (bank->target->state != TARGET_HALTED) {
2642 LOG_ERROR("Target not halted");
2643 return ERROR_TARGET_NOT_HALTED;
2644 }
2645
2646 private = get_sam4_bank_private(bank);
2647 if (!private) {
2648 LOG_ERROR("Invalid/unknown bank number");
2649 return ERROR_FAIL;
2650 }
2651
2652 r = sam4_read_all_regs(private->chip);
2653 if (r != ERROR_OK)
2654 return r;
2655
2656 LOG_DEBUG("Here");
2657 if (private->chip->probed)
2658 r = sam4_get_info(private->chip);
2659 else
2660 r = sam4_get_details(private);
2661 if (r != ERROR_OK)
2662 return r;
2663
2664 /* update the flash bank size */
2665 for (unsigned int x = 0; x < SAM4_MAX_FLASH_BANKS; x++) {
2666 if (bank->base == private->chip->details.bank[x].base_address) {
2667 bank->size = private->chip->details.bank[x].size_bytes;
2668 LOG_DEBUG("SAM4 Set flash bank to " TARGET_ADDR_FMT " - "
2669 TARGET_ADDR_FMT ", idx %d", bank->base,
2670 bank->base + bank->size, x);
2671 break;
2672 }
2673 }
2674
2675 if (!bank->sectors) {
2676 bank->sectors = calloc(private->nsectors, (sizeof((bank->sectors)[0])));
2677 if (!bank->sectors) {
2678 LOG_ERROR("No memory!");
2679 return ERROR_FAIL;
2680 }
2681 bank->num_sectors = private->nsectors;
2682
2683 for (unsigned int x = 0; x < bank->num_sectors; x++) {
2684 bank->sectors[x].size = private->sector_size;
2685 bank->sectors[x].offset = x * (private->sector_size);
2686 /* mark as unknown */
2687 bank->sectors[x].is_erased = -1;
2688 bank->sectors[x].is_protected = -1;
2689 }
2690 }
2691
2692 private->probed = true;
2693
2694 r = sam4_protect_check(bank);
2695 if (r != ERROR_OK)
2696 return r;
2697
2698 LOG_DEBUG("Bank = %d, nbanks = %d",
2699 private->bank_number, private->chip->details.n_banks);
2700 if ((private->bank_number + 1) == private->chip->details.n_banks) {
2701 /* read unique id, */
2702 /* it appears to be associated with the *last* flash bank. */
2703 flashd_read_uid(private);
2704 }
2705
2706 return r;
2707 }
2708
2709 static int sam4_auto_probe(struct flash_bank *bank)
2710 {
2711 struct sam4_bank_private *private;
2712
2713 private = get_sam4_bank_private(bank);
2714 if (private && private->probed)
2715 return ERROR_OK;
2716
2717 return sam4_probe(bank);
2718 }
2719
2720 static int sam4_erase(struct flash_bank *bank, unsigned int first,
2721 unsigned int last)
2722 {
2723 struct sam4_bank_private *private;
2724 int r;
2725 int page_count;
2726 /*16 pages equals 8KB - Same size as a lock region*/
2727 page_count = 16;
2728 uint32_t status;
2729
2730 LOG_DEBUG("Here");
2731 if (bank->target->state != TARGET_HALTED) {
2732 LOG_ERROR("Target not halted");
2733 return ERROR_TARGET_NOT_HALTED;
2734 }
2735
2736 r = sam4_auto_probe(bank);
2737 if (r != ERROR_OK) {
2738 LOG_DEBUG("Here,r=%d", r);
2739 return r;
2740 }
2741
2742 private = get_sam4_bank_private(bank);
2743 if (!(private->probed))
2744 return ERROR_FLASH_BANK_NOT_PROBED;
2745
2746 if ((first == 0) && ((last + 1) == private->nsectors)) {
2747 /* whole chip */
2748 LOG_DEBUG("Here");
2749 return flashd_erase_entire_bank(private);
2750 }
2751 LOG_INFO("sam4 does not auto-erase while programming (Erasing relevant sectors)");
2752 LOG_INFO("sam4 First: 0x%08x Last: 0x%08x", first, last);
2753 for (unsigned int i = first; i <= last; i++) {
2754 /*16 pages equals 8KB - Same size as a lock region*/
2755 r = flashd_erase_pages(private, (i * page_count), page_count, &status);
2756 LOG_INFO("Erasing sector: 0x%08x", i);
2757 if (r != ERROR_OK)
2758 LOG_ERROR("SAM4: Error performing Erase page @ lock region number %u",
2759 i);
2760 if (status & (1 << 2)) {
2761 LOG_ERROR("SAM4: Lock Region %u is locked", i);
2762 return ERROR_FAIL;
2763 }
2764 if (status & (1 << 1)) {
2765 LOG_ERROR("SAM4: Flash Command error @lock region %u", i);
2766 return ERROR_FAIL;
2767 }
2768 }
2769
2770 return ERROR_OK;
2771 }
2772
2773 static int sam4_protect(struct flash_bank *bank, int set, unsigned int first,
2774 unsigned int last)
2775 {
2776 struct sam4_bank_private *private;
2777 int r;
2778
2779 LOG_DEBUG("Here");
2780 if (bank->target->state != TARGET_HALTED) {
2781 LOG_ERROR("Target not halted");
2782 return ERROR_TARGET_NOT_HALTED;
2783 }
2784
2785 private = get_sam4_bank_private(bank);
2786 if (!(private->probed))
2787 return ERROR_FLASH_BANK_NOT_PROBED;
2788
2789 if (set)
2790 r = flashd_lock(private, first, last);
2791 else
2792 r = flashd_unlock(private, first, last);
2793 LOG_DEBUG("End: r=%d", r);
2794
2795 return r;
2796
2797 }
2798
2799 static int sam4_page_read(struct sam4_bank_private *private, unsigned pagenum, uint8_t *buf)
2800 {
2801 uint32_t adr;
2802 int r;
2803
2804 adr = pagenum * private->page_size;
2805 adr = adr + private->base_address;
2806
2807 r = target_read_memory(private->chip->target,
2808 adr,
2809 4, /* THIS*MUST*BE* in 32bit values */
2810 private->page_size / 4,
2811 buf);
2812 if (r != ERROR_OK)
2813 LOG_ERROR("SAM4: Flash program failed to read page phys address: 0x%08x",
2814 (unsigned int)(adr));
2815 return r;
2816 }
2817
2818 static int sam4_set_wait(struct sam4_bank_private *private)
2819 {
2820 uint32_t fmr; /* EEFC Flash Mode Register */
2821 int r;
2822
2823 /* Get flash mode register value */
2824 r = target_read_u32(private->chip->target, private->controller_address, &fmr);
2825 if (r != ERROR_OK) {
2826 LOG_ERROR("Error Read failed: read flash mode register");
2827 return r;
2828 }
2829
2830 /* Clear flash wait state field */
2831 fmr &= 0xfffff0ff;
2832
2833 /* set FWS (flash wait states) field in the FMR (flash mode register) */
2834 fmr |= (private->flash_wait_states << 8);
2835
2836 LOG_DEBUG("Flash Mode: 0x%08x", ((unsigned int)(fmr)));
2837 r = target_write_u32(private->bank->target, private->controller_address, fmr);
2838 if (r != ERROR_OK)
2839 LOG_ERROR("Error Write failed: set flash mode register");
2840
2841 return r;
2842 }
2843
2844 static int sam4_page_write(struct sam4_bank_private *private, unsigned pagenum, const uint8_t *buf)
2845 {
2846 uint32_t adr;
2847 uint32_t status;
2848 int r;
2849
2850 adr = pagenum * private->page_size;
2851 adr = (adr + private->base_address);
2852
2853 /* 1st sector 8kBytes - page 0 - 15*/
2854 /* 2nd sector 8kBytes - page 16 - 30*/
2855 /* 3rd sector 48kBytes - page 31 - 127*/
2856 LOG_DEBUG("Wr Page %u @ phys address: 0x%08x", pagenum, (unsigned int)(adr));
2857 r = target_write_memory(private->chip->target,
2858 adr,
2859 4, /* THIS*MUST*BE* in 32bit values */
2860 private->page_size / 4,
2861 buf);
2862 if (r != ERROR_OK) {
2863 LOG_ERROR("SAM4: Failed to write (buffer) page at phys address 0x%08x",
2864 (unsigned int)(adr));
2865 return r;
2866 }
2867
2868 r = efc_perform_command(private,
2869 /* send Erase & Write Page */
2870 AT91C_EFC_FCMD_WP, /*AT91C_EFC_FCMD_EWP only works on first two 8kb sectors*/
2871 pagenum,
2872 &status);
2873
2874 if (r != ERROR_OK)
2875 LOG_ERROR("SAM4: Error performing Write page @ phys address 0x%08x",
2876 (unsigned int)(adr));
2877 if (status & (1 << 2)) {
2878 LOG_ERROR("SAM4: Page @ Phys address 0x%08x is locked", (unsigned int)(adr));
2879 return ERROR_FAIL;
2880 }
2881 if (status & (1 << 1)) {
2882 LOG_ERROR("SAM4: Flash Command error @phys address 0x%08x", (unsigned int)(adr));
2883 return ERROR_FAIL;
2884 }
2885 return ERROR_OK;
2886 }
2887
2888 static int sam4_write(struct flash_bank *bank,
2889 const uint8_t *buffer,
2890 uint32_t offset,
2891 uint32_t count)
2892 {
2893 int n;
2894 unsigned page_cur;
2895 unsigned page_end;
2896 int r;
2897 unsigned page_offset;
2898 struct sam4_bank_private *private;
2899 uint8_t *pagebuffer;
2900
2901 /* in case we bail further below, set this to null */
2902 pagebuffer = NULL;
2903
2904 /* ignore dumb requests */
2905 if (count == 0) {
2906 r = ERROR_OK;
2907 goto done;
2908 }
2909
2910 if (bank->target->state != TARGET_HALTED) {
2911 LOG_ERROR("Target not halted");
2912 r = ERROR_TARGET_NOT_HALTED;
2913 goto done;
2914 }
2915
2916 private = get_sam4_bank_private(bank);
2917 if (!(private->probed)) {
2918 r = ERROR_FLASH_BANK_NOT_PROBED;
2919 goto done;
2920 }
2921
2922 if ((offset + count) > private->size_bytes) {
2923 LOG_ERROR("Flash write error - past end of bank");
2924 LOG_ERROR(" offset: 0x%08x, count 0x%08x, BankEnd: 0x%08x",
2925 (unsigned int)(offset),
2926 (unsigned int)(count),
2927 (unsigned int)(private->size_bytes));
2928 r = ERROR_FAIL;
2929 goto done;
2930 }
2931
2932 pagebuffer = malloc(private->page_size);
2933 if (!pagebuffer) {
2934 LOG_ERROR("No memory for %d Byte page buffer", (int)(private->page_size));
2935 r = ERROR_FAIL;
2936 goto done;
2937 }
2938
2939 r = sam4_set_wait(private);
2940 if (r != ERROR_OK)
2941 goto done;
2942
2943 /* what page do we start & end in? */
2944 page_cur = offset / private->page_size;
2945 page_end = (offset + count - 1) / private->page_size;
2946
2947 LOG_DEBUG("Offset: 0x%08x, Count: 0x%08x", (unsigned int)(offset), (unsigned int)(count));
2948 LOG_DEBUG("Page start: %d, Page End: %d", (int)(page_cur), (int)(page_end));
2949
2950 /* Special case: all one page */
2951 /* */
2952 /* Otherwise: */
2953 /* (1) non-aligned start */
2954 /* (2) body pages */
2955 /* (3) non-aligned end. */
2956
2957 /* Handle special case - all one page. */
2958 if (page_cur == page_end) {
2959 LOG_DEBUG("Special case, all in one page");
2960 r = sam4_page_read(private, page_cur, pagebuffer);
2961 if (r != ERROR_OK)
2962 goto done;
2963
2964 page_offset = (offset & (private->page_size-1));
2965 memcpy(pagebuffer + page_offset,
2966 buffer,
2967 count);
2968
2969 r = sam4_page_write(private, page_cur, pagebuffer);
2970 if (r != ERROR_OK)
2971 goto done;
2972 r = ERROR_OK;
2973 goto done;
2974 }
2975
2976 /* non-aligned start */
2977 page_offset = offset & (private->page_size - 1);
2978 if (page_offset) {
2979 LOG_DEBUG("Not-Aligned start");
2980 /* read the partial */
2981 r = sam4_page_read(private, page_cur, pagebuffer);
2982 if (r != ERROR_OK)
2983 goto done;
2984
2985 /* over-write with new data */
2986 n = (private->page_size - page_offset);
2987 memcpy(pagebuffer + page_offset,
2988 buffer,
2989 n);
2990
2991 r = sam4_page_write(private, page_cur, pagebuffer);
2992 if (r != ERROR_OK)
2993 goto done;
2994
2995 count -= n;
2996 offset += n;
2997 buffer += n;
2998 page_cur++;
2999 }
3000
3001 /* By checking that offset is correct here, we also
3002 fix a clang warning */
3003 assert(offset % private->page_size == 0);
3004
3005 /* intermediate large pages */
3006 /* also - the final *terminal* */
3007 /* if that terminal page is a full page */
3008 LOG_DEBUG("Full Page Loop: cur=%d, end=%d, count = 0x%08x",
3009 (int)page_cur, (int)page_end, (unsigned int)(count));
3010
3011 while ((page_cur < page_end) &&
3012 (count >= private->page_size)) {
3013 r = sam4_page_write(private, page_cur, buffer);
3014 if (r != ERROR_OK)
3015 goto done;
3016 count -= private->page_size;
3017 buffer += private->page_size;
3018 page_cur += 1;
3019 }
3020
3021 /* terminal partial page? */
3022 if (count) {
3023 LOG_DEBUG("Terminal partial page, count = 0x%08x", (unsigned int)(count));
3024 /* we have a partial page */
3025 r = sam4_page_read(private, page_cur, pagebuffer);
3026 if (r != ERROR_OK)
3027 goto done;
3028 /* data goes at start */
3029 memcpy(pagebuffer, buffer, count);
3030 r = sam4_page_write(private, page_cur, pagebuffer);
3031 if (r != ERROR_OK)
3032 goto done;
3033 }
3034 LOG_DEBUG("Done!");
3035 r = ERROR_OK;
3036 done:
3037 free(pagebuffer);
3038 return r;
3039 }
3040
3041 COMMAND_HANDLER(sam4_handle_info_command)
3042 {
3043 struct sam4_chip *chip;
3044 chip = get_current_sam4(CMD);
3045 if (!chip)
3046 return ERROR_OK;
3047
3048 unsigned x;
3049 int r;
3050
3051 /* bank0 must exist before we can do anything */
3052 if (!chip->details.bank[0].bank) {
3053 x = 0;
3054 need_define:
3055 command_print(CMD,
3056 "Please define bank %d via command: flash bank %s ... ",
3057 x,
3058 at91sam4_flash.name);
3059 return ERROR_FAIL;
3060 }
3061
3062 /* if bank 0 is not probed, then probe it */
3063 if (!(chip->details.bank[0].probed)) {
3064 r = sam4_auto_probe(chip->details.bank[0].bank);
3065 if (r != ERROR_OK)
3066 return ERROR_FAIL;
3067 }
3068 /* above guarantees the "chip details" structure is valid */
3069 /* and thus, bank private areas are valid */
3070 /* and we have a SAM4 chip, what a concept! */
3071
3072 /* auto-probe other banks, 0 done above */
3073 for (x = 1; x < SAM4_MAX_FLASH_BANKS; x++) {
3074 /* skip banks not present */
3075 if (!(chip->details.bank[x].present))
3076 continue;
3077
3078 if (!chip->details.bank[x].bank)
3079 goto need_define;
3080
3081 if (chip->details.bank[x].probed)
3082 continue;
3083
3084 r = sam4_auto_probe(chip->details.bank[x].bank);
3085 if (r != ERROR_OK)
3086 return r;
3087 }
3088
3089 r = sam4_get_info(chip);
3090 if (r != ERROR_OK) {
3091 LOG_DEBUG("Sam4Info, Failed %d", r);
3092 return r;
3093 }
3094
3095 return ERROR_OK;
3096 }
3097
3098 COMMAND_HANDLER(sam4_handle_gpnvm_command)
3099 {
3100 unsigned x, v;
3101 int r, who;
3102 struct sam4_chip *chip;
3103
3104 chip = get_current_sam4(CMD);
3105 if (!chip)
3106 return ERROR_OK;
3107
3108 if (chip->target->state != TARGET_HALTED) {
3109 LOG_ERROR("sam4 - target not halted");
3110 return ERROR_TARGET_NOT_HALTED;
3111 }
3112
3113 if (!chip->details.bank[0].bank) {
3114 command_print(CMD, "Bank0 must be defined first via: flash bank %s ...",
3115 at91sam4_flash.name);
3116 return ERROR_FAIL;
3117 }
3118 if (!chip->details.bank[0].probed) {
3119 r = sam4_auto_probe(chip->details.bank[0].bank);
3120 if (r != ERROR_OK)
3121 return r;
3122 }
3123
3124 switch (CMD_ARGC) {
3125 default:
3126 return ERROR_COMMAND_SYNTAX_ERROR;
3127 case 0:
3128 goto showall;
3129 case 1:
3130 who = -1;
3131 break;
3132 case 2:
3133 if ((strcmp(CMD_ARGV[0], "show") == 0) && (strcmp(CMD_ARGV[1], "all") == 0))
3134 who = -1;
3135 else {
3136 uint32_t v32;
3137 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], v32);
3138 who = v32;
3139 }
3140 break;
3141 }
3142
3143 if (strcmp("show", CMD_ARGV[0]) == 0) {
3144 if (who == -1) {
3145 showall:
3146 r = ERROR_OK;
3147 for (x = 0; x < chip->details.n_gpnvms; x++) {
3148 r = flashd_get_gpnvm(&(chip->details.bank[0]), x, &v);
3149 if (r != ERROR_OK)
3150 break;
3151 command_print(CMD, "sam4-gpnvm%u: %u", x, v);
3152 }
3153 return r;
3154 }
3155 if ((who >= 0) && (((unsigned)(who)) < chip->details.n_gpnvms)) {
3156 r = flashd_get_gpnvm(&(chip->details.bank[0]), who, &v);
3157 if (r == ERROR_OK)
3158 command_print(CMD, "sam4-gpnvm%u: %u", who, v);
3159 return r;
3160 } else {
3161 command_print(CMD, "sam4-gpnvm invalid GPNVM: %u", who);
3162 return ERROR_COMMAND_SYNTAX_ERROR;
3163 }
3164 }
3165
3166 if (who == -1) {
3167 command_print(CMD, "Missing GPNVM number");
3168 return ERROR_COMMAND_SYNTAX_ERROR;
3169 }
3170
3171 if (strcmp("set", CMD_ARGV[0]) == 0)
3172 r = flashd_set_gpnvm(&(chip->details.bank[0]), who);
3173 else if ((strcmp("clr", CMD_ARGV[0]) == 0) ||
3174 (strcmp("clear", CMD_ARGV[0]) == 0)) /* quietly accept both */
3175 r = flashd_clr_gpnvm(&(chip->details.bank[0]), who);
3176 else {
3177 command_print(CMD, "Unknown command: %s", CMD_ARGV[0]);
3178 r = ERROR_COMMAND_SYNTAX_ERROR;
3179 }
3180 return r;
3181 }
3182
3183 COMMAND_HANDLER(sam4_handle_slowclk_command)
3184 {
3185 struct sam4_chip *chip;
3186
3187 chip = get_current_sam4(CMD);
3188 if (!chip)
3189 return ERROR_OK;
3190
3191 switch (CMD_ARGC) {
3192 case 0:
3193 /* show */
3194 break;
3195 case 1:
3196 {
3197 /* set */
3198 uint32_t v;
3199 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], v);
3200 if (v > 200000) {
3201 /* absurd slow clock of 200Khz? */
3202 command_print(CMD, "Absurd/illegal slow clock freq: %d\n", (int)(v));
3203 return ERROR_COMMAND_SYNTAX_ERROR;
3204 }
3205 chip->cfg.slow_freq = v;
3206 break;
3207 }
3208 default:
3209 /* error */
3210 command_print(CMD, "Too many parameters");
3211 return ERROR_COMMAND_SYNTAX_ERROR;
3212 }
3213 command_print(CMD, "Slowclk freq: %d.%03dkhz",
3214 (int)(chip->cfg.slow_freq / 1000),
3215 (int)(chip->cfg.slow_freq % 1000));
3216 return ERROR_OK;
3217 }
3218
3219 static const struct command_registration at91sam4_exec_command_handlers[] = {
3220 {
3221 .name = "gpnvm",
3222 .handler = sam4_handle_gpnvm_command,
3223 .mode = COMMAND_EXEC,
3224 .usage = "[('clr'|'set'|'show') bitnum]",
3225 .help = "Without arguments, shows all bits in the gpnvm "
3226 "register. Otherwise, clears, sets, or shows one "
3227 "General Purpose Non-Volatile Memory (gpnvm) bit.",
3228 },
3229 {
3230 .name = "info",
3231 .handler = sam4_handle_info_command,
3232 .mode = COMMAND_EXEC,
3233 .help = "Print information about the current at91sam4 chip "
3234 "and its flash configuration.",
3235 .usage = "",
3236 },
3237 {
3238 .name = "slowclk",
3239 .handler = sam4_handle_slowclk_command,
3240 .mode = COMMAND_EXEC,
3241 .usage = "[clock_hz]",
3242 .help = "Display or set the slowclock frequency "
3243 "(default 32768 Hz).",
3244 },
3245 COMMAND_REGISTRATION_DONE
3246 };
3247 static const struct command_registration at91sam4_command_handlers[] = {
3248 {
3249 .name = "at91sam4",
3250 .mode = COMMAND_ANY,
3251 .help = "at91sam4 flash command group",
3252 .usage = "",
3253 .chain = at91sam4_exec_command_handlers,
3254 },
3255 COMMAND_REGISTRATION_DONE
3256 };
3257
3258 const struct flash_driver at91sam4_flash = {
3259 .name = "at91sam4",
3260 .commands = at91sam4_command_handlers,
3261 .flash_bank_command = sam4_flash_bank_command,
3262 .erase = sam4_erase,
3263 .protect = sam4_protect,
3264 .write = sam4_write,
3265 .read = default_flash_read,
3266 .probe = sam4_probe,
3267 .auto_probe = sam4_auto_probe,
3268 .erase_check = default_flash_blank_check,
3269 .protect_check = sam4_protect_check,
3270 .info = sam4_info,
3271 .free_driver_priv = sam4_free_driver_priv,
3272 };
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