1 // SPDX-License-Identifier: GPL-2.0-or-later
3 /***************************************************************************
4 * Copyright (C) 2013 by Andrey Yurovsky *
5 * Andrey Yurovsky <yurovsky@gmail.com> *
6 ***************************************************************************/
13 #include "helper/binarybuffer.h"
15 #include <helper/time_support.h>
16 #include <jtag/jtag.h>
17 #include <target/cortex_m.h>
19 #define SAMD_NUM_PROT_BLOCKS 16
20 #define SAMD_PAGE_SIZE_MAX 1024
22 #define SAMD_FLASH ((uint32_t)0x00000000) /* physical Flash memory */
23 #define SAMD_USER_ROW ((uint32_t)0x00804000) /* User Row of Flash */
24 #define SAMD_PAC1 0x41000000 /* Peripheral Access Control 1 */
25 #define SAMD_DSU 0x41002000 /* Device Service Unit */
26 #define SAMD_NVMCTRL 0x41004000 /* Non-volatile memory controller */
28 #define SAMD_DSU_STATUSA 1 /* DSU status register */
29 #define SAMD_DSU_DID 0x18 /* Device ID register */
30 #define SAMD_DSU_CTRL_EXT 0x100 /* CTRL register, external access */
32 #define SAMD_NVMCTRL_CTRLA 0x00 /* NVM control A register */
33 #define SAMD_NVMCTRL_CTRLB 0x04 /* NVM control B register */
34 #define SAMD_NVMCTRL_PARAM 0x08 /* NVM parameters register */
35 #define SAMD_NVMCTRL_INTFLAG 0x14 /* NVM Interrupt Flag Status & Clear */
36 #define SAMD_NVMCTRL_STATUS 0x18 /* NVM status register */
37 #define SAMD_NVMCTRL_ADDR 0x1C /* NVM address register */
38 #define SAMD_NVMCTRL_LOCK 0x20 /* NVM Lock section register */
40 #define SAMD_CMDEX_KEY 0xA5UL
41 #define SAMD_NVM_CMD(n) ((SAMD_CMDEX_KEY << 8) | (n & 0x7F))
43 /* NVMCTRL commands. See Table 20-4 in 42129F–SAM–10/2013 */
44 #define SAMD_NVM_CMD_ER 0x02 /* Erase Row */
45 #define SAMD_NVM_CMD_WP 0x04 /* Write Page */
46 #define SAMD_NVM_CMD_EAR 0x05 /* Erase Auxiliary Row */
47 #define SAMD_NVM_CMD_WAP 0x06 /* Write Auxiliary Page */
48 #define SAMD_NVM_CMD_LR 0x40 /* Lock Region */
49 #define SAMD_NVM_CMD_UR 0x41 /* Unlock Region */
50 #define SAMD_NVM_CMD_SPRM 0x42 /* Set Power Reduction Mode */
51 #define SAMD_NVM_CMD_CPRM 0x43 /* Clear Power Reduction Mode */
52 #define SAMD_NVM_CMD_PBC 0x44 /* Page Buffer Clear */
53 #define SAMD_NVM_CMD_SSB 0x45 /* Set Security Bit */
54 #define SAMD_NVM_CMD_INVALL 0x46 /* Invalidate all caches */
57 #define SAMD_NVM_CTRLB_MANW 0x80
59 /* NVMCTRL_INTFLAG bits */
60 #define SAMD_NVM_INTFLAG_READY 0x01
62 /* Known identifiers */
63 #define SAMD_PROCESSOR_M0 0x01
64 #define SAMD_FAMILY_D 0x00
65 #define SAMD_FAMILY_L 0x01
66 #define SAMD_FAMILY_C 0x02
67 #define SAMD_SERIES_20 0x00
68 #define SAMD_SERIES_21 0x01
69 #define SAMD_SERIES_22 0x02
70 #define SAMD_SERIES_10 0x02
71 #define SAMD_SERIES_11 0x03
72 #define SAMD_SERIES_09 0x04
74 /* Device ID macros */
75 #define SAMD_GET_PROCESSOR(id) (id >> 28)
76 #define SAMD_GET_FAMILY(id) (((id >> 23) & 0x1F))
77 #define SAMD_GET_SERIES(id) (((id >> 16) & 0x3F))
78 #define SAMD_GET_DEVSEL(id) (id & 0xFF)
80 /* Bits to mask out lockbits in user row */
81 #define NVMUSERROW_LOCKBIT_MASK 0x0000FFFFFFFFFFFFULL
90 /* Known SAMD09 parts. DID reset values missing in RM, see
91 * https://github.com/avrxml/asf/blob/master/sam0/utils/cmsis/samd09/include/ */
92 static const struct samd_part samd09_parts
[] = {
93 { 0x0, "SAMD09D14A", 16, 4 },
94 { 0x7, "SAMD09C13A", 8, 4 },
97 /* Known SAMD10 parts */
98 static const struct samd_part samd10_parts
[] = {
99 { 0x0, "SAMD10D14AMU", 16, 4 },
100 { 0x1, "SAMD10D13AMU", 8, 4 },
101 { 0x2, "SAMD10D12AMU", 4, 4 },
102 { 0x3, "SAMD10D14ASU", 16, 4 },
103 { 0x4, "SAMD10D13ASU", 8, 4 },
104 { 0x5, "SAMD10D12ASU", 4, 4 },
105 { 0x6, "SAMD10C14A", 16, 4 },
106 { 0x7, "SAMD10C13A", 8, 4 },
107 { 0x8, "SAMD10C12A", 4, 4 },
110 /* Known SAMD11 parts */
111 static const struct samd_part samd11_parts
[] = {
112 { 0x0, "SAMD11D14AM", 16, 4 },
113 { 0x1, "SAMD11D13AMU", 8, 4 },
114 { 0x2, "SAMD11D12AMU", 4, 4 },
115 { 0x3, "SAMD11D14ASS", 16, 4 },
116 { 0x4, "SAMD11D13ASU", 8, 4 },
117 { 0x5, "SAMD11D12ASU", 4, 4 },
118 { 0x6, "SAMD11C14A", 16, 4 },
119 { 0x7, "SAMD11C13A", 8, 4 },
120 { 0x8, "SAMD11C12A", 4, 4 },
121 { 0x9, "SAMD11D14AU", 16, 4 },
124 /* Known SAMD20 parts. See Table 12-8 in 42129F–SAM–10/2013 */
125 static const struct samd_part samd20_parts
[] = {
126 { 0x0, "SAMD20J18A", 256, 32 },
127 { 0x1, "SAMD20J17A", 128, 16 },
128 { 0x2, "SAMD20J16A", 64, 8 },
129 { 0x3, "SAMD20J15A", 32, 4 },
130 { 0x4, "SAMD20J14A", 16, 2 },
131 { 0x5, "SAMD20G18A", 256, 32 },
132 { 0x6, "SAMD20G17A", 128, 16 },
133 { 0x7, "SAMD20G16A", 64, 8 },
134 { 0x8, "SAMD20G15A", 32, 4 },
135 { 0x9, "SAMD20G14A", 16, 2 },
136 { 0xA, "SAMD20E18A", 256, 32 },
137 { 0xB, "SAMD20E17A", 128, 16 },
138 { 0xC, "SAMD20E16A", 64, 8 },
139 { 0xD, "SAMD20E15A", 32, 4 },
140 { 0xE, "SAMD20E14A", 16, 2 },
143 /* Known SAMD21 parts. */
144 static const struct samd_part samd21_parts
[] = {
145 { 0x0, "SAMD21J18A", 256, 32 },
146 { 0x1, "SAMD21J17A", 128, 16 },
147 { 0x2, "SAMD21J16A", 64, 8 },
148 { 0x3, "SAMD21J15A", 32, 4 },
149 { 0x4, "SAMD21J14A", 16, 2 },
150 { 0x5, "SAMD21G18A", 256, 32 },
151 { 0x6, "SAMD21G17A", 128, 16 },
152 { 0x7, "SAMD21G16A", 64, 8 },
153 { 0x8, "SAMD21G15A", 32, 4 },
154 { 0x9, "SAMD21G14A", 16, 2 },
155 { 0xA, "SAMD21E18A", 256, 32 },
156 { 0xB, "SAMD21E17A", 128, 16 },
157 { 0xC, "SAMD21E16A", 64, 8 },
158 { 0xD, "SAMD21E15A", 32, 4 },
159 { 0xE, "SAMD21E14A", 16, 2 },
161 /* SAMR21 parts have integrated SAMD21 with a radio */
162 { 0x18, "SAMR21G19A", 256, 32 }, /* with 512k of serial flash */
163 { 0x19, "SAMR21G18A", 256, 32 },
164 { 0x1A, "SAMR21G17A", 128, 32 },
165 { 0x1B, "SAMR21G16A", 64, 16 },
166 { 0x1C, "SAMR21E18A", 256, 32 },
167 { 0x1D, "SAMR21E17A", 128, 32 },
168 { 0x1E, "SAMR21E16A", 64, 16 },
170 /* SAMD21 B Variants (Table 3-7 from rev I of datasheet) */
171 { 0x20, "SAMD21J16B", 64, 8 },
172 { 0x21, "SAMD21J15B", 32, 4 },
173 { 0x23, "SAMD21G16B", 64, 8 },
174 { 0x24, "SAMD21G15B", 32, 4 },
175 { 0x26, "SAMD21E16B", 64, 8 },
176 { 0x27, "SAMD21E15B", 32, 4 },
178 /* SAMD21 D and L Variants (from Errata)
179 http://ww1.microchip.com/downloads/en/DeviceDoc/
180 SAM-D21-Family-Silicon-Errata-and-DataSheet-Clarification-DS80000760D.pdf */
181 { 0x55, "SAMD21E16BU", 64, 8 },
182 { 0x56, "SAMD21E15BU", 32, 4 },
183 { 0x57, "SAMD21G16L", 64, 8 },
184 { 0x3E, "SAMD21E16L", 64, 8 },
185 { 0x3F, "SAMD21E15L", 32, 4 },
186 { 0x62, "SAMD21E16CU", 64, 8 },
187 { 0x63, "SAMD21E15CU", 32, 4 },
188 { 0x92, "SAMD21J17D", 128, 16 },
189 { 0x93, "SAMD21G17D", 128, 16 },
190 { 0x94, "SAMD21E17D", 128, 16 },
191 { 0x95, "SAMD21E17DU", 128, 16 },
192 { 0x96, "SAMD21G17L", 128, 16 },
193 { 0x97, "SAMD21E17L", 128, 16 },
195 /* Known SAMDA1 parts.
196 SAMD-A1 series uses the same series identifier like the SAMD21
197 taken from http://ww1.microchip.com/downloads/en/DeviceDoc/40001895A.pdf (pages 14-17) */
198 { 0x29, "SAMDA1J16A", 64, 8 },
199 { 0x2A, "SAMDA1J15A", 32, 4 },
200 { 0x2B, "SAMDA1J14A", 16, 4 },
201 { 0x2C, "SAMDA1G16A", 64, 8 },
202 { 0x2D, "SAMDA1G15A", 32, 4 },
203 { 0x2E, "SAMDA1G14A", 16, 4 },
204 { 0x2F, "SAMDA1E16A", 64, 8 },
205 { 0x30, "SAMDA1E15A", 32, 4 },
206 { 0x31, "SAMDA1E14A", 16, 4 },
207 { 0x64, "SAMDA1J16B", 64, 8 },
208 { 0x65, "SAMDA1J15B", 32, 4 },
209 { 0x66, "SAMDA1J14B", 16, 4 },
210 { 0x67, "SAMDA1G16B", 64, 8 },
211 { 0x68, "SAMDA1G15B", 32, 4 },
212 { 0x69, "SAMDA1G14B", 16, 4 },
213 { 0x6A, "SAMDA1E16B", 64, 8 },
214 { 0x6B, "SAMDA1E15B", 32, 4 },
215 { 0x6C, "SAMDA1E14B", 16, 4 },
218 /* Known SAML21 parts. */
219 static const struct samd_part saml21_parts
[] = {
220 { 0x00, "SAML21J18A", 256, 32 },
221 { 0x01, "SAML21J17A", 128, 16 },
222 { 0x02, "SAML21J16A", 64, 8 },
223 { 0x05, "SAML21G18A", 256, 32 },
224 { 0x06, "SAML21G17A", 128, 16 },
225 { 0x07, "SAML21G16A", 64, 8 },
226 { 0x0A, "SAML21E18A", 256, 32 },
227 { 0x0B, "SAML21E17A", 128, 16 },
228 { 0x0C, "SAML21E16A", 64, 8 },
229 { 0x0D, "SAML21E15A", 32, 4 },
230 { 0x0F, "SAML21J18B", 256, 32 },
231 { 0x10, "SAML21J17B", 128, 16 },
232 { 0x11, "SAML21J16B", 64, 8 },
233 { 0x14, "SAML21G18B", 256, 32 },
234 { 0x15, "SAML21G17B", 128, 16 },
235 { 0x16, "SAML21G16B", 64, 8 },
236 { 0x19, "SAML21E18B", 256, 32 },
237 { 0x1A, "SAML21E17B", 128, 16 },
238 { 0x1B, "SAML21E16B", 64, 8 },
239 { 0x1C, "SAML21E15B", 32, 4 },
241 /* SAMR30 parts have integrated SAML21 with a radio */
242 { 0x1E, "SAMR30G18A", 256, 32 },
243 { 0x1F, "SAMR30E18A", 256, 32 },
245 /* SAMR34/R35 parts have integrated SAML21 with a lora radio */
246 { 0x28, "SAMR34J18", 256, 40 },
247 { 0x29, "SAMR34J17", 128, 24 },
248 { 0x2A, "SAMR34J16", 64, 12 },
249 { 0x2B, "SAMR35J18", 256, 40 },
250 { 0x2C, "SAMR35J17", 128, 24 },
251 { 0x2D, "SAMR35J16", 64, 12 },
254 /* Known SAML22 parts. */
255 static const struct samd_part saml22_parts
[] = {
256 { 0x00, "SAML22N18A", 256, 32 },
257 { 0x01, "SAML22N17A", 128, 16 },
258 { 0x02, "SAML22N16A", 64, 8 },
259 { 0x05, "SAML22J18A", 256, 32 },
260 { 0x06, "SAML22J17A", 128, 16 },
261 { 0x07, "SAML22J16A", 64, 8 },
262 { 0x0A, "SAML22G18A", 256, 32 },
263 { 0x0B, "SAML22G17A", 128, 16 },
264 { 0x0C, "SAML22G16A", 64, 8 },
267 /* Known SAMC20 parts. */
268 static const struct samd_part samc20_parts
[] = {
269 { 0x00, "SAMC20J18A", 256, 32 },
270 { 0x01, "SAMC20J17A", 128, 16 },
271 { 0x02, "SAMC20J16A", 64, 8 },
272 { 0x03, "SAMC20J15A", 32, 4 },
273 { 0x05, "SAMC20G18A", 256, 32 },
274 { 0x06, "SAMC20G17A", 128, 16 },
275 { 0x07, "SAMC20G16A", 64, 8 },
276 { 0x08, "SAMC20G15A", 32, 4 },
277 { 0x0A, "SAMC20E18A", 256, 32 },
278 { 0x0B, "SAMC20E17A", 128, 16 },
279 { 0x0C, "SAMC20E16A", 64, 8 },
280 { 0x0D, "SAMC20E15A", 32, 4 },
281 { 0x20, "SAMC20N18A", 256, 32 },
282 { 0x21, "SAMC20N17A", 128, 16 },
285 /* Known SAMC21 parts. */
286 static const struct samd_part samc21_parts
[] = {
287 { 0x00, "SAMC21J18A", 256, 32 },
288 { 0x01, "SAMC21J17A", 128, 16 },
289 { 0x02, "SAMC21J16A", 64, 8 },
290 { 0x03, "SAMC21J15A", 32, 4 },
291 { 0x05, "SAMC21G18A", 256, 32 },
292 { 0x06, "SAMC21G17A", 128, 16 },
293 { 0x07, "SAMC21G16A", 64, 8 },
294 { 0x08, "SAMC21G15A", 32, 4 },
295 { 0x0A, "SAMC21E18A", 256, 32 },
296 { 0x0B, "SAMC21E17A", 128, 16 },
297 { 0x0C, "SAMC21E16A", 64, 8 },
298 { 0x0D, "SAMC21E15A", 32, 4 },
299 { 0x20, "SAMC21N18A", 256, 32 },
300 { 0x21, "SAMC21N17A", 128, 16 },
303 /* Each family of parts contains a parts table in the DEVSEL field of DID. The
304 * processor ID, family ID, and series ID are used to determine which exact
305 * family this is and then we can use the corresponding table. */
310 const struct samd_part
*parts
;
312 uint64_t nvm_userrow_res_mask
; /* protect bits which are reserved, 0 -> protect */
315 /* Known SAMD families */
316 static const struct samd_family samd_families
[] = {
317 { SAMD_PROCESSOR_M0
, SAMD_FAMILY_D
, SAMD_SERIES_20
,
318 samd20_parts
, ARRAY_SIZE(samd20_parts
),
319 0xFFFF01FFFE01FF77ULL
},
320 { SAMD_PROCESSOR_M0
, SAMD_FAMILY_D
, SAMD_SERIES_21
,
321 samd21_parts
, ARRAY_SIZE(samd21_parts
),
322 0xFFFF01FFFE01FF77ULL
},
323 { SAMD_PROCESSOR_M0
, SAMD_FAMILY_D
, SAMD_SERIES_09
,
324 samd09_parts
, ARRAY_SIZE(samd09_parts
),
325 0xFFFF01FFFE01FF77ULL
},
326 { SAMD_PROCESSOR_M0
, SAMD_FAMILY_D
, SAMD_SERIES_10
,
327 samd10_parts
, ARRAY_SIZE(samd10_parts
),
328 0xFFFF01FFFE01FF77ULL
},
329 { SAMD_PROCESSOR_M0
, SAMD_FAMILY_D
, SAMD_SERIES_11
,
330 samd11_parts
, ARRAY_SIZE(samd11_parts
),
331 0xFFFF01FFFE01FF77ULL
},
332 { SAMD_PROCESSOR_M0
, SAMD_FAMILY_L
, SAMD_SERIES_21
,
333 saml21_parts
, ARRAY_SIZE(saml21_parts
),
334 0xFFFF03FFFC01FF77ULL
},
335 { SAMD_PROCESSOR_M0
, SAMD_FAMILY_L
, SAMD_SERIES_22
,
336 saml22_parts
, ARRAY_SIZE(saml22_parts
),
337 0xFFFF03FFFC01FF77ULL
},
338 { SAMD_PROCESSOR_M0
, SAMD_FAMILY_C
, SAMD_SERIES_20
,
339 samc20_parts
, ARRAY_SIZE(samc20_parts
),
340 0xFFFF03FFFC01FF77ULL
},
341 { SAMD_PROCESSOR_M0
, SAMD_FAMILY_C
, SAMD_SERIES_21
,
342 samc21_parts
, ARRAY_SIZE(samc21_parts
),
343 0xFFFF03FFFC01FF77ULL
},
353 struct target
*target
;
358 * Gives the family structure to specific device id.
359 * @param id The id of the device.
360 * @return On failure NULL, otherwise a pointer to the structure.
362 static const struct samd_family
*samd_find_family(uint32_t id
)
364 uint8_t processor
= SAMD_GET_PROCESSOR(id
);
365 uint8_t family
= SAMD_GET_FAMILY(id
);
366 uint8_t series
= SAMD_GET_SERIES(id
);
368 for (unsigned i
= 0; i
< ARRAY_SIZE(samd_families
); i
++) {
369 if (samd_families
[i
].processor
== processor
&&
370 samd_families
[i
].series
== series
&&
371 samd_families
[i
].family
== family
)
372 return &samd_families
[i
];
379 * Gives the part structure to specific device id.
380 * @param id The id of the device.
381 * @return On failure NULL, otherwise a pointer to the structure.
383 static const struct samd_part
*samd_find_part(uint32_t id
)
385 uint8_t devsel
= SAMD_GET_DEVSEL(id
);
386 const struct samd_family
*family
= samd_find_family(id
);
390 for (unsigned i
= 0; i
< family
->num_parts
; i
++) {
391 if (family
->parts
[i
].id
== devsel
)
392 return &family
->parts
[i
];
398 static int samd_protect_check(struct flash_bank
*bank
)
403 res
= target_read_u16(bank
->target
,
404 SAMD_NVMCTRL
+ SAMD_NVMCTRL_LOCK
, &lock
);
408 /* Lock bits are active-low */
409 for (unsigned int prot_block
= 0; prot_block
< bank
->num_prot_blocks
; prot_block
++)
410 bank
->prot_blocks
[prot_block
].is_protected
= !(lock
& (1u<<prot_block
));
415 static int samd_get_flash_page_info(struct target
*target
,
416 uint32_t *sizep
, int *nump
)
421 res
= target_read_u32(target
, SAMD_NVMCTRL
+ SAMD_NVMCTRL_PARAM
, ¶m
);
422 if (res
== ERROR_OK
) {
423 /* The PSZ field (bits 18:16) indicate the page size bytes as 2^(3+n)
424 * so 0 is 8KB and 7 is 1024KB. */
426 *sizep
= (8 << ((param
>> 16) & 0x7));
427 /* The NVMP field (bits 15:0) indicates the total number of pages */
429 *nump
= param
& 0xFFFF;
431 LOG_ERROR("Couldn't read NVM Parameters register");
437 static int samd_probe(struct flash_bank
*bank
)
441 struct samd_info
*chip
= (struct samd_info
*)bank
->driver_priv
;
442 const struct samd_part
*part
;
447 res
= target_read_u32(bank
->target
, SAMD_DSU
+ SAMD_DSU_DID
, &id
);
448 if (res
!= ERROR_OK
) {
449 LOG_ERROR("Couldn't read Device ID register");
453 part
= samd_find_part(id
);
455 LOG_ERROR("Couldn't find part corresponding to DID %08" PRIx32
, id
);
459 bank
->size
= part
->flash_kb
* 1024;
461 res
= samd_get_flash_page_info(bank
->target
, &chip
->page_size
,
463 if (res
!= ERROR_OK
) {
464 LOG_ERROR("Couldn't determine Flash page size");
468 /* Sanity check: the total flash size in the DSU should match the page size
469 * multiplied by the number of pages. */
470 if (bank
->size
!= chip
->num_pages
* chip
->page_size
) {
471 LOG_WARNING("SAMD: bank size doesn't match NVM parameters. "
472 "Identified %" PRIu32
"KB Flash but NVMCTRL reports %u %" PRIu32
"B pages",
473 part
->flash_kb
, chip
->num_pages
, chip
->page_size
);
476 /* Erase granularity = 1 row = 4 pages */
477 chip
->sector_size
= chip
->page_size
* 4;
479 /* Allocate the sector table */
480 bank
->num_sectors
= chip
->num_pages
/ 4;
481 bank
->sectors
= alloc_block_array(0, chip
->sector_size
, bank
->num_sectors
);
485 /* 16 protection blocks per device */
486 chip
->prot_block_size
= bank
->size
/ SAMD_NUM_PROT_BLOCKS
;
488 /* Allocate the table of protection blocks */
489 bank
->num_prot_blocks
= SAMD_NUM_PROT_BLOCKS
;
490 bank
->prot_blocks
= alloc_block_array(0, chip
->prot_block_size
, bank
->num_prot_blocks
);
491 if (!bank
->prot_blocks
)
494 samd_protect_check(bank
);
499 LOG_INFO("SAMD MCU: %s (%" PRIu32
"KB Flash, %" PRIu32
"KB RAM)", part
->name
,
500 part
->flash_kb
, part
->ram_kb
);
505 static int samd_check_error(struct target
*target
)
510 int timeout_ms
= 1000;
511 int64_t ts_start
= timeval_ms();
514 ret
= target_read_u8(target
,
515 SAMD_NVMCTRL
+ SAMD_NVMCTRL_INTFLAG
, &intflag
);
516 if (ret
!= ERROR_OK
) {
517 LOG_ERROR("Can't read NVM intflag");
520 if (intflag
& SAMD_NVM_INTFLAG_READY
)
523 } while (timeval_ms() - ts_start
< timeout_ms
);
525 if (!(intflag
& SAMD_NVM_INTFLAG_READY
)) {
526 LOG_ERROR("SAMD: NVM programming timed out");
527 return ERROR_FLASH_OPERATION_FAILED
;
530 ret
= target_read_u16(target
,
531 SAMD_NVMCTRL
+ SAMD_NVMCTRL_STATUS
, &status
);
532 if (ret
!= ERROR_OK
) {
533 LOG_ERROR("Can't read NVM status");
537 if ((status
& 0x001C) == 0)
540 if (status
& (1 << 4)) { /* NVME */
541 LOG_ERROR("SAMD: NVM Error");
542 ret
= ERROR_FLASH_OPERATION_FAILED
;
545 if (status
& (1 << 3)) { /* LOCKE */
546 LOG_ERROR("SAMD: NVM lock error");
547 ret
= ERROR_FLASH_PROTECTED
;
550 if (status
& (1 << 2)) { /* PROGE */
551 LOG_ERROR("SAMD: NVM programming error");
552 ret
= ERROR_FLASH_OPER_UNSUPPORTED
;
555 /* Clear the error conditions by writing a one to them */
556 ret2
= target_write_u16(target
,
557 SAMD_NVMCTRL
+ SAMD_NVMCTRL_STATUS
, status
);
558 if (ret2
!= ERROR_OK
)
559 LOG_ERROR("Can't clear NVM error conditions");
564 static int samd_issue_nvmctrl_command(struct target
*target
, uint16_t cmd
)
568 if (target
->state
!= TARGET_HALTED
) {
569 LOG_ERROR("Target not halted");
570 return ERROR_TARGET_NOT_HALTED
;
573 /* Issue the NVM command */
574 /* 32-bit write is used to ensure atomic operation on ST-Link */
575 res
= target_write_u32(target
,
576 SAMD_NVMCTRL
+ SAMD_NVMCTRL_CTRLA
, SAMD_NVM_CMD(cmd
));
580 /* Check to see if the NVM command resulted in an error condition. */
581 return samd_check_error(target
);
585 * Erases a flash-row at the given address.
586 * @param target Pointer to the target structure.
587 * @param address The address of the row.
588 * @return On success ERROR_OK, on failure an errorcode.
590 static int samd_erase_row(struct target
*target
, uint32_t address
)
594 /* Set an address contained in the row to be erased */
595 res
= target_write_u32(target
,
596 SAMD_NVMCTRL
+ SAMD_NVMCTRL_ADDR
, address
>> 1);
598 /* Issue the Erase Row command to erase that row. */
600 res
= samd_issue_nvmctrl_command(target
,
601 address
== SAMD_USER_ROW
? SAMD_NVM_CMD_EAR
: SAMD_NVM_CMD_ER
);
603 if (res
!= ERROR_OK
) {
604 LOG_ERROR("Failed to erase row containing %08" PRIx32
, address
);
612 * Returns the bitmask of reserved bits in register.
613 * @param target Pointer to the target structure.
614 * @param mask Bitmask, 0 -> value stays untouched.
615 * @return On success ERROR_OK, on failure an errorcode.
617 static int samd_get_reservedmask(struct target
*target
, uint64_t *mask
)
620 /* Get the devicetype */
622 res
= target_read_u32(target
, SAMD_DSU
+ SAMD_DSU_DID
, &id
);
623 if (res
!= ERROR_OK
) {
624 LOG_ERROR("Couldn't read Device ID register");
627 const struct samd_family
*family
;
628 family
= samd_find_family(id
);
630 LOG_ERROR("Couldn't determine device family");
633 *mask
= family
->nvm_userrow_res_mask
;
637 static int read_userrow(struct target
*target
, uint64_t *userrow
)
642 res
= target_read_memory(target
, SAMD_USER_ROW
, 4, 2, buffer
);
646 *userrow
= target_buffer_get_u64(target
, buffer
);
651 * Modify the contents of the User Row in Flash. The User Row itself
652 * has a size of one page and contains a combination of "fuses" and
653 * calibration data. Bits which have a value of zero in the mask will
654 * not be changed. Up to now devices only use the first 64 bits.
655 * @param target Pointer to the target structure.
656 * @param value_input The value to write.
657 * @param value_mask Bitmask, 0 -> value stays untouched.
658 * @return On success ERROR_OK, on failure an errorcode.
660 static int samd_modify_user_row_masked(struct target
*target
,
661 uint64_t value_input
, uint64_t value_mask
)
665 bool manual_wp
= true;
667 /* Retrieve the MCU's page size, in bytes. This is also the size of the
668 * entire User Row. */
670 res
= samd_get_flash_page_info(target
, &page_size
, NULL
);
671 if (res
!= ERROR_OK
) {
672 LOG_ERROR("Couldn't determine Flash page size");
676 /* Make sure the size is sane. */
677 assert(page_size
<= SAMD_PAGE_SIZE_MAX
&&
678 page_size
>= sizeof(value_input
));
680 uint8_t buf
[SAMD_PAGE_SIZE_MAX
];
681 /* Read the user row (comprising one page) by words. */
682 res
= target_read_memory(target
, SAMD_USER_ROW
, 4, page_size
/ 4, buf
);
686 uint64_t value_device
;
687 res
= read_userrow(target
, &value_device
);
690 uint64_t value_new
= (value_input
& value_mask
) | (value_device
& ~value_mask
);
692 /* We will need to erase before writing if the new value needs a '1' in any
693 * position for which the current value had a '0'. Otherwise we can avoid
695 if ((~value_device
) & value_new
) {
696 res
= samd_erase_row(target
, SAMD_USER_ROW
);
697 if (res
!= ERROR_OK
) {
698 LOG_ERROR("Couldn't erase user row");
704 target_buffer_set_u64(target
, buf
, value_new
);
706 /* Write the page buffer back out to the target. */
707 res
= target_write_memory(target
, SAMD_USER_ROW
, 4, page_size
/ 4, buf
);
711 /* Check if we need to do manual page write commands */
712 res
= target_read_u32(target
, SAMD_NVMCTRL
+ SAMD_NVMCTRL_CTRLB
, &nvm_ctrlb
);
714 manual_wp
= (nvm_ctrlb
& SAMD_NVM_CTRLB_MANW
) != 0;
716 LOG_ERROR("Read of NVM register CTRKB failed.");
720 /* Trigger flash write */
721 res
= samd_issue_nvmctrl_command(target
, SAMD_NVM_CMD_WAP
);
723 res
= samd_check_error(target
);
730 * Modifies the user row register to the given value.
731 * @param target Pointer to the target structure.
732 * @param value The value to write.
733 * @param startb The bit-offset by which the given value is shifted.
734 * @param endb The bit-offset of the last bit in value to write.
735 * @return On success ERROR_OK, on failure an errorcode.
737 static int samd_modify_user_row(struct target
*target
, uint64_t value
,
738 uint8_t startb
, uint8_t endb
)
742 for (i
= startb
; i
<= endb
; i
++)
743 mask
|= ((uint64_t)1) << i
;
745 return samd_modify_user_row_masked(target
, value
<< startb
, mask
);
748 static int samd_protect(struct flash_bank
*bank
, int set
,
749 unsigned int first
, unsigned int last
)
753 /* We can issue lock/unlock region commands with the target running but
754 * the settings won't persist unless we're able to modify the LOCK regions
755 * and that requires the target to be halted. */
756 if (bank
->target
->state
!= TARGET_HALTED
) {
757 LOG_ERROR("Target not halted");
758 return ERROR_TARGET_NOT_HALTED
;
761 for (unsigned int prot_block
= first
; prot_block
<= last
; prot_block
++) {
762 if (set
!= bank
->prot_blocks
[prot_block
].is_protected
) {
763 /* Load an address that is within this protection block (we use offset 0) */
764 res
= target_write_u32(bank
->target
,
765 SAMD_NVMCTRL
+ SAMD_NVMCTRL_ADDR
,
766 bank
->prot_blocks
[prot_block
].offset
>> 1);
770 /* Tell the controller to lock that block */
771 res
= samd_issue_nvmctrl_command(bank
->target
,
772 set
? SAMD_NVM_CMD_LR
: SAMD_NVM_CMD_UR
);
778 /* We've now applied our changes, however they will be undone by the next
779 * reset unless we also apply them to the LOCK bits in the User Page. The
780 * LOCK bits start at bit 48, corresponding to Sector 0 and end with bit 63,
781 * corresponding to Sector 15. A '1' means unlocked and a '0' means
782 * locked. See Table 9-3 in the SAMD20 datasheet for more details. */
784 res
= samd_modify_user_row(bank
->target
,
785 set
? (uint64_t)0 : (uint64_t)UINT64_MAX
,
786 48 + first
, 48 + last
);
788 LOG_WARNING("SAMD: protect settings were not made persistent!");
793 samd_protect_check(bank
);
798 static int samd_erase(struct flash_bank
*bank
, unsigned int first
,
802 struct samd_info
*chip
= (struct samd_info
*)bank
->driver_priv
;
804 if (bank
->target
->state
!= TARGET_HALTED
) {
805 LOG_ERROR("Target not halted");
807 return ERROR_TARGET_NOT_HALTED
;
811 if (samd_probe(bank
) != ERROR_OK
)
812 return ERROR_FLASH_BANK_NOT_PROBED
;
815 /* For each sector to be erased */
816 for (unsigned int s
= first
; s
<= last
; s
++) {
817 res
= samd_erase_row(bank
->target
, bank
->sectors
[s
].offset
);
818 if (res
!= ERROR_OK
) {
819 LOG_ERROR("SAMD: failed to erase sector %d at 0x%08" PRIx32
, s
, bank
->sectors
[s
].offset
);
828 static int samd_write(struct flash_bank
*bank
, const uint8_t *buffer
,
829 uint32_t offset
, uint32_t count
)
837 struct samd_info
*chip
= (struct samd_info
*)bank
->driver_priv
;
841 if (bank
->target
->state
!= TARGET_HALTED
) {
842 LOG_ERROR("Target not halted");
843 return ERROR_TARGET_NOT_HALTED
;
847 if (samd_probe(bank
) != ERROR_OK
)
848 return ERROR_FLASH_BANK_NOT_PROBED
;
851 /* Check if we need to do manual page write commands */
852 res
= target_read_u32(bank
->target
, SAMD_NVMCTRL
+ SAMD_NVMCTRL_CTRLB
, &nvm_ctrlb
);
857 if (nvm_ctrlb
& SAMD_NVM_CTRLB_MANW
)
862 res
= samd_issue_nvmctrl_command(bank
->target
, SAMD_NVM_CMD_PBC
);
863 if (res
!= ERROR_OK
) {
864 LOG_ERROR("%s: %d", __func__
, __LINE__
);
869 nb
= chip
->page_size
- offset
% chip
->page_size
;
873 address
= bank
->base
+ offset
;
874 pg_offset
= offset
% chip
->page_size
;
876 if (offset
% 4 || (offset
+ nb
) % 4) {
877 /* Either start or end of write is not word aligned */
879 pb
= malloc(chip
->page_size
);
884 /* Set temporary page buffer to 0xff and overwrite the relevant part */
885 memset(pb
, 0xff, chip
->page_size
);
886 memcpy(pb
+ pg_offset
, buffer
, nb
);
888 /* Align start address to a word boundary */
889 address
-= offset
% 4;
890 pg_offset
-= offset
% 4;
891 assert(pg_offset
% 4 == 0);
893 /* Extend length to whole words */
894 nw
= (nb
+ offset
% 4 + 3) / 4;
895 assert(pg_offset
+ 4 * nw
<= chip
->page_size
);
897 /* Now we have original data extended by 0xff bytes
898 * to the nearest word boundary on both start and end */
899 res
= target_write_memory(bank
->target
, address
, 4, nw
, pb
+ pg_offset
);
903 assert(pg_offset
+ 4 * nw
<= chip
->page_size
);
905 /* Word aligned data, use direct write from buffer */
906 res
= target_write_memory(bank
->target
, address
, 4, nw
, buffer
);
908 if (res
!= ERROR_OK
) {
909 LOG_ERROR("%s: %d", __func__
, __LINE__
);
913 /* Devices with errata 13134 have automatic page write enabled by default
914 * For other devices issue a write page CMD to the NVM
915 * If the page has not been written up to the last word
916 * then issue CMD_WP always */
917 if (manual_wp
|| pg_offset
+ 4 * nw
< chip
->page_size
) {
918 res
= samd_issue_nvmctrl_command(bank
->target
, SAMD_NVM_CMD_WP
);
920 /* Access through AHB is stalled while flash is being programmed */
923 res
= samd_check_error(bank
->target
);
926 if (res
!= ERROR_OK
) {
927 LOG_ERROR("%s: write failed at address 0x%08" PRIx32
, __func__
, address
);
931 /* We're done with the page contents */
942 FLASH_BANK_COMMAND_HANDLER(samd_flash_bank_command
)
944 if (bank
->base
!= SAMD_FLASH
) {
945 LOG_ERROR("Address " TARGET_ADDR_FMT
946 " invalid bank address (try 0x%08" PRIx32
947 "[at91samd series] )",
948 bank
->base
, SAMD_FLASH
);
952 struct samd_info
*chip
;
953 chip
= calloc(1, sizeof(*chip
));
955 LOG_ERROR("No memory for flash bank chip info");
959 chip
->target
= bank
->target
;
960 chip
->probed
= false;
962 bank
->driver_priv
= chip
;
967 COMMAND_HANDLER(samd_handle_chip_erase_command
)
969 struct target
*target
= get_current_target(CMD_CTX
);
970 int res
= ERROR_FAIL
;
973 /* Enable access to the DSU by disabling the write protect bit */
974 target_write_u32(target
, SAMD_PAC1
, (1<<1));
975 /* intentionally without error checking - not accessible on secured chip */
977 /* Tell the DSU to perform a full chip erase. It takes about 240ms to
978 * perform the erase. */
979 res
= target_write_u8(target
, SAMD_DSU
+ SAMD_DSU_CTRL_EXT
, (1<<4));
981 command_print(CMD
, "chip erase started");
983 command_print(CMD
, "write to DSU CTRL failed");
989 COMMAND_HANDLER(samd_handle_set_security_command
)
992 struct target
*target
= get_current_target(CMD_CTX
);
994 if (CMD_ARGC
< 1 || (CMD_ARGC
>= 1 && (strcmp(CMD_ARGV
[0], "enable")))) {
995 command_print(CMD
, "supply the \"enable\" argument to proceed.");
996 return ERROR_COMMAND_SYNTAX_ERROR
;
1000 if (target
->state
!= TARGET_HALTED
) {
1001 LOG_ERROR("Target not halted");
1002 return ERROR_TARGET_NOT_HALTED
;
1005 res
= samd_issue_nvmctrl_command(target
, SAMD_NVM_CMD_SSB
);
1007 /* Check (and clear) error conditions */
1008 if (res
== ERROR_OK
)
1009 command_print(CMD
, "chip secured on next power-cycle");
1011 command_print(CMD
, "failed to secure chip");
1017 COMMAND_HANDLER(samd_handle_eeprom_command
)
1020 struct target
*target
= get_current_target(CMD_CTX
);
1023 if (target
->state
!= TARGET_HALTED
) {
1024 LOG_ERROR("Target not halted");
1025 return ERROR_TARGET_NOT_HALTED
;
1028 if (CMD_ARGC
>= 1) {
1029 int val
= atoi(CMD_ARGV
[0]);
1035 /* Try to match size in bytes with corresponding size code */
1036 for (code
= 0; code
<= 6; code
++) {
1037 if (val
== (2 << (13 - code
)))
1042 command_print(CMD
, "Invalid EEPROM size. Please see "
1043 "datasheet for a list valid sizes.");
1044 return ERROR_COMMAND_SYNTAX_ERROR
;
1048 res
= samd_modify_user_row(target
, code
, 4, 6);
1051 res
= target_read_u16(target
, SAMD_USER_ROW
, &val
);
1052 if (res
== ERROR_OK
) {
1053 uint32_t size
= ((val
>> 4) & 0x7); /* grab size code */
1056 command_print(CMD
, "EEPROM is disabled");
1058 /* Otherwise, 6 is 256B, 0 is 16KB */
1059 command_print(CMD
, "EEPROM size is %u bytes",
1060 (2 << (13 - size
)));
1069 COMMAND_HANDLER(samd_handle_nvmuserrow_command
)
1072 struct target
*target
= get_current_target(CMD_CTX
);
1076 command_print(CMD
, "Too much Arguments given.");
1077 return ERROR_COMMAND_SYNTAX_ERROR
;
1081 if (target
->state
!= TARGET_HALTED
) {
1082 LOG_ERROR("Target not halted.");
1083 return ERROR_TARGET_NOT_HALTED
;
1087 res
= samd_get_reservedmask(target
, &mask
);
1088 if (res
!= ERROR_OK
) {
1089 LOG_ERROR("Couldn't determine the mask for reserved bits.");
1092 mask
&= NVMUSERROW_LOCKBIT_MASK
;
1095 COMMAND_PARSE_NUMBER(u64
, CMD_ARGV
[0], value
);
1097 if (CMD_ARGC
== 2) {
1099 COMMAND_PARSE_NUMBER(u64
, CMD_ARGV
[1], mask_temp
);
1103 res
= samd_modify_user_row_masked(target
, value
, mask
);
1104 if (res
!= ERROR_OK
)
1110 res
= read_userrow(target
, &value
);
1111 if (res
== ERROR_OK
)
1112 command_print(CMD
, "NVMUSERROW: 0x%016"PRIX64
, value
);
1114 LOG_ERROR("NVMUSERROW could not be read.");
1119 COMMAND_HANDLER(samd_handle_bootloader_command
)
1122 struct target
*target
= get_current_target(CMD_CTX
);
1125 if (target
->state
!= TARGET_HALTED
) {
1126 LOG_ERROR("Target not halted");
1127 return ERROR_TARGET_NOT_HALTED
;
1130 /* Retrieve the MCU's page size, in bytes. */
1132 res
= samd_get_flash_page_info(target
, &page_size
, NULL
);
1133 if (res
!= ERROR_OK
) {
1134 LOG_ERROR("Couldn't determine Flash page size");
1138 if (CMD_ARGC
>= 1) {
1139 int val
= atoi(CMD_ARGV
[0]);
1145 /* Try to match size in bytes with corresponding size code */
1146 for (code
= 0; code
<= 6; code
++) {
1147 if ((unsigned int)val
== (2UL << (8UL - code
)) * page_size
)
1152 command_print(CMD
, "Invalid bootloader size. Please "
1153 "see datasheet for a list valid sizes.");
1154 return ERROR_COMMAND_SYNTAX_ERROR
;
1159 res
= samd_modify_user_row(target
, code
, 0, 2);
1162 res
= target_read_u16(target
, SAMD_USER_ROW
, &val
);
1163 if (res
== ERROR_OK
) {
1164 uint32_t size
= (val
& 0x7); /* grab size code */
1170 nb
= (2 << (8 - size
)) * page_size
;
1172 /* There are 4 pages per row */
1173 command_print(CMD
, "Bootloader size is %" PRIu32
" bytes (%" PRIu32
" rows)",
1174 nb
, (uint32_t)(nb
/ (page_size
* 4)));
1184 COMMAND_HANDLER(samd_handle_reset_deassert
)
1186 struct target
*target
= get_current_target(CMD_CTX
);
1187 int retval
= ERROR_OK
;
1188 enum reset_types jtag_reset_config
= jtag_get_reset_config();
1190 /* If the target has been unresponsive before, try to re-establish
1191 * communication now - CPU is held in reset by DSU, DAP is working */
1192 if (!target_was_examined(target
))
1193 target_examine_one(target
);
1194 target_poll(target
);
1196 /* In case of sysresetreq, debug retains state set in cortex_m_assert_reset()
1197 * so we just release reset held by DSU
1199 * n_RESET (srst) clears the DP, so reenable debug and set vector catch here
1201 * After vectreset DSU release is not needed however makes no harm
1203 if (target
->reset_halt
&& (jtag_reset_config
& RESET_HAS_SRST
)) {
1204 retval
= target_write_u32(target
, DCB_DHCSR
, DBGKEY
| C_HALT
| C_DEBUGEN
);
1205 if (retval
== ERROR_OK
)
1206 retval
= target_write_u32(target
, DCB_DEMCR
,
1207 TRCENA
| VC_HARDERR
| VC_BUSERR
| VC_CORERESET
);
1208 /* do not return on error here, releasing DSU reset is more important */
1211 /* clear CPU Reset Phase Extension bit */
1212 int retval2
= target_write_u8(target
, SAMD_DSU
+ SAMD_DSU_STATUSA
, (1<<1));
1213 if (retval2
!= ERROR_OK
)
1219 static const struct command_registration at91samd_exec_command_handlers
[] = {
1221 .name
= "dsu_reset_deassert",
1222 .handler
= samd_handle_reset_deassert
,
1223 .mode
= COMMAND_EXEC
,
1224 .help
= "Deassert internal reset held by DSU.",
1228 .name
= "chip-erase",
1229 .handler
= samd_handle_chip_erase_command
,
1230 .mode
= COMMAND_EXEC
,
1231 .help
= "Erase the entire Flash by using the Chip-"
1232 "Erase feature in the Device Service Unit (DSU).",
1236 .name
= "set-security",
1237 .handler
= samd_handle_set_security_command
,
1238 .mode
= COMMAND_EXEC
,
1239 .help
= "Secure the chip's Flash by setting the Security Bit. "
1240 "This makes it impossible to read the Flash contents. "
1241 "The only way to undo this is to issue the chip-erase "
1243 .usage
= "'enable'",
1247 .usage
= "[size_in_bytes]",
1248 .handler
= samd_handle_eeprom_command
,
1249 .mode
= COMMAND_EXEC
,
1250 .help
= "Show or set the EEPROM size setting, stored in the User Row. "
1251 "Please see Table 20-3 of the SAMD20 datasheet for allowed values. "
1252 "Changes are stored immediately but take affect after the MCU is "
1256 .name
= "bootloader",
1257 .usage
= "[size_in_bytes]",
1258 .handler
= samd_handle_bootloader_command
,
1259 .mode
= COMMAND_EXEC
,
1260 .help
= "Show or set the bootloader size, stored in the User Row. "
1261 "Please see Table 20-2 of the SAMD20 datasheet for allowed values. "
1262 "Changes are stored immediately but take affect after the MCU is "
1266 .name
= "nvmuserrow",
1267 .usage
= "[value] [mask]",
1268 .handler
= samd_handle_nvmuserrow_command
,
1269 .mode
= COMMAND_EXEC
,
1270 .help
= "Show or set the nvmuserrow register. It is 64 bit wide "
1271 "and located at address 0x804000. Use the optional mask argument "
1272 "to prevent changes at positions where the bitvalue is zero. "
1273 "For security reasons the lock- and reserved-bits are masked out "
1274 "in background and therefore cannot be changed.",
1276 COMMAND_REGISTRATION_DONE
1279 static const struct command_registration at91samd_command_handlers
[] = {
1282 .mode
= COMMAND_ANY
,
1283 .help
= "at91samd flash command group",
1285 .chain
= at91samd_exec_command_handlers
,
1287 COMMAND_REGISTRATION_DONE
1290 const struct flash_driver at91samd_flash
= {
1292 .commands
= at91samd_command_handlers
,
1293 .flash_bank_command
= samd_flash_bank_command
,
1294 .erase
= samd_erase
,
1295 .protect
= samd_protect
,
1296 .write
= samd_write
,
1297 .read
= default_flash_read
,
1298 .probe
= samd_probe
,
1299 .auto_probe
= samd_probe
,
1300 .erase_check
= default_flash_blank_check
,
1301 .protect_check
= samd_protect_check
,
1302 .free_driver_priv
= default_flash_free_driver_priv
,
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