1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2011 by Andreas Fritiofson *
9 * andreas.fritiofson@gmail.com *
11 * Copyright (C) 2013 by Roman Dmitrienko *
14 * Copyright (C) 2014 Nemui Trinomius *
15 * nemuisan_kawausogasuki@live.jp *
17 * This program is free software; you can redistribute it and/or modify *
18 * it under the terms of the GNU General Public License as published by *
19 * the Free Software Foundation; either version 2 of the License, or *
20 * (at your option) any later version. *
22 * This program is distributed in the hope that it will be useful, *
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
25 * GNU General Public License for more details. *
27 * You should have received a copy of the GNU General Public License *
28 * along with this program; if not, write to the *
29 * Free Software Foundation, Inc., *
30 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
31 ***************************************************************************/
38 #include <helper/binarybuffer.h>
39 #include <target/algorithm.h>
40 #include <target/armv7m.h>
41 #include <target/cortex_m.h>
43 /* keep family IDs in decimal */
44 #define EFM_FAMILY_ID_GECKO 71
45 #define EFM_FAMILY_ID_GIANT_GECKO 72
46 #define EFM_FAMILY_ID_TINY_GECKO 73
47 #define EFM_FAMILY_ID_LEOPARD_GECKO 74
48 #define EFM_FAMILY_ID_WONDER_GECKO 75
49 #define EFM_FAMILY_ID_ZERO_GECKO 76
50 #define EFM_FAMILY_ID_HAPPY_GECKO 77
51 #define EZR_FAMILY_ID_WONDER_GECKO 120
52 #define EZR_FAMILY_ID_LEOPARD_GECKO 121
54 #define EFM32_FLASH_ERASE_TMO 100
55 #define EFM32_FLASH_WDATAREADY_TMO 100
56 #define EFM32_FLASH_WRITE_TMO 100
58 /* size in bytes, not words; must fit all Gecko devices */
59 #define LOCKBITS_PAGE_SZ 512
61 #define EFM32_MSC_INFO_BASE 0x0fe00000
63 #define EFM32_MSC_USER_DATA EFM32_MSC_INFO_BASE
64 #define EFM32_MSC_LOCK_BITS (EFM32_MSC_INFO_BASE+0x4000)
65 #define EFM32_MSC_DEV_INFO (EFM32_MSC_INFO_BASE+0x8000)
67 /* PAGE_SIZE is only present in Leopard, Giant and Wonder Gecko MCUs */
68 #define EFM32_MSC_DI_PAGE_SIZE (EFM32_MSC_DEV_INFO+0x1e7)
69 #define EFM32_MSC_DI_FLASH_SZ (EFM32_MSC_DEV_INFO+0x1f8)
70 #define EFM32_MSC_DI_RAM_SZ (EFM32_MSC_DEV_INFO+0x1fa)
71 #define EFM32_MSC_DI_PART_NUM (EFM32_MSC_DEV_INFO+0x1fc)
72 #define EFM32_MSC_DI_PART_FAMILY (EFM32_MSC_DEV_INFO+0x1fe)
73 #define EFM32_MSC_DI_PROD_REV (EFM32_MSC_DEV_INFO+0x1ff)
75 #define EFM32_MSC_REGBASE 0x400c0000
76 #define EFM32_MSC_WRITECTRL (EFM32_MSC_REGBASE+0x008)
77 #define EFM32_MSC_WRITECTRL_WREN_MASK 0x1
78 #define EFM32_MSC_WRITECMD (EFM32_MSC_REGBASE+0x00c)
79 #define EFM32_MSC_WRITECMD_LADDRIM_MASK 0x1
80 #define EFM32_MSC_WRITECMD_ERASEPAGE_MASK 0x2
81 #define EFM32_MSC_WRITECMD_WRITEONCE_MASK 0x8
82 #define EFM32_MSC_ADDRB (EFM32_MSC_REGBASE+0x010)
83 #define EFM32_MSC_WDATA (EFM32_MSC_REGBASE+0x018)
84 #define EFM32_MSC_STATUS (EFM32_MSC_REGBASE+0x01c)
85 #define EFM32_MSC_STATUS_BUSY_MASK 0x1
86 #define EFM32_MSC_STATUS_LOCKED_MASK 0x2
87 #define EFM32_MSC_STATUS_INVADDR_MASK 0x4
88 #define EFM32_MSC_STATUS_WDATAREADY_MASK 0x8
89 #define EFM32_MSC_STATUS_WORDTIMEOUT_MASK 0x10
90 #define EFM32_MSC_STATUS_ERASEABORTED_MASK 0x20
91 #define EFM32_MSC_LOCK (EFM32_MSC_REGBASE+0x03c)
92 #define EFM32_MSC_LOCK_LOCKKEY 0x1b71
94 struct efm32x_flash_bank
{
96 uint32_t lb_page
[LOCKBITS_PAGE_SZ
/4];
100 uint16_t flash_sz_kib
;
108 static int efm32x_write(struct flash_bank
*bank
, const uint8_t *buffer
,
109 uint32_t offset
, uint32_t count
);
111 static int efm32x_get_flash_size(struct flash_bank
*bank
, uint16_t *flash_sz
)
113 return target_read_u16(bank
->target
, EFM32_MSC_DI_FLASH_SZ
, flash_sz
);
116 static int efm32x_get_ram_size(struct flash_bank
*bank
, uint16_t *ram_sz
)
118 return target_read_u16(bank
->target
, EFM32_MSC_DI_RAM_SZ
, ram_sz
);
121 static int efm32x_get_part_num(struct flash_bank
*bank
, uint16_t *pnum
)
123 return target_read_u16(bank
->target
, EFM32_MSC_DI_PART_NUM
, pnum
);
126 static int efm32x_get_part_family(struct flash_bank
*bank
, uint8_t *pfamily
)
128 return target_read_u8(bank
->target
, EFM32_MSC_DI_PART_FAMILY
, pfamily
);
131 static int efm32x_get_prod_rev(struct flash_bank
*bank
, uint8_t *prev
)
133 return target_read_u8(bank
->target
, EFM32_MSC_DI_PROD_REV
, prev
);
136 static int efm32x_read_info(struct flash_bank
*bank
,
137 struct efm32_info
*efm32_info
)
142 memset(efm32_info
, 0, sizeof(struct efm32_info
));
144 ret
= target_read_u32(bank
->target
, CPUID
, &cpuid
);
148 if (((cpuid
>> 4) & 0xfff) == 0xc23) {
149 /* Cortex M3 device */
150 } else if (((cpuid
>> 4) & 0xfff) == 0xc24) {
151 /* Cortex M4 device(WONDER GECKO) */
152 } else if (((cpuid
>> 4) & 0xfff) == 0xc60) {
153 /* Cortex M0plus device */
155 LOG_ERROR("Target is not Cortex-Mx Device");
159 ret
= efm32x_get_flash_size(bank
, &(efm32_info
->flash_sz_kib
));
163 ret
= efm32x_get_ram_size(bank
, &(efm32_info
->ram_sz_kib
));
167 ret
= efm32x_get_part_num(bank
, &(efm32_info
->part_num
));
171 ret
= efm32x_get_part_family(bank
, &(efm32_info
->part_family
));
175 ret
= efm32x_get_prod_rev(bank
, &(efm32_info
->prod_rev
));
179 if (EFM_FAMILY_ID_GECKO
== efm32_info
->part_family
||
180 EFM_FAMILY_ID_TINY_GECKO
== efm32_info
->part_family
)
181 efm32_info
->page_size
= 512;
182 else if (EFM_FAMILY_ID_ZERO_GECKO
== efm32_info
->part_family
||
183 EFM_FAMILY_ID_HAPPY_GECKO
== efm32_info
->part_family
)
184 efm32_info
->page_size
= 1024;
185 else if (EFM_FAMILY_ID_GIANT_GECKO
== efm32_info
->part_family
||
186 EFM_FAMILY_ID_LEOPARD_GECKO
== efm32_info
->part_family
) {
187 if (efm32_info
->prod_rev
>= 18) {
189 ret
= target_read_u8(bank
->target
, EFM32_MSC_DI_PAGE_SIZE
,
194 efm32_info
->page_size
= (1 << ((pg_size
+10) & 0xff));
196 /* EFM32 GG/LG errata: MEM_INFO_PAGE_SIZE is invalid
197 for MCUs with PROD_REV < 18 */
198 if (efm32_info
->flash_sz_kib
< 512)
199 efm32_info
->page_size
= 2048;
201 efm32_info
->page_size
= 4096;
204 if ((2048 != efm32_info
->page_size
) &&
205 (4096 != efm32_info
->page_size
)) {
206 LOG_ERROR("Invalid page size %u", efm32_info
->page_size
);
209 } else if (EFM_FAMILY_ID_WONDER_GECKO
== efm32_info
->part_family
||
210 EZR_FAMILY_ID_WONDER_GECKO
== efm32_info
->part_family
||
211 EZR_FAMILY_ID_LEOPARD_GECKO
== efm32_info
->part_family
) {
213 ret
= target_read_u8(bank
->target
, EFM32_MSC_DI_PAGE_SIZE
,
218 efm32_info
->page_size
= (1 << ((pg_size
+10) & 0xff));
219 if (2048 != efm32_info
->page_size
) {
220 LOG_ERROR("Invalid page size %u", efm32_info
->page_size
);
224 LOG_ERROR("Unknown MCU family %d", efm32_info
->part_family
);
232 * Helper to create a human friendly string describing a part
234 static int efm32x_decode_info(struct efm32_info
*info
, char *buf
, int buf_size
)
238 switch (info
->part_family
) {
239 case EZR_FAMILY_ID_WONDER_GECKO
:
240 case EZR_FAMILY_ID_LEOPARD_GECKO
:
241 printed
= snprintf(buf
, buf_size
, "EZR32 ");
244 printed
= snprintf(buf
, buf_size
, "EFM32 ");
251 return ERROR_BUF_TOO_SMALL
;
253 switch (info
->part_family
) {
254 case EFM_FAMILY_ID_GECKO
:
255 printed
= snprintf(buf
, buf_size
, "Gecko");
257 case EFM_FAMILY_ID_GIANT_GECKO
:
258 printed
= snprintf(buf
, buf_size
, "Giant Gecko");
260 case EFM_FAMILY_ID_TINY_GECKO
:
261 printed
= snprintf(buf
, buf_size
, "Tiny Gecko");
263 case EFM_FAMILY_ID_LEOPARD_GECKO
:
264 case EZR_FAMILY_ID_LEOPARD_GECKO
:
265 printed
= snprintf(buf
, buf_size
, "Leopard Gecko");
267 case EFM_FAMILY_ID_WONDER_GECKO
:
268 case EZR_FAMILY_ID_WONDER_GECKO
:
269 printed
= snprintf(buf
, buf_size
, "Wonder Gecko");
271 case EFM_FAMILY_ID_ZERO_GECKO
:
272 printed
= snprintf(buf
, buf_size
, "Zero Gecko");
274 case EFM_FAMILY_ID_HAPPY_GECKO
:
275 printed
= snprintf(buf
, buf_size
, "Happy Gecko");
283 return ERROR_BUF_TOO_SMALL
;
285 printed
= snprintf(buf
, buf_size
, " - Rev: %d", info
->prod_rev
);
290 return ERROR_BUF_TOO_SMALL
;
295 /* flash bank efm32 <base> <size> 0 0 <target#>
297 FLASH_BANK_COMMAND_HANDLER(efm32x_flash_bank_command
)
299 struct efm32x_flash_bank
*efm32x_info
;
302 return ERROR_COMMAND_SYNTAX_ERROR
;
304 efm32x_info
= malloc(sizeof(struct efm32x_flash_bank
));
306 bank
->driver_priv
= efm32x_info
;
307 efm32x_info
->probed
= 0;
308 memset(efm32x_info
->lb_page
, 0xff, LOCKBITS_PAGE_SZ
);
313 /* set or reset given bits in a register */
314 static int efm32x_set_reg_bits(struct flash_bank
*bank
, uint32_t reg
,
315 uint32_t bitmask
, int set
)
318 uint32_t reg_val
= 0;
320 ret
= target_read_u32(bank
->target
, reg
, ®_val
);
329 return target_write_u32(bank
->target
, reg
, reg_val
);
332 static int efm32x_set_wren(struct flash_bank
*bank
, int write_enable
)
334 return efm32x_set_reg_bits(bank
, EFM32_MSC_WRITECTRL
,
335 EFM32_MSC_WRITECTRL_WREN_MASK
, write_enable
);
338 static int efm32x_msc_lock(struct flash_bank
*bank
, int lock
)
340 return target_write_u32(bank
->target
, EFM32_MSC_LOCK
,
341 (lock
? 0 : EFM32_MSC_LOCK_LOCKKEY
));
344 static int efm32x_wait_status(struct flash_bank
*bank
, int timeout
,
345 uint32_t wait_mask
, int wait_for_set
)
351 ret
= target_read_u32(bank
->target
, EFM32_MSC_STATUS
, &status
);
355 LOG_DEBUG("status: 0x%" PRIx32
"", status
);
357 if (((status
& wait_mask
) == 0) && (0 == wait_for_set
))
359 else if (((status
& wait_mask
) != 0) && wait_for_set
)
362 if (timeout
-- <= 0) {
363 LOG_ERROR("timed out waiting for MSC status");
370 if (status
& EFM32_MSC_STATUS_ERASEABORTED_MASK
)
371 LOG_WARNING("page erase was aborted");
376 static int efm32x_erase_page(struct flash_bank
*bank
, uint32_t addr
)
378 /* this function DOES NOT set WREN; must be set already */
379 /* 1. write address to ADDRB
381 3. check status (INVADDR, LOCKED)
383 5. wait until !STATUS_BUSY
388 LOG_DEBUG("erasing flash page at 0x%08" PRIx32
, addr
);
390 ret
= target_write_u32(bank
->target
, EFM32_MSC_ADDRB
, addr
);
394 ret
= efm32x_set_reg_bits(bank
, EFM32_MSC_WRITECMD
,
395 EFM32_MSC_WRITECMD_LADDRIM_MASK
, 1);
399 ret
= target_read_u32(bank
->target
, EFM32_MSC_STATUS
, &status
);
403 LOG_DEBUG("status 0x%" PRIx32
, status
);
405 if (status
& EFM32_MSC_STATUS_LOCKED_MASK
) {
406 LOG_ERROR("Page is locked");
408 } else if (status
& EFM32_MSC_STATUS_INVADDR_MASK
) {
409 LOG_ERROR("Invalid address 0x%" PRIx32
, addr
);
413 ret
= efm32x_set_reg_bits(bank
, EFM32_MSC_WRITECMD
,
414 EFM32_MSC_WRITECMD_ERASEPAGE_MASK
, 1);
418 return efm32x_wait_status(bank
, EFM32_FLASH_ERASE_TMO
,
419 EFM32_MSC_STATUS_BUSY_MASK
, 0);
422 static int efm32x_erase(struct flash_bank
*bank
, int first
, int last
)
424 struct target
*target
= bank
->target
;
428 if (TARGET_HALTED
!= target
->state
) {
429 LOG_ERROR("Target not halted");
430 return ERROR_TARGET_NOT_HALTED
;
433 efm32x_msc_lock(bank
, 0);
434 ret
= efm32x_set_wren(bank
, 1);
435 if (ERROR_OK
!= ret
) {
436 LOG_ERROR("Failed to enable MSC write");
440 for (i
= first
; i
<= last
; i
++) {
441 ret
= efm32x_erase_page(bank
, bank
->sectors
[i
].offset
);
443 LOG_ERROR("Failed to erase page %d", i
);
446 ret
= efm32x_set_wren(bank
, 0);
447 efm32x_msc_lock(bank
, 1);
452 static int efm32x_read_lock_data(struct flash_bank
*bank
)
454 struct efm32x_flash_bank
*efm32x_info
= bank
->driver_priv
;
455 struct target
*target
= bank
->target
;
458 uint32_t *ptr
= NULL
;
461 assert(!(bank
->num_sectors
& 0x1f));
463 data_size
= bank
->num_sectors
/ 8; /* number of data bytes */
464 data_size
/= 4; /* ...and data dwords */
466 ptr
= efm32x_info
->lb_page
;
468 for (i
= 0; i
< data_size
; i
++, ptr
++) {
469 ret
= target_read_u32(target
, EFM32_MSC_LOCK_BITS
+i
*4, ptr
);
470 if (ERROR_OK
!= ret
) {
471 LOG_ERROR("Failed to read PLW %d", i
);
476 /* also, read ULW, DLW and MLW */
479 ptr
= efm32x_info
->lb_page
+ 126;
480 ret
= target_read_u32(target
, EFM32_MSC_LOCK_BITS
+126*4, ptr
);
481 if (ERROR_OK
!= ret
) {
482 LOG_ERROR("Failed to read ULW");
487 ptr
= efm32x_info
->lb_page
+ 127;
488 ret
= target_read_u32(target
, EFM32_MSC_LOCK_BITS
+127*4, ptr
);
489 if (ERROR_OK
!= ret
) {
490 LOG_ERROR("Failed to read DLW");
494 /* MLW, word 125, present in GG and LG */
495 ptr
= efm32x_info
->lb_page
+ 125;
496 ret
= target_read_u32(target
, EFM32_MSC_LOCK_BITS
+125*4, ptr
);
497 if (ERROR_OK
!= ret
) {
498 LOG_ERROR("Failed to read MLW");
505 static int efm32x_write_lock_data(struct flash_bank
*bank
)
507 struct efm32x_flash_bank
*efm32x_info
= bank
->driver_priv
;
510 ret
= efm32x_erase_page(bank
, EFM32_MSC_LOCK_BITS
);
511 if (ERROR_OK
!= ret
) {
512 LOG_ERROR("Failed to erase LB page");
516 return efm32x_write(bank
, (uint8_t *)efm32x_info
->lb_page
, EFM32_MSC_LOCK_BITS
,
520 static int efm32x_get_page_lock(struct flash_bank
*bank
, size_t page
)
522 struct efm32x_flash_bank
*efm32x_info
= bank
->driver_priv
;
523 uint32_t dw
= efm32x_info
->lb_page
[page
>> 5];
526 mask
= 1 << (page
& 0x1f);
528 return (dw
& mask
) ? 0 : 1;
531 static int efm32x_set_page_lock(struct flash_bank
*bank
, size_t page
, int set
)
533 struct efm32x_flash_bank
*efm32x_info
= bank
->driver_priv
;
534 uint32_t *dw
= &efm32x_info
->lb_page
[page
>> 5];
537 mask
= 1 << (page
& 0x1f);
547 static int efm32x_protect(struct flash_bank
*bank
, int set
, int first
, int last
)
549 struct target
*target
= bank
->target
;
554 LOG_ERROR("Erase device data to reset page locks");
558 if (target
->state
!= TARGET_HALTED
) {
559 LOG_ERROR("Target not halted");
560 return ERROR_TARGET_NOT_HALTED
;
563 for (i
= first
; i
<= last
; i
++) {
564 ret
= efm32x_set_page_lock(bank
, i
, set
);
565 if (ERROR_OK
!= ret
) {
566 LOG_ERROR("Failed to set lock on page %d", i
);
571 ret
= efm32x_write_lock_data(bank
);
572 if (ERROR_OK
!= ret
) {
573 LOG_ERROR("Failed to write LB page");
580 static int efm32x_write_block(struct flash_bank
*bank
, const uint8_t *buf
,
581 uint32_t offset
, uint32_t count
)
583 struct target
*target
= bank
->target
;
584 uint32_t buffer_size
= 16384;
585 struct working_area
*write_algorithm
;
586 struct working_area
*source
;
587 uint32_t address
= bank
->base
+ offset
;
588 struct reg_param reg_params
[5];
589 struct armv7m_algorithm armv7m_info
;
592 /* see contrib/loaders/flash/efm32.S for src */
593 static const uint8_t efm32x_flash_write_code
[] = {
594 /* #define EFM32_MSC_WRITECTRL_OFFSET 0x008 */
595 /* #define EFM32_MSC_WRITECMD_OFFSET 0x00c */
596 /* #define EFM32_MSC_ADDRB_OFFSET 0x010 */
597 /* #define EFM32_MSC_WDATA_OFFSET 0x018 */
598 /* #define EFM32_MSC_STATUS_OFFSET 0x01c */
599 /* #define EFM32_MSC_LOCK_OFFSET 0x03c */
601 0x15, 0x4e, /* ldr r6, =#0x1b71 */
602 0xc6, 0x63, /* str r6, [r0, #EFM32_MSC_LOCK_OFFSET] */
603 0x01, 0x26, /* movs r6, #1 */
604 0x86, 0x60, /* str r6, [r0, #EFM32_MSC_WRITECTRL_OFFSET] */
607 0x16, 0x68, /* ldr r6, [r2, #0] */
608 0x00, 0x2e, /* cmp r6, #0 */
609 0x22, 0xd0, /* beq exit */
610 0x55, 0x68, /* ldr r5, [r2, #4] */
611 0xb5, 0x42, /* cmp r5, r6 */
612 0xf9, 0xd0, /* beq wait_fifo */
614 0x04, 0x61, /* str r4, [r0, #EFM32_MSC_ADDRB_OFFSET] */
615 0x01, 0x26, /* movs r6, #1 */
616 0xc6, 0x60, /* str r6, [r0, #EFM32_MSC_WRITECMD_OFFSET] */
617 0xc6, 0x69, /* ldr r6, [r0, #EFM32_MSC_STATUS_OFFSET] */
618 0x06, 0x27, /* movs r7, #6 */
619 0x3e, 0x42, /* tst r6, r7 */
620 0x16, 0xd1, /* bne error */
622 /* wait_wdataready: */
623 0xc6, 0x69, /* ldr r6, [r0, #EFM32_MSC_STATUS_OFFSET] */
624 0x08, 0x27, /* movs r7, #8 */
625 0x3e, 0x42, /* tst r6, r7 */
626 0xfb, 0xd0, /* beq wait_wdataready */
628 0x2e, 0x68, /* ldr r6, [r5] */
629 0x86, 0x61, /* str r6, [r0, #EFM32_MSC_WDATA_OFFSET] */
630 0x08, 0x26, /* movs r6, #8 */
631 0xc6, 0x60, /* str r6, [r0, #EFM32_MSC_WRITECMD_OFFSET] */
633 0x04, 0x35, /* adds r5, #4 */
634 0x04, 0x34, /* adds r4, #4 */
637 0xc6, 0x69, /* ldr r6, [r0, #EFM32_MSC_STATUS_OFFSET] */
638 0x01, 0x27, /* movs r7, #1 */
639 0x3e, 0x42, /* tst r6, r7 */
640 0xfb, 0xd1, /* bne busy */
642 0x9d, 0x42, /* cmp r5, r3 */
643 0x01, 0xd3, /* bcc no_wrap */
644 0x15, 0x46, /* mov r5, r2 */
645 0x08, 0x35, /* adds r5, #8 */
648 0x55, 0x60, /* str r5, [r2, #4] */
649 0x01, 0x39, /* subs r1, r1, #1 */
650 0x00, 0x29, /* cmp r1, #0 */
651 0x02, 0xd0, /* beq exit */
652 0xdb, 0xe7, /* b wait_fifo */
655 0x00, 0x20, /* movs r0, #0 */
656 0x50, 0x60, /* str r0, [r2, #4] */
659 0x30, 0x46, /* mov r0, r6 */
660 0x00, 0xbe, /* bkpt #0 */
663 0x71, 0x1b, 0x00, 0x00
666 /* flash write code */
667 if (target_alloc_working_area(target
, sizeof(efm32x_flash_write_code
),
668 &write_algorithm
) != ERROR_OK
) {
669 LOG_WARNING("no working area available, can't do block memory writes");
670 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
673 ret
= target_write_buffer(target
, write_algorithm
->address
,
674 sizeof(efm32x_flash_write_code
), efm32x_flash_write_code
);
679 while (target_alloc_working_area_try(target
, buffer_size
, &source
) != ERROR_OK
) {
681 buffer_size
&= ~3UL; /* Make sure it's 4 byte aligned */
682 if (buffer_size
<= 256) {
683 /* we already allocated the writing code, but failed to get a
684 * buffer, free the algorithm */
685 target_free_working_area(target
, write_algorithm
);
687 LOG_WARNING("no large enough working area available, can't do block memory writes");
688 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
692 init_reg_param(®_params
[0], "r0", 32, PARAM_IN_OUT
); /* flash base (in), status (out) */
693 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
); /* count (word-32bit) */
694 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
); /* buffer start */
695 init_reg_param(®_params
[3], "r3", 32, PARAM_OUT
); /* buffer end */
696 init_reg_param(®_params
[4], "r4", 32, PARAM_IN_OUT
); /* target address */
698 buf_set_u32(reg_params
[0].value
, 0, 32, EFM32_MSC_REGBASE
);
699 buf_set_u32(reg_params
[1].value
, 0, 32, count
);
700 buf_set_u32(reg_params
[2].value
, 0, 32, source
->address
);
701 buf_set_u32(reg_params
[3].value
, 0, 32, source
->address
+ source
->size
);
702 buf_set_u32(reg_params
[4].value
, 0, 32, address
);
704 armv7m_info
.common_magic
= ARMV7M_COMMON_MAGIC
;
705 armv7m_info
.core_mode
= ARM_MODE_THREAD
;
707 ret
= target_run_flash_async_algorithm(target
, buf
, count
, 4,
710 source
->address
, source
->size
,
711 write_algorithm
->address
, 0,
714 if (ret
== ERROR_FLASH_OPERATION_FAILED
) {
715 LOG_ERROR("flash write failed at address 0x%"PRIx32
,
716 buf_get_u32(reg_params
[4].value
, 0, 32));
718 if (buf_get_u32(reg_params
[0].value
, 0, 32) &
719 EFM32_MSC_STATUS_LOCKED_MASK
) {
720 LOG_ERROR("flash memory write protected");
723 if (buf_get_u32(reg_params
[0].value
, 0, 32) &
724 EFM32_MSC_STATUS_INVADDR_MASK
) {
725 LOG_ERROR("invalid flash memory write address");
729 target_free_working_area(target
, source
);
730 target_free_working_area(target
, write_algorithm
);
732 destroy_reg_param(®_params
[0]);
733 destroy_reg_param(®_params
[1]);
734 destroy_reg_param(®_params
[2]);
735 destroy_reg_param(®_params
[3]);
736 destroy_reg_param(®_params
[4]);
741 static int efm32x_write_word(struct flash_bank
*bank
, uint32_t addr
,
744 /* this function DOES NOT set WREN; must be set already */
745 /* 1. write address to ADDRB
747 3. check status (INVADDR, LOCKED)
748 4. wait for WDATAREADY
749 5. write data to WDATA
750 6. write WRITECMD_WRITEONCE to WRITECMD
751 7. wait until !STATUS_BUSY
754 /* FIXME: EFM32G ref states (7.3.2) that writes should be
755 * performed twice per dword */
760 /* if not called, GDB errors will be reported during large writes */
763 ret
= target_write_u32(bank
->target
, EFM32_MSC_ADDRB
, addr
);
767 ret
= efm32x_set_reg_bits(bank
, EFM32_MSC_WRITECMD
,
768 EFM32_MSC_WRITECMD_LADDRIM_MASK
, 1);
772 ret
= target_read_u32(bank
->target
, EFM32_MSC_STATUS
, &status
);
776 LOG_DEBUG("status 0x%" PRIx32
, status
);
778 if (status
& EFM32_MSC_STATUS_LOCKED_MASK
) {
779 LOG_ERROR("Page is locked");
781 } else if (status
& EFM32_MSC_STATUS_INVADDR_MASK
) {
782 LOG_ERROR("Invalid address 0x%" PRIx32
, addr
);
786 ret
= efm32x_wait_status(bank
, EFM32_FLASH_WDATAREADY_TMO
,
787 EFM32_MSC_STATUS_WDATAREADY_MASK
, 1);
788 if (ERROR_OK
!= ret
) {
789 LOG_ERROR("Wait for WDATAREADY failed");
793 ret
= target_write_u32(bank
->target
, EFM32_MSC_WDATA
, val
);
794 if (ERROR_OK
!= ret
) {
795 LOG_ERROR("WDATA write failed");
799 ret
= target_write_u32(bank
->target
, EFM32_MSC_WRITECMD
,
800 EFM32_MSC_WRITECMD_WRITEONCE_MASK
);
801 if (ERROR_OK
!= ret
) {
802 LOG_ERROR("WRITECMD write failed");
806 ret
= efm32x_wait_status(bank
, EFM32_FLASH_WRITE_TMO
,
807 EFM32_MSC_STATUS_BUSY_MASK
, 0);
808 if (ERROR_OK
!= ret
) {
809 LOG_ERROR("Wait for BUSY failed");
816 static int efm32x_write(struct flash_bank
*bank
, const uint8_t *buffer
,
817 uint32_t offset
, uint32_t count
)
819 struct target
*target
= bank
->target
;
820 uint8_t *new_buffer
= NULL
;
822 if (target
->state
!= TARGET_HALTED
) {
823 LOG_ERROR("Target not halted");
824 return ERROR_TARGET_NOT_HALTED
;
828 LOG_ERROR("offset 0x%" PRIx32
" breaks required 4-byte "
829 "alignment", offset
);
830 return ERROR_FLASH_DST_BREAKS_ALIGNMENT
;
834 uint32_t old_count
= count
;
835 count
= (old_count
| 3) + 1;
836 new_buffer
= malloc(count
);
837 if (new_buffer
== NULL
) {
838 LOG_ERROR("odd number of bytes to write and no memory "
839 "for padding buffer");
842 LOG_INFO("odd number of bytes to write (%" PRIu32
"), extending to %" PRIu32
" "
843 "and padding with 0xff", old_count
, count
);
844 memset(new_buffer
, 0xff, count
);
845 buffer
= memcpy(new_buffer
, buffer
, old_count
);
848 uint32_t words_remaining
= count
/ 4;
851 /* unlock flash registers */
852 efm32x_msc_lock(bank
, 0);
853 retval
= efm32x_set_wren(bank
, 1);
854 if (retval
!= ERROR_OK
)
857 /* try using a block write */
858 retval
= efm32x_write_block(bank
, buffer
, offset
, words_remaining
);
860 if (retval
== ERROR_TARGET_RESOURCE_NOT_AVAILABLE
) {
861 /* if block write failed (no sufficient working area),
862 * we use normal (slow) single word accesses */
863 LOG_WARNING("couldn't use block writes, falling back to single "
866 while (words_remaining
> 0) {
868 memcpy(&value
, buffer
, sizeof(uint32_t));
870 retval
= efm32x_write_word(bank
, offset
, value
);
871 if (retval
!= ERROR_OK
)
872 goto reset_pg_and_lock
;
881 retval2
= efm32x_set_wren(bank
, 0);
882 efm32x_msc_lock(bank
, 1);
883 if (retval
== ERROR_OK
)
893 static int efm32x_probe(struct flash_bank
*bank
)
895 struct efm32x_flash_bank
*efm32x_info
= bank
->driver_priv
;
896 struct efm32_info efm32_mcu_info
;
899 uint32_t base_address
= 0x00000000;
902 efm32x_info
->probed
= 0;
903 memset(efm32x_info
->lb_page
, 0xff, LOCKBITS_PAGE_SZ
);
905 ret
= efm32x_read_info(bank
, &efm32_mcu_info
);
909 ret
= efm32x_decode_info(&efm32_mcu_info
, buf
, sizeof(buf
));
913 LOG_INFO("detected part: %s", buf
);
914 LOG_INFO("flash size = %dkbytes", efm32_mcu_info
.flash_sz_kib
);
915 LOG_INFO("flash page size = %dbytes", efm32_mcu_info
.page_size
);
917 assert(0 != efm32_mcu_info
.page_size
);
919 int num_pages
= efm32_mcu_info
.flash_sz_kib
* 1024 /
920 efm32_mcu_info
.page_size
;
922 assert(num_pages
> 0);
926 bank
->sectors
= NULL
;
929 bank
->base
= base_address
;
930 bank
->size
= (num_pages
* efm32_mcu_info
.page_size
);
931 bank
->num_sectors
= num_pages
;
933 ret
= efm32x_read_lock_data(bank
);
934 if (ERROR_OK
!= ret
) {
935 LOG_ERROR("Failed to read LB data");
939 bank
->sectors
= malloc(sizeof(struct flash_sector
) * num_pages
);
941 for (i
= 0; i
< num_pages
; i
++) {
942 bank
->sectors
[i
].offset
= i
* efm32_mcu_info
.page_size
;
943 bank
->sectors
[i
].size
= efm32_mcu_info
.page_size
;
944 bank
->sectors
[i
].is_erased
= -1;
945 bank
->sectors
[i
].is_protected
= 1;
948 efm32x_info
->probed
= 1;
953 static int efm32x_auto_probe(struct flash_bank
*bank
)
955 struct efm32x_flash_bank
*efm32x_info
= bank
->driver_priv
;
956 if (efm32x_info
->probed
)
958 return efm32x_probe(bank
);
961 static int efm32x_protect_check(struct flash_bank
*bank
)
963 struct target
*target
= bank
->target
;
967 if (target
->state
!= TARGET_HALTED
) {
968 LOG_ERROR("Target not halted");
969 return ERROR_TARGET_NOT_HALTED
;
972 ret
= efm32x_read_lock_data(bank
);
973 if (ERROR_OK
!= ret
) {
974 LOG_ERROR("Failed to read LB data");
978 assert(NULL
!= bank
->sectors
);
980 for (i
= 0; i
< bank
->num_sectors
; i
++)
981 bank
->sectors
[i
].is_protected
= efm32x_get_page_lock(bank
, i
);
986 static int get_efm32x_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
988 struct efm32_info info
;
991 ret
= efm32x_read_info(bank
, &info
);
992 if (ERROR_OK
!= ret
) {
993 LOG_ERROR("Failed to read EFM32 info");
997 return efm32x_decode_info(&info
, buf
, buf_size
);
1000 static const struct command_registration efm32x_exec_command_handlers
[] = {
1001 COMMAND_REGISTRATION_DONE
1004 static const struct command_registration efm32x_command_handlers
[] = {
1007 .mode
= COMMAND_ANY
,
1008 .help
= "efm32 flash command group",
1010 .chain
= efm32x_exec_command_handlers
,
1012 COMMAND_REGISTRATION_DONE
1015 struct flash_driver efm32_flash
= {
1017 .commands
= efm32x_command_handlers
,
1018 .flash_bank_command
= efm32x_flash_bank_command
,
1019 .erase
= efm32x_erase
,
1020 .protect
= efm32x_protect
,
1021 .write
= efm32x_write
,
1022 .read
= default_flash_read
,
1023 .probe
= efm32x_probe
,
1024 .auto_probe
= efm32x_auto_probe
,
1025 .erase_check
= default_flash_blank_check
,
1026 .protect_check
= efm32x_protect_check
,
1027 .info
= get_efm32x_info
,
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