1 // SPDX-License-Identifier: GPL-2.0-or-later
3 /***************************************************************************
4 * Copyright (C) 2011 by Mathias Kuester *
7 * Copyright (C) 2011 sleep(5) ltd *
8 * tomas@sleepfive.com *
10 * Copyright (C) 2012 by Christopher D. Kilgour *
11 * techie at whiterocker.com *
13 * Copyright (C) 2013 Nemui Trinomius *
14 * nemuisan_kawausogasuki@live.jp *
16 * Copyright (C) 2015 Tomas Vanek *
18 ***************************************************************************/
24 #include "jtag/interface.h"
26 #include <helper/binarybuffer.h>
27 #include <helper/time_support.h>
28 #include <target/target_type.h>
29 #include <target/algorithm.h>
30 #include <target/arm_adi_v5.h>
31 #include <target/armv7m.h>
32 #include <target/cortex_m.h>
35 * Implementation Notes
37 * The persistent memories in the Kinetis chip families K10 through
38 * K70 are all manipulated with the Flash Memory Module. Some
39 * variants call this module the FTFE, others call it the FTFL. To
40 * indicate that both are considered here, we use FTFX.
42 * Within the module, according to the chip variant, the persistent
43 * memory is divided into what Freescale terms Program Flash, FlexNVM,
44 * and FlexRAM. All chip variants have Program Flash. Some chip
45 * variants also have FlexNVM and FlexRAM, which always appear
48 * A given Kinetis chip may have 1, 2 or 4 blocks of flash. Here we map
49 * each block to a separate bank. Each block size varies by chip and
50 * may be determined by the read-only SIM_FCFG1 register. The sector
51 * size within each bank/block varies by chip, and may be 1, 2 or 4k.
52 * The sector size may be different for flash and FlexNVM.
54 * The first half of the flash (1 or 2 blocks) is always Program Flash
55 * and always starts at address 0x00000000. The "PFLSH" flag, bit 23
56 * of the read-only SIM_FCFG2 register, determines whether the second
57 * half of the flash is also Program Flash or FlexNVM+FlexRAM. When
58 * PFLSH is set, the second from the first half. When PFLSH is clear,
59 * the second half of flash is FlexNVM and always starts at address
60 * 0x10000000. FlexRAM, which is also present when PFLSH is clear,
61 * always starts at address 0x14000000.
63 * The Flash Memory Module provides a register set where flash
64 * commands are loaded to perform flash operations like erase and
65 * program. Different commands are available depending on whether
66 * Program Flash or FlexNVM/FlexRAM is being manipulated. Although
67 * the commands used are quite consistent between flash blocks, the
68 * parameters they accept differ according to the flash sector size.
73 #define FCF_ADDRESS 0x00000400
77 #define FCF_FDPROT 0xf
80 #define FLEXRAM 0x14000000
82 #define MSCM_OCMDR0 0x40001400
83 #define MSCM_OCMDR1 0x40001404
84 #define FMC_PFB01CR 0x4001f004
85 #define FTFX_FSTAT 0x40020000
86 #define FTFX_FCNFG 0x40020001
87 #define FTFX_FCCOB3 0x40020004
88 #define FTFX_FPROT3 0x40020010
89 #define FTFX_FDPROT 0x40020017
90 #define SIM_BASE 0x40047000
91 #define SIM_BASE_KL28 0x40074000
92 #define SIM_COPC 0x40048100
93 /* SIM_COPC does not exist on devices with changed SIM_BASE */
94 #define WDOG_BASE 0x40052000
95 #define WDOG32_KE1X 0x40052000
96 #define WDOG32_KL28 0x40076000
97 #define SMC_PMCTRL 0x4007E001
98 #define SMC_PMSTAT 0x4007E003
99 #define SMC32_PMCTRL 0x4007E00C
100 #define SMC32_PMSTAT 0x4007E014
101 #define PMC_REGSC 0x4007D002
102 #define MC_PMCTRL 0x4007E003
103 #define MCM_PLACR 0xF000300C
106 #define SIM_SOPT1_OFFSET 0x0000
107 #define SIM_SDID_OFFSET 0x1024
108 #define SIM_FCFG1_OFFSET 0x104c
109 #define SIM_FCFG2_OFFSET 0x1050
111 #define WDOG_STCTRLH_OFFSET 0
112 #define WDOG32_CS_OFFSET 0
115 #define PM_STAT_RUN 0x01
116 #define PM_STAT_VLPR 0x04
117 #define PM_CTRL_RUNM_RUN 0x00
120 #define FTFX_CMD_BLOCKSTAT 0x00
121 #define FTFX_CMD_SECTSTAT 0x01
122 #define FTFX_CMD_LWORDPROG 0x06
123 #define FTFX_CMD_SECTERASE 0x09
124 #define FTFX_CMD_SECTWRITE 0x0b
125 #define FTFX_CMD_MASSERASE 0x44
126 #define FTFX_CMD_PGMPART 0x80
127 #define FTFX_CMD_SETFLEXRAM 0x81
129 /* The older Kinetis K series uses the following SDID layout :
136 * The newer Kinetis series uses the following SDID layout :
138 * Bit 27-24 : SUBFAMID
139 * Bit 23-20 : SERIESID
140 * Bit 19-16 : SRAMSIZE
142 * Bit 6-4 : Reserved (0)
145 * We assume that if bits 31-16 are 0 then it's an older
149 #define KINETIS_SOPT1_RAMSIZE_MASK 0x0000F000
150 #define KINETIS_SOPT1_RAMSIZE_K24FN1M 0x0000B000
152 #define KINETIS_SDID_K_SERIES_MASK 0x0000FFFF
154 #define KINETIS_SDID_DIEID_MASK 0x00000F80
156 #define KINETIS_SDID_DIEID_K22FN128 0x00000680 /* smaller pflash with FTFA */
157 #define KINETIS_SDID_DIEID_K22FN256 0x00000A80
158 #define KINETIS_SDID_DIEID_K22FN512 0x00000E80
159 #define KINETIS_SDID_DIEID_K24FN256 0x00000700
161 #define KINETIS_SDID_DIEID_K24FN1M 0x00000300 /* Detect Errata 7534 */
163 /* We can't rely solely on the FAMID field to determine the MCU
164 * type since some FAMID values identify multiple MCUs with
165 * different flash sector sizes (K20 and K22 for instance).
166 * Therefore we combine it with the DIEID bits which may possibly
167 * break if Freescale bumps the DIEID for a particular MCU. */
168 #define KINETIS_K_SDID_TYPE_MASK 0x00000FF0
169 #define KINETIS_K_SDID_K10_M50 0x00000000
170 #define KINETIS_K_SDID_K10_M72 0x00000080
171 #define KINETIS_K_SDID_K10_M100 0x00000100
172 #define KINETIS_K_SDID_K10_M120 0x00000180
173 #define KINETIS_K_SDID_K11 0x00000220
174 #define KINETIS_K_SDID_K12 0x00000200
175 #define KINETIS_K_SDID_K20_M50 0x00000010
176 #define KINETIS_K_SDID_K20_M72 0x00000090
177 #define KINETIS_K_SDID_K20_M100 0x00000110
178 #define KINETIS_K_SDID_K20_M120 0x00000190
179 #define KINETIS_K_SDID_K21_M50 0x00000230
180 #define KINETIS_K_SDID_K21_M120 0x00000330
181 #define KINETIS_K_SDID_K22_M50 0x00000210
182 #define KINETIS_K_SDID_K22_M120 0x00000310
183 #define KINETIS_K_SDID_K30_M72 0x000000A0
184 #define KINETIS_K_SDID_K30_M100 0x00000120
185 #define KINETIS_K_SDID_K40_M72 0x000000B0
186 #define KINETIS_K_SDID_K40_M100 0x00000130
187 #define KINETIS_K_SDID_K50_M72 0x000000E0
188 #define KINETIS_K_SDID_K51_M72 0x000000F0
189 #define KINETIS_K_SDID_K53 0x00000170
190 #define KINETIS_K_SDID_K60_M100 0x00000140
191 #define KINETIS_K_SDID_K60_M150 0x000001C0
192 #define KINETIS_K_SDID_K70_M150 0x000001D0
194 #define KINETIS_K_REVID_MASK 0x0000F000
195 #define KINETIS_K_REVID_SHIFT 12
197 #define KINETIS_SDID_SERIESID_MASK 0x00F00000
198 #define KINETIS_SDID_SERIESID_K 0x00000000
199 #define KINETIS_SDID_SERIESID_KL 0x00100000
200 #define KINETIS_SDID_SERIESID_KE 0x00200000
201 #define KINETIS_SDID_SERIESID_KW 0x00500000
202 #define KINETIS_SDID_SERIESID_KV 0x00600000
204 #define KINETIS_SDID_SUBFAMID_SHIFT 24
205 #define KINETIS_SDID_SUBFAMID_MASK 0x0F000000
206 #define KINETIS_SDID_SUBFAMID_KX0 0x00000000
207 #define KINETIS_SDID_SUBFAMID_KX1 0x01000000
208 #define KINETIS_SDID_SUBFAMID_KX2 0x02000000
209 #define KINETIS_SDID_SUBFAMID_KX3 0x03000000
210 #define KINETIS_SDID_SUBFAMID_KX4 0x04000000
211 #define KINETIS_SDID_SUBFAMID_KX5 0x05000000
212 #define KINETIS_SDID_SUBFAMID_KX6 0x06000000
213 #define KINETIS_SDID_SUBFAMID_KX7 0x07000000
214 #define KINETIS_SDID_SUBFAMID_KX8 0x08000000
216 #define KINETIS_SDID_FAMILYID_SHIFT 28
217 #define KINETIS_SDID_FAMILYID_MASK 0xF0000000
218 #define KINETIS_SDID_FAMILYID_K0X 0x00000000
219 #define KINETIS_SDID_FAMILYID_K1X 0x10000000
220 #define KINETIS_SDID_FAMILYID_K2X 0x20000000
221 #define KINETIS_SDID_FAMILYID_K3X 0x30000000
222 #define KINETIS_SDID_FAMILYID_K4X 0x40000000
223 #define KINETIS_SDID_FAMILYID_K5X 0x50000000
224 #define KINETIS_SDID_FAMILYID_K6X 0x60000000
225 #define KINETIS_SDID_FAMILYID_K7X 0x70000000
226 #define KINETIS_SDID_FAMILYID_K8X 0x80000000
227 #define KINETIS_SDID_FAMILYID_KL8X 0x90000000
229 /* The field originally named DIEID has new name/meaning on KE1x */
230 #define KINETIS_SDID_PROJECTID_MASK KINETIS_SDID_DIEID_MASK
231 #define KINETIS_SDID_PROJECTID_KE1XF 0x00000080
232 #define KINETIS_SDID_PROJECTID_KE1XZ 0x00000100
234 /* The S32K series uses a different, incompatible SDID layout :
235 * Bit 31-28 : GENERATION
236 * Bit 27-24 : SUBSERIES
237 * Bit 23-20 : DERIVATE
238 * Bit 19-16 : RAMSIZE
244 #define KINETIS_SDID_S32K_SERIES_MASK 0xFF000000 /* GENERATION + SUBSERIES */
245 #define KINETIS_SDID_S32K_SERIES_K11X 0x11000000
246 #define KINETIS_SDID_S32K_SERIES_K14X 0x14000000
248 #define KINETIS_SDID_S32K_DERIVATE_MASK 0x00F00000
249 #define KINETIS_SDID_S32K_DERIVATE_KXX2 0x00200000
250 #define KINETIS_SDID_S32K_DERIVATE_KXX3 0x00300000
251 #define KINETIS_SDID_S32K_DERIVATE_KXX4 0x00400000
252 #define KINETIS_SDID_S32K_DERIVATE_KXX5 0x00500000
253 #define KINETIS_SDID_S32K_DERIVATE_KXX6 0x00600000
254 #define KINETIS_SDID_S32K_DERIVATE_KXX8 0x00800000
256 struct kinetis_flash_bank
{
257 struct kinetis_chip
*k_chip
;
259 unsigned bank_number
; /* bank number in particular chip */
260 struct flash_bank
*bank
;
262 uint32_t sector_size
;
263 uint32_t protection_size
;
264 uint32_t prog_base
; /* base address for FTFx operations */
265 /* usually same as bank->base for pflash, differs for FlexNVM */
266 uint32_t protection_block
; /* number of first protection block in this bank */
276 #define KINETIS_MAX_BANKS 4u
278 struct kinetis_chip
{
279 struct target
*target
;
285 uint32_t fcfg2_maxaddr0_shifted
;
286 uint32_t fcfg2_maxaddr1_shifted
;
288 unsigned num_pflash_blocks
, num_nvm_blocks
;
289 unsigned pflash_sector_size
, nvm_sector_size
;
290 unsigned max_flash_prog_size
;
292 uint32_t pflash_base
;
293 uint32_t pflash_size
;
295 uint32_t nvm_size
; /* whole FlexNVM */
296 uint32_t dflash_size
; /* accessible rest of FlexNVM if EEPROM backup uses part of FlexNVM */
298 uint32_t progr_accel_ram
;
307 FS_PROGRAM_SECTOR
= 1,
308 FS_PROGRAM_LONGWORD
= 2,
309 FS_PROGRAM_PHRASE
= 4, /* Unsupported */
311 FS_NO_CMD_BLOCKSTAT
= 0x40,
312 FS_WIDTH_256BIT
= 0x80,
318 KINETIS_CACHE_K
, /* invalidate using FMC->PFB0CR/PFB01CR */
319 KINETIS_CACHE_L
, /* invalidate using MCM->PLACR */
320 KINETIS_CACHE_MSCM
, /* devices like KE1xF, invalidate MSCM->OCMDR0 */
321 KINETIS_CACHE_MSCM2
, /* devices like S32K, invalidate MSCM->OCMDR0 and MSCM->OCMDR1 */
341 struct kinetis_flash_bank banks
[KINETIS_MAX_BANKS
];
344 struct kinetis_type
{
349 static const struct kinetis_type kinetis_types_old
[] = {
350 { KINETIS_K_SDID_K10_M50
, "MK10D%s5" },
351 { KINETIS_K_SDID_K10_M72
, "MK10D%s7" },
352 { KINETIS_K_SDID_K10_M100
, "MK10D%s10" },
353 { KINETIS_K_SDID_K10_M120
, "MK10F%s12" },
354 { KINETIS_K_SDID_K11
, "MK11D%s5" },
355 { KINETIS_K_SDID_K12
, "MK12D%s5" },
357 { KINETIS_K_SDID_K20_M50
, "MK20D%s5" },
358 { KINETIS_K_SDID_K20_M72
, "MK20D%s7" },
359 { KINETIS_K_SDID_K20_M100
, "MK20D%s10" },
360 { KINETIS_K_SDID_K20_M120
, "MK20F%s12" },
361 { KINETIS_K_SDID_K21_M50
, "MK21D%s5" },
362 { KINETIS_K_SDID_K21_M120
, "MK21F%s12" },
363 { KINETIS_K_SDID_K22_M50
, "MK22D%s5" },
364 { KINETIS_K_SDID_K22_M120
, "MK22F%s12" },
366 { KINETIS_K_SDID_K30_M72
, "MK30D%s7" },
367 { KINETIS_K_SDID_K30_M100
, "MK30D%s10" },
369 { KINETIS_K_SDID_K40_M72
, "MK40D%s7" },
370 { KINETIS_K_SDID_K40_M100
, "MK40D%s10" },
372 { KINETIS_K_SDID_K50_M72
, "MK50D%s7" },
373 { KINETIS_K_SDID_K51_M72
, "MK51D%s7" },
374 { KINETIS_K_SDID_K53
, "MK53D%s10" },
376 { KINETIS_K_SDID_K60_M100
, "MK60D%s10" },
377 { KINETIS_K_SDID_K60_M150
, "MK60F%s15" },
379 { KINETIS_K_SDID_K70_M150
, "MK70F%s15" },
385 #define MDM_REG_STAT 0x00
386 #define MDM_REG_CTRL 0x04
387 #define MDM_REG_ID 0xfc
389 #define MDM_STAT_FMEACK (1<<0)
390 #define MDM_STAT_FREADY (1<<1)
391 #define MDM_STAT_SYSSEC (1<<2)
392 #define MDM_STAT_SYSRES (1<<3)
393 #define MDM_STAT_FMEEN (1<<5)
394 #define MDM_STAT_BACKDOOREN (1<<6)
395 #define MDM_STAT_LPEN (1<<7)
396 #define MDM_STAT_VLPEN (1<<8)
397 #define MDM_STAT_LLSMODEXIT (1<<9)
398 #define MDM_STAT_VLLSXMODEXIT (1<<10)
399 #define MDM_STAT_CORE_HALTED (1<<16)
400 #define MDM_STAT_CORE_SLEEPDEEP (1<<17)
401 #define MDM_STAT_CORESLEEPING (1<<18)
403 #define MDM_CTRL_FMEIP (1<<0)
404 #define MDM_CTRL_DBG_DIS (1<<1)
405 #define MDM_CTRL_DBG_REQ (1<<2)
406 #define MDM_CTRL_SYS_RES_REQ (1<<3)
407 #define MDM_CTRL_CORE_HOLD_RES (1<<4)
408 #define MDM_CTRL_VLLSX_DBG_REQ (1<<5)
409 #define MDM_CTRL_VLLSX_DBG_ACK (1<<6)
410 #define MDM_CTRL_VLLSX_STAT_ACK (1<<7)
412 #define MDM_ACCESS_TIMEOUT 500 /* msec */
415 static bool allow_fcf_writes
;
416 static uint8_t fcf_fopt
= 0xff;
417 static bool create_banks
;
420 const struct flash_driver kinetis_flash
;
421 static int kinetis_write_inner(struct flash_bank
*bank
, const uint8_t *buffer
,
422 uint32_t offset
, uint32_t count
);
423 static int kinetis_probe_chip(struct kinetis_chip
*k_chip
);
424 static int kinetis_probe_chip_s32k(struct kinetis_chip
*k_chip
);
425 static int kinetis_auto_probe(struct flash_bank
*bank
);
428 static int kinetis_mdm_write_register(struct adiv5_dap
*dap
, unsigned reg
, uint32_t value
)
430 LOG_DEBUG("MDM_REG[0x%02x] <- %08" PRIX32
, reg
, value
);
432 struct adiv5_ap
*ap
= dap_get_ap(dap
, MDM_AP
);
434 LOG_DEBUG("MDM: failed to get AP");
438 int retval
= dap_queue_ap_write(ap
, reg
, value
);
439 if (retval
!= ERROR_OK
) {
440 LOG_DEBUG("MDM: failed to queue a write request");
445 retval
= dap_run(dap
);
447 if (retval
!= ERROR_OK
) {
448 LOG_DEBUG("MDM: dap_run failed");
456 static int kinetis_mdm_read_register(struct adiv5_dap
*dap
, unsigned reg
, uint32_t *result
)
458 struct adiv5_ap
*ap
= dap_get_ap(dap
, MDM_AP
);
460 LOG_DEBUG("MDM: failed to get AP");
464 int retval
= dap_queue_ap_read(ap
, reg
, result
);
465 if (retval
!= ERROR_OK
) {
466 LOG_DEBUG("MDM: failed to queue a read request");
471 retval
= dap_run(dap
);
473 if (retval
!= ERROR_OK
) {
474 LOG_DEBUG("MDM: dap_run failed");
478 LOG_DEBUG("MDM_REG[0x%02x]: %08" PRIX32
, reg
, *result
);
482 static int kinetis_mdm_poll_register(struct adiv5_dap
*dap
, unsigned reg
,
483 uint32_t mask
, uint32_t value
, uint32_t timeout_ms
)
487 int64_t ms_timeout
= timeval_ms() + timeout_ms
;
490 retval
= kinetis_mdm_read_register(dap
, reg
, &val
);
491 if (retval
!= ERROR_OK
|| (val
& mask
) == value
)
495 } while (timeval_ms() < ms_timeout
);
497 LOG_DEBUG("MDM: polling timed out");
502 * This command can be used to break a watchdog reset loop when
503 * connecting to an unsecured target. Unlike other commands, halt will
504 * automatically retry as it does not know how far into the boot process
505 * it is when the command is called.
507 COMMAND_HANDLER(kinetis_mdm_halt
)
509 struct target
*target
= get_current_target(CMD_CTX
);
510 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
511 struct adiv5_dap
*dap
= cortex_m
->armv7m
.arm
.dap
;
515 int64_t ms_timeout
= timeval_ms() + MDM_ACCESS_TIMEOUT
;
518 LOG_ERROR("Cannot perform halt with a high-level adapter");
525 kinetis_mdm_write_register(dap
, MDM_REG_CTRL
, MDM_CTRL_CORE_HOLD_RES
);
529 retval
= kinetis_mdm_read_register(dap
, MDM_REG_STAT
, &stat
);
530 if (retval
!= ERROR_OK
) {
531 LOG_DEBUG("MDM: failed to read MDM_REG_STAT");
535 /* Repeat setting MDM_CTRL_CORE_HOLD_RES until system is out of
536 * reset with flash ready and without security
538 if ((stat
& (MDM_STAT_FREADY
| MDM_STAT_SYSSEC
| MDM_STAT_SYSRES
))
539 == (MDM_STAT_FREADY
| MDM_STAT_SYSRES
))
542 if (timeval_ms() >= ms_timeout
) {
543 LOG_ERROR("MDM: halt timed out");
548 LOG_DEBUG("MDM: halt succeeded after %d attempts.", tries
);
551 /* enable polling in case kinetis_check_flash_security_status disabled it */
552 jtag_poll_set_enabled(true);
556 target
->reset_halt
= true;
557 target
->type
->assert_reset(target
);
559 retval
= kinetis_mdm_write_register(dap
, MDM_REG_CTRL
, 0);
560 if (retval
!= ERROR_OK
) {
561 LOG_ERROR("MDM: failed to clear MDM_REG_CTRL");
565 target
->type
->deassert_reset(target
);
570 COMMAND_HANDLER(kinetis_mdm_reset
)
572 struct target
*target
= get_current_target(CMD_CTX
);
573 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
574 struct adiv5_dap
*dap
= cortex_m
->armv7m
.arm
.dap
;
578 LOG_ERROR("Cannot perform reset with a high-level adapter");
582 retval
= kinetis_mdm_write_register(dap
, MDM_REG_CTRL
, MDM_CTRL_SYS_RES_REQ
);
583 if (retval
!= ERROR_OK
) {
584 LOG_ERROR("MDM: failed to write MDM_REG_CTRL");
588 retval
= kinetis_mdm_poll_register(dap
, MDM_REG_STAT
, MDM_STAT_SYSRES
, 0, 500);
589 if (retval
!= ERROR_OK
) {
590 LOG_ERROR("MDM: failed to assert reset");
594 retval
= kinetis_mdm_write_register(dap
, MDM_REG_CTRL
, 0);
595 if (retval
!= ERROR_OK
) {
596 LOG_ERROR("MDM: failed to clear MDM_REG_CTRL");
604 * This function implements the procedure to mass erase the flash via
605 * SWD/JTAG on Kinetis K and L series of devices as it is described in
606 * AN4835 "Production Flash Programming Best Practices for Kinetis K-
607 * and L-series MCUs" Section 4.2.1. To prevent a watchdog reset loop,
608 * the core remains halted after this function completes as suggested
609 * by the application note.
611 COMMAND_HANDLER(kinetis_mdm_mass_erase
)
613 struct target
*target
= get_current_target(CMD_CTX
);
614 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
615 struct adiv5_dap
*dap
= cortex_m
->armv7m
.arm
.dap
;
618 LOG_ERROR("Cannot perform mass erase with a high-level adapter");
625 * ... Power on the processor, or if power has already been
626 * applied, assert the RESET pin to reset the processor. For
627 * devices that do not have a RESET pin, write the System
628 * Reset Request bit in the MDM-AP control register after
629 * establishing communication...
632 /* assert SRST if configured */
633 bool has_srst
= jtag_get_reset_config() & RESET_HAS_SRST
;
635 adapter_assert_reset();
637 retval
= kinetis_mdm_write_register(dap
, MDM_REG_CTRL
, MDM_CTRL_SYS_RES_REQ
);
638 if (retval
!= ERROR_OK
&& !has_srst
) {
639 LOG_ERROR("MDM: failed to assert reset");
640 goto deassert_reset_and_exit
;
644 * ... Read the MDM-AP status register repeatedly and wait for
645 * stable conditions suitable for mass erase:
646 * - mass erase is enabled
648 * - reset is finished
650 * Mass erase is started as soon as all conditions are met in 32
651 * subsequent status reads.
653 * In case of not stable conditions (RESET/WDOG loop in secured device)
654 * the user is asked for manual pressing of RESET button
657 int cnt_mass_erase_disabled
= 0;
659 int64_t ms_start
= timeval_ms();
660 bool man_reset_requested
= false;
664 int64_t ms_elapsed
= timeval_ms() - ms_start
;
666 if (!man_reset_requested
&& ms_elapsed
> 100) {
667 LOG_INFO("MDM: Press RESET button now if possible.");
668 man_reset_requested
= true;
671 if (ms_elapsed
> 3000) {
672 LOG_ERROR("MDM: waiting for mass erase conditions timed out.");
673 LOG_INFO("Mass erase of a secured MCU is not possible without hardware reset.");
674 LOG_INFO("Connect SRST, use 'reset_config srst_only' and retry.");
675 goto deassert_reset_and_exit
;
677 retval
= kinetis_mdm_read_register(dap
, MDM_REG_STAT
, &stat
);
678 if (retval
!= ERROR_OK
) {
683 if (!(stat
& MDM_STAT_FMEEN
)) {
685 cnt_mass_erase_disabled
++;
686 if (cnt_mass_erase_disabled
> 10) {
687 LOG_ERROR("MDM: mass erase is disabled");
688 goto deassert_reset_and_exit
;
693 if ((stat
& (MDM_STAT_FREADY
| MDM_STAT_SYSRES
)) == MDM_STAT_FREADY
)
698 } while (cnt_ready
< 32);
701 * ... Write the MDM-AP control register to set the Flash Mass
702 * Erase in Progress bit. This will start the mass erase
705 retval
= kinetis_mdm_write_register(dap
, MDM_REG_CTRL
, MDM_CTRL_SYS_RES_REQ
| MDM_CTRL_FMEIP
);
706 if (retval
!= ERROR_OK
) {
707 LOG_ERROR("MDM: failed to start mass erase");
708 goto deassert_reset_and_exit
;
712 * ... Read the MDM-AP control register until the Flash Mass
713 * Erase in Progress bit clears...
714 * Data sheed defines erase time <3.6 sec/512kB flash block.
715 * The biggest device has 4 pflash blocks => timeout 16 sec.
717 retval
= kinetis_mdm_poll_register(dap
, MDM_REG_CTRL
, MDM_CTRL_FMEIP
, 0, 16000);
718 if (retval
!= ERROR_OK
) {
719 LOG_ERROR("MDM: mass erase timeout");
720 goto deassert_reset_and_exit
;
724 /* enable polling in case kinetis_check_flash_security_status disabled it */
725 jtag_poll_set_enabled(true);
729 target
->reset_halt
= true;
730 target
->type
->assert_reset(target
);
733 * ... Negate the RESET signal or clear the System Reset Request
734 * bit in the MDM-AP control register.
736 retval
= kinetis_mdm_write_register(dap
, MDM_REG_CTRL
, 0);
737 if (retval
!= ERROR_OK
)
738 LOG_ERROR("MDM: failed to clear MDM_REG_CTRL");
740 target
->type
->deassert_reset(target
);
744 deassert_reset_and_exit
:
745 kinetis_mdm_write_register(dap
, MDM_REG_CTRL
, 0);
747 adapter_deassert_reset();
751 static const uint32_t kinetis_known_mdm_ids
[] = {
752 0x001C0000, /* Kinetis-K Series */
753 0x001C0020, /* Kinetis-L/M/V/E Series */
754 0x001C0030, /* Kinetis with a Cortex-M7, in time of writing KV58 */
758 * This function implements the procedure to connect to
759 * SWD/JTAG on Kinetis K and L series of devices as it is described in
760 * AN4835 "Production Flash Programming Best Practices for Kinetis K-
761 * and L-series MCUs" Section 4.1.1
763 COMMAND_HANDLER(kinetis_check_flash_security_status
)
765 struct target
*target
= get_current_target(CMD_CTX
);
766 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
767 struct adiv5_dap
*dap
= cortex_m
->armv7m
.arm
.dap
;
770 LOG_WARNING("Cannot check flash security status with a high-level adapter");
775 return ERROR_OK
; /* too early to check, in JTAG mode ops may not be initialised */
781 * ... The MDM-AP ID register can be read to verify that the
782 * connection is working correctly...
784 retval
= kinetis_mdm_read_register(dap
, MDM_REG_ID
, &val
);
785 if (retval
!= ERROR_OK
) {
786 LOG_ERROR("MDM: failed to read ID register");
791 return ERROR_OK
; /* dap not yet initialised */
794 for (size_t i
= 0; i
< ARRAY_SIZE(kinetis_known_mdm_ids
); i
++) {
795 if (val
== kinetis_known_mdm_ids
[i
]) {
802 LOG_WARNING("MDM: unknown ID %08" PRIX32
, val
);
805 * ... Read the System Security bit to determine if security is enabled.
806 * If System Security = 0, then proceed. If System Security = 1, then
807 * communication with the internals of the processor, including the
808 * flash, will not be possible without issuing a mass erase command or
809 * unsecuring the part through other means (backdoor key unlock)...
811 retval
= kinetis_mdm_read_register(dap
, MDM_REG_STAT
, &val
);
812 if (retval
!= ERROR_OK
) {
813 LOG_ERROR("MDM: failed to read MDM_REG_STAT");
818 * System Security bit is also active for short time during reset.
819 * If a MCU has blank flash and runs in RESET/WDOG loop,
820 * System Security bit is active most of time!
821 * We should observe Flash Ready bit and read status several times
822 * to avoid false detection of secured MCU
824 int secured_score
= 0, flash_not_ready_score
= 0;
826 if ((val
& (MDM_STAT_SYSSEC
| MDM_STAT_FREADY
)) != MDM_STAT_FREADY
) {
828 struct adiv5_ap
*ap
= dap_get_ap(dap
, MDM_AP
);
830 LOG_ERROR("MDM: failed to get AP");
834 for (unsigned int i
= 0; i
< 32; i
++) {
835 stats
[i
] = MDM_STAT_FREADY
;
836 dap_queue_ap_read(ap
, MDM_REG_STAT
, &stats
[i
]);
838 retval
= dap_run(dap
);
840 if (retval
!= ERROR_OK
) {
841 LOG_DEBUG("MDM: dap_run failed when validating secured state");
844 for (unsigned int i
= 0; i
< 32; i
++) {
845 if (stats
[i
] & MDM_STAT_SYSSEC
)
847 if (!(stats
[i
] & MDM_STAT_FREADY
))
848 flash_not_ready_score
++;
852 if (flash_not_ready_score
<= 8 && secured_score
> 24) {
853 jtag_poll_set_enabled(false);
855 LOG_WARNING("*********** ATTENTION! ATTENTION! ATTENTION! ATTENTION! **********");
856 LOG_WARNING("**** ****");
857 LOG_WARNING("**** Your Kinetis MCU is in secured state, which means that, ****");
858 LOG_WARNING("**** with exception for very basic communication, JTAG/SWD ****");
859 LOG_WARNING("**** interface will NOT work. In order to restore its ****");
860 LOG_WARNING("**** functionality please issue 'kinetis mdm mass_erase' ****");
861 LOG_WARNING("**** command, power cycle the MCU and restart OpenOCD. ****");
862 LOG_WARNING("**** ****");
863 LOG_WARNING("*********** ATTENTION! ATTENTION! ATTENTION! ATTENTION! **********");
865 } else if (flash_not_ready_score
> 24) {
866 jtag_poll_set_enabled(false);
867 LOG_WARNING("**** Your Kinetis MCU is probably locked-up in RESET/WDOG loop. ****");
868 LOG_WARNING("**** Common reason is a blank flash (at least a reset vector). ****");
869 LOG_WARNING("**** Issue 'kinetis mdm halt' command or if SRST is connected ****");
870 LOG_WARNING("**** and configured, use 'reset halt' ****");
871 LOG_WARNING("**** If MCU cannot be halted, it is likely secured and running ****");
872 LOG_WARNING("**** in RESET/WDOG loop. Issue 'kinetis mdm mass_erase' ****");
875 LOG_INFO("MDM: Chip is unsecured. Continuing.");
876 jtag_poll_set_enabled(true);
883 static struct kinetis_chip
*kinetis_get_chip(struct target
*target
)
885 struct flash_bank
*bank_iter
;
886 struct kinetis_flash_bank
*k_bank
;
888 /* iterate over all kinetis banks */
889 for (bank_iter
= flash_bank_list(); bank_iter
; bank_iter
= bank_iter
->next
) {
890 if (bank_iter
->driver
!= &kinetis_flash
891 || bank_iter
->target
!= target
)
894 k_bank
= bank_iter
->driver_priv
;
899 return k_bank
->k_chip
;
904 static int kinetis_chip_options(struct kinetis_chip
*k_chip
, int argc
, const char *argv
[])
906 for (int i
= 0; i
< argc
; i
++) {
907 if (strcmp(argv
[i
], "-sim-base") == 0) {
909 k_chip
->sim_base
= strtoul(argv
[++i
], NULL
, 0);
910 } else if (strcmp(argv
[i
], "-s32k") == 0) {
911 k_chip
->chip_type
= CT_S32K
;
913 LOG_ERROR("Unsupported flash bank option %s", argv
[i
]);
918 FLASH_BANK_COMMAND_HANDLER(kinetis_flash_bank_command
)
920 struct target
*target
= bank
->target
;
921 struct kinetis_chip
*k_chip
;
922 struct kinetis_flash_bank
*k_bank
;
926 return ERROR_COMMAND_SYNTAX_ERROR
;
928 LOG_INFO("add flash_bank kinetis %s", bank
->name
);
930 k_chip
= kinetis_get_chip(target
);
933 k_chip
= calloc(sizeof(struct kinetis_chip
), 1);
935 LOG_ERROR("No memory");
939 k_chip
->target
= target
;
941 /* only the first defined bank can define chip options */
942 retval
= kinetis_chip_options(k_chip
, CMD_ARGC
- 6, CMD_ARGV
+ 6);
943 if (retval
!= ERROR_OK
)
947 if (k_chip
->num_banks
>= KINETIS_MAX_BANKS
) {
948 LOG_ERROR("Only %u Kinetis flash banks are supported", KINETIS_MAX_BANKS
);
952 bank
->driver_priv
= k_bank
= &(k_chip
->banks
[k_chip
->num_banks
]);
953 k_bank
->k_chip
= k_chip
;
954 k_bank
->bank_number
= k_chip
->num_banks
;
962 static void kinetis_free_driver_priv(struct flash_bank
*bank
)
964 struct kinetis_flash_bank
*k_bank
= bank
->driver_priv
;
968 struct kinetis_chip
*k_chip
= k_bank
->k_chip
;
973 if (k_chip
->num_banks
== 0)
978 static int kinetis_create_missing_banks(struct kinetis_chip
*k_chip
)
981 struct kinetis_flash_bank
*k_bank
;
982 struct flash_bank
*bank
;
983 char base_name
[69], name
[87], num
[11];
986 num_blocks
= k_chip
->num_pflash_blocks
+ k_chip
->num_nvm_blocks
;
987 if (num_blocks
> KINETIS_MAX_BANKS
) {
988 LOG_ERROR("Only %u Kinetis flash banks are supported", KINETIS_MAX_BANKS
);
992 bank
= k_chip
->banks
[0].bank
;
993 if (bank
&& bank
->name
) {
994 strncpy(base_name
, bank
->name
, sizeof(base_name
) - 1);
995 base_name
[sizeof(base_name
) - 1] = '\0';
996 p
= strstr(base_name
, ".pflash");
999 if (k_chip
->num_pflash_blocks
> 1) {
1000 /* rename first bank if numbering is needed */
1001 snprintf(name
, sizeof(name
), "%s.pflash0", base_name
);
1003 bank
->name
= strdup(name
);
1007 strncpy(base_name
, target_name(k_chip
->target
), sizeof(base_name
) - 1);
1008 base_name
[sizeof(base_name
) - 1] = '\0';
1009 p
= strstr(base_name
, ".cpu");
1014 for (unsigned int bank_idx
= 1; bank_idx
< num_blocks
; bank_idx
++) {
1015 k_bank
= &(k_chip
->banks
[bank_idx
]);
1016 bank
= k_bank
->bank
;
1023 if (bank_idx
< k_chip
->num_pflash_blocks
) {
1025 if (k_chip
->num_pflash_blocks
> 1)
1026 snprintf(num
, sizeof(num
), "%u", bank_idx
);
1029 if (k_chip
->num_nvm_blocks
> 1)
1030 snprintf(num
, sizeof(num
), "%u",
1031 bank_idx
- k_chip
->num_pflash_blocks
);
1034 bank
= calloc(sizeof(struct flash_bank
), 1);
1038 bank
->target
= k_chip
->target
;
1039 bank
->driver
= &kinetis_flash
;
1040 bank
->default_padded_value
= bank
->erased_value
= 0xff;
1042 snprintf(name
, sizeof(name
), "%s.%s%s",
1043 base_name
, class, num
);
1044 bank
->name
= strdup(name
);
1046 bank
->driver_priv
= k_bank
= &(k_chip
->banks
[k_chip
->num_banks
]);
1047 k_bank
->k_chip
= k_chip
;
1048 k_bank
->bank_number
= bank_idx
;
1049 k_bank
->bank
= bank
;
1050 if (k_chip
->num_banks
<= bank_idx
)
1051 k_chip
->num_banks
= bank_idx
+ 1;
1053 flash_bank_add(bank
);
1059 static int kinetis_disable_wdog_algo(struct target
*target
, size_t code_size
, const uint8_t *code
, uint32_t wdog_base
)
1061 struct working_area
*wdog_algorithm
;
1062 struct armv7m_algorithm armv7m_info
;
1063 struct reg_param reg_params
[1];
1066 if (target
->state
!= TARGET_HALTED
) {
1067 LOG_ERROR("Target not halted");
1068 return ERROR_TARGET_NOT_HALTED
;
1071 retval
= target_alloc_working_area(target
, code_size
, &wdog_algorithm
);
1072 if (retval
!= ERROR_OK
)
1075 retval
= target_write_buffer(target
, wdog_algorithm
->address
,
1077 if (retval
== ERROR_OK
) {
1078 armv7m_info
.common_magic
= ARMV7M_COMMON_MAGIC
;
1079 armv7m_info
.core_mode
= ARM_MODE_THREAD
;
1081 init_reg_param(®_params
[0], "r0", 32, PARAM_OUT
);
1082 buf_set_u32(reg_params
[0].value
, 0, 32, wdog_base
);
1084 retval
= target_run_algorithm(target
, 0, NULL
, 1, reg_params
,
1085 wdog_algorithm
->address
,
1086 wdog_algorithm
->address
+ code_size
- 2,
1089 destroy_reg_param(®_params
[0]);
1091 if (retval
!= ERROR_OK
)
1092 LOG_ERROR("Error executing Kinetis WDOG unlock algorithm");
1095 target_free_working_area(target
, wdog_algorithm
);
1100 /* Disable the watchdog on Kinetis devices
1101 * Standard Kx WDOG peripheral checks timing and therefore requires to run algo.
1103 static int kinetis_disable_wdog_kx(struct target
*target
)
1105 const uint32_t wdog_base
= WDOG_BASE
;
1109 static const uint8_t kinetis_unlock_wdog_code
[] = {
1110 #include "../../../contrib/loaders/watchdog/armv7m_kinetis_wdog.inc"
1113 retval
= target_read_u16(target
, wdog_base
+ WDOG_STCTRLH_OFFSET
, &wdog
);
1114 if (retval
!= ERROR_OK
)
1117 if ((wdog
& 0x1) == 0) {
1118 /* watchdog already disabled */
1121 LOG_INFO("Disabling Kinetis watchdog (initial WDOG_STCTRLH = 0x%04" PRIx16
")", wdog
);
1123 retval
= kinetis_disable_wdog_algo(target
, sizeof(kinetis_unlock_wdog_code
), kinetis_unlock_wdog_code
, wdog_base
);
1124 if (retval
!= ERROR_OK
)
1127 retval
= target_read_u16(target
, wdog_base
+ WDOG_STCTRLH_OFFSET
, &wdog
);
1128 if (retval
!= ERROR_OK
)
1131 LOG_INFO("WDOG_STCTRLH = 0x%04" PRIx16
, wdog
);
1132 return (wdog
& 0x1) ? ERROR_FAIL
: ERROR_OK
;
1135 static int kinetis_disable_wdog32(struct target
*target
, uint32_t wdog_base
)
1140 static const uint8_t kinetis_unlock_wdog_code
[] = {
1141 #include "../../../contrib/loaders/watchdog/armv7m_kinetis_wdog32.inc"
1144 retval
= target_read_u32(target
, wdog_base
+ WDOG32_CS_OFFSET
, &wdog_cs
);
1145 if (retval
!= ERROR_OK
)
1148 if ((wdog_cs
& 0x80) == 0)
1149 return ERROR_OK
; /* watchdog already disabled */
1151 LOG_INFO("Disabling Kinetis watchdog (initial WDOG_CS 0x%08" PRIx32
")", wdog_cs
);
1153 retval
= kinetis_disable_wdog_algo(target
, sizeof(kinetis_unlock_wdog_code
), kinetis_unlock_wdog_code
, wdog_base
);
1154 if (retval
!= ERROR_OK
)
1157 retval
= target_read_u32(target
, wdog_base
+ WDOG32_CS_OFFSET
, &wdog_cs
);
1158 if (retval
!= ERROR_OK
)
1161 if ((wdog_cs
& 0x80) == 0)
1162 return ERROR_OK
; /* watchdog disabled successfully */
1164 LOG_ERROR("Cannot disable Kinetis watchdog (WDOG_CS 0x%08" PRIx32
"), issue 'reset init'", wdog_cs
);
1168 static int kinetis_disable_wdog(struct kinetis_chip
*k_chip
)
1170 struct target
*target
= k_chip
->target
;
1174 if (!k_chip
->probed
) {
1175 switch (k_chip
->chip_type
) {
1177 retval
= kinetis_probe_chip_s32k(k_chip
);
1180 retval
= kinetis_probe_chip(k_chip
);
1182 if (retval
!= ERROR_OK
)
1186 switch (k_chip
->watchdog_type
) {
1187 case KINETIS_WDOG_K
:
1188 return kinetis_disable_wdog_kx(target
);
1190 case KINETIS_WDOG_COP
:
1191 retval
= target_read_u8(target
, SIM_COPC
, &sim_copc
);
1192 if (retval
!= ERROR_OK
)
1195 if ((sim_copc
& 0xc) == 0)
1196 return ERROR_OK
; /* watchdog already disabled */
1198 LOG_INFO("Disabling Kinetis watchdog (initial SIM_COPC 0x%02" PRIx8
")", sim_copc
);
1199 retval
= target_write_u8(target
, SIM_COPC
, sim_copc
& ~0xc);
1200 if (retval
!= ERROR_OK
)
1203 retval
= target_read_u8(target
, SIM_COPC
, &sim_copc
);
1204 if (retval
!= ERROR_OK
)
1207 if ((sim_copc
& 0xc) == 0)
1208 return ERROR_OK
; /* watchdog disabled successfully */
1210 LOG_ERROR("Cannot disable Kinetis watchdog (SIM_COPC 0x%02" PRIx8
"), issue 'reset init'", sim_copc
);
1213 case KINETIS_WDOG32_KE1X
:
1214 return kinetis_disable_wdog32(target
, WDOG32_KE1X
);
1216 case KINETIS_WDOG32_KL28
:
1217 return kinetis_disable_wdog32(target
, WDOG32_KL28
);
1224 COMMAND_HANDLER(kinetis_disable_wdog_handler
)
1227 struct target
*target
= get_current_target(CMD_CTX
);
1228 struct kinetis_chip
*k_chip
= kinetis_get_chip(target
);
1234 return ERROR_COMMAND_SYNTAX_ERROR
;
1236 result
= kinetis_disable_wdog(k_chip
);
1241 static int kinetis_ftfx_decode_error(uint8_t fstat
)
1244 LOG_ERROR("Flash operation failed, illegal command");
1245 return ERROR_FLASH_OPER_UNSUPPORTED
;
1247 } else if (fstat
& 0x10)
1248 LOG_ERROR("Flash operation failed, protection violated");
1250 else if (fstat
& 0x40)
1251 LOG_ERROR("Flash operation failed, read collision");
1253 else if (fstat
& 0x80)
1257 LOG_ERROR("Flash operation timed out");
1259 return ERROR_FLASH_OPERATION_FAILED
;
1262 static int kinetis_ftfx_clear_error(struct target
*target
)
1264 /* reset error flags */
1265 return target_write_u8(target
, FTFX_FSTAT
, 0x70);
1269 static int kinetis_ftfx_prepare(struct target
*target
)
1274 /* wait until busy */
1275 for (unsigned int i
= 0; i
< 50; i
++) {
1276 result
= target_read_u8(target
, FTFX_FSTAT
, &fstat
);
1277 if (result
!= ERROR_OK
)
1284 if ((fstat
& 0x80) == 0) {
1285 LOG_ERROR("Flash controller is busy");
1286 return ERROR_FLASH_OPERATION_FAILED
;
1288 if (fstat
!= 0x80) {
1289 /* reset error flags */
1290 result
= kinetis_ftfx_clear_error(target
);
1295 /* Kinetis Program-LongWord Microcodes */
1296 static const uint8_t kinetis_flash_write_code
[] = {
1297 #include "../../../contrib/loaders/flash/kinetis/kinetis_flash.inc"
1300 /* Program LongWord Block Write */
1301 static int kinetis_write_block(struct flash_bank
*bank
, const uint8_t *buffer
,
1302 uint32_t offset
, uint32_t wcount
)
1304 struct target
*target
= bank
->target
;
1305 uint32_t buffer_size
;
1306 struct working_area
*write_algorithm
;
1307 struct working_area
*source
;
1308 struct kinetis_flash_bank
*k_bank
= bank
->driver_priv
;
1309 uint32_t address
= k_bank
->prog_base
+ offset
;
1310 uint32_t end_address
;
1311 struct reg_param reg_params
[5];
1312 struct armv7m_algorithm armv7m_info
;
1316 /* allocate working area with flash programming code */
1317 if (target_alloc_working_area(target
, sizeof(kinetis_flash_write_code
),
1318 &write_algorithm
) != ERROR_OK
) {
1319 LOG_WARNING("no working area available, can't do block memory writes");
1320 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1323 retval
= target_write_buffer(target
, write_algorithm
->address
,
1324 sizeof(kinetis_flash_write_code
), kinetis_flash_write_code
);
1325 if (retval
!= ERROR_OK
)
1328 /* memory buffer, size *must* be multiple of word */
1329 buffer_size
= target_get_working_area_avail(target
) & ~(sizeof(uint32_t) - 1);
1330 if (buffer_size
< 256) {
1331 LOG_WARNING("large enough working area not available, can't do block memory writes");
1332 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1333 } else if (buffer_size
> 16384) {
1334 /* probably won't benefit from more than 16k ... */
1335 buffer_size
= 16384;
1338 if (target_alloc_working_area(target
, buffer_size
, &source
) != ERROR_OK
) {
1339 LOG_ERROR("allocating working area failed");
1340 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1343 armv7m_info
.common_magic
= ARMV7M_COMMON_MAGIC
;
1344 armv7m_info
.core_mode
= ARM_MODE_THREAD
;
1346 init_reg_param(®_params
[0], "r0", 32, PARAM_IN_OUT
); /* address */
1347 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
); /* word count */
1348 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
);
1349 init_reg_param(®_params
[3], "r3", 32, PARAM_OUT
);
1350 init_reg_param(®_params
[4], "r4", 32, PARAM_OUT
);
1352 buf_set_u32(reg_params
[0].value
, 0, 32, address
);
1353 buf_set_u32(reg_params
[1].value
, 0, 32, wcount
);
1354 buf_set_u32(reg_params
[2].value
, 0, 32, source
->address
);
1355 buf_set_u32(reg_params
[3].value
, 0, 32, source
->address
+ source
->size
);
1356 buf_set_u32(reg_params
[4].value
, 0, 32, FTFX_FSTAT
);
1358 retval
= target_run_flash_async_algorithm(target
, buffer
, wcount
, 4,
1361 source
->address
, source
->size
,
1362 write_algorithm
->address
, 0,
1365 if (retval
== ERROR_FLASH_OPERATION_FAILED
) {
1366 end_address
= buf_get_u32(reg_params
[0].value
, 0, 32);
1368 LOG_ERROR("Error writing flash at %08" PRIx32
, end_address
);
1370 retval
= target_read_u8(target
, FTFX_FSTAT
, &fstat
);
1371 if (retval
== ERROR_OK
) {
1372 retval
= kinetis_ftfx_decode_error(fstat
);
1374 /* reset error flags */
1375 target_write_u8(target
, FTFX_FSTAT
, 0x70);
1377 } else if (retval
!= ERROR_OK
)
1378 LOG_ERROR("Error executing kinetis Flash programming algorithm");
1380 target_free_working_area(target
, source
);
1381 target_free_working_area(target
, write_algorithm
);
1383 destroy_reg_param(®_params
[0]);
1384 destroy_reg_param(®_params
[1]);
1385 destroy_reg_param(®_params
[2]);
1386 destroy_reg_param(®_params
[3]);
1387 destroy_reg_param(®_params
[4]);
1392 static int kinetis_protect(struct flash_bank
*bank
, int set
, unsigned int first
,
1395 if (allow_fcf_writes
) {
1396 LOG_ERROR("Protection setting is possible with 'kinetis fcf_source protection' only!");
1400 if (!bank
->prot_blocks
|| bank
->num_prot_blocks
== 0) {
1401 LOG_ERROR("No protection possible for current bank!");
1402 return ERROR_FLASH_BANK_INVALID
;
1405 for (unsigned int i
= first
; i
< bank
->num_prot_blocks
&& i
<= last
; i
++)
1406 bank
->prot_blocks
[i
].is_protected
= set
;
1408 LOG_INFO("Protection bits will be written at the next FCF sector erase or write.");
1409 LOG_INFO("Do not issue 'flash info' command until protection is written,");
1410 LOG_INFO("doing so would re-read protection status from MCU.");
1415 static int kinetis_protect_check(struct flash_bank
*bank
)
1417 struct kinetis_flash_bank
*k_bank
= bank
->driver_priv
;
1422 if (k_bank
->flash_class
== FC_PFLASH
) {
1424 /* read protection register */
1425 result
= target_read_u32(bank
->target
, FTFX_FPROT3
, &fprot
);
1426 if (result
!= ERROR_OK
)
1429 /* Every bit protects 1/32 of the full flash (not necessarily just this bank) */
1431 } else if (k_bank
->flash_class
== FC_FLEX_NVM
) {
1434 /* read protection register */
1435 result
= target_read_u8(bank
->target
, FTFX_FDPROT
, &fdprot
);
1436 if (result
!= ERROR_OK
)
1442 LOG_ERROR("Protection checks for FlexRAM not supported");
1443 return ERROR_FLASH_BANK_INVALID
;
1446 b
= k_bank
->protection_block
;
1447 for (unsigned int i
= 0; i
< bank
->num_prot_blocks
; i
++) {
1448 if ((fprot
>> b
) & 1)
1449 bank
->prot_blocks
[i
].is_protected
= 0;
1451 bank
->prot_blocks
[i
].is_protected
= 1;
1460 static int kinetis_fill_fcf(struct flash_bank
*bank
, uint8_t *fcf
)
1462 uint32_t fprot
= 0xffffffff;
1463 uint8_t fsec
= 0xfe; /* set MCU unsecure */
1464 uint8_t fdprot
= 0xff;
1465 unsigned num_blocks
;
1466 uint32_t pflash_bit
;
1468 struct flash_bank
*bank_iter
;
1469 struct kinetis_flash_bank
*k_bank
= bank
->driver_priv
;
1470 struct kinetis_chip
*k_chip
= k_bank
->k_chip
;
1472 memset(fcf
, 0xff, FCF_SIZE
);
1477 /* iterate over all kinetis banks */
1478 /* current bank is bank 0, it contains FCF */
1479 num_blocks
= k_chip
->num_pflash_blocks
+ k_chip
->num_nvm_blocks
;
1480 for (unsigned int bank_idx
= 0; bank_idx
< num_blocks
; bank_idx
++) {
1481 k_bank
= &(k_chip
->banks
[bank_idx
]);
1482 bank_iter
= k_bank
->bank
;
1485 LOG_WARNING("Missing bank %u configuration, FCF protection flags may be incomplete", bank_idx
);
1489 kinetis_auto_probe(bank_iter
);
1491 assert(bank_iter
->prot_blocks
);
1493 if (k_bank
->flash_class
== FC_PFLASH
) {
1494 for (unsigned int i
= 0; i
< bank_iter
->num_prot_blocks
; i
++) {
1495 if (bank_iter
->prot_blocks
[i
].is_protected
== 1)
1496 fprot
&= ~pflash_bit
;
1501 } else if (k_bank
->flash_class
== FC_FLEX_NVM
) {
1502 for (unsigned int i
= 0; i
< bank_iter
->num_prot_blocks
; i
++) {
1503 if (bank_iter
->prot_blocks
[i
].is_protected
== 1)
1504 fdprot
&= ~dflash_bit
;
1512 target_buffer_set_u32(bank
->target
, fcf
+ FCF_FPROT
, fprot
);
1513 fcf
[FCF_FSEC
] = fsec
;
1514 fcf
[FCF_FOPT
] = fcf_fopt
;
1515 fcf
[FCF_FDPROT
] = fdprot
;
1519 static int kinetis_ftfx_command(struct target
*target
, uint8_t fcmd
, uint32_t faddr
,
1520 uint8_t fccob4
, uint8_t fccob5
, uint8_t fccob6
, uint8_t fccob7
,
1521 uint8_t fccob8
, uint8_t fccob9
, uint8_t fccoba
, uint8_t fccobb
,
1522 uint8_t *ftfx_fstat
)
1524 uint8_t command
[12] = {faddr
& 0xff, (faddr
>> 8) & 0xff, (faddr
>> 16) & 0xff, fcmd
,
1525 fccob7
, fccob6
, fccob5
, fccob4
,
1526 fccobb
, fccoba
, fccob9
, fccob8
};
1529 int64_t ms_timeout
= timeval_ms() + 250;
1531 result
= target_write_memory(target
, FTFX_FCCOB3
, 4, 3, command
);
1532 if (result
!= ERROR_OK
)
1536 result
= target_write_u8(target
, FTFX_FSTAT
, 0x80);
1537 if (result
!= ERROR_OK
)
1542 result
= target_read_u8(target
, FTFX_FSTAT
, &fstat
);
1544 if (result
!= ERROR_OK
)
1550 } while (timeval_ms() < ms_timeout
);
1553 *ftfx_fstat
= fstat
;
1555 if ((fstat
& 0xf0) != 0x80) {
1556 LOG_DEBUG("ftfx command failed FSTAT: %02X FCCOB: %02X%02X%02X%02X %02X%02X%02X%02X %02X%02X%02X%02X",
1557 fstat
, command
[3], command
[2], command
[1], command
[0],
1558 command
[7], command
[6], command
[5], command
[4],
1559 command
[11], command
[10], command
[9], command
[8]);
1561 return kinetis_ftfx_decode_error(fstat
);
1568 static int kinetis_read_pmstat(struct kinetis_chip
*k_chip
, uint8_t *pmstat
)
1572 struct target
*target
= k_chip
->target
;
1574 switch (k_chip
->sysmodectrlr_type
) {
1576 result
= target_read_u8(target
, SMC_PMSTAT
, pmstat
);
1580 result
= target_read_u32(target
, SMC32_PMSTAT
, &stat32
);
1581 if (result
== ERROR_OK
)
1582 *pmstat
= stat32
& 0xff;
1586 /* emulate SMC by reading PMC_REGSC bit 3 (VLPRS) */
1587 result
= target_read_u8(target
, PMC_REGSC
, pmstat
);
1588 if (result
== ERROR_OK
) {
1590 *pmstat
= PM_STAT_VLPR
;
1592 *pmstat
= PM_STAT_RUN
;
1599 static int kinetis_check_run_mode(struct kinetis_chip
*k_chip
)
1603 struct target
*target
;
1606 LOG_ERROR("Chip not probed.");
1609 target
= k_chip
->target
;
1611 if (target
->state
!= TARGET_HALTED
) {
1612 LOG_ERROR("Target not halted");
1613 return ERROR_TARGET_NOT_HALTED
;
1616 result
= kinetis_read_pmstat(k_chip
, &pmstat
);
1617 if (result
!= ERROR_OK
)
1620 if (pmstat
== PM_STAT_RUN
)
1623 if (pmstat
== PM_STAT_VLPR
) {
1624 /* It is safe to switch from VLPR to RUN mode without changing clock */
1625 LOG_INFO("Switching from VLPR to RUN mode.");
1627 switch (k_chip
->sysmodectrlr_type
) {
1629 result
= target_write_u8(target
, SMC_PMCTRL
, PM_CTRL_RUNM_RUN
);
1633 result
= target_write_u32(target
, SMC32_PMCTRL
, PM_CTRL_RUNM_RUN
);
1637 result
= target_write_u32(target
, MC_PMCTRL
, PM_CTRL_RUNM_RUN
);
1640 if (result
!= ERROR_OK
)
1643 for (unsigned int i
= 100; i
> 0; i
--) {
1644 result
= kinetis_read_pmstat(k_chip
, &pmstat
);
1645 if (result
!= ERROR_OK
)
1648 if (pmstat
== PM_STAT_RUN
)
1653 LOG_ERROR("Flash operation not possible in current run mode: SMC_PMSTAT: 0x%x", pmstat
);
1654 LOG_ERROR("Issue a 'reset init' command.");
1655 return ERROR_TARGET_NOT_HALTED
;
1659 static void kinetis_invalidate_flash_cache(struct kinetis_chip
*k_chip
)
1661 struct target
*target
= k_chip
->target
;
1663 switch (k_chip
->cache_type
) {
1664 case KINETIS_CACHE_K
:
1665 target_write_u8(target
, FMC_PFB01CR
+ 2, 0xf0);
1666 /* Set CINV_WAY bits - request invalidate of all cache ways */
1667 /* FMC_PFB0CR has same address and CINV_WAY bits as FMC_PFB01CR */
1670 case KINETIS_CACHE_L
:
1671 target_write_u8(target
, MCM_PLACR
+ 1, 0x04);
1672 /* set bit CFCC - Clear Flash Controller Cache */
1675 case KINETIS_CACHE_MSCM
:
1676 target_write_u32(target
, MSCM_OCMDR0
, 0x30);
1677 /* disable data prefetch and flash speculate */
1680 case KINETIS_CACHE_MSCM2
:
1681 target_write_u32(target
, MSCM_OCMDR0
, 0x30);
1682 target_write_u32(target
, MSCM_OCMDR1
, 0x30);
1683 /* disable data prefetch and flash speculate */
1692 static int kinetis_erase(struct flash_bank
*bank
, unsigned int first
,
1696 struct kinetis_flash_bank
*k_bank
= bank
->driver_priv
;
1697 struct kinetis_chip
*k_chip
= k_bank
->k_chip
;
1699 result
= kinetis_check_run_mode(k_chip
);
1700 if (result
!= ERROR_OK
)
1703 /* reset error flags */
1704 result
= kinetis_ftfx_prepare(bank
->target
);
1705 if (result
!= ERROR_OK
)
1708 if ((first
> bank
->num_sectors
) || (last
> bank
->num_sectors
))
1709 return ERROR_FLASH_OPERATION_FAILED
;
1712 * FIXME: TODO: use the 'Erase Flash Block' command if the
1713 * requested erase is PFlash or NVM and encompasses the entire
1714 * block. Should be quicker.
1716 for (unsigned int i
= first
; i
<= last
; i
++) {
1717 /* set command and sector address */
1718 result
= kinetis_ftfx_command(bank
->target
, FTFX_CMD_SECTERASE
, k_bank
->prog_base
+ bank
->sectors
[i
].offset
,
1719 0, 0, 0, 0, 0, 0, 0, 0, NULL
);
1721 if (result
!= ERROR_OK
) {
1722 LOG_WARNING("erase sector %u failed", i
);
1723 return ERROR_FLASH_OPERATION_FAILED
;
1726 if (k_bank
->prog_base
== 0
1727 && bank
->sectors
[i
].offset
<= FCF_ADDRESS
1728 && bank
->sectors
[i
].offset
+ bank
->sectors
[i
].size
> FCF_ADDRESS
+ FCF_SIZE
) {
1729 if (allow_fcf_writes
) {
1730 LOG_WARNING("Flash Configuration Field erased, DO NOT reset or power off the device");
1731 LOG_WARNING("until correct FCF is programmed or MCU gets security lock.");
1733 uint8_t fcf_buffer
[FCF_SIZE
];
1735 kinetis_fill_fcf(bank
, fcf_buffer
);
1736 result
= kinetis_write_inner(bank
, fcf_buffer
, FCF_ADDRESS
, FCF_SIZE
);
1737 if (result
!= ERROR_OK
)
1738 LOG_WARNING("Flash Configuration Field write failed");
1740 LOG_DEBUG("Generated FCF written");
1745 kinetis_invalidate_flash_cache(k_bank
->k_chip
);
1750 static int kinetis_make_ram_ready(struct target
*target
)
1755 /* check if ram ready */
1756 result
= target_read_u8(target
, FTFX_FCNFG
, &ftfx_fcnfg
);
1757 if (result
!= ERROR_OK
)
1760 if (ftfx_fcnfg
& (1 << 1))
1761 return ERROR_OK
; /* ram ready */
1763 /* make flex ram available */
1764 result
= kinetis_ftfx_command(target
, FTFX_CMD_SETFLEXRAM
, 0x00ff0000,
1765 0, 0, 0, 0, 0, 0, 0, 0, NULL
);
1766 if (result
!= ERROR_OK
)
1767 return ERROR_FLASH_OPERATION_FAILED
;
1770 result
= target_read_u8(target
, FTFX_FCNFG
, &ftfx_fcnfg
);
1771 if (result
!= ERROR_OK
)
1774 if (ftfx_fcnfg
& (1 << 1))
1775 return ERROR_OK
; /* ram ready */
1777 return ERROR_FLASH_OPERATION_FAILED
;
1781 static int kinetis_write_sections(struct flash_bank
*bank
, const uint8_t *buffer
,
1782 uint32_t offset
, uint32_t count
)
1784 int result
= ERROR_OK
;
1785 struct kinetis_flash_bank
*k_bank
= bank
->driver_priv
;
1786 struct kinetis_chip
*k_chip
= k_bank
->k_chip
;
1787 uint8_t *buffer_aligned
= NULL
;
1789 * Kinetis uses different terms for the granularity of
1790 * sector writes, e.g. "phrase" or "128 bits". We use
1791 * the generic term "chunk". The largest possible
1792 * Kinetis "chunk" is 16 bytes (128 bits).
1794 uint32_t prog_section_chunk_bytes
= k_bank
->sector_size
>> 8;
1795 uint32_t prog_size_bytes
= k_chip
->max_flash_prog_size
;
1798 uint32_t size
= prog_size_bytes
- offset
% prog_size_bytes
;
1799 uint32_t align_begin
= offset
% prog_section_chunk_bytes
;
1801 uint32_t size_aligned
;
1802 uint16_t chunk_count
;
1808 align_end
= (align_begin
+ size
) % prog_section_chunk_bytes
;
1810 align_end
= prog_section_chunk_bytes
- align_end
;
1812 size_aligned
= align_begin
+ size
+ align_end
;
1813 chunk_count
= size_aligned
/ prog_section_chunk_bytes
;
1815 if (size
!= size_aligned
) {
1816 /* aligned section: the first, the last or the only */
1817 if (!buffer_aligned
)
1818 buffer_aligned
= malloc(prog_size_bytes
);
1820 memset(buffer_aligned
, 0xff, size_aligned
);
1821 memcpy(buffer_aligned
+ align_begin
, buffer
, size
);
1823 result
= target_write_memory(bank
->target
, k_chip
->progr_accel_ram
,
1824 4, size_aligned
/ 4, buffer_aligned
);
1826 LOG_DEBUG("section @ " TARGET_ADDR_FMT
" aligned begin %" PRIu32
1828 bank
->base
+ offset
, align_begin
, align_end
);
1830 result
= target_write_memory(bank
->target
, k_chip
->progr_accel_ram
,
1831 4, size_aligned
/ 4, buffer
);
1833 LOG_DEBUG("write section @ " TARGET_ADDR_FMT
" with length %" PRIu32
1835 bank
->base
+ offset
, size
);
1837 if (result
!= ERROR_OK
) {
1838 LOG_ERROR("target_write_memory failed");
1842 /* execute section-write command */
1843 result
= kinetis_ftfx_command(bank
->target
, FTFX_CMD_SECTWRITE
,
1844 k_bank
->prog_base
+ offset
- align_begin
,
1845 chunk_count
>>8, chunk_count
, 0, 0,
1846 0, 0, 0, 0, &ftfx_fstat
);
1848 if (result
!= ERROR_OK
) {
1849 LOG_ERROR("Error writing section at " TARGET_ADDR_FMT
,
1850 bank
->base
+ offset
);
1854 if (ftfx_fstat
& 0x01) {
1855 LOG_ERROR("Flash write error at " TARGET_ADDR_FMT
,
1856 bank
->base
+ offset
);
1857 if (k_bank
->prog_base
== 0 && offset
== FCF_ADDRESS
+ FCF_SIZE
1858 && (k_chip
->flash_support
& FS_WIDTH_256BIT
)) {
1859 LOG_ERROR("Flash write immediately after the end of Flash Config Field shows error");
1860 LOG_ERROR("because the flash memory is 256 bits wide (data were written correctly).");
1861 LOG_ERROR("Either change the linker script to add a gap of 16 bytes after FCF");
1862 LOG_ERROR("or set 'kinetis fcf_source write'");
1873 free(buffer_aligned
);
1878 static int kinetis_write_inner(struct flash_bank
*bank
, const uint8_t *buffer
,
1879 uint32_t offset
, uint32_t count
)
1882 bool fallback
= false;
1883 struct kinetis_flash_bank
*k_bank
= bank
->driver_priv
;
1884 struct kinetis_chip
*k_chip
= k_bank
->k_chip
;
1886 if (!(k_chip
->flash_support
& FS_PROGRAM_SECTOR
)) {
1887 /* fallback to longword write */
1889 LOG_INFO("This device supports Program Longword execution only.");
1891 result
= kinetis_make_ram_ready(bank
->target
);
1892 if (result
!= ERROR_OK
) {
1894 LOG_WARNING("FlexRAM not ready, fallback to slow longword write.");
1898 LOG_DEBUG("flash write @ " TARGET_ADDR_FMT
, bank
->base
+ offset
);
1901 /* program section command */
1902 kinetis_write_sections(bank
, buffer
, offset
, count
);
1903 } else if (k_chip
->flash_support
& FS_PROGRAM_LONGWORD
) {
1904 /* program longword command, not supported in FTFE */
1905 uint8_t *new_buffer
= NULL
;
1907 /* check word alignment */
1909 LOG_ERROR("offset 0x%" PRIx32
" breaks the required alignment", offset
);
1910 return ERROR_FLASH_DST_BREAKS_ALIGNMENT
;
1914 uint32_t old_count
= count
;
1915 count
= (old_count
| 3) + 1;
1916 new_buffer
= malloc(count
);
1918 LOG_ERROR("odd number of bytes to write and no memory "
1919 "for padding buffer");
1922 LOG_INFO("odd number of bytes to write (%" PRIu32
"), extending to %" PRIu32
" "
1923 "and padding with 0xff", old_count
, count
);
1924 memset(new_buffer
+ old_count
, 0xff, count
- old_count
);
1925 buffer
= memcpy(new_buffer
, buffer
, old_count
);
1928 uint32_t words_remaining
= count
/ 4;
1930 kinetis_disable_wdog(k_chip
);
1932 /* try using a block write */
1933 result
= kinetis_write_block(bank
, buffer
, offset
, words_remaining
);
1935 if (result
== ERROR_TARGET_RESOURCE_NOT_AVAILABLE
) {
1936 /* if block write failed (no sufficient working area),
1937 * we use normal (slow) single word accesses */
1938 LOG_WARNING("couldn't use block writes, falling back to single "
1941 while (words_remaining
) {
1944 LOG_DEBUG("write longword @ %08" PRIx32
, (uint32_t)(bank
->base
+ offset
));
1946 result
= kinetis_ftfx_command(bank
->target
, FTFX_CMD_LWORDPROG
, k_bank
->prog_base
+ offset
,
1947 buffer
[3], buffer
[2], buffer
[1], buffer
[0],
1948 0, 0, 0, 0, &ftfx_fstat
);
1950 if (result
!= ERROR_OK
) {
1951 LOG_ERROR("Error writing longword at " TARGET_ADDR_FMT
,
1952 bank
->base
+ offset
);
1956 if (ftfx_fstat
& 0x01)
1957 LOG_ERROR("Flash write error at " TARGET_ADDR_FMT
,
1958 bank
->base
+ offset
);
1969 LOG_ERROR("Flash write strategy not implemented");
1970 return ERROR_FLASH_OPERATION_FAILED
;
1973 kinetis_invalidate_flash_cache(k_chip
);
1978 static int kinetis_write(struct flash_bank
*bank
, const uint8_t *buffer
,
1979 uint32_t offset
, uint32_t count
)
1982 bool set_fcf
= false;
1983 bool fcf_in_data_valid
= false;
1984 bool fcf_differs
= false;
1986 struct kinetis_flash_bank
*k_bank
= bank
->driver_priv
;
1987 struct kinetis_chip
*k_chip
= k_bank
->k_chip
;
1988 uint8_t fcf_buffer
[FCF_SIZE
];
1989 uint8_t fcf_current
[FCF_SIZE
];
1990 uint8_t fcf_in_data
[FCF_SIZE
];
1992 result
= kinetis_check_run_mode(k_chip
);
1993 if (result
!= ERROR_OK
)
1996 /* reset error flags */
1997 result
= kinetis_ftfx_prepare(bank
->target
);
1998 if (result
!= ERROR_OK
)
2001 if (k_bank
->prog_base
== 0 && !allow_fcf_writes
) {
2002 if (bank
->sectors
[1].offset
<= FCF_ADDRESS
)
2003 sect
= 1; /* 1kb sector, FCF in 2nd sector */
2005 if (offset
< bank
->sectors
[sect
].offset
+ bank
->sectors
[sect
].size
2006 && offset
+ count
> bank
->sectors
[sect
].offset
)
2007 set_fcf
= true; /* write to any part of sector with FCF */
2011 kinetis_fill_fcf(bank
, fcf_buffer
);
2013 fcf_in_data_valid
= offset
<= FCF_ADDRESS
2014 && offset
+ count
>= FCF_ADDRESS
+ FCF_SIZE
;
2015 if (fcf_in_data_valid
) {
2016 memcpy(fcf_in_data
, buffer
+ FCF_ADDRESS
- offset
, FCF_SIZE
);
2017 if (memcmp(fcf_in_data
, fcf_buffer
, 8)) {
2019 LOG_INFO("Setting of backdoor key is not supported in mode 'kinetis fcf_source protection'.");
2021 if (memcmp(fcf_in_data
+ FCF_FPROT
, fcf_buffer
+ FCF_FPROT
, 4)) {
2023 LOG_INFO("Flash protection requested in the programmed file differs from current setting.");
2025 if (fcf_in_data
[FCF_FDPROT
] != fcf_buffer
[FCF_FDPROT
]) {
2027 LOG_INFO("Data flash protection requested in the programmed file differs from current setting.");
2029 if ((fcf_in_data
[FCF_FSEC
] & 3) != 2) {
2030 fcf_in_data_valid
= false;
2031 LOG_INFO("Device security requested in the programmed file! Write denied.");
2032 } else if (fcf_in_data
[FCF_FSEC
] != fcf_buffer
[FCF_FSEC
]) {
2034 LOG_INFO("Strange unsecure mode 0x%02" PRIx8
2035 " requested in the programmed file, set FSEC = 0x%02" PRIx8
2036 " in the startup code!",
2037 fcf_in_data
[FCF_FSEC
], fcf_buffer
[FCF_FSEC
]);
2039 if (fcf_in_data
[FCF_FOPT
] != fcf_buffer
[FCF_FOPT
]) {
2041 LOG_INFO("FOPT requested in the programmed file differs from current setting, set 'kinetis fopt 0x%02"
2042 PRIx8
"'.", fcf_in_data
[FCF_FOPT
]);
2045 /* If the device has ECC flash, then we cannot re-program FCF */
2047 if (k_chip
->flash_support
& FS_ECC
) {
2048 fcf_in_data_valid
= false;
2049 LOG_INFO("Cannot re-program FCF. Expect verify errors at FCF (0x400-0x40f).");
2051 LOG_INFO("Trying to re-program FCF.");
2052 if (!(k_chip
->flash_support
& FS_PROGRAM_LONGWORD
))
2053 LOG_INFO("Flash re-programming may fail on this device!");
2059 if (set_fcf
&& !fcf_in_data_valid
) {
2060 if (offset
< FCF_ADDRESS
) {
2061 /* write part preceding FCF */
2062 result
= kinetis_write_inner(bank
, buffer
, offset
, FCF_ADDRESS
- offset
);
2063 if (result
!= ERROR_OK
)
2067 result
= target_read_memory(bank
->target
, bank
->base
+ FCF_ADDRESS
, 4, FCF_SIZE
/ 4, fcf_current
);
2068 if (result
== ERROR_OK
&& memcmp(fcf_current
, fcf_buffer
, FCF_SIZE
) == 0)
2072 /* write FCF if differs from flash - eliminate multiple writes */
2073 result
= kinetis_write_inner(bank
, fcf_buffer
, FCF_ADDRESS
, FCF_SIZE
);
2074 if (result
!= ERROR_OK
)
2078 LOG_WARNING("Flash Configuration Field written.");
2079 LOG_WARNING("Reset or power off the device to make settings effective.");
2081 if (offset
+ count
> FCF_ADDRESS
+ FCF_SIZE
) {
2082 uint32_t delta
= FCF_ADDRESS
+ FCF_SIZE
- offset
;
2083 /* write part after FCF */
2084 result
= kinetis_write_inner(bank
, buffer
+ delta
, FCF_ADDRESS
+ FCF_SIZE
, count
- delta
);
2089 /* no FCF fiddling, normal write */
2090 return kinetis_write_inner(bank
, buffer
, offset
, count
);
2095 static int kinetis_probe_chip_s32k(struct kinetis_chip
*k_chip
)
2098 uint8_t fcfg1_eesize
, fcfg1_depart
;
2099 uint32_t ee_size
= 0;
2100 uint32_t pflash_size_k
, nvm_size_k
, dflash_size_k
;
2101 unsigned int generation
= 0, subseries
= 0, derivate
= 0;
2103 struct target
*target
= k_chip
->target
;
2104 k_chip
->probed
= false;
2105 k_chip
->pflash_sector_size
= 0;
2106 k_chip
->pflash_base
= 0;
2107 k_chip
->nvm_base
= 0x10000000;
2108 k_chip
->progr_accel_ram
= FLEXRAM
;
2109 k_chip
->flash_support
= FS_PROGRAM_PHRASE
| FS_PROGRAM_SECTOR
;
2110 k_chip
->watchdog_type
= KINETIS_WDOG32_KE1X
;
2112 if (k_chip
->sim_base
== 0)
2113 k_chip
->sim_base
= SIM_BASE
;
2115 result
= target_read_u32(target
, k_chip
->sim_base
+ SIM_SDID_OFFSET
, &k_chip
->sim_sdid
);
2116 if (result
!= ERROR_OK
)
2119 generation
= (k_chip
->sim_sdid
) >> 28 & 0x0f;
2120 subseries
= (k_chip
->sim_sdid
) >> 24 & 0x0f;
2121 derivate
= (k_chip
->sim_sdid
) >> 20 & 0x0f;
2123 switch (k_chip
->sim_sdid
& KINETIS_SDID_S32K_SERIES_MASK
) {
2124 case KINETIS_SDID_S32K_SERIES_K11X
:
2125 k_chip
->cache_type
= KINETIS_CACHE_L
;
2126 k_chip
->num_pflash_blocks
= 1;
2127 k_chip
->num_nvm_blocks
= 1;
2128 /* Non-interleaved */
2129 k_chip
->max_flash_prog_size
= 512;
2131 switch (k_chip
->sim_sdid
& KINETIS_SDID_S32K_DERIVATE_MASK
) {
2132 case KINETIS_SDID_S32K_DERIVATE_KXX6
:
2133 /* S32K116 CPU 48Mhz Flash 128KB RAM 17KB+2KB */
2134 /* Non-Interleaved */
2135 k_chip
->pflash_size
= 128 << 10;
2136 k_chip
->pflash_sector_size
= 2 << 10;
2137 /* Non-Interleaved */
2138 k_chip
->nvm_size
= 32 << 10;
2139 k_chip
->nvm_sector_size
= 2 << 10;
2141 case KINETIS_SDID_S32K_DERIVATE_KXX8
:
2142 /* S32K118 CPU 80Mhz Flash 256KB+32KB RAM 32KB+4KB */
2143 /* Non-Interleaved */
2144 k_chip
->pflash_size
= 256 << 10;
2145 k_chip
->pflash_sector_size
= 2 << 10;
2146 /* Non-Interleaved */
2147 k_chip
->nvm_size
= 32 << 10;
2148 k_chip
->nvm_sector_size
= 2 << 10;
2153 case KINETIS_SDID_S32K_SERIES_K14X
:
2154 k_chip
->cache_type
= KINETIS_CACHE_MSCM2
;
2155 k_chip
->num_pflash_blocks
= 1;
2156 k_chip
->num_nvm_blocks
= 1;
2157 /* Non-interleaved */
2158 k_chip
->max_flash_prog_size
= 512;
2159 switch (k_chip
->sim_sdid
& KINETIS_SDID_S32K_DERIVATE_MASK
) {
2160 case KINETIS_SDID_S32K_DERIVATE_KXX2
:
2161 case KINETIS_SDID_S32K_DERIVATE_KXX3
:
2162 /* S32K142/S32K142W CPU 80Mhz Flash 256KB+64KB RAM 32KB+4KB */
2163 /* Non-Interleaved */
2164 k_chip
->pflash_size
= 256 << 10;
2165 k_chip
->pflash_sector_size
= 2 << 10;
2166 /* Non-Interleaved */
2167 k_chip
->nvm_size
= 64 << 10;
2168 k_chip
->nvm_sector_size
= 2 << 10;
2170 case KINETIS_SDID_S32K_DERIVATE_KXX4
:
2171 case KINETIS_SDID_S32K_DERIVATE_KXX5
:
2172 /* S32K144/S32K144W CPU 80Mhz Flash 512KB+64KB RAM 64KB+4KB */
2174 k_chip
->pflash_size
= 512 << 10;
2175 k_chip
->pflash_sector_size
= 4 << 10;
2176 /* Non-Interleaved */
2177 k_chip
->nvm_size
= 64 << 10;
2178 k_chip
->nvm_sector_size
= 2 << 10;
2180 case KINETIS_SDID_S32K_DERIVATE_KXX6
:
2181 /* S32K146 CPU 80Mhz Flash 1024KB+64KB RAM 128KB+4KB */
2183 k_chip
->pflash_size
= 1024 << 10;
2184 k_chip
->pflash_sector_size
= 4 << 10;
2185 k_chip
->num_pflash_blocks
= 2;
2186 /* Non-Interleaved */
2187 k_chip
->nvm_size
= 64 << 10;
2188 k_chip
->nvm_sector_size
= 2 << 10;
2190 case KINETIS_SDID_S32K_DERIVATE_KXX8
:
2191 /* S32K148 CPU 80Mhz Flash 1536KB+512KB RAM 256KB+4KB */
2193 k_chip
->pflash_size
= 1536 << 10;
2194 k_chip
->pflash_sector_size
= 4 << 10;
2195 k_chip
->num_pflash_blocks
= 3;
2197 k_chip
->nvm_size
= 512 << 10;
2198 k_chip
->nvm_sector_size
= 4 << 10;
2200 k_chip
->max_flash_prog_size
= 1 << 10;
2206 LOG_ERROR("Unsupported S32K1xx-series");
2209 if (k_chip
->pflash_sector_size
== 0) {
2210 LOG_ERROR("MCU is unsupported, SDID 0x%08" PRIx32
, k_chip
->sim_sdid
);
2211 return ERROR_FLASH_OPER_UNSUPPORTED
;
2214 result
= target_read_u32(target
, k_chip
->sim_base
+ SIM_FCFG1_OFFSET
, &k_chip
->sim_fcfg1
);
2215 if (result
!= ERROR_OK
)
2217 k_chip
->sim_fcfg2
= 0; /* S32K1xx does not implement FCFG2 register. */
2219 fcfg1_depart
= (k_chip
->sim_fcfg1
>> 12) & 0x0f;
2220 fcfg1_eesize
= (k_chip
->sim_fcfg1
>> 16) & 0x0f;
2221 if (fcfg1_eesize
<= 9)
2222 ee_size
= (16 << (10 - fcfg1_eesize
));
2223 if ((fcfg1_depart
& 0x8) == 0) {
2224 /* Binary 0xxx values encode the amount reserved for EEPROM emulation. */
2226 k_chip
->dflash_size
= k_chip
->nvm_size
- (4096 << fcfg1_depart
);
2228 k_chip
->dflash_size
= k_chip
->nvm_size
;
2230 /* Binary 1xxx valued encode the DFlash size. */
2231 if (fcfg1_depart
& 0x7)
2232 k_chip
->dflash_size
= 4096 << (fcfg1_depart
& 0x7);
2234 k_chip
->dflash_size
= 0;
2237 snprintf(k_chip
->name
, sizeof(k_chip
->name
), "S32K%u%u%u",
2238 generation
, subseries
, derivate
);
2240 pflash_size_k
= k_chip
->pflash_size
/ 1024;
2241 dflash_size_k
= k_chip
->dflash_size
/ 1024;
2243 LOG_INFO("%s detected: %u flash blocks", k_chip
->name
, k_chip
->num_pflash_blocks
+ k_chip
->num_nvm_blocks
);
2244 LOG_INFO("%u PFlash banks: %" PRIu32
" KiB total", k_chip
->num_pflash_blocks
, pflash_size_k
);
2246 nvm_size_k
= k_chip
->nvm_size
/ 1024;
2248 if (k_chip
->num_nvm_blocks
) {
2249 LOG_INFO("%u FlexNVM banks: %" PRIu32
" KiB total, %" PRIu32
" KiB available as data flash, %"
2250 PRIu32
" bytes FlexRAM",
2251 k_chip
->num_nvm_blocks
, nvm_size_k
, dflash_size_k
, ee_size
);
2254 k_chip
->probed
= true;
2257 kinetis_create_missing_banks(k_chip
);
2263 static int kinetis_probe_chip(struct kinetis_chip
*k_chip
)
2266 uint8_t fcfg1_nvmsize
, fcfg1_pfsize
, fcfg1_eesize
, fcfg1_depart
;
2267 uint8_t fcfg2_pflsh
;
2268 uint32_t ee_size
= 0;
2269 uint32_t pflash_size_k
, nvm_size_k
, dflash_size_k
;
2270 uint32_t pflash_size_m
;
2271 unsigned num_blocks
= 0;
2272 unsigned maxaddr_shift
= 13;
2273 struct target
*target
= k_chip
->target
;
2275 unsigned familyid
= 0, subfamid
= 0;
2276 unsigned cpu_mhz
= 120;
2277 bool use_nvm_marking
= false;
2278 char flash_marking
[12], nvm_marking
[2];
2281 k_chip
->probed
= false;
2282 k_chip
->pflash_sector_size
= 0;
2283 k_chip
->pflash_base
= 0;
2284 k_chip
->nvm_base
= 0x10000000;
2285 k_chip
->progr_accel_ram
= FLEXRAM
;
2289 if (k_chip
->sim_base
)
2290 result
= target_read_u32(target
, k_chip
->sim_base
+ SIM_SDID_OFFSET
, &k_chip
->sim_sdid
);
2292 result
= target_read_u32(target
, SIM_BASE
+ SIM_SDID_OFFSET
, &k_chip
->sim_sdid
);
2293 if (result
== ERROR_OK
)
2294 k_chip
->sim_base
= SIM_BASE
;
2296 result
= target_read_u32(target
, SIM_BASE_KL28
+ SIM_SDID_OFFSET
, &k_chip
->sim_sdid
);
2297 if (result
== ERROR_OK
)
2298 k_chip
->sim_base
= SIM_BASE_KL28
;
2301 if (result
!= ERROR_OK
)
2304 if ((k_chip
->sim_sdid
& (~KINETIS_SDID_K_SERIES_MASK
)) == 0) {
2305 /* older K-series MCU */
2306 uint32_t mcu_type
= k_chip
->sim_sdid
& KINETIS_K_SDID_TYPE_MASK
;
2307 k_chip
->cache_type
= KINETIS_CACHE_K
;
2308 k_chip
->watchdog_type
= KINETIS_WDOG_K
;
2311 case KINETIS_K_SDID_K10_M50
:
2312 case KINETIS_K_SDID_K20_M50
:
2314 k_chip
->pflash_sector_size
= 1<<10;
2315 k_chip
->nvm_sector_size
= 1<<10;
2317 k_chip
->flash_support
= FS_PROGRAM_LONGWORD
| FS_PROGRAM_SECTOR
;
2319 case KINETIS_K_SDID_K10_M72
:
2320 case KINETIS_K_SDID_K20_M72
:
2321 case KINETIS_K_SDID_K30_M72
:
2322 case KINETIS_K_SDID_K30_M100
:
2323 case KINETIS_K_SDID_K40_M72
:
2324 case KINETIS_K_SDID_K40_M100
:
2325 case KINETIS_K_SDID_K50_M72
:
2326 /* 2kB sectors, 1kB FlexNVM sectors */
2327 k_chip
->pflash_sector_size
= 2<<10;
2328 k_chip
->nvm_sector_size
= 1<<10;
2330 k_chip
->flash_support
= FS_PROGRAM_LONGWORD
| FS_PROGRAM_SECTOR
;
2331 k_chip
->max_flash_prog_size
= 1<<10;
2333 case KINETIS_K_SDID_K10_M100
:
2334 case KINETIS_K_SDID_K20_M100
:
2335 case KINETIS_K_SDID_K11
:
2336 case KINETIS_K_SDID_K12
:
2337 case KINETIS_K_SDID_K21_M50
:
2338 case KINETIS_K_SDID_K22_M50
:
2339 case KINETIS_K_SDID_K51_M72
:
2340 case KINETIS_K_SDID_K53
:
2341 case KINETIS_K_SDID_K60_M100
:
2343 k_chip
->pflash_sector_size
= 2<<10;
2344 k_chip
->nvm_sector_size
= 2<<10;
2346 k_chip
->flash_support
= FS_PROGRAM_LONGWORD
| FS_PROGRAM_SECTOR
;
2348 case KINETIS_K_SDID_K21_M120
:
2349 case KINETIS_K_SDID_K22_M120
:
2350 /* 4kB sectors (MK21FN1M0, MK21FX512, MK22FN1M0, MK22FX512) */
2351 k_chip
->pflash_sector_size
= 4<<10;
2352 k_chip
->max_flash_prog_size
= 1<<10;
2353 k_chip
->nvm_sector_size
= 4<<10;
2355 k_chip
->flash_support
= FS_PROGRAM_PHRASE
| FS_PROGRAM_SECTOR
;
2357 case KINETIS_K_SDID_K10_M120
:
2358 case KINETIS_K_SDID_K20_M120
:
2359 case KINETIS_K_SDID_K60_M150
:
2360 case KINETIS_K_SDID_K70_M150
:
2362 k_chip
->pflash_sector_size
= 4<<10;
2363 k_chip
->nvm_sector_size
= 4<<10;
2365 k_chip
->flash_support
= FS_PROGRAM_PHRASE
| FS_PROGRAM_SECTOR
;
2368 LOG_ERROR("Unsupported K-family FAMID");
2371 for (size_t idx
= 0; idx
< ARRAY_SIZE(kinetis_types_old
); idx
++) {
2372 if (kinetis_types_old
[idx
].sdid
== mcu_type
) {
2373 strcpy(name
, kinetis_types_old
[idx
].name
);
2374 use_nvm_marking
= true;
2379 /* first revision of some devices has no SMC */
2381 case KINETIS_K_SDID_K10_M100
:
2382 case KINETIS_K_SDID_K20_M100
:
2383 case KINETIS_K_SDID_K30_M100
:
2384 case KINETIS_K_SDID_K40_M100
:
2385 case KINETIS_K_SDID_K60_M100
:
2387 uint32_t revid
= (k_chip
->sim_sdid
& KINETIS_K_REVID_MASK
) >> KINETIS_K_REVID_SHIFT
;
2388 /* highest bit set corresponds to rev 2.x */
2390 k_chip
->sysmodectrlr_type
= KINETIS_MC
;
2391 strcat(name
, " Rev 1.x");
2398 /* Newer K-series or KL series MCU */
2399 familyid
= (k_chip
->sim_sdid
& KINETIS_SDID_FAMILYID_MASK
) >> KINETIS_SDID_FAMILYID_SHIFT
;
2400 subfamid
= (k_chip
->sim_sdid
& KINETIS_SDID_SUBFAMID_MASK
) >> KINETIS_SDID_SUBFAMID_SHIFT
;
2402 switch (k_chip
->sim_sdid
& KINETIS_SDID_SERIESID_MASK
) {
2403 case KINETIS_SDID_SERIESID_K
:
2404 use_nvm_marking
= true;
2405 k_chip
->cache_type
= KINETIS_CACHE_K
;
2406 k_chip
->watchdog_type
= KINETIS_WDOG_K
;
2408 switch (k_chip
->sim_sdid
& (KINETIS_SDID_FAMILYID_MASK
| KINETIS_SDID_SUBFAMID_MASK
)) {
2409 case KINETIS_SDID_FAMILYID_K0X
| KINETIS_SDID_SUBFAMID_KX2
:
2410 /* K02FN64, K02FN128: FTFA, 2kB sectors */
2411 k_chip
->pflash_sector_size
= 2<<10;
2413 k_chip
->flash_support
= FS_PROGRAM_LONGWORD
;
2417 case KINETIS_SDID_FAMILYID_K2X
| KINETIS_SDID_SUBFAMID_KX2
: {
2418 /* MK24FN1M reports as K22, this should detect it (according to errata note 1N83J) */
2420 result
= target_read_u32(target
, k_chip
->sim_base
+ SIM_SOPT1_OFFSET
, &sopt1
);
2421 if (result
!= ERROR_OK
)
2424 if (((k_chip
->sim_sdid
& (KINETIS_SDID_DIEID_MASK
)) == KINETIS_SDID_DIEID_K24FN1M
) &&
2425 ((sopt1
& KINETIS_SOPT1_RAMSIZE_MASK
) == KINETIS_SOPT1_RAMSIZE_K24FN1M
)) {
2427 k_chip
->pflash_sector_size
= 4<<10;
2429 k_chip
->flash_support
= FS_PROGRAM_PHRASE
| FS_PROGRAM_SECTOR
;
2430 k_chip
->max_flash_prog_size
= 1<<10;
2431 subfamid
= 4; /* errata 1N83J fix */
2434 if ((k_chip
->sim_sdid
& (KINETIS_SDID_DIEID_MASK
)) == KINETIS_SDID_DIEID_K22FN128
2435 || (k_chip
->sim_sdid
& (KINETIS_SDID_DIEID_MASK
)) == KINETIS_SDID_DIEID_K22FN256
2436 || (k_chip
->sim_sdid
& (KINETIS_SDID_DIEID_MASK
)) == KINETIS_SDID_DIEID_K22FN512
) {
2437 /* K22 with new-style SDID - smaller pflash with FTFA, 2kB sectors */
2438 k_chip
->pflash_sector_size
= 2<<10;
2439 /* autodetect 1 or 2 blocks */
2440 k_chip
->flash_support
= FS_PROGRAM_LONGWORD
;
2443 LOG_ERROR("Unsupported Kinetis K22 DIEID");
2446 case KINETIS_SDID_FAMILYID_K2X
| KINETIS_SDID_SUBFAMID_KX4
:
2447 k_chip
->pflash_sector_size
= 4<<10;
2448 if ((k_chip
->sim_sdid
& (KINETIS_SDID_DIEID_MASK
)) == KINETIS_SDID_DIEID_K24FN256
) {
2449 /* K24FN256 - smaller pflash with FTFA */
2451 k_chip
->flash_support
= FS_PROGRAM_LONGWORD
;
2454 /* K24FN1M without errata 7534 */
2456 k_chip
->flash_support
= FS_PROGRAM_PHRASE
| FS_PROGRAM_SECTOR
;
2457 k_chip
->max_flash_prog_size
= 1<<10;
2460 case KINETIS_SDID_FAMILYID_K6X
| KINETIS_SDID_SUBFAMID_KX1
: /* errata 7534 - should be K63 */
2461 case KINETIS_SDID_FAMILYID_K6X
| KINETIS_SDID_SUBFAMID_KX2
: /* errata 7534 - should be K64 */
2462 subfamid
+= 2; /* errata 7534 fix */
2464 case KINETIS_SDID_FAMILYID_K6X
| KINETIS_SDID_SUBFAMID_KX3
:
2466 case KINETIS_SDID_FAMILYID_K6X
| KINETIS_SDID_SUBFAMID_KX4
:
2467 /* K64FN1M0, K64FX512 */
2468 k_chip
->pflash_sector_size
= 4<<10;
2469 k_chip
->nvm_sector_size
= 4<<10;
2470 k_chip
->max_flash_prog_size
= 1<<10;
2472 k_chip
->flash_support
= FS_PROGRAM_PHRASE
| FS_PROGRAM_SECTOR
;
2475 case KINETIS_SDID_FAMILYID_K2X
| KINETIS_SDID_SUBFAMID_KX6
:
2477 case KINETIS_SDID_FAMILYID_K6X
| KINETIS_SDID_SUBFAMID_KX6
:
2478 /* K66FN2M0, K66FX1M0 */
2479 k_chip
->pflash_sector_size
= 4<<10;
2480 k_chip
->nvm_sector_size
= 4<<10;
2481 k_chip
->max_flash_prog_size
= 1<<10;
2483 k_chip
->flash_support
= FS_PROGRAM_PHRASE
| FS_PROGRAM_SECTOR
| FS_ECC
;
2487 case KINETIS_SDID_FAMILYID_K2X
| KINETIS_SDID_SUBFAMID_KX7
:
2489 case KINETIS_SDID_FAMILYID_K2X
| KINETIS_SDID_SUBFAMID_KX8
:
2491 k_chip
->pflash_sector_size
= 4<<10;
2492 k_chip
->max_flash_prog_size
= 1<<10;
2494 k_chip
->flash_support
= FS_PROGRAM_PHRASE
| FS_PROGRAM_SECTOR
| FS_ECC
;
2498 case KINETIS_SDID_FAMILYID_K8X
| KINETIS_SDID_SUBFAMID_KX0
:
2499 case KINETIS_SDID_FAMILYID_K8X
| KINETIS_SDID_SUBFAMID_KX1
:
2500 case KINETIS_SDID_FAMILYID_K8X
| KINETIS_SDID_SUBFAMID_KX2
:
2501 /* K80FN256, K81FN256, K82FN256 */
2502 k_chip
->pflash_sector_size
= 4<<10;
2504 k_chip
->flash_support
= FS_PROGRAM_LONGWORD
| FS_NO_CMD_BLOCKSTAT
;
2508 case KINETIS_SDID_FAMILYID_KL8X
| KINETIS_SDID_SUBFAMID_KX1
:
2509 case KINETIS_SDID_FAMILYID_KL8X
| KINETIS_SDID_SUBFAMID_KX2
:
2510 /* KL81Z128, KL82Z128 */
2511 k_chip
->pflash_sector_size
= 2<<10;
2513 k_chip
->flash_support
= FS_PROGRAM_LONGWORD
| FS_NO_CMD_BLOCKSTAT
;
2514 k_chip
->cache_type
= KINETIS_CACHE_L
;
2516 use_nvm_marking
= false;
2517 snprintf(name
, sizeof(name
), "MKL8%uZ%%s7",
2522 LOG_ERROR("Unsupported Kinetis FAMILYID SUBFAMID");
2525 if (name
[0] == '\0')
2526 snprintf(name
, sizeof(name
), "MK%u%uF%%s%u",
2527 familyid
, subfamid
, cpu_mhz
/ 10);
2530 case KINETIS_SDID_SERIESID_KL
:
2532 k_chip
->pflash_sector_size
= 1<<10;
2533 k_chip
->nvm_sector_size
= 1<<10;
2534 /* autodetect 1 or 2 blocks */
2535 k_chip
->flash_support
= FS_PROGRAM_LONGWORD
;
2536 k_chip
->cache_type
= KINETIS_CACHE_L
;
2537 k_chip
->watchdog_type
= KINETIS_WDOG_COP
;
2540 switch (k_chip
->sim_sdid
& (KINETIS_SDID_FAMILYID_MASK
| KINETIS_SDID_SUBFAMID_MASK
)) {
2541 case KINETIS_SDID_FAMILYID_K1X
| KINETIS_SDID_SUBFAMID_KX3
:
2542 case KINETIS_SDID_FAMILYID_K2X
| KINETIS_SDID_SUBFAMID_KX3
:
2546 case KINETIS_SDID_FAMILYID_K2X
| KINETIS_SDID_SUBFAMID_KX8
:
2548 k_chip
->pflash_sector_size
= 2<<10;
2550 k_chip
->watchdog_type
= KINETIS_WDOG32_KL28
;
2551 k_chip
->sysmodectrlr_type
= KINETIS_SMC32
;
2555 snprintf(name
, sizeof(name
), "MKL%u%uZ%%s%u",
2556 familyid
, subfamid
, cpu_mhz
/ 10);
2559 case KINETIS_SDID_SERIESID_KW
:
2560 /* Newer KW-series (all KW series except KW2xD, KW01Z) */
2562 switch (k_chip
->sim_sdid
& (KINETIS_SDID_FAMILYID_MASK
| KINETIS_SDID_SUBFAMID_MASK
)) {
2563 case KINETIS_SDID_FAMILYID_K4X
| KINETIS_SDID_SUBFAMID_KX0
:
2565 case KINETIS_SDID_FAMILYID_K3X
| KINETIS_SDID_SUBFAMID_KX0
:
2567 case KINETIS_SDID_FAMILYID_K2X
| KINETIS_SDID_SUBFAMID_KX0
:
2569 /* FTFA, 1kB sectors */
2570 k_chip
->pflash_sector_size
= 1<<10;
2571 k_chip
->nvm_sector_size
= 1<<10;
2572 /* autodetect 1 or 2 blocks */
2573 k_chip
->flash_support
= FS_PROGRAM_LONGWORD
;
2574 k_chip
->cache_type
= KINETIS_CACHE_L
;
2575 k_chip
->watchdog_type
= KINETIS_WDOG_COP
;
2577 case KINETIS_SDID_FAMILYID_K4X
| KINETIS_SDID_SUBFAMID_KX1
:
2579 case KINETIS_SDID_FAMILYID_K3X
| KINETIS_SDID_SUBFAMID_KX1
:
2581 case KINETIS_SDID_FAMILYID_K2X
| KINETIS_SDID_SUBFAMID_KX1
:
2583 /* FTFA, 2kB sectors */
2584 k_chip
->pflash_sector_size
= 2<<10;
2585 k_chip
->nvm_sector_size
= 2<<10;
2586 /* autodetect 1 or 2 blocks */
2587 k_chip
->flash_support
= FS_PROGRAM_LONGWORD
;
2588 k_chip
->cache_type
= KINETIS_CACHE_L
;
2589 k_chip
->watchdog_type
= KINETIS_WDOG_COP
;
2592 LOG_ERROR("Unsupported KW FAMILYID SUBFAMID");
2594 snprintf(name
, sizeof(name
), "MKW%u%uZ%%s%u",
2595 familyid
, subfamid
, cpu_mhz
/ 10);
2598 case KINETIS_SDID_SERIESID_KV
:
2600 k_chip
->watchdog_type
= KINETIS_WDOG_K
;
2601 switch (k_chip
->sim_sdid
& (KINETIS_SDID_FAMILYID_MASK
| KINETIS_SDID_SUBFAMID_MASK
)) {
2602 case KINETIS_SDID_FAMILYID_K1X
| KINETIS_SDID_SUBFAMID_KX0
:
2603 /* KV10: FTFA, 1kB sectors */
2604 k_chip
->pflash_sector_size
= 1<<10;
2606 k_chip
->flash_support
= FS_PROGRAM_LONGWORD
;
2607 k_chip
->cache_type
= KINETIS_CACHE_L
;
2608 strcpy(name
, "MKV10Z%s7");
2611 case KINETIS_SDID_FAMILYID_K1X
| KINETIS_SDID_SUBFAMID_KX1
:
2612 /* KV11: FTFA, 2kB sectors */
2613 k_chip
->pflash_sector_size
= 2<<10;
2615 k_chip
->flash_support
= FS_PROGRAM_LONGWORD
;
2616 k_chip
->cache_type
= KINETIS_CACHE_L
;
2617 strcpy(name
, "MKV11Z%s7");
2620 case KINETIS_SDID_FAMILYID_K3X
| KINETIS_SDID_SUBFAMID_KX0
:
2621 /* KV30: FTFA, 2kB sectors, 1 block */
2622 case KINETIS_SDID_FAMILYID_K3X
| KINETIS_SDID_SUBFAMID_KX1
:
2623 /* KV31: FTFA, 2kB sectors, 2 blocks */
2624 k_chip
->pflash_sector_size
= 2<<10;
2625 /* autodetect 1 or 2 blocks */
2626 k_chip
->flash_support
= FS_PROGRAM_LONGWORD
;
2627 k_chip
->cache_type
= KINETIS_CACHE_K
;
2630 case KINETIS_SDID_FAMILYID_K4X
| KINETIS_SDID_SUBFAMID_KX2
:
2631 case KINETIS_SDID_FAMILYID_K4X
| KINETIS_SDID_SUBFAMID_KX4
:
2632 case KINETIS_SDID_FAMILYID_K4X
| KINETIS_SDID_SUBFAMID_KX6
:
2633 /* KV4x: FTFA, 4kB sectors */
2634 k_chip
->pflash_sector_size
= 4<<10;
2636 k_chip
->flash_support
= FS_PROGRAM_LONGWORD
;
2637 k_chip
->cache_type
= KINETIS_CACHE_K
;
2641 case KINETIS_SDID_FAMILYID_K5X
| KINETIS_SDID_SUBFAMID_KX6
:
2642 case KINETIS_SDID_FAMILYID_K5X
| KINETIS_SDID_SUBFAMID_KX8
:
2643 /* KV5x: FTFE, 8kB sectors */
2644 k_chip
->pflash_sector_size
= 8<<10;
2645 k_chip
->max_flash_prog_size
= 1<<10;
2648 k_chip
->flash_support
= FS_PROGRAM_PHRASE
| FS_PROGRAM_SECTOR
| FS_WIDTH_256BIT
| FS_ECC
;
2649 k_chip
->pflash_base
= 0x10000000;
2650 k_chip
->progr_accel_ram
= 0x18000000;
2655 LOG_ERROR("Unsupported KV FAMILYID SUBFAMID");
2658 if (name
[0] == '\0')
2659 snprintf(name
, sizeof(name
), "MKV%u%uF%%s%u",
2660 familyid
, subfamid
, cpu_mhz
/ 10);
2663 case KINETIS_SDID_SERIESID_KE
:
2665 k_chip
->watchdog_type
= KINETIS_WDOG32_KE1X
;
2666 switch (k_chip
->sim_sdid
&
2667 (KINETIS_SDID_FAMILYID_MASK
| KINETIS_SDID_SUBFAMID_MASK
| KINETIS_SDID_PROJECTID_MASK
)) {
2668 case KINETIS_SDID_FAMILYID_K1X
| KINETIS_SDID_SUBFAMID_KX4
| KINETIS_SDID_PROJECTID_KE1XZ
:
2669 case KINETIS_SDID_FAMILYID_K1X
| KINETIS_SDID_SUBFAMID_KX5
| KINETIS_SDID_PROJECTID_KE1XZ
:
2670 /* KE1xZ: FTFE, 2kB sectors */
2671 k_chip
->pflash_sector_size
= 2<<10;
2672 k_chip
->nvm_sector_size
= 2<<10;
2673 k_chip
->max_flash_prog_size
= 1<<9;
2675 k_chip
->flash_support
= FS_PROGRAM_PHRASE
| FS_PROGRAM_SECTOR
;
2676 k_chip
->cache_type
= KINETIS_CACHE_L
;
2679 snprintf(name
, sizeof(name
), "MKE%u%uZ%%s%u",
2680 familyid
, subfamid
, cpu_mhz
/ 10);
2683 case KINETIS_SDID_FAMILYID_K1X
| KINETIS_SDID_SUBFAMID_KX4
| KINETIS_SDID_PROJECTID_KE1XF
:
2684 case KINETIS_SDID_FAMILYID_K1X
| KINETIS_SDID_SUBFAMID_KX6
| KINETIS_SDID_PROJECTID_KE1XF
:
2685 case KINETIS_SDID_FAMILYID_K1X
| KINETIS_SDID_SUBFAMID_KX8
| KINETIS_SDID_PROJECTID_KE1XF
:
2686 /* KE1xF: FTFE, 4kB sectors */
2687 k_chip
->pflash_sector_size
= 4<<10;
2688 k_chip
->nvm_sector_size
= 2<<10;
2689 k_chip
->max_flash_prog_size
= 1<<10;
2691 k_chip
->flash_support
= FS_PROGRAM_PHRASE
| FS_PROGRAM_SECTOR
;
2692 k_chip
->cache_type
= KINETIS_CACHE_MSCM
;
2695 snprintf(name
, sizeof(name
), "MKE%u%uF%%s%u",
2696 familyid
, subfamid
, cpu_mhz
/ 10);
2700 LOG_ERROR("Unsupported KE FAMILYID SUBFAMID");
2705 LOG_ERROR("Unsupported K-series");
2709 if (k_chip
->pflash_sector_size
== 0) {
2710 LOG_ERROR("MCU is unsupported, SDID 0x%08" PRIx32
, k_chip
->sim_sdid
);
2711 return ERROR_FLASH_OPER_UNSUPPORTED
;
2714 result
= target_read_u32(target
, k_chip
->sim_base
+ SIM_FCFG1_OFFSET
, &k_chip
->sim_fcfg1
);
2715 if (result
!= ERROR_OK
)
2718 result
= target_read_u32(target
, k_chip
->sim_base
+ SIM_FCFG2_OFFSET
, &k_chip
->sim_fcfg2
);
2719 if (result
!= ERROR_OK
)
2722 LOG_DEBUG("SDID: 0x%08" PRIX32
" FCFG1: 0x%08" PRIX32
" FCFG2: 0x%08" PRIX32
, k_chip
->sim_sdid
,
2723 k_chip
->sim_fcfg1
, k_chip
->sim_fcfg2
);
2725 fcfg1_nvmsize
= (uint8_t)((k_chip
->sim_fcfg1
>> 28) & 0x0f);
2726 fcfg1_pfsize
= (uint8_t)((k_chip
->sim_fcfg1
>> 24) & 0x0f);
2727 fcfg1_eesize
= (uint8_t)((k_chip
->sim_fcfg1
>> 16) & 0x0f);
2728 fcfg1_depart
= (uint8_t)((k_chip
->sim_fcfg1
>> 8) & 0x0f);
2730 fcfg2_pflsh
= (uint8_t)((k_chip
->sim_fcfg2
>> 23) & 0x01);
2731 k_chip
->fcfg2_maxaddr0_shifted
= ((k_chip
->sim_fcfg2
>> 24) & 0x7f) << maxaddr_shift
;
2732 k_chip
->fcfg2_maxaddr1_shifted
= ((k_chip
->sim_fcfg2
>> 16) & 0x7f) << maxaddr_shift
;
2734 if (num_blocks
== 0)
2735 num_blocks
= k_chip
->fcfg2_maxaddr1_shifted
? 2 : 1;
2736 else if (k_chip
->fcfg2_maxaddr1_shifted
== 0 && num_blocks
>= 2 && fcfg2_pflsh
) {
2737 /* fcfg2_maxaddr1 may be zero due to partitioning whole NVM as EEPROM backup
2738 * Do not adjust block count in this case! */
2740 LOG_WARNING("MAXADDR1 is zero, number of flash banks adjusted to 1");
2741 } else if (k_chip
->fcfg2_maxaddr1_shifted
!= 0 && num_blocks
== 1) {
2743 LOG_WARNING("MAXADDR1 is non zero, number of flash banks adjusted to 2");
2746 /* when the PFLSH bit is set, there is no FlexNVM/FlexRAM */
2748 switch (fcfg1_nvmsize
) {
2754 k_chip
->nvm_size
= 1 << (14 + (fcfg1_nvmsize
>> 1));
2757 if (k_chip
->pflash_sector_size
>= 4<<10)
2758 k_chip
->nvm_size
= 512<<10;
2761 k_chip
->nvm_size
= 256<<10;
2764 k_chip
->nvm_size
= 0;
2768 switch (fcfg1_eesize
) {
2779 ee_size
= (16 << (10 - fcfg1_eesize
));
2786 switch (fcfg1_depart
) {
2793 k_chip
->dflash_size
= k_chip
->nvm_size
- (4096 << fcfg1_depart
);
2797 k_chip
->dflash_size
= 0;
2804 k_chip
->dflash_size
= 4096 << (fcfg1_depart
& 0x7);
2807 k_chip
->dflash_size
= k_chip
->nvm_size
;
2812 switch (fcfg1_pfsize
) {
2814 k_chip
->pflash_size
= 8192;
2823 k_chip
->pflash_size
= 1 << (14 + (fcfg1_pfsize
>> 1));
2826 /* a peculiar case: Freescale states different sizes for 0xf
2827 * KL03P24M48SF0RM 32 KB .... duplicate of code 0x3
2828 * K02P64M100SFARM 128 KB ... duplicate of code 0x7
2829 * K22P121M120SF8RM 256 KB ... duplicate of code 0x9
2830 * K22P121M120SF7RM 512 KB ... duplicate of code 0xb
2831 * K22P100M120SF5RM 1024 KB ... duplicate of code 0xd
2832 * K26P169M180SF5RM 2048 KB ... the only unique value
2833 * fcfg2_maxaddr0 seems to be the only clue to pflash_size
2834 * Checking fcfg2_maxaddr0 in bank probe is pointless then
2837 k_chip
->pflash_size
= k_chip
->fcfg2_maxaddr0_shifted
* num_blocks
;
2839 k_chip
->pflash_size
= k_chip
->fcfg2_maxaddr0_shifted
* num_blocks
/ 2;
2840 if (k_chip
->pflash_size
!= 2048<<10)
2841 LOG_WARNING("SIM_FCFG1 PFSIZE = 0xf: please check if pflash is %" PRIu32
" KB", k_chip
->pflash_size
>>10);
2845 k_chip
->pflash_size
= 0;
2849 if (k_chip
->flash_support
& FS_PROGRAM_SECTOR
&& k_chip
->max_flash_prog_size
== 0) {
2850 k_chip
->max_flash_prog_size
= k_chip
->pflash_sector_size
;
2851 /* Program section size is equal to sector size by default */
2855 k_chip
->num_pflash_blocks
= num_blocks
;
2856 k_chip
->num_nvm_blocks
= 0;
2858 k_chip
->num_pflash_blocks
= (num_blocks
+ 1) / 2;
2859 k_chip
->num_nvm_blocks
= num_blocks
- k_chip
->num_pflash_blocks
;
2862 if (use_nvm_marking
) {
2863 nvm_marking
[0] = k_chip
->num_nvm_blocks
? 'X' : 'N';
2864 nvm_marking
[1] = '\0';
2866 nvm_marking
[0] = '\0';
2868 pflash_size_k
= k_chip
->pflash_size
/ 1024;
2869 pflash_size_m
= pflash_size_k
/ 1024;
2871 snprintf(flash_marking
, sizeof(flash_marking
), "%s%" PRIu32
"M0xxx", nvm_marking
, pflash_size_m
);
2873 snprintf(flash_marking
, sizeof(flash_marking
), "%s%" PRIu32
"xxx", nvm_marking
, pflash_size_k
);
2875 snprintf(k_chip
->name
, sizeof(k_chip
->name
), name
, flash_marking
);
2876 LOG_INFO("Kinetis %s detected: %u flash blocks", k_chip
->name
, num_blocks
);
2877 LOG_INFO("%u PFlash banks: %" PRIu32
" KiB total", k_chip
->num_pflash_blocks
, pflash_size_k
);
2878 if (k_chip
->num_nvm_blocks
) {
2879 nvm_size_k
= k_chip
->nvm_size
/ 1024;
2880 dflash_size_k
= k_chip
->dflash_size
/ 1024;
2881 LOG_INFO("%u FlexNVM banks: %" PRIu32
" KiB total, %" PRIu32
" KiB available as data flash, %"
2882 PRIu32
" bytes FlexRAM", k_chip
->num_nvm_blocks
, nvm_size_k
, dflash_size_k
, ee_size
);
2885 k_chip
->probed
= true;
2888 kinetis_create_missing_banks(k_chip
);
2893 static int kinetis_probe(struct flash_bank
*bank
)
2896 uint8_t fcfg2_maxaddr0
, fcfg2_pflsh
, fcfg2_maxaddr1
;
2897 unsigned num_blocks
, first_nvm_bank
;
2899 struct kinetis_flash_bank
*k_bank
= bank
->driver_priv
;
2900 struct kinetis_chip
*k_chip
;
2903 k_chip
= k_bank
->k_chip
;
2905 k_bank
->probed
= false;
2907 if (!k_chip
->probed
) {
2908 switch (k_chip
->chip_type
) {
2910 result
= kinetis_probe_chip_s32k(k_chip
);
2913 result
= kinetis_probe_chip(k_chip
);
2915 if (result
!= ERROR_OK
)
2919 num_blocks
= k_chip
->num_pflash_blocks
+ k_chip
->num_nvm_blocks
;
2920 first_nvm_bank
= k_chip
->num_pflash_blocks
;
2922 if (k_bank
->bank_number
< k_chip
->num_pflash_blocks
) {
2923 /* pflash, banks start at address zero */
2924 k_bank
->flash_class
= FC_PFLASH
;
2925 bank
->size
= (k_chip
->pflash_size
/ k_chip
->num_pflash_blocks
);
2926 bank
->base
= k_chip
->pflash_base
+ bank
->size
* k_bank
->bank_number
;
2927 k_bank
->prog_base
= 0x00000000 + bank
->size
* k_bank
->bank_number
;
2928 k_bank
->sector_size
= k_chip
->pflash_sector_size
;
2929 /* pflash is divided into 32 protection areas for
2930 * parts with more than 32K of PFlash. For parts with
2931 * less the protection unit is set to 1024 bytes */
2932 k_bank
->protection_size
= MAX(k_chip
->pflash_size
/ 32, 1024);
2933 bank
->num_prot_blocks
= bank
->size
/ k_bank
->protection_size
;
2934 k_bank
->protection_block
= bank
->num_prot_blocks
* k_bank
->bank_number
;
2936 size_k
= bank
->size
/ 1024;
2937 LOG_DEBUG("Kinetis bank %u: %" PRIu32
"k PFlash, FTFx base 0x%08" PRIx32
", sect %" PRIu32
,
2938 k_bank
->bank_number
, size_k
, k_bank
->prog_base
, k_bank
->sector_size
);
2940 } else if (k_bank
->bank_number
< num_blocks
) {
2941 /* nvm, banks start at address 0x10000000 */
2942 unsigned nvm_ord
= k_bank
->bank_number
- first_nvm_bank
;
2945 k_bank
->flash_class
= FC_FLEX_NVM
;
2946 bank
->size
= k_chip
->nvm_size
/ k_chip
->num_nvm_blocks
;
2947 bank
->base
= k_chip
->nvm_base
+ bank
->size
* nvm_ord
;
2948 k_bank
->prog_base
= 0x00800000 + bank
->size
* nvm_ord
;
2949 k_bank
->sector_size
= k_chip
->nvm_sector_size
;
2950 if (k_chip
->dflash_size
== 0) {
2951 k_bank
->protection_size
= 0;
2954 for (i
= k_chip
->dflash_size
; ~i
& 1; i
>>= 1)
2957 k_bank
->protection_size
= k_chip
->dflash_size
/ 8; /* data flash size = 2^^n */
2959 k_bank
->protection_size
= k_chip
->nvm_size
/ 8; /* TODO: verify on SF1, not documented in RM */
2961 bank
->num_prot_blocks
= 8 / k_chip
->num_nvm_blocks
;
2962 k_bank
->protection_block
= bank
->num_prot_blocks
* nvm_ord
;
2964 /* EEPROM backup part of FlexNVM is not accessible, use dflash_size as a limit */
2965 if (k_chip
->dflash_size
> bank
->size
* nvm_ord
)
2966 limit
= k_chip
->dflash_size
- bank
->size
* nvm_ord
;
2970 if (bank
->size
> limit
) {
2972 LOG_DEBUG("FlexNVM bank %u limited to 0x%08" PRIx32
" due to active EEPROM backup",
2973 k_bank
->bank_number
, limit
);
2976 size_k
= bank
->size
/ 1024;
2977 LOG_DEBUG("Kinetis bank %u: %" PRIu32
"k FlexNVM, FTFx base 0x%08" PRIx32
", sect %" PRIu32
,
2978 k_bank
->bank_number
, size_k
, k_bank
->prog_base
, k_bank
->sector_size
);
2981 LOG_ERROR("Cannot determine parameters for bank %u, only %u banks on device",
2982 k_bank
->bank_number
, num_blocks
);
2983 return ERROR_FLASH_BANK_INVALID
;
2986 /* S32K1xx does not implement FCFG2 register. Skip checks. */
2987 if (k_chip
->chip_type
!= CT_S32K
) {
2988 fcfg2_pflsh
= (uint8_t)((k_chip
->sim_fcfg2
>> 23) & 0x01);
2989 fcfg2_maxaddr0
= (uint8_t)((k_chip
->sim_fcfg2
>> 24) & 0x7f);
2990 fcfg2_maxaddr1
= (uint8_t)((k_chip
->sim_fcfg2
>> 16) & 0x7f);
2992 if (k_bank
->bank_number
== 0 && k_chip
->fcfg2_maxaddr0_shifted
!= bank
->size
)
2993 LOG_WARNING("MAXADDR0 0x%02" PRIx8
" check failed,"
2994 " please report to OpenOCD mailing list", fcfg2_maxaddr0
);
2997 if (k_bank
->bank_number
== 1 && k_chip
->fcfg2_maxaddr1_shifted
!= bank
->size
)
2998 LOG_WARNING("MAXADDR1 0x%02" PRIx8
" check failed,"
2999 " please report to OpenOCD mailing list", fcfg2_maxaddr1
);
3001 if (k_bank
->bank_number
== first_nvm_bank
3002 && k_chip
->fcfg2_maxaddr1_shifted
!= k_chip
->dflash_size
)
3003 LOG_WARNING("FlexNVM MAXADDR1 0x%02" PRIx8
" check failed,"
3004 " please report to OpenOCD mailing list", fcfg2_maxaddr1
);
3008 free(bank
->sectors
);
3009 bank
->sectors
= NULL
;
3011 free(bank
->prot_blocks
);
3012 bank
->prot_blocks
= NULL
;
3014 if (k_bank
->sector_size
== 0) {
3015 LOG_ERROR("Unknown sector size for bank %u", bank
->bank_number
);
3016 return ERROR_FLASH_BANK_INVALID
;
3019 bank
->num_sectors
= bank
->size
/ k_bank
->sector_size
;
3021 if (bank
->num_sectors
> 0) {
3022 /* FlexNVM bank can be used for EEPROM backup therefore zero sized */
3023 bank
->sectors
= alloc_block_array(0, k_bank
->sector_size
, bank
->num_sectors
);
3027 bank
->prot_blocks
= alloc_block_array(0, k_bank
->protection_size
, bank
->num_prot_blocks
);
3028 if (!bank
->prot_blocks
)
3032 bank
->num_prot_blocks
= 0;
3035 k_bank
->probed
= true;
3040 static int kinetis_auto_probe(struct flash_bank
*bank
)
3042 struct kinetis_flash_bank
*k_bank
= bank
->driver_priv
;
3044 if (k_bank
&& k_bank
->probed
)
3047 return kinetis_probe(bank
);
3050 static int kinetis_info(struct flash_bank
*bank
, struct command_invocation
*cmd
)
3052 const char *bank_class_names
[] = {
3053 "(ANY)", "PFlash", "FlexNVM", "FlexRAM"
3056 struct kinetis_flash_bank
*k_bank
= bank
->driver_priv
;
3057 struct kinetis_chip
*k_chip
= k_bank
->k_chip
;
3058 uint32_t size_k
= bank
->size
/ 1024;
3060 command_print_sameline(cmd
,
3061 "%s %s: %" PRIu32
"k %s bank %s at " TARGET_ADDR_FMT
,
3062 bank
->driver
->name
, k_chip
->name
,
3063 size_k
, bank_class_names
[k_bank
->flash_class
],
3064 bank
->name
, bank
->base
);
3069 static int kinetis_blank_check(struct flash_bank
*bank
)
3071 struct kinetis_flash_bank
*k_bank
= bank
->driver_priv
;
3072 struct kinetis_chip
*k_chip
= k_bank
->k_chip
;
3075 /* surprisingly blank check does not work in VLPR and HSRUN modes */
3076 result
= kinetis_check_run_mode(k_chip
);
3077 if (result
!= ERROR_OK
)
3080 /* reset error flags */
3081 result
= kinetis_ftfx_prepare(bank
->target
);
3082 if (result
!= ERROR_OK
)
3085 if (k_bank
->flash_class
== FC_PFLASH
|| k_bank
->flash_class
== FC_FLEX_NVM
) {
3086 bool block_dirty
= true;
3087 bool use_block_cmd
= !(k_chip
->flash_support
& FS_NO_CMD_BLOCKSTAT
);
3090 if (use_block_cmd
&& k_bank
->flash_class
== FC_FLEX_NVM
) {
3091 uint8_t fcfg1_depart
= (uint8_t)((k_chip
->sim_fcfg1
>> 8) & 0x0f);
3092 /* block operation cannot be used on FlexNVM when EEPROM backup partition is set */
3093 if (fcfg1_depart
!= 0xf && fcfg1_depart
!= 0)
3094 use_block_cmd
= false;
3097 if (use_block_cmd
) {
3098 /* check if whole bank is blank */
3099 result
= kinetis_ftfx_command(bank
->target
, FTFX_CMD_BLOCKSTAT
, k_bank
->prog_base
,
3100 0, 0, 0, 0, 0, 0, 0, 0, &ftfx_fstat
);
3102 if (result
!= ERROR_OK
)
3103 kinetis_ftfx_clear_error(bank
->target
);
3104 else if ((ftfx_fstat
& 0x01) == 0)
3105 block_dirty
= false;
3109 /* the whole bank is not erased, check sector-by-sector */
3110 for (unsigned int i
= 0; i
< bank
->num_sectors
; i
++) {
3112 result
= kinetis_ftfx_command(bank
->target
, FTFX_CMD_SECTSTAT
,
3113 k_bank
->prog_base
+ bank
->sectors
[i
].offset
,
3114 1, 0, 0, 0, 0, 0, 0, 0, &ftfx_fstat
);
3116 if (result
== ERROR_OK
) {
3117 bank
->sectors
[i
].is_erased
= !(ftfx_fstat
& 0x01);
3119 LOG_DEBUG("Ignoring error on PFlash sector blank-check");
3120 kinetis_ftfx_clear_error(bank
->target
);
3121 bank
->sectors
[i
].is_erased
= -1;
3125 /* the whole bank is erased, update all sectors */
3126 for (unsigned int i
= 0; i
< bank
->num_sectors
; i
++)
3127 bank
->sectors
[i
].is_erased
= 1;
3130 LOG_WARNING("kinetis_blank_check not supported yet for FlexRAM");
3131 return ERROR_FLASH_OPERATION_FAILED
;
3138 COMMAND_HANDLER(kinetis_nvm_partition
)
3142 unsigned num_blocks
, first_nvm_bank
;
3143 unsigned long par
, log2
= 0, ee1
= 0, ee2
= 0;
3144 enum { SHOW_INFO
, DF_SIZE
, EEBKP_SIZE
} sz_type
= SHOW_INFO
;
3146 uint8_t load_flex_ram
= 1;
3147 uint8_t ee_size_code
= 0x3f;
3148 uint8_t flex_nvm_partition_code
= 0;
3149 uint8_t ee_split
= 3;
3150 struct target
*target
= get_current_target(CMD_CTX
);
3151 struct kinetis_chip
*k_chip
;
3154 k_chip
= kinetis_get_chip(target
);
3156 if (k_chip
->chip_type
== CT_S32K
) {
3157 LOG_ERROR("NVM partition not supported on S32K1xx (yet).");
3161 if (CMD_ARGC
>= 2) {
3162 if (strcmp(CMD_ARGV
[0], "dataflash") == 0)
3164 else if (strcmp(CMD_ARGV
[0], "eebkp") == 0)
3165 sz_type
= EEBKP_SIZE
;
3167 COMMAND_PARSE_NUMBER(ulong
, CMD_ARGV
[1], par
);
3168 while (par
>> (log2
+ 3))
3174 LOG_ERROR("Chip not probed.");
3177 result
= target_read_u32(target
, k_chip
->sim_base
+ SIM_FCFG1_OFFSET
, &sim_fcfg1
);
3178 if (result
!= ERROR_OK
)
3181 flex_nvm_partition_code
= (uint8_t)((sim_fcfg1
>> 8) & 0x0f);
3182 switch (flex_nvm_partition_code
) {
3184 command_print(CMD
, "No EEPROM backup, data flash only");
3192 command_print(CMD
, "EEPROM backup %d KB", 4 << flex_nvm_partition_code
);
3195 command_print(CMD
, "No data flash, EEPROM backup only");
3203 command_print(CMD
, "data flash %d KB", 4 << (flex_nvm_partition_code
& 7));
3206 command_print(CMD
, "No EEPROM backup, data flash only (DEPART not set)");
3209 command_print(CMD
, "Unsupported EEPROM backup size code 0x%02" PRIx8
, flex_nvm_partition_code
);
3214 flex_nvm_partition_code
= 0x8 | log2
;
3218 flex_nvm_partition_code
= log2
;
3222 if (CMD_ARGC
== 3) {
3224 COMMAND_PARSE_NUMBER(ulong
, CMD_ARGV
[2], eex
);
3225 ee1
= ee2
= eex
/ 2;
3226 } else if (CMD_ARGC
>= 4) {
3227 COMMAND_PARSE_NUMBER(ulong
, CMD_ARGV
[2], ee1
);
3228 COMMAND_PARSE_NUMBER(ulong
, CMD_ARGV
[3], ee2
);
3231 enable
= ee1
+ ee2
> 0;
3233 for (log2
= 2; ; log2
++) {
3234 if (ee1
+ ee2
== (16u << 10) >> log2
)
3236 if (ee1
+ ee2
> (16u << 10) >> log2
|| log2
>= 9) {
3237 LOG_ERROR("Unsupported EEPROM size");
3238 return ERROR_FLASH_OPERATION_FAILED
;
3244 else if (ee1
* 7 == ee2
)
3246 else if (ee1
!= ee2
) {
3247 LOG_ERROR("Unsupported EEPROM sizes ratio");
3248 return ERROR_FLASH_OPERATION_FAILED
;
3251 ee_size_code
= log2
| ee_split
<< 4;
3255 COMMAND_PARSE_ON_OFF(CMD_ARGV
[4], enable
);
3259 LOG_INFO("DEPART 0x%" PRIx8
", EEPROM size code 0x%" PRIx8
,
3260 flex_nvm_partition_code
, ee_size_code
);
3262 result
= kinetis_check_run_mode(k_chip
);
3263 if (result
!= ERROR_OK
)
3266 /* reset error flags */
3267 result
= kinetis_ftfx_prepare(target
);
3268 if (result
!= ERROR_OK
)
3271 result
= kinetis_ftfx_command(target
, FTFX_CMD_PGMPART
, load_flex_ram
,
3272 ee_size_code
, flex_nvm_partition_code
, 0, 0,
3274 if (result
!= ERROR_OK
)
3277 command_print(CMD
, "FlexNVM partition set. Please reset MCU.");
3280 first_nvm_bank
= k_chip
->num_pflash_blocks
;
3281 num_blocks
= k_chip
->num_pflash_blocks
+ k_chip
->num_nvm_blocks
;
3282 for (bank_idx
= first_nvm_bank
; bank_idx
< num_blocks
; bank_idx
++)
3283 k_chip
->banks
[bank_idx
].probed
= false; /* re-probe before next use */
3284 k_chip
->probed
= false;
3287 command_print(CMD
, "FlexNVM banks will be re-probed to set new data flash size.");
3291 COMMAND_HANDLER(kinetis_fcf_source_handler
)
3294 return ERROR_COMMAND_SYNTAX_ERROR
;
3296 if (CMD_ARGC
== 1) {
3297 if (strcmp(CMD_ARGV
[0], "write") == 0)
3298 allow_fcf_writes
= true;
3299 else if (strcmp(CMD_ARGV
[0], "protection") == 0)
3300 allow_fcf_writes
= false;
3302 return ERROR_COMMAND_SYNTAX_ERROR
;
3305 if (allow_fcf_writes
) {
3306 command_print(CMD
, "Arbitrary Flash Configuration Field writes enabled.");
3307 command_print(CMD
, "Protection info writes to FCF disabled.");
3308 LOG_WARNING("BEWARE: incorrect flash configuration may permanently lock the device.");
3310 command_print(CMD
, "Protection info writes to Flash Configuration Field enabled.");
3311 command_print(CMD
, "Arbitrary FCF writes disabled. Mode safe from unwanted locking of the device.");
3317 COMMAND_HANDLER(kinetis_fopt_handler
)
3320 return ERROR_COMMAND_SYNTAX_ERROR
;
3322 if (CMD_ARGC
== 1) {
3323 COMMAND_PARSE_NUMBER(u8
, CMD_ARGV
[0], fcf_fopt
);
3325 command_print(CMD
, "FCF_FOPT 0x%02" PRIx8
, fcf_fopt
);
3331 COMMAND_HANDLER(kinetis_create_banks_handler
)
3334 return ERROR_COMMAND_SYNTAX_ERROR
;
3336 create_banks
= true;
3342 static const struct command_registration kinetis_security_command_handlers
[] = {
3344 .name
= "check_security",
3345 .mode
= COMMAND_EXEC
,
3346 .help
= "Check status of device security lock",
3348 .handler
= kinetis_check_flash_security_status
,
3352 .mode
= COMMAND_EXEC
,
3353 .help
= "Issue a halt via the MDM-AP",
3355 .handler
= kinetis_mdm_halt
,
3358 .name
= "mass_erase",
3359 .mode
= COMMAND_EXEC
,
3360 .help
= "Issue a complete flash erase via the MDM-AP",
3362 .handler
= kinetis_mdm_mass_erase
,
3366 .mode
= COMMAND_EXEC
,
3367 .help
= "Issue a reset via the MDM-AP",
3369 .handler
= kinetis_mdm_reset
,
3371 COMMAND_REGISTRATION_DONE
3374 static const struct command_registration kinetis_exec_command_handlers
[] = {
3377 .mode
= COMMAND_ANY
,
3378 .help
= "MDM-AP command group",
3380 .chain
= kinetis_security_command_handlers
,
3383 .name
= "disable_wdog",
3384 .mode
= COMMAND_EXEC
,
3385 .help
= "Disable the watchdog timer",
3387 .handler
= kinetis_disable_wdog_handler
,
3390 .name
= "nvm_partition",
3391 .mode
= COMMAND_EXEC
,
3392 .help
= "Show/set data flash or EEPROM backup size in kilobytes,"
3393 " set two EEPROM sizes in bytes and FlexRAM loading during reset",
3394 .usage
= "('info'|'dataflash' size|'eebkp' size) [eesize1 eesize2] ['on'|'off']",
3395 .handler
= kinetis_nvm_partition
,
3398 .name
= "fcf_source",
3399 .mode
= COMMAND_EXEC
,
3400 .help
= "Use protection as a source for Flash Configuration Field or allow writing arbitrary values to the FCF"
3401 " Mode 'protection' is safe from unwanted locking of the device.",
3402 .usage
= "['protection'|'write']",
3403 .handler
= kinetis_fcf_source_handler
,
3407 .mode
= COMMAND_EXEC
,
3408 .help
= "FCF_FOPT value source in 'kinetis fcf_source protection' mode",
3410 .handler
= kinetis_fopt_handler
,
3413 .name
= "create_banks",
3414 .mode
= COMMAND_CONFIG
,
3415 .help
= "Driver creates additional banks if device with two/four flash blocks is probed",
3416 .handler
= kinetis_create_banks_handler
,
3419 COMMAND_REGISTRATION_DONE
3422 static const struct command_registration kinetis_command_handler
[] = {
3425 .mode
= COMMAND_ANY
,
3426 .help
= "Kinetis flash controller commands",
3428 .chain
= kinetis_exec_command_handlers
,
3430 COMMAND_REGISTRATION_DONE
3435 const struct flash_driver kinetis_flash
= {
3437 .commands
= kinetis_command_handler
,
3438 .flash_bank_command
= kinetis_flash_bank_command
,
3439 .erase
= kinetis_erase
,
3440 .protect
= kinetis_protect
,
3441 .write
= kinetis_write
,
3442 .read
= default_flash_read
,
3443 .probe
= kinetis_probe
,
3444 .auto_probe
= kinetis_auto_probe
,
3445 .erase_check
= kinetis_blank_check
,
3446 .protect_check
= kinetis_protect_check
,
3447 .info
= kinetis_info
,
3448 .free_driver_priv
= kinetis_free_driver_priv
,