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nrf51: show proper part number
[openocd.git] / src / flash / nor / nrf51.c
1 /***************************************************************************
2 * Copyright (C) 2013 Synapse Product Development *
3 * Andrey Smirnov <andrew.smironv@gmail.com> *
4 * Angus Gratton <gus@projectgus.com> *
5 * Erdem U. Altunyurt <spamjunkeater@gmail.com> *
6 * *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
11 * *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
16 * *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
19 ***************************************************************************/
20
21 #ifdef HAVE_CONFIG_H
22 #include "config.h"
23 #endif
24
25 #include "imp.h"
26 #include <target/algorithm.h>
27 #include <target/armv7m.h>
28 #include <helper/types.h>
29
30 enum {
31 NRF51_FLASH_BASE = 0x00000000,
32 };
33
34 enum nrf51_ficr_registers {
35 NRF51_FICR_BASE = 0x10000000, /* Factory Information Configuration Registers */
36
37 #define NRF51_FICR_REG(offset) (NRF51_FICR_BASE + offset)
38
39 NRF51_FICR_CODEPAGESIZE = NRF51_FICR_REG(0x010),
40 NRF51_FICR_CODESIZE = NRF51_FICR_REG(0x014),
41 NRF51_FICR_CLENR0 = NRF51_FICR_REG(0x028),
42 NRF51_FICR_PPFC = NRF51_FICR_REG(0x02C),
43 NRF51_FICR_NUMRAMBLOCK = NRF51_FICR_REG(0x034),
44 NRF51_FICR_SIZERAMBLOCK0 = NRF51_FICR_REG(0x038),
45 NRF51_FICR_SIZERAMBLOCK1 = NRF51_FICR_REG(0x03C),
46 NRF51_FICR_SIZERAMBLOCK2 = NRF51_FICR_REG(0x040),
47 NRF51_FICR_SIZERAMBLOCK3 = NRF51_FICR_REG(0x044),
48 NRF51_FICR_CONFIGID = NRF51_FICR_REG(0x05C),
49 NRF51_FICR_DEVICEID0 = NRF51_FICR_REG(0x060),
50 NRF51_FICR_DEVICEID1 = NRF51_FICR_REG(0x064),
51 NRF51_FICR_ER0 = NRF51_FICR_REG(0x080),
52 NRF51_FICR_ER1 = NRF51_FICR_REG(0x084),
53 NRF51_FICR_ER2 = NRF51_FICR_REG(0x088),
54 NRF51_FICR_ER3 = NRF51_FICR_REG(0x08C),
55 NRF51_FICR_IR0 = NRF51_FICR_REG(0x090),
56 NRF51_FICR_IR1 = NRF51_FICR_REG(0x094),
57 NRF51_FICR_IR2 = NRF51_FICR_REG(0x098),
58 NRF51_FICR_IR3 = NRF51_FICR_REG(0x09C),
59 NRF51_FICR_DEVICEADDRTYPE = NRF51_FICR_REG(0x0A0),
60 NRF51_FICR_DEVICEADDR0 = NRF51_FICR_REG(0x0A4),
61 NRF51_FICR_DEVICEADDR1 = NRF51_FICR_REG(0x0A8),
62 NRF51_FICR_OVERRIDEN = NRF51_FICR_REG(0x0AC),
63 NRF51_FICR_NRF_1MBIT0 = NRF51_FICR_REG(0x0B0),
64 NRF51_FICR_NRF_1MBIT1 = NRF51_FICR_REG(0x0B4),
65 NRF51_FICR_NRF_1MBIT2 = NRF51_FICR_REG(0x0B8),
66 NRF51_FICR_NRF_1MBIT3 = NRF51_FICR_REG(0x0BC),
67 NRF51_FICR_NRF_1MBIT4 = NRF51_FICR_REG(0x0C0),
68 NRF51_FICR_BLE_1MBIT0 = NRF51_FICR_REG(0x0EC),
69 NRF51_FICR_BLE_1MBIT1 = NRF51_FICR_REG(0x0F0),
70 NRF51_FICR_BLE_1MBIT2 = NRF51_FICR_REG(0x0F4),
71 NRF51_FICR_BLE_1MBIT3 = NRF51_FICR_REG(0x0F8),
72 NRF51_FICR_BLE_1MBIT4 = NRF51_FICR_REG(0x0FC),
73 };
74
75 enum nrf51_uicr_registers {
76 NRF51_UICR_BASE = 0x10001000, /* User Information
77 * Configuration Regsters */
78
79 NRF51_UICR_SIZE = 0x100,
80
81 #define NRF51_UICR_REG(offset) (NRF51_UICR_BASE + offset)
82
83 NRF51_UICR_CLENR0 = NRF51_UICR_REG(0x000),
84 NRF51_UICR_RBPCONF = NRF51_UICR_REG(0x004),
85 NRF51_UICR_XTALFREQ = NRF51_UICR_REG(0x008),
86 NRF51_UICR_FWID = NRF51_UICR_REG(0x010),
87 };
88
89 enum nrf51_nvmc_registers {
90 NRF51_NVMC_BASE = 0x4001E000, /* Non-Volatile Memory
91 * Controller Regsters */
92
93 #define NRF51_NVMC_REG(offset) (NRF51_NVMC_BASE + offset)
94
95 NRF51_NVMC_READY = NRF51_NVMC_REG(0x400),
96 NRF51_NVMC_CONFIG = NRF51_NVMC_REG(0x504),
97 NRF51_NVMC_ERASEPAGE = NRF51_NVMC_REG(0x508),
98 NRF51_NVMC_ERASEALL = NRF51_NVMC_REG(0x50C),
99 NRF51_NVMC_ERASEUICR = NRF51_NVMC_REG(0x514),
100 };
101
102 enum nrf51_nvmc_config_bits {
103 NRF51_NVMC_CONFIG_REN = 0x00,
104 NRF51_NVMC_CONFIG_WEN = 0x01,
105 NRF51_NVMC_CONFIG_EEN = 0x02,
106
107 };
108
109 struct nrf51_info {
110 uint32_t code_page_size;
111
112 struct {
113 bool probed;
114 int (*write) (struct flash_bank *bank,
115 struct nrf51_info *chip,
116 const uint8_t *buffer, uint32_t offset, uint32_t count);
117 } bank[2];
118 struct target *target;
119 };
120
121 struct nrf51_device_spec {
122 uint16_t hwid;
123 const char *part;
124 const char *variant;
125 const char *build_code;
126 unsigned int flash_size_kb;
127 };
128
129 /* The known devices table below is derived from the "nRF51 Series
130 * Compatibility Matrix" document, which can be found by searching for
131 * ATTN-51 on the Nordic Semi website:
132 *
133 * http://www.nordicsemi.com/eng/content/search?SearchText=ATTN-51
134 *
135 * Up to date with Matrix v2.0, plus some additional HWIDs.
136 *
137 * The additional HWIDs apply where the build code in the matrix is
138 * shown as Gx0, Bx0, etc. In these cases the HWID in the matrix is
139 * for x==0, x!=0 means different (unspecified) HWIDs.
140 */
141 static const struct nrf51_device_spec nrf51_known_devices_table[] = {
142 /* nRF51822 Devices (IC rev 1). */
143 {
144 .hwid = 0x001D,
145 .part = "51822",
146 .variant = "QFAA",
147 .build_code = "CA/C0",
148 .flash_size_kb = 256,
149 },
150 {
151 .hwid = 0x0026,
152 .part = "51822",
153 .variant = "QFAB",
154 .build_code = "AA",
155 .flash_size_kb = 128,
156 },
157 {
158 .hwid = 0x0027,
159 .part = "51822",
160 .variant = "QFAB",
161 .build_code = "A0",
162 .flash_size_kb = 128,
163 },
164 {
165 .hwid = 0x0020,
166 .part = "51822",
167 .variant = "CEAA",
168 .build_code = "BA",
169 .flash_size_kb = 256,
170 },
171 {
172 .hwid = 0x002F,
173 .part = "51822",
174 .variant = "CEAA",
175 .build_code = "B0",
176 .flash_size_kb = 256,
177 },
178
179 /* nRF51822 Devices (IC rev 2). */
180 {
181 .hwid = 0x002A,
182 .part = "51822",
183 .variant = "QFAA",
184 .build_code = "FA0",
185 .flash_size_kb = 256,
186 },
187 {
188 .hwid = 0x0044,
189 .part = "51822",
190 .variant = "QFAA",
191 .build_code = "GC0",
192 .flash_size_kb = 256,
193 },
194 {
195 .hwid = 0x003C,
196 .part = "51822",
197 .variant = "QFAA",
198 .build_code = "G0",
199 .flash_size_kb = 256,
200 },
201 {
202 .hwid = 0x0057,
203 .part = "51822",
204 .variant = "QFAA",
205 .build_code = "G2",
206 .flash_size_kb = 256,
207 },
208 {
209 .hwid = 0x0058,
210 .part = "51822",
211 .variant = "QFAA",
212 .build_code = "G3",
213 .flash_size_kb = 256,
214 },
215 {
216 .hwid = 0x004C,
217 .part = "51822",
218 .variant = "QFAB",
219 .build_code = "B0",
220 .flash_size_kb = 128,
221 },
222 {
223 .hwid = 0x0040,
224 .part = "51822",
225 .variant = "CEAA",
226 .build_code = "CA0",
227 .flash_size_kb = 256,
228 },
229 {
230 .hwid = 0x0047,
231 .part = "51822",
232 .variant = "CEAA",
233 .build_code = "DA0",
234 .flash_size_kb = 256,
235 },
236 {
237 .hwid = 0x004D,
238 .part = "51822",
239 .variant = "CEAA",
240 .build_code = "D00",
241 .flash_size_kb = 256,
242 },
243
244 /* nRF51822 Devices (IC rev 3). */
245 {
246 .hwid = 0x0072,
247 .part = "51822",
248 .variant = "QFAA",
249 .build_code = "H0",
250 .flash_size_kb = 256,
251 },
252 {
253 .hwid = 0x007B,
254 .part = "51822",
255 .variant = "QFAB",
256 .build_code = "C0",
257 .flash_size_kb = 128,
258 },
259 {
260 .hwid = 0x0083,
261 .part = "51822",
262 .variant = "QFAC",
263 .build_code = "A0",
264 .flash_size_kb = 256,
265 },
266 {
267 .hwid = 0x0084,
268 .part = "51822",
269 .variant = "QFAC",
270 .build_code = "A1",
271 .flash_size_kb = 256,
272 },
273 {
274 .hwid = 0x007D,
275 .part = "51822",
276 .variant = "CDAB",
277 .build_code = "A0",
278 .flash_size_kb = 128,
279 },
280 {
281 .hwid = 0x0079,
282 .part = "51822",
283 .variant = "CEAA",
284 .build_code = "E0",
285 .flash_size_kb = 256,
286 },
287 {
288 .hwid = 0x0087,
289 .part = "51822",
290 .variant = "CFAC",
291 .build_code = "A0",
292 .flash_size_kb = 256,
293 },
294
295 /* nRF51422 Devices (IC rev 1). */
296 {
297 .hwid = 0x001E,
298 .part = "51422",
299 .variant = "QFAA",
300 .build_code = "CA",
301 .flash_size_kb = 256,
302 },
303 {
304 .hwid = 0x0024,
305 .part = "51422",
306 .variant = "QFAA",
307 .build_code = "C0",
308 .flash_size_kb = 256,
309 },
310 {
311 .hwid = 0x0031,
312 .part = "51422",
313 .variant = "CEAA",
314 .build_code = "A0A",
315 .flash_size_kb = 256,
316 },
317
318 /* nRF51422 Devices (IC rev 2). */
319 {
320 .hwid = 0x002D,
321 .part = "51422",
322 .variant = "QFAA",
323 .build_code = "DAA",
324 .flash_size_kb = 256,
325 },
326 {
327 .hwid = 0x002E,
328 .part = "51422",
329 .variant = "QFAA",
330 .build_code = "E0",
331 .flash_size_kb = 256,
332 },
333 {
334 .hwid = 0x0061,
335 .part = "51422",
336 .variant = "QFAB",
337 .build_code = "A00",
338 .flash_size_kb = 128,
339 },
340 {
341 .hwid = 0x0050,
342 .part = "51422",
343 .variant = "CEAA",
344 .build_code = "B0",
345 .flash_size_kb = 256,
346 },
347
348 /* nRF51422 Devices (IC rev 3). */
349 {
350 .hwid = 0x0073,
351 .part = "51422",
352 .variant = "QFAA",
353 .build_code = "F0",
354 .flash_size_kb = 256,
355 },
356 {
357 .hwid = 0x007C,
358 .part = "51422",
359 .variant = "QFAB",
360 .build_code = "B0",
361 .flash_size_kb = 128,
362 },
363 {
364 .hwid = 0x0085,
365 .part = "51422",
366 .variant = "QFAC",
367 .build_code = "A0",
368 .flash_size_kb = 256,
369 },
370 {
371 .hwid = 0x0086,
372 .part = "51422",
373 .variant = "QFAC",
374 .build_code = "A1",
375 .flash_size_kb = 256,
376 },
377 {
378 .hwid = 0x007E,
379 .part = "51422",
380 .variant = "CDAB",
381 .build_code = "A0",
382 .flash_size_kb = 128,
383 },
384 {
385 .hwid = 0x007A,
386 .part = "51422",
387 .variant = "CEAA",
388 .build_code = "C0",
389 .flash_size_kb = 256,
390 },
391 {
392 .hwid = 0x0088,
393 .part = "51422",
394 .variant = "CFAC",
395 .build_code = "A0",
396 .flash_size_kb = 256,
397 },
398
399 /* Some early nRF51-DK (PCA10028) & nRF51-Dongle (PCA10031) boards
400 with built-in jlink seem to use engineering samples not listed
401 in the nRF51 Series Compatibility Matrix V1.0. */
402 {
403 .hwid = 0x0071,
404 .part = "51822",
405 .variant = "QFAC",
406 .build_code = "AB",
407 .flash_size_kb = 256,
408 },
409 };
410
411 static int nrf51_bank_is_probed(struct flash_bank *bank)
412 {
413 struct nrf51_info *chip = bank->driver_priv;
414
415 assert(chip != NULL);
416
417 return chip->bank[bank->bank_number].probed;
418 }
419 static int nrf51_probe(struct flash_bank *bank);
420
421 static int nrf51_get_probed_chip_if_halted(struct flash_bank *bank, struct nrf51_info **chip)
422 {
423 if (bank->target->state != TARGET_HALTED) {
424 LOG_ERROR("Target not halted");
425 return ERROR_TARGET_NOT_HALTED;
426 }
427
428 *chip = bank->driver_priv;
429
430 int probed = nrf51_bank_is_probed(bank);
431 if (probed < 0)
432 return probed;
433 else if (!probed)
434 return nrf51_probe(bank);
435 else
436 return ERROR_OK;
437 }
438
439 static int nrf51_wait_for_nvmc(struct nrf51_info *chip)
440 {
441 uint32_t ready;
442 int res;
443 int timeout = 100;
444
445 do {
446 res = target_read_u32(chip->target, NRF51_NVMC_READY, &ready);
447 if (res != ERROR_OK) {
448 LOG_ERROR("Couldn't read NVMC_READY register");
449 return res;
450 }
451
452 if (ready == 0x00000001)
453 return ERROR_OK;
454
455 alive_sleep(1);
456 } while (timeout--);
457
458 LOG_DEBUG("Timed out waiting for NVMC_READY");
459 return ERROR_FLASH_BUSY;
460 }
461
462 static int nrf51_nvmc_erase_enable(struct nrf51_info *chip)
463 {
464 int res;
465 res = target_write_u32(chip->target,
466 NRF51_NVMC_CONFIG,
467 NRF51_NVMC_CONFIG_EEN);
468
469 if (res != ERROR_OK) {
470 LOG_ERROR("Failed to enable erase operation");
471 return res;
472 }
473
474 /*
475 According to NVMC examples in Nordic SDK busy status must be
476 checked after writing to NVMC_CONFIG
477 */
478 res = nrf51_wait_for_nvmc(chip);
479 if (res != ERROR_OK)
480 LOG_ERROR("Erase enable did not complete");
481
482 return res;
483 }
484
485 static int nrf51_nvmc_write_enable(struct nrf51_info *chip)
486 {
487 int res;
488 res = target_write_u32(chip->target,
489 NRF51_NVMC_CONFIG,
490 NRF51_NVMC_CONFIG_WEN);
491
492 if (res != ERROR_OK) {
493 LOG_ERROR("Failed to enable write operation");
494 return res;
495 }
496
497 /*
498 According to NVMC examples in Nordic SDK busy status must be
499 checked after writing to NVMC_CONFIG
500 */
501 res = nrf51_wait_for_nvmc(chip);
502 if (res != ERROR_OK)
503 LOG_ERROR("Write enable did not complete");
504
505 return res;
506 }
507
508 static int nrf51_nvmc_read_only(struct nrf51_info *chip)
509 {
510 int res;
511 res = target_write_u32(chip->target,
512 NRF51_NVMC_CONFIG,
513 NRF51_NVMC_CONFIG_REN);
514
515 if (res != ERROR_OK) {
516 LOG_ERROR("Failed to enable read-only operation");
517 return res;
518 }
519 /*
520 According to NVMC examples in Nordic SDK busy status must be
521 checked after writing to NVMC_CONFIG
522 */
523 res = nrf51_wait_for_nvmc(chip);
524 if (res != ERROR_OK)
525 LOG_ERROR("Read only enable did not complete");
526
527 return res;
528 }
529
530 static int nrf51_nvmc_generic_erase(struct nrf51_info *chip,
531 uint32_t erase_register, uint32_t erase_value)
532 {
533 int res;
534
535 res = nrf51_nvmc_erase_enable(chip);
536 if (res != ERROR_OK)
537 goto error;
538
539 res = target_write_u32(chip->target,
540 erase_register,
541 erase_value);
542 if (res != ERROR_OK)
543 goto set_read_only;
544
545 res = nrf51_wait_for_nvmc(chip);
546 if (res != ERROR_OK)
547 goto set_read_only;
548
549 return nrf51_nvmc_read_only(chip);
550
551 set_read_only:
552 nrf51_nvmc_read_only(chip);
553 error:
554 LOG_ERROR("Failed to erase reg: 0x%08"PRIx32" val: 0x%08"PRIx32,
555 erase_register, erase_value);
556 return ERROR_FAIL;
557 }
558
559 static int nrf51_protect_check(struct flash_bank *bank)
560 {
561 int res;
562 uint32_t clenr0;
563
564 /* UICR cannot be write protected so just return early */
565 if (bank->base == NRF51_UICR_BASE)
566 return ERROR_OK;
567
568 struct nrf51_info *chip = bank->driver_priv;
569
570 assert(chip != NULL);
571
572 res = target_read_u32(chip->target, NRF51_FICR_CLENR0,
573 &clenr0);
574 if (res != ERROR_OK) {
575 LOG_ERROR("Couldn't read code region 0 size[FICR]");
576 return res;
577 }
578
579 if (clenr0 == 0xFFFFFFFF) {
580 res = target_read_u32(chip->target, NRF51_UICR_CLENR0,
581 &clenr0);
582 if (res != ERROR_OK) {
583 LOG_ERROR("Couldn't read code region 0 size[UICR]");
584 return res;
585 }
586 }
587
588 for (int i = 0; i < bank->num_sectors; i++)
589 bank->sectors[i].is_protected =
590 clenr0 != 0xFFFFFFFF && bank->sectors[i].offset < clenr0;
591
592 return ERROR_OK;
593 }
594
595 static int nrf51_protect(struct flash_bank *bank, int set, int first, int last)
596 {
597 int res;
598 uint32_t clenr0, ppfc;
599 struct nrf51_info *chip;
600
601 /* UICR cannot be write protected so just bail out early */
602 if (bank->base == NRF51_UICR_BASE)
603 return ERROR_FAIL;
604
605 res = nrf51_get_probed_chip_if_halted(bank, &chip);
606 if (res != ERROR_OK)
607 return res;
608
609 if (first != 0) {
610 LOG_ERROR("Code region 0 must start at the begining of the bank");
611 return ERROR_FAIL;
612 }
613
614 res = target_read_u32(chip->target, NRF51_FICR_PPFC,
615 &ppfc);
616 if (res != ERROR_OK) {
617 LOG_ERROR("Couldn't read PPFC register");
618 return res;
619 }
620
621 if ((ppfc & 0xFF) == 0x00) {
622 LOG_ERROR("Code region 0 size was pre-programmed at the factory, can't change flash protection settings");
623 return ERROR_FAIL;
624 }
625
626 res = target_read_u32(chip->target, NRF51_UICR_CLENR0,
627 &clenr0);
628 if (res != ERROR_OK) {
629 LOG_ERROR("Couldn't read code region 0 size[UICR]");
630 return res;
631 }
632
633 if (clenr0 == 0xFFFFFFFF) {
634 res = target_write_u32(chip->target, NRF51_UICR_CLENR0,
635 clenr0);
636 if (res != ERROR_OK) {
637 LOG_ERROR("Couldn't write code region 0 size[UICR]");
638 return res;
639 }
640
641 } else {
642 LOG_ERROR("You need to perform chip erase before changing the protection settings");
643 }
644
645 nrf51_protect_check(bank);
646
647 return ERROR_OK;
648 }
649
650 static int nrf51_probe(struct flash_bank *bank)
651 {
652 uint32_t hwid;
653 int res;
654 struct nrf51_info *chip = bank->driver_priv;
655
656 res = target_read_u32(chip->target, NRF51_FICR_CONFIGID, &hwid);
657 if (res != ERROR_OK) {
658 LOG_ERROR("Couldn't read CONFIGID register");
659 return res;
660 }
661
662 hwid &= 0xFFFF; /* HWID is stored in the lower two
663 * bytes of the CONFIGID register */
664
665 const struct nrf51_device_spec *spec = NULL;
666 for (size_t i = 0; i < ARRAY_SIZE(nrf51_known_devices_table); i++) {
667 if (hwid == nrf51_known_devices_table[i].hwid) {
668 spec = &nrf51_known_devices_table[i];
669 break;
670 }
671 }
672
673 if (!chip->bank[0].probed && !chip->bank[1].probed) {
674 if (spec)
675 LOG_INFO("nRF%s-%s(build code: %s) %ukB Flash",
676 spec->part, spec->variant, spec->build_code,
677 spec->flash_size_kb);
678 else
679 LOG_WARNING("Unknown device (HWID 0x%08" PRIx32 ")", hwid);
680 }
681
682 if (bank->base == NRF51_FLASH_BASE) {
683 /* The value stored in NRF51_FICR_CODEPAGESIZE is the number of bytes in one page of FLASH. */
684 res = target_read_u32(chip->target, NRF51_FICR_CODEPAGESIZE,
685 &chip->code_page_size);
686 if (res != ERROR_OK) {
687 LOG_ERROR("Couldn't read code page size");
688 return res;
689 }
690
691 /* Note the register name is misleading,
692 * NRF51_FICR_CODESIZE is the number of pages in flash memory, not the number of bytes! */
693 res = target_read_u32(chip->target, NRF51_FICR_CODESIZE,
694 (uint32_t *) &bank->num_sectors);
695 if (res != ERROR_OK) {
696 LOG_ERROR("Couldn't read code memory size");
697 return res;
698 }
699
700 bank->size = bank->num_sectors * chip->code_page_size;
701
702 if (spec && bank->size / 1024 != spec->flash_size_kb)
703 LOG_WARNING("Chip's reported Flash capacity does not match expected one");
704
705 bank->sectors = calloc(bank->num_sectors,
706 sizeof((bank->sectors)[0]));
707 if (!bank->sectors)
708 return ERROR_FLASH_BANK_NOT_PROBED;
709
710 /* Fill out the sector information: all NRF51 sectors are the same size and
711 * there is always a fixed number of them. */
712 for (int i = 0; i < bank->num_sectors; i++) {
713 bank->sectors[i].size = chip->code_page_size;
714 bank->sectors[i].offset = i * chip->code_page_size;
715
716 /* mark as unknown */
717 bank->sectors[i].is_erased = -1;
718 bank->sectors[i].is_protected = -1;
719 }
720
721 nrf51_protect_check(bank);
722
723 chip->bank[0].probed = true;
724 } else {
725 bank->size = NRF51_UICR_SIZE;
726 bank->num_sectors = 1;
727 bank->sectors = calloc(bank->num_sectors,
728 sizeof((bank->sectors)[0]));
729 if (!bank->sectors)
730 return ERROR_FLASH_BANK_NOT_PROBED;
731
732 bank->sectors[0].size = bank->size;
733 bank->sectors[0].offset = 0;
734
735 /* mark as unknown */
736 bank->sectors[0].is_erased = 0;
737 bank->sectors[0].is_protected = 0;
738
739 chip->bank[1].probed = true;
740 }
741
742 return ERROR_OK;
743 }
744
745 static int nrf51_auto_probe(struct flash_bank *bank)
746 {
747 int probed = nrf51_bank_is_probed(bank);
748
749 if (probed < 0)
750 return probed;
751 else if (probed)
752 return ERROR_OK;
753 else
754 return nrf51_probe(bank);
755 }
756
757 static struct flash_sector *nrf51_find_sector_by_address(struct flash_bank *bank, uint32_t address)
758 {
759 struct nrf51_info *chip = bank->driver_priv;
760
761 for (int i = 0; i < bank->num_sectors; i++)
762 if (bank->sectors[i].offset <= address &&
763 address < (bank->sectors[i].offset + chip->code_page_size))
764 return &bank->sectors[i];
765 return NULL;
766 }
767
768 static int nrf51_erase_all(struct nrf51_info *chip)
769 {
770 LOG_DEBUG("Erasing all non-volatile memory");
771 return nrf51_nvmc_generic_erase(chip,
772 NRF51_NVMC_ERASEALL,
773 0x00000001);
774 }
775
776 static int nrf51_erase_page(struct flash_bank *bank,
777 struct nrf51_info *chip,
778 struct flash_sector *sector)
779 {
780 int res;
781
782 LOG_DEBUG("Erasing page at 0x%"PRIx32, sector->offset);
783 if (sector->is_protected) {
784 LOG_ERROR("Cannot erase protected sector at 0x%" PRIx32, sector->offset);
785 return ERROR_FAIL;
786 }
787
788 if (bank->base == NRF51_UICR_BASE) {
789 uint32_t ppfc;
790 res = target_read_u32(chip->target, NRF51_FICR_PPFC,
791 &ppfc);
792 if (res != ERROR_OK) {
793 LOG_ERROR("Couldn't read PPFC register");
794 return res;
795 }
796
797 if ((ppfc & 0xFF) == 0xFF) {
798 /* We can't erase the UICR. Double-check to
799 see if it's already erased before complaining. */
800 default_flash_blank_check(bank);
801 if (sector->is_erased == 1)
802 return ERROR_OK;
803
804 LOG_ERROR("The chip was not pre-programmed with SoftDevice stack and UICR cannot be erased separately. Please issue mass erase before trying to write to this region");
805 return ERROR_FAIL;
806 }
807
808 res = nrf51_nvmc_generic_erase(chip,
809 NRF51_NVMC_ERASEUICR,
810 0x00000001);
811
812
813 } else {
814 res = nrf51_nvmc_generic_erase(chip,
815 NRF51_NVMC_ERASEPAGE,
816 sector->offset);
817 }
818
819 if (res == ERROR_OK)
820 sector->is_erased = 1;
821
822 return res;
823 }
824
825 static const uint8_t nrf51_flash_write_code[] = {
826 /* See contrib/loaders/flash/cortex-m0.S */
827 /* <wait_fifo>: */
828 0x0d, 0x68, /* ldr r5, [r1, #0] */
829 0x00, 0x2d, /* cmp r5, #0 */
830 0x0b, 0xd0, /* beq.n 1e <exit> */
831 0x4c, 0x68, /* ldr r4, [r1, #4] */
832 0xac, 0x42, /* cmp r4, r5 */
833 0xf9, 0xd0, /* beq.n 0 <wait_fifo> */
834 0x20, 0xcc, /* ldmia r4!, {r5} */
835 0x20, 0xc3, /* stmia r3!, {r5} */
836 0x94, 0x42, /* cmp r4, r2 */
837 0x01, 0xd3, /* bcc.n 18 <no_wrap> */
838 0x0c, 0x46, /* mov r4, r1 */
839 0x08, 0x34, /* adds r4, #8 */
840 /* <no_wrap>: */
841 0x4c, 0x60, /* str r4, [r1, #4] */
842 0x04, 0x38, /* subs r0, #4 */
843 0xf0, 0xd1, /* bne.n 0 <wait_fifo> */
844 /* <exit>: */
845 0x00, 0xbe /* bkpt 0x0000 */
846 };
847
848
849 /* Start a low level flash write for the specified region */
850 static int nrf51_ll_flash_write(struct nrf51_info *chip, uint32_t offset, const uint8_t *buffer, uint32_t bytes)
851 {
852 struct target *target = chip->target;
853 uint32_t buffer_size = 8192;
854 struct working_area *write_algorithm;
855 struct working_area *source;
856 uint32_t address = NRF51_FLASH_BASE + offset;
857 struct reg_param reg_params[4];
858 struct armv7m_algorithm armv7m_info;
859 int retval = ERROR_OK;
860
861
862 LOG_DEBUG("Writing buffer to flash offset=0x%"PRIx32" bytes=0x%"PRIx32, offset, bytes);
863 assert(bytes % 4 == 0);
864
865 /* allocate working area with flash programming code */
866 if (target_alloc_working_area(target, sizeof(nrf51_flash_write_code),
867 &write_algorithm) != ERROR_OK) {
868 LOG_WARNING("no working area available, falling back to slow memory writes");
869
870 for (; bytes > 0; bytes -= 4) {
871 retval = target_write_memory(chip->target, offset, 4, 1, buffer);
872 if (retval != ERROR_OK)
873 return retval;
874
875 retval = nrf51_wait_for_nvmc(chip);
876 if (retval != ERROR_OK)
877 return retval;
878
879 offset += 4;
880 buffer += 4;
881 }
882
883 return ERROR_OK;
884 }
885
886 LOG_WARNING("using fast async flash loader. This is currently supported");
887 LOG_WARNING("only with ST-Link and CMSIS-DAP. If you have issues, add");
888 LOG_WARNING("\"set WORKAREASIZE 0\" before sourcing nrf51.cfg to disable it");
889
890 retval = target_write_buffer(target, write_algorithm->address,
891 sizeof(nrf51_flash_write_code),
892 nrf51_flash_write_code);
893 if (retval != ERROR_OK)
894 return retval;
895
896 /* memory buffer */
897 while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK) {
898 buffer_size /= 2;
899 buffer_size &= ~3UL; /* Make sure it's 4 byte aligned */
900 if (buffer_size <= 256) {
901 /* free working area, write algorithm already allocated */
902 target_free_working_area(target, write_algorithm);
903
904 LOG_WARNING("No large enough working area available, can't do block memory writes");
905 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
906 }
907 }
908
909 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
910 armv7m_info.core_mode = ARM_MODE_THREAD;
911
912 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* byte count */
913 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* buffer start */
914 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT); /* buffer end */
915 init_reg_param(&reg_params[3], "r3", 32, PARAM_IN_OUT); /* target address */
916
917 buf_set_u32(reg_params[0].value, 0, 32, bytes);
918 buf_set_u32(reg_params[1].value, 0, 32, source->address);
919 buf_set_u32(reg_params[2].value, 0, 32, source->address + source->size);
920 buf_set_u32(reg_params[3].value, 0, 32, address);
921
922 retval = target_run_flash_async_algorithm(target, buffer, bytes/4, 4,
923 0, NULL,
924 4, reg_params,
925 source->address, source->size,
926 write_algorithm->address, 0,
927 &armv7m_info);
928
929 target_free_working_area(target, source);
930 target_free_working_area(target, write_algorithm);
931
932 destroy_reg_param(&reg_params[0]);
933 destroy_reg_param(&reg_params[1]);
934 destroy_reg_param(&reg_params[2]);
935 destroy_reg_param(&reg_params[3]);
936
937 return retval;
938 }
939
940 /* Check and erase flash sectors in specified range then start a low level page write.
941 start/end must be sector aligned.
942 */
943 static int nrf51_write_pages(struct flash_bank *bank, uint32_t start, uint32_t end, const uint8_t *buffer)
944 {
945 int res = ERROR_FAIL;
946 struct nrf51_info *chip = bank->driver_priv;
947 struct flash_sector *sector;
948 uint32_t offset;
949
950 assert(start % chip->code_page_size == 0);
951 assert(end % chip->code_page_size == 0);
952
953 /* Erase all sectors */
954 for (offset = start; offset < end; offset += chip->code_page_size) {
955 sector = nrf51_find_sector_by_address(bank, offset);
956 if (!sector) {
957 LOG_ERROR("Invalid sector @ 0x%08"PRIx32, offset);
958 return ERROR_FLASH_SECTOR_INVALID;
959 }
960
961 if (sector->is_protected) {
962 LOG_ERROR("Can't erase protected sector @ 0x%08"PRIx32, offset);
963 goto error;
964 }
965
966 if (sector->is_erased != 1) { /* 1 = erased, 0= not erased, -1 = unknown */
967 res = nrf51_erase_page(bank, chip, sector);
968 if (res != ERROR_OK) {
969 LOG_ERROR("Failed to erase sector @ 0x%08"PRIx32, sector->offset);
970 goto error;
971 }
972 }
973 sector->is_erased = 0;
974 }
975
976 res = nrf51_nvmc_write_enable(chip);
977 if (res != ERROR_OK)
978 goto error;
979
980 res = nrf51_ll_flash_write(chip, start, buffer, (end - start));
981 if (res != ERROR_OK)
982 goto set_read_only;
983
984 return nrf51_nvmc_read_only(chip);
985
986 set_read_only:
987 nrf51_nvmc_read_only(chip);
988 error:
989 LOG_ERROR("Failed to write to nrf51 flash");
990 return res;
991 }
992
993 static int nrf51_erase(struct flash_bank *bank, int first, int last)
994 {
995 int res;
996 struct nrf51_info *chip;
997
998 res = nrf51_get_probed_chip_if_halted(bank, &chip);
999 if (res != ERROR_OK)
1000 return res;
1001
1002 /* For each sector to be erased */
1003 for (int s = first; s <= last && res == ERROR_OK; s++)
1004 res = nrf51_erase_page(bank, chip, &bank->sectors[s]);
1005
1006 return res;
1007 }
1008
1009 static int nrf51_code_flash_write(struct flash_bank *bank,
1010 struct nrf51_info *chip,
1011 const uint8_t *buffer, uint32_t offset, uint32_t count)
1012 {
1013
1014 int res;
1015 /* Need to perform reads to fill any gaps we need to preserve in the first page,
1016 before the start of buffer, or in the last page, after the end of buffer */
1017 uint32_t first_page = offset/chip->code_page_size;
1018 uint32_t last_page = DIV_ROUND_UP(offset+count, chip->code_page_size);
1019
1020 uint32_t first_page_offset = first_page * chip->code_page_size;
1021 uint32_t last_page_offset = last_page * chip->code_page_size;
1022
1023 LOG_DEBUG("Padding write from 0x%08"PRIx32"-0x%08"PRIx32" as 0x%08"PRIx32"-0x%08"PRIx32,
1024 offset, offset+count, first_page_offset, last_page_offset);
1025
1026 uint32_t page_cnt = last_page - first_page;
1027 uint8_t buffer_to_flash[page_cnt*chip->code_page_size];
1028
1029 /* Fill in any space between start of first page and start of buffer */
1030 uint32_t pre = offset - first_page_offset;
1031 if (pre > 0) {
1032 res = target_read_memory(bank->target,
1033 first_page_offset,
1034 1,
1035 pre,
1036 buffer_to_flash);
1037 if (res != ERROR_OK)
1038 return res;
1039 }
1040
1041 /* Fill in main contents of buffer */
1042 memcpy(buffer_to_flash+pre, buffer, count);
1043
1044 /* Fill in any space between end of buffer and end of last page */
1045 uint32_t post = last_page_offset - (offset+count);
1046 if (post > 0) {
1047 /* Retrieve the full row contents from Flash */
1048 res = target_read_memory(bank->target,
1049 offset + count,
1050 1,
1051 post,
1052 buffer_to_flash+pre+count);
1053 if (res != ERROR_OK)
1054 return res;
1055 }
1056
1057 return nrf51_write_pages(bank, first_page_offset, last_page_offset, buffer_to_flash);
1058 }
1059
1060 static int nrf51_uicr_flash_write(struct flash_bank *bank,
1061 struct nrf51_info *chip,
1062 const uint8_t *buffer, uint32_t offset, uint32_t count)
1063 {
1064 int res;
1065 uint8_t uicr[NRF51_UICR_SIZE];
1066 struct flash_sector *sector = &bank->sectors[0];
1067
1068 if ((offset + count) > NRF51_UICR_SIZE)
1069 return ERROR_FAIL;
1070
1071 res = target_read_memory(bank->target,
1072 NRF51_UICR_BASE,
1073 1,
1074 NRF51_UICR_SIZE,
1075 uicr);
1076
1077 if (res != ERROR_OK)
1078 return res;
1079
1080 if (sector->is_erased != 1) {
1081 res = nrf51_erase_page(bank, chip, sector);
1082 if (res != ERROR_OK)
1083 return res;
1084 }
1085
1086 res = nrf51_nvmc_write_enable(chip);
1087 if (res != ERROR_OK)
1088 return res;
1089
1090 memcpy(&uicr[offset], buffer, count);
1091
1092 res = nrf51_ll_flash_write(chip, NRF51_UICR_BASE, uicr, NRF51_UICR_SIZE);
1093 if (res != ERROR_OK) {
1094 nrf51_nvmc_read_only(chip);
1095 return res;
1096 }
1097
1098 return nrf51_nvmc_read_only(chip);
1099 }
1100
1101
1102 static int nrf51_write(struct flash_bank *bank, const uint8_t *buffer,
1103 uint32_t offset, uint32_t count)
1104 {
1105 int res;
1106 struct nrf51_info *chip;
1107
1108 res = nrf51_get_probed_chip_if_halted(bank, &chip);
1109 if (res != ERROR_OK)
1110 return res;
1111
1112 return chip->bank[bank->bank_number].write(bank, chip, buffer, offset, count);
1113 }
1114
1115
1116 FLASH_BANK_COMMAND_HANDLER(nrf51_flash_bank_command)
1117 {
1118 static struct nrf51_info *chip;
1119
1120 switch (bank->base) {
1121 case NRF51_FLASH_BASE:
1122 bank->bank_number = 0;
1123 break;
1124 case NRF51_UICR_BASE:
1125 bank->bank_number = 1;
1126 break;
1127 default:
1128 LOG_ERROR("Invalid bank address 0x%08" PRIx32, bank->base);
1129 return ERROR_FAIL;
1130 }
1131
1132 if (!chip) {
1133 /* Create a new chip */
1134 chip = calloc(1, sizeof(*chip));
1135 if (!chip)
1136 return ERROR_FAIL;
1137
1138 chip->target = bank->target;
1139 }
1140
1141 switch (bank->base) {
1142 case NRF51_FLASH_BASE:
1143 chip->bank[bank->bank_number].write = nrf51_code_flash_write;
1144 break;
1145 case NRF51_UICR_BASE:
1146 chip->bank[bank->bank_number].write = nrf51_uicr_flash_write;
1147 break;
1148 }
1149
1150 chip->bank[bank->bank_number].probed = false;
1151 bank->driver_priv = chip;
1152
1153 return ERROR_OK;
1154 }
1155
1156 COMMAND_HANDLER(nrf51_handle_mass_erase_command)
1157 {
1158 int res;
1159 struct flash_bank *bank = NULL;
1160 struct target *target = get_current_target(CMD_CTX);
1161
1162 res = get_flash_bank_by_addr(target, NRF51_FLASH_BASE, true, &bank);
1163 if (res != ERROR_OK)
1164 return res;
1165
1166 assert(bank != NULL);
1167
1168 struct nrf51_info *chip;
1169
1170 res = nrf51_get_probed_chip_if_halted(bank, &chip);
1171 if (res != ERROR_OK)
1172 return res;
1173
1174 uint32_t ppfc;
1175
1176 res = target_read_u32(target, NRF51_FICR_PPFC,
1177 &ppfc);
1178 if (res != ERROR_OK) {
1179 LOG_ERROR("Couldn't read PPFC register");
1180 return res;
1181 }
1182
1183 if ((ppfc & 0xFF) == 0x00) {
1184 LOG_ERROR("Code region 0 size was pre-programmed at the factory, "
1185 "mass erase command won't work.");
1186 return ERROR_FAIL;
1187 }
1188
1189 res = nrf51_erase_all(chip);
1190 if (res != ERROR_OK) {
1191 LOG_ERROR("Failed to erase the chip");
1192 nrf51_protect_check(bank);
1193 return res;
1194 }
1195
1196 for (int i = 0; i < bank->num_sectors; i++)
1197 bank->sectors[i].is_erased = 1;
1198
1199 res = nrf51_protect_check(bank);
1200 if (res != ERROR_OK) {
1201 LOG_ERROR("Failed to check chip's write protection");
1202 return res;
1203 }
1204
1205 res = get_flash_bank_by_addr(target, NRF51_UICR_BASE, true, &bank);
1206 if (res != ERROR_OK)
1207 return res;
1208
1209 bank->sectors[0].is_erased = 1;
1210
1211 return ERROR_OK;
1212 }
1213
1214 static int nrf51_info(struct flash_bank *bank, char *buf, int buf_size)
1215 {
1216 int res;
1217
1218 struct nrf51_info *chip;
1219
1220 res = nrf51_get_probed_chip_if_halted(bank, &chip);
1221 if (res != ERROR_OK)
1222 return res;
1223
1224 static struct {
1225 const uint32_t address;
1226 uint32_t value;
1227 } ficr[] = {
1228 { .address = NRF51_FICR_CODEPAGESIZE },
1229 { .address = NRF51_FICR_CODESIZE },
1230 { .address = NRF51_FICR_CLENR0 },
1231 { .address = NRF51_FICR_PPFC },
1232 { .address = NRF51_FICR_NUMRAMBLOCK },
1233 { .address = NRF51_FICR_SIZERAMBLOCK0 },
1234 { .address = NRF51_FICR_SIZERAMBLOCK1 },
1235 { .address = NRF51_FICR_SIZERAMBLOCK2 },
1236 { .address = NRF51_FICR_SIZERAMBLOCK3 },
1237 { .address = NRF51_FICR_CONFIGID },
1238 { .address = NRF51_FICR_DEVICEID0 },
1239 { .address = NRF51_FICR_DEVICEID1 },
1240 { .address = NRF51_FICR_ER0 },
1241 { .address = NRF51_FICR_ER1 },
1242 { .address = NRF51_FICR_ER2 },
1243 { .address = NRF51_FICR_ER3 },
1244 { .address = NRF51_FICR_IR0 },
1245 { .address = NRF51_FICR_IR1 },
1246 { .address = NRF51_FICR_IR2 },
1247 { .address = NRF51_FICR_IR3 },
1248 { .address = NRF51_FICR_DEVICEADDRTYPE },
1249 { .address = NRF51_FICR_DEVICEADDR0 },
1250 { .address = NRF51_FICR_DEVICEADDR1 },
1251 { .address = NRF51_FICR_OVERRIDEN },
1252 { .address = NRF51_FICR_NRF_1MBIT0 },
1253 { .address = NRF51_FICR_NRF_1MBIT1 },
1254 { .address = NRF51_FICR_NRF_1MBIT2 },
1255 { .address = NRF51_FICR_NRF_1MBIT3 },
1256 { .address = NRF51_FICR_NRF_1MBIT4 },
1257 { .address = NRF51_FICR_BLE_1MBIT0 },
1258 { .address = NRF51_FICR_BLE_1MBIT1 },
1259 { .address = NRF51_FICR_BLE_1MBIT2 },
1260 { .address = NRF51_FICR_BLE_1MBIT3 },
1261 { .address = NRF51_FICR_BLE_1MBIT4 },
1262 }, uicr[] = {
1263 { .address = NRF51_UICR_CLENR0, },
1264 { .address = NRF51_UICR_RBPCONF },
1265 { .address = NRF51_UICR_XTALFREQ },
1266 { .address = NRF51_UICR_FWID },
1267 };
1268
1269 for (size_t i = 0; i < ARRAY_SIZE(ficr); i++) {
1270 res = target_read_u32(chip->target, ficr[i].address,
1271 &ficr[i].value);
1272 if (res != ERROR_OK) {
1273 LOG_ERROR("Couldn't read %" PRIx32, ficr[i].address);
1274 return res;
1275 }
1276 }
1277
1278 for (size_t i = 0; i < ARRAY_SIZE(uicr); i++) {
1279 res = target_read_u32(chip->target, uicr[i].address,
1280 &uicr[i].value);
1281 if (res != ERROR_OK) {
1282 LOG_ERROR("Couldn't read %" PRIx32, uicr[i].address);
1283 return res;
1284 }
1285 }
1286
1287 snprintf(buf, buf_size,
1288 "\n[factory information control block]\n\n"
1289 "code page size: %"PRIu32"B\n"
1290 "code memory size: %"PRIu32"kB\n"
1291 "code region 0 size: %"PRIu32"kB\n"
1292 "pre-programmed code: %s\n"
1293 "number of ram blocks: %"PRIu32"\n"
1294 "ram block 0 size: %"PRIu32"B\n"
1295 "ram block 1 size: %"PRIu32"B\n"
1296 "ram block 2 size: %"PRIu32"B\n"
1297 "ram block 3 size: %"PRIu32 "B\n"
1298 "config id: %" PRIx32 "\n"
1299 "device id: 0x%"PRIx32"%08"PRIx32"\n"
1300 "encryption root: 0x%08"PRIx32"%08"PRIx32"%08"PRIx32"%08"PRIx32"\n"
1301 "identity root: 0x%08"PRIx32"%08"PRIx32"%08"PRIx32"%08"PRIx32"\n"
1302 "device address type: 0x%"PRIx32"\n"
1303 "device address: 0x%"PRIx32"%08"PRIx32"\n"
1304 "override enable: %"PRIx32"\n"
1305 "NRF_1MBIT values: %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32"\n"
1306 "BLE_1MBIT values: %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32"\n"
1307 "\n[user information control block]\n\n"
1308 "code region 0 size: %"PRIu32"kB\n"
1309 "read back protection configuration: %"PRIx32"\n"
1310 "reset value for XTALFREQ: %"PRIx32"\n"
1311 "firmware id: 0x%04"PRIx32,
1312 ficr[0].value,
1313 (ficr[1].value * ficr[0].value) / 1024,
1314 (ficr[2].value == 0xFFFFFFFF) ? 0 : ficr[2].value / 1024,
1315 ((ficr[3].value & 0xFF) == 0x00) ? "present" : "not present",
1316 ficr[4].value,
1317 ficr[5].value,
1318 (ficr[6].value == 0xFFFFFFFF) ? 0 : ficr[6].value,
1319 (ficr[7].value == 0xFFFFFFFF) ? 0 : ficr[7].value,
1320 (ficr[8].value == 0xFFFFFFFF) ? 0 : ficr[8].value,
1321 ficr[9].value,
1322 ficr[10].value, ficr[11].value,
1323 ficr[12].value, ficr[13].value, ficr[14].value, ficr[15].value,
1324 ficr[16].value, ficr[17].value, ficr[18].value, ficr[19].value,
1325 ficr[20].value,
1326 ficr[21].value, ficr[22].value,
1327 ficr[23].value,
1328 ficr[24].value, ficr[25].value, ficr[26].value, ficr[27].value, ficr[28].value,
1329 ficr[29].value, ficr[30].value, ficr[31].value, ficr[32].value, ficr[33].value,
1330 (uicr[0].value == 0xFFFFFFFF) ? 0 : uicr[0].value / 1024,
1331 uicr[1].value & 0xFFFF,
1332 uicr[2].value & 0xFF,
1333 uicr[3].value & 0xFFFF);
1334
1335 return ERROR_OK;
1336 }
1337
1338 static const struct command_registration nrf51_exec_command_handlers[] = {
1339 {
1340 .name = "mass_erase",
1341 .handler = nrf51_handle_mass_erase_command,
1342 .mode = COMMAND_EXEC,
1343 .help = "Erase all flash contents of the chip.",
1344 },
1345 COMMAND_REGISTRATION_DONE
1346 };
1347
1348 static const struct command_registration nrf51_command_handlers[] = {
1349 {
1350 .name = "nrf51",
1351 .mode = COMMAND_ANY,
1352 .help = "nrf51 flash command group",
1353 .usage = "",
1354 .chain = nrf51_exec_command_handlers,
1355 },
1356 COMMAND_REGISTRATION_DONE
1357 };
1358
1359 struct flash_driver nrf51_flash = {
1360 .name = "nrf51",
1361 .commands = nrf51_command_handlers,
1362 .flash_bank_command = nrf51_flash_bank_command,
1363 .info = nrf51_info,
1364 .erase = nrf51_erase,
1365 .protect = nrf51_protect,
1366 .write = nrf51_write,
1367 .read = default_flash_read,
1368 .probe = nrf51_probe,
1369 .auto_probe = nrf51_auto_probe,
1370 .erase_check = default_flash_blank_check,
1371 .protect_check = nrf51_protect_check,
1372 };
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