1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Renesas RCar Gen3 RPC Hyperflash driver
4 * Based on U-Boot RPC Hyperflash driver
6 * Copyright (C) 2016 Renesas Electronics Corporation
7 * Copyright (C) 2016 Cogent Embedded, Inc.
8 * Copyright (C) 2017-2019 Marek Vasut <marek.vasut@gmail.com>
18 #include <helper/binarybuffer.h>
19 #include <helper/bits.h>
20 #include <helper/time_support.h>
22 #define RPC_CMNCR 0x0000 /* R/W */
23 #define RPC_CMNCR_MD BIT(31)
24 #define RPC_CMNCR_MOIIO0(val) (((val) & 0x3) << 16)
25 #define RPC_CMNCR_MOIIO1(val) (((val) & 0x3) << 18)
26 #define RPC_CMNCR_MOIIO2(val) (((val) & 0x3) << 20)
27 #define RPC_CMNCR_MOIIO3(val) (((val) & 0x3) << 22)
28 #define RPC_CMNCR_MOIIO_HIZ (RPC_CMNCR_MOIIO0(3) | RPC_CMNCR_MOIIO1(3) | \
29 RPC_CMNCR_MOIIO2(3) | RPC_CMNCR_MOIIO3(3))
30 #define RPC_CMNCR_IO0FV(val) (((val) & 0x3) << 8)
31 #define RPC_CMNCR_IO2FV(val) (((val) & 0x3) << 12)
32 #define RPC_CMNCR_IO3FV(val) (((val) & 0x3) << 14)
33 #define RPC_CMNCR_IOFV_HIZ (RPC_CMNCR_IO0FV(3) | RPC_CMNCR_IO2FV(3) | \
35 #define RPC_CMNCR_BSZ(val) (((val) & 0x3) << 0)
37 #define RPC_SSLDR 0x0004 /* R/W */
38 #define RPC_SSLDR_SPNDL(d) (((d) & 0x7) << 16)
39 #define RPC_SSLDR_SLNDL(d) (((d) & 0x7) << 8)
40 #define RPC_SSLDR_SCKDL(d) (((d) & 0x7) << 0)
42 #define RPC_DRCR 0x000C /* R/W */
43 #define RPC_DRCR_SSLN BIT(24)
44 #define RPC_DRCR_RBURST(v) (((v) & 0x1F) << 16)
45 #define RPC_DRCR_RCF BIT(9)
46 #define RPC_DRCR_RBE BIT(8)
47 #define RPC_DRCR_SSLE BIT(0)
49 #define RPC_DRCMR 0x0010 /* R/W */
50 #define RPC_DRCMR_CMD(c) (((c) & 0xFF) << 16)
51 #define RPC_DRCMR_OCMD(c) (((c) & 0xFF) << 0)
53 #define RPC_DREAR 0x0014 /* R/W */
54 #define RPC_DREAR_EAV(v) (((v) & 0xFF) << 16)
55 #define RPC_DREAR_EAC(v) (((v) & 0x7) << 0)
57 #define RPC_DROPR 0x0018 /* R/W */
58 #define RPC_DROPR_OPD3(o) (((o) & 0xFF) << 24)
59 #define RPC_DROPR_OPD2(o) (((o) & 0xFF) << 16)
60 #define RPC_DROPR_OPD1(o) (((o) & 0xFF) << 8)
61 #define RPC_DROPR_OPD0(o) (((o) & 0xFF) << 0)
63 #define RPC_DRENR 0x001C /* R/W */
64 #define RPC_DRENR_CDB(o) (uint32_t)((((o) & 0x3) << 30))
65 #define RPC_DRENR_OCDB(o) (((o) & 0x3) << 28)
66 #define RPC_DRENR_ADB(o) (((o) & 0x3) << 24)
67 #define RPC_DRENR_OPDB(o) (((o) & 0x3) << 20)
68 #define RPC_DRENR_SPIDB(o) (((o) & 0x3) << 16)
69 #define RPC_DRENR_DME BIT(15)
70 #define RPC_DRENR_CDE BIT(14)
71 #define RPC_DRENR_OCDE BIT(12)
72 #define RPC_DRENR_ADE(v) (((v) & 0xF) << 8)
73 #define RPC_DRENR_OPDE(v) (((v) & 0xF) << 4)
75 #define RPC_SMCR 0x0020 /* R/W */
76 #define RPC_SMCR_SSLKP BIT(8)
77 #define RPC_SMCR_SPIRE BIT(2)
78 #define RPC_SMCR_SPIWE BIT(1)
79 #define RPC_SMCR_SPIE BIT(0)
81 #define RPC_SMCMR 0x0024 /* R/W */
82 #define RPC_SMCMR_CMD(c) (((c) & 0xFF) << 16)
83 #define RPC_SMCMR_OCMD(c) (((c) & 0xFF) << 0)
85 #define RPC_SMADR 0x0028 /* R/W */
86 #define RPC_SMOPR 0x002C /* R/W */
87 #define RPC_SMOPR_OPD0(o) (((o) & 0xFF) << 0)
88 #define RPC_SMOPR_OPD1(o) (((o) & 0xFF) << 8)
89 #define RPC_SMOPR_OPD2(o) (((o) & 0xFF) << 16)
90 #define RPC_SMOPR_OPD3(o) (((o) & 0xFF) << 24)
92 #define RPC_SMENR 0x0030 /* R/W */
93 #define RPC_SMENR_CDB(o) (((o) & 0x3) << 30)
94 #define RPC_SMENR_OCDB(o) (((o) & 0x3) << 28)
95 #define RPC_SMENR_ADB(o) (((o) & 0x3) << 24)
96 #define RPC_SMENR_OPDB(o) (((o) & 0x3) << 20)
97 #define RPC_SMENR_SPIDB(o) (((o) & 0x3) << 16)
98 #define RPC_SMENR_DME BIT(15)
99 #define RPC_SMENR_CDE BIT(14)
100 #define RPC_SMENR_OCDE BIT(12)
101 #define RPC_SMENR_ADE(v) (((v) & 0xF) << 8)
102 #define RPC_SMENR_OPDE(v) (((v) & 0xF) << 4)
103 #define RPC_SMENR_SPIDE(v) (((v) & 0xF) << 0)
105 #define RPC_SMRDR0 0x0038 /* R */
106 #define RPC_SMRDR1 0x003C /* R */
107 #define RPC_SMWDR0 0x0040 /* R/W */
108 #define RPC_SMWDR1 0x0044 /* R/W */
109 #define RPC_CMNSR 0x0048 /* R */
110 #define RPC_CMNSR_SSLF BIT(1)
111 #define RPC_CMNSR_TEND BIT(0)
113 #define RPC_DRDMCR 0x0058 /* R/W */
114 #define RPC_DRDMCR_DMCYC(v) (((v) & 0xF) << 0)
116 #define RPC_DRDRENR 0x005C /* R/W */
117 #define RPC_DRDRENR_HYPE (0x5 << 12)
118 #define RPC_DRDRENR_ADDRE BIT(8)
119 #define RPC_DRDRENR_OPDRE BIT(4)
120 #define RPC_DRDRENR_DRDRE BIT(0)
122 #define RPC_SMDMCR 0x0060 /* R/W */
123 #define RPC_SMDMCR_DMCYC(v) (((v) & 0xF) << 0)
125 #define RPC_SMDRENR 0x0064 /* R/W */
126 #define RPC_SMDRENR_HYPE (0x5 << 12)
127 #define RPC_SMDRENR_ADDRE BIT(8)
128 #define RPC_SMDRENR_OPDRE BIT(4)
129 #define RPC_SMDRENR_SPIDRE BIT(0)
131 #define RPC_PHYCNT 0x007C /* R/W */
132 #define RPC_PHYCNT_CAL BIT(31)
133 #define PRC_PHYCNT_OCTA_AA BIT(22)
134 #define PRC_PHYCNT_OCTA_SA BIT(23)
135 #define PRC_PHYCNT_EXDS BIT(21)
136 #define RPC_PHYCNT_OCT BIT(20)
137 #define RPC_PHYCNT_WBUF2 BIT(4)
138 #define RPC_PHYCNT_WBUF BIT(2)
139 #define RPC_PHYCNT_MEM(v) (((v) & 0x3) << 0)
141 #define RPC_PHYINT 0x0088 /* R/W */
142 #define RPC_PHYINT_RSTEN BIT(18)
143 #define RPC_PHYINT_WPEN BIT(17)
144 #define RPC_PHYINT_INTEN BIT(16)
145 #define RPC_PHYINT_RST BIT(2)
146 #define RPC_PHYINT_WP BIT(1)
147 #define RPC_PHYINT_INT BIT(0)
149 #define RPC_WBUF 0x8000 /* R/W size=4/8/16/32/64Bytes */
150 #define RPC_WBUF_SIZE 0x100
152 static uint32_t rpc_base
= 0xee200000;
153 static uint32_t mem_base
= 0x08000000;
156 RPC_HF_SIZE_16BIT
= RPC_SMENR_SPIDE(0x8),
157 RPC_HF_SIZE_32BIT
= RPC_SMENR_SPIDE(0xC),
158 RPC_HF_SIZE_64BIT
= RPC_SMENR_SPIDE(0xF),
161 static int rpc_hf_wait_tend(struct target
*target
)
163 uint32_t reg
= rpc_base
+ RPC_CMNSR
;
165 unsigned long timeout
= 1000;
169 endtime
= timeval_ms() + timeout
;
171 ret
= target_read_u32(target
, reg
, &val
);
175 if (val
& RPC_CMNSR_TEND
)
179 } while (timeval_ms() < endtime
);
181 LOG_ERROR("timeout");
182 return ERROR_TIMEOUT_REACHED
;
185 static int clrsetbits_u32(struct target
*target
, uint32_t reg
,
186 uint32_t clr
, uint32_t set
)
191 ret
= target_read_u32(target
, reg
, &val
);
198 return target_write_u32(target
, reg
, val
);
201 static int rpc_hf_mode(struct target
*target
, bool manual
)
206 ret
= rpc_hf_wait_tend(target
);
207 if (ret
!= ERROR_OK
) {
208 LOG_ERROR("Mode TEND timeout");
212 ret
= clrsetbits_u32(target
, rpc_base
+ RPC_PHYCNT
,
213 RPC_PHYCNT_WBUF
| RPC_PHYCNT_WBUF2
|
214 RPC_PHYCNT_CAL
| RPC_PHYCNT_MEM(3),
215 RPC_PHYCNT_CAL
| RPC_PHYCNT_MEM(3));
219 ret
= clrsetbits_u32(target
, rpc_base
+ RPC_CMNCR
,
220 RPC_CMNCR_MD
| RPC_CMNCR_BSZ(3),
221 RPC_CMNCR_MOIIO_HIZ
| RPC_CMNCR_IOFV_HIZ
|
222 (manual
? RPC_CMNCR_MD
: 0) | RPC_CMNCR_BSZ(1));
229 ret
= target_write_u32(target
, rpc_base
+ RPC_DRCR
,
230 RPC_DRCR_RBURST(0x1F) | RPC_DRCR_RCF
|
235 ret
= target_write_u32(target
, rpc_base
+ RPC_DRCMR
,
236 RPC_DRCMR_CMD(0xA0));
239 ret
= target_write_u32(target
, rpc_base
+ RPC_DRENR
,
240 RPC_DRENR_CDB(2) | RPC_DRENR_OCDB(2) |
241 RPC_DRENR_ADB(2) | RPC_DRENR_SPIDB(2) |
242 RPC_DRENR_CDE
| RPC_DRENR_OCDE
|
247 ret
= target_write_u32(target
, rpc_base
+ RPC_DRDMCR
,
248 RPC_DRDMCR_DMCYC(0xE));
252 ret
= target_write_u32(target
, rpc_base
+ RPC_DRDRENR
,
253 RPC_DRDRENR_HYPE
| RPC_DRDRENR_ADDRE
|
259 return target_read_u32(target
, rpc_base
+ RPC_DRCR
, &val
);
262 static int rpc_hf_xfer(struct target
*target
, target_addr_t addr
,
263 uint32_t wdata
, uint32_t *rdata
, enum rpc_hf_size size
,
264 bool write
, const uint8_t *wbuf
, unsigned int wbuf_size
)
269 if (wbuf_size
!= 0) {
270 ret
= rpc_hf_wait_tend(target
);
271 if (ret
!= ERROR_OK
) {
272 LOG_ERROR("Xfer TEND timeout");
276 /* Write calibration magic */
277 ret
= target_write_u32(target
, rpc_base
+ RPC_DRCR
, 0x01FF0301);
281 ret
= target_write_u32(target
, rpc_base
+ RPC_PHYCNT
, 0x80030277);
285 ret
= target_write_memory(target
, rpc_base
| RPC_WBUF
, 4,
286 wbuf_size
/ 4, wbuf
);
290 ret
= clrsetbits_u32(target
, rpc_base
+ RPC_CMNCR
,
291 RPC_CMNCR_MD
| RPC_CMNCR_BSZ(3),
292 RPC_CMNCR_MOIIO_HIZ
| RPC_CMNCR_IOFV_HIZ
|
293 RPC_CMNCR_MD
| RPC_CMNCR_BSZ(1));
297 ret
= rpc_hf_mode(target
, 1);
302 /* Submit HF address, SMCMR CMD[7] ~= CA Bit# 47 (R/nW) */
303 ret
= target_write_u32(target
, rpc_base
+ RPC_SMCMR
,
304 write
? 0 : RPC_SMCMR_CMD(0x80));
308 ret
= target_write_u32(target
, rpc_base
+ RPC_SMADR
,
313 ret
= target_write_u32(target
, rpc_base
+ RPC_SMOPR
, 0x0);
317 ret
= target_write_u32(target
, rpc_base
+ RPC_SMDRENR
,
318 RPC_SMDRENR_HYPE
| RPC_SMDRENR_ADDRE
|
323 val
= RPC_SMENR_CDB(2) | RPC_SMENR_OCDB(2) |
324 RPC_SMENR_ADB(2) | RPC_SMENR_SPIDB(2) |
325 (wbuf_size
? RPC_SMENR_OPDB(2) : 0) |
326 RPC_SMENR_CDE
| RPC_SMENR_OCDE
| RPC_SMENR_ADE(4) | size
;
329 ret
= target_write_u32(target
, rpc_base
+ RPC_SMENR
, val
);
333 if (wbuf_size
== 0) {
334 buf_bswap32((uint8_t *)&wdata
, (uint8_t *)&wdata
, 4);
335 ret
= target_write_u32(target
, rpc_base
+ RPC_SMWDR0
,
341 ret
= target_write_u32(target
, rpc_base
+ RPC_SMCR
,
342 RPC_SMCR_SPIWE
| RPC_SMCR_SPIE
);
346 val
|= RPC_SMENR_DME
;
348 ret
= target_write_u32(target
, rpc_base
+ RPC_SMDMCR
,
349 RPC_SMDMCR_DMCYC(0xE));
353 ret
= target_write_u32(target
, rpc_base
+ RPC_SMENR
, val
);
357 ret
= target_write_u32(target
, rpc_base
+ RPC_SMCR
,
358 RPC_SMCR_SPIRE
| RPC_SMCR_SPIE
);
362 ret
= rpc_hf_wait_tend(target
);
367 ret
= target_read_u32(target
, rpc_base
+ RPC_SMRDR0
, &val32
);
370 buf_bswap32((uint8_t *)&val32
, (uint8_t *)&val32
, 4);
374 ret
= rpc_hf_mode(target
, 0);
376 LOG_ERROR("Xfer done TEND timeout");
380 static int rpchf_target_write_memory(struct flash_bank
*bank
, target_addr_t addr
,
381 uint32_t count
, const uint8_t *buffer
)
383 struct target
*target
= bank
->target
;
389 wdata
= buffer
[0] | (buffer
[1] << 8);
391 return rpc_hf_xfer(target
, addr
, wdata
, NULL
, RPC_HF_SIZE_16BIT
,
395 static int rpchf_target_read_memory(struct flash_bank
*bank
, target_addr_t addr
,
396 uint32_t count
, uint8_t *buffer
)
398 struct target
*target
= bank
->target
;
402 for (i
= 0; i
< count
; i
++) {
403 ret
= rpc_hf_xfer(target
, addr
+ (2 * i
), 0, &rdata
,
404 RPC_HF_SIZE_16BIT
, false, NULL
, 0);
407 buffer
[(2 * i
) + 0] = rdata
& 0xff;
408 buffer
[(2 * i
) + 1] = (rdata
>> 8) & 0xff;
414 FLASH_BANK_COMMAND_HANDLER(rpchf_flash_bank_command
)
416 struct cfi_flash_bank
*cfi_info
;
419 ret
= cfi_flash_bank_cmd(bank
, CMD_ARGC
, CMD_ARGV
);
423 cfi_info
= bank
->driver_priv
;
424 cfi_info
->read_mem
= rpchf_target_read_memory
;
425 cfi_info
->write_mem
= rpchf_target_write_memory
;
430 static int rpchf_spansion_write_words(struct flash_bank
*bank
, const uint8_t *word
,
431 uint32_t wordcount
, uint32_t address
)
434 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
435 struct cfi_spansion_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
437 /* Calculate buffer size and boundary mask
438 * buffersize is (buffer size per chip) * (number of chips)
439 * bufferwsize is buffersize in words */
440 uint32_t buffersize
= RPC_WBUF_SIZE
;
441 uint32_t buffermask
= buffersize
- 1;
442 uint32_t bufferwsize
= buffersize
/ 2;
444 /* Check for valid range */
445 if (address
& buffermask
) {
446 LOG_ERROR("Write address at base " TARGET_ADDR_FMT
447 ", address 0x%" PRIx32
" not aligned to 2^%d boundary",
448 bank
->base
, address
, cfi_info
->max_buf_write_size
);
449 return ERROR_FLASH_OPERATION_FAILED
;
452 /* Check for valid size */
453 if (wordcount
> bufferwsize
) {
454 LOG_ERROR("Number of data words %" PRId32
" exceeds available buffersize %"
455 PRId32
, wordcount
, buffersize
);
456 return ERROR_FLASH_OPERATION_FAILED
;
460 retval
= cfi_spansion_unlock_seq(bank
);
461 if (retval
!= ERROR_OK
)
464 retval
= cfi_send_command(bank
, 0xa0, cfi_flash_address(bank
, 0, pri_ext
->_unlock1
));
465 if (retval
!= ERROR_OK
)
468 retval
= rpc_hf_xfer(bank
->target
, address
, 0, NULL
, RPC_HF_SIZE_64BIT
, true, word
, wordcount
* 2);
469 if (retval
!= ERROR_OK
)
472 if (cfi_spansion_wait_status_busy(bank
, cfi_info
->word_write_timeout
) != ERROR_OK
) {
473 retval
= cfi_send_command(bank
, 0xf0, cfi_flash_address(bank
, 0, 0x0));
474 if (retval
!= ERROR_OK
)
477 LOG_ERROR("couldn't write block at base " TARGET_ADDR_FMT
478 ", address 0x%" PRIx32
", size 0x%" PRIx32
, bank
->base
, address
,
480 return ERROR_FLASH_OPERATION_FAILED
;
486 static int rpchf_write_words(struct flash_bank
*bank
, const uint8_t *word
,
487 uint32_t wordcount
, uint32_t address
)
489 return rpchf_spansion_write_words(bank
, word
, wordcount
, address
);
492 static int rpchf_write(struct flash_bank
*bank
, const uint8_t *buffer
, uint32_t offset
, uint32_t count
)
494 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
495 uint32_t address
= bank
->base
+ offset
; /* address of first byte to be programmed */
497 int align
; /* number of unaligned bytes */
498 uint8_t current_word
[CFI_MAX_BUS_WIDTH
* 4]; /* word (bus_width size) currently being
502 if (bank
->target
->state
!= TARGET_HALTED
) {
503 LOG_ERROR("Target not halted");
504 return ERROR_TARGET_NOT_HALTED
;
507 if (offset
+ count
> bank
->size
)
508 return ERROR_FLASH_DST_OUT_OF_BANK
;
510 if (cfi_info
->qry
[0] != 'Q')
511 return ERROR_FLASH_BANK_NOT_PROBED
;
513 /* start at the first byte of the first word (bus_width size) */
514 write_p
= address
& ~(bank
->bus_width
- 1);
515 align
= address
- write_p
;
517 LOG_INFO("Fixup %d unaligned head bytes", align
);
519 /* read a complete word from flash */
520 retval
= cfi_target_read_memory(bank
, write_p
, 1, current_word
);
521 if (retval
!= ERROR_OK
)
524 /* replace only bytes that must be written */
525 for (unsigned int i
= align
; (i
< bank
->bus_width
) && (count
> 0); i
++, count
--) {
526 if (cfi_info
->data_swap
)
527 /* data bytes are swapped (reverse endianness) */
528 current_word
[bank
->bus_width
- i
] = *buffer
++;
530 current_word
[i
] = *buffer
++;
533 retval
= cfi_write_word(bank
, current_word
, write_p
);
534 if (retval
!= ERROR_OK
)
536 write_p
+= bank
->bus_width
;
539 /* Calculate buffer size and boundary mask
540 * buffersize is (buffer size per chip) * (number of chips)
541 * bufferwsize is buffersize in words */
542 uint32_t buffersize
= RPC_WBUF_SIZE
;
543 uint32_t buffermask
= buffersize
-1;
544 uint32_t bufferwsize
= buffersize
/ bank
->bus_width
;
546 /* fall back to memory writes */
547 while (count
>= (uint32_t)bank
->bus_width
) {
549 if ((write_p
& 0xff) == 0) {
550 LOG_INFO("Programming at 0x%08" PRIx32
", count 0x%08"
551 PRIx32
" bytes remaining", write_p
, count
);
554 if ((bufferwsize
> 0) && (count
>= buffersize
) &&
555 !(write_p
& buffermask
)) {
556 retval
= rpchf_write_words(bank
, buffer
, bufferwsize
, write_p
);
557 if (retval
== ERROR_OK
) {
558 buffer
+= buffersize
;
559 write_p
+= buffersize
;
562 } else if (retval
!= ERROR_FLASH_OPER_UNSUPPORTED
)
565 /* try the slow way? */
567 for (unsigned int i
= 0; i
< bank
->bus_width
; i
++)
568 current_word
[i
] = *buffer
++;
570 retval
= cfi_write_word(bank
, current_word
, write_p
);
571 if (retval
!= ERROR_OK
)
574 write_p
+= bank
->bus_width
;
575 count
-= bank
->bus_width
;
579 /* return to read array mode, so we can read from flash again for padding */
580 retval
= cfi_reset(bank
);
581 if (retval
!= ERROR_OK
)
584 /* handle unaligned tail bytes */
586 LOG_INFO("Fixup %" PRId32
" unaligned tail bytes", count
);
588 /* read a complete word from flash */
589 retval
= cfi_target_read_memory(bank
, write_p
, 1, current_word
);
590 if (retval
!= ERROR_OK
)
593 /* replace only bytes that must be written */
594 for (unsigned int i
= 0; (i
< bank
->bus_width
) && (count
> 0); i
++, count
--)
595 if (cfi_info
->data_swap
)
596 /* data bytes are swapped (reverse endianness) */
597 current_word
[bank
->bus_width
- i
] = *buffer
++;
599 current_word
[i
] = *buffer
++;
601 retval
= cfi_write_word(bank
, current_word
, write_p
);
602 if (retval
!= ERROR_OK
)
606 /* return to read array mode */
607 return cfi_reset(bank
);
610 static int rpchf_read(struct flash_bank
*bank
, uint8_t *buffer
, uint32_t offset
, uint32_t count
)
612 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
613 struct target
*target
= bank
->target
;
615 LOG_DEBUG("reading buffer of %" PRIi32
" byte at 0x%8.8" PRIx32
,
618 if (bank
->target
->state
!= TARGET_HALTED
) {
619 LOG_ERROR("Target not halted");
620 return ERROR_TARGET_NOT_HALTED
;
623 if (offset
+ count
> bank
->size
)
624 return ERROR_FLASH_DST_OUT_OF_BANK
;
626 if (cfi_info
->qry
[0] != 'Q')
627 return ERROR_FLASH_BANK_NOT_PROBED
;
629 return target_read_memory(target
, offset
| mem_base
,
630 4, count
/ 4, buffer
);
633 const struct flash_driver renesas_rpchf_flash
= {
635 .flash_bank_command
= rpchf_flash_bank_command
,
637 .protect
= cfi_protect
,
638 .write
= rpchf_write
,
641 .auto_probe
= cfi_auto_probe
,
642 .erase_check
= default_flash_blank_check
,
643 .protect_check
= cfi_protect_check
,
644 .info
= cfi_get_info
,
645 .free_driver_priv
= default_flash_free_driver_priv
,
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