1 // SPDX-License-Identifier: GPL-2.0-only
4 * SH QSPI (Quad SPI) driver
5 * Copyright (C) 2019 Marek Vasut <marek.vasut@gmail.com>
7 * Based on U-Boot SH QSPI driver
8 * Copyright (C) 2013 Renesas Electronics Corporation
9 * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
18 #include <helper/binarybuffer.h>
19 #include <helper/bits.h>
20 #include <helper/time_support.h>
21 #include <helper/types.h>
22 #include <jtag/jtag.h>
23 #include <target/algorithm.h>
24 #include <target/arm.h>
25 #include <target/arm_opcodes.h>
26 #include <target/target.h>
28 /* SH QSPI register bit masks <REG>_<BIT> */
29 #define SPCR_MSTR 0x08
31 #define SPSR_SPRFF 0x80
32 #define SPSR_SPTEF 0x20
33 #define SPPCR_IO3FV 0x04
34 #define SPPCR_IO2FV 0x02
35 #define SPPCR_IO1FV 0x01
36 #define SPBDCR_RXBC0 BIT(0)
37 #define SPCMD_SCKDEN BIT(15)
38 #define SPCMD_SLNDEN BIT(14)
39 #define SPCMD_SPNDEN BIT(13)
40 #define SPCMD_SSLKP BIT(7)
41 #define SPCMD_BRDV0 BIT(2)
42 #define SPCMD_INIT1 (SPCMD_SCKDEN | SPCMD_SLNDEN | \
43 SPCMD_SPNDEN | SPCMD_SSLKP | \
45 #define SPCMD_INIT2 (SPCMD_SPNDEN | SPCMD_SSLKP | \
47 #define SPBFCR_TXRST BIT(7)
48 #define SPBFCR_RXRST BIT(6)
49 #define SPBFCR_TXTRG 0x30
50 #define SPBFCR_RXTRG 0x07
52 /* SH QSPI register set */
53 #define SH_QSPI_SPCR 0x00
54 #define SH_QSPI_SSLP 0x01
55 #define SH_QSPI_SPPCR 0x02
56 #define SH_QSPI_SPSR 0x03
57 #define SH_QSPI_SPDR 0x04
58 #define SH_QSPI_SPSCR 0x08
59 #define SH_QSPI_SPSSR 0x09
60 #define SH_QSPI_SPBR 0x0a
61 #define SH_QSPI_SPDCR 0x0b
62 #define SH_QSPI_SPCKD 0x0c
63 #define SH_QSPI_SSLND 0x0d
64 #define SH_QSPI_SPND 0x0e
65 #define SH_QSPI_DUMMY0 0x0f
66 #define SH_QSPI_SPCMD0 0x10
67 #define SH_QSPI_SPCMD1 0x12
68 #define SH_QSPI_SPCMD2 0x14
69 #define SH_QSPI_SPCMD3 0x16
70 #define SH_QSPI_SPBFCR 0x18
71 #define SH_QSPI_DUMMY1 0x19
72 #define SH_QSPI_SPBDCR 0x1a
73 #define SH_QSPI_SPBMUL0 0x1c
74 #define SH_QSPI_SPBMUL1 0x20
75 #define SH_QSPI_SPBMUL2 0x24
76 #define SH_QSPI_SPBMUL3 0x28
78 struct sh_qspi_flash_bank
{
79 const struct flash_device
*dev
;
82 struct working_area
*io_algorithm
;
83 struct working_area
*source
;
84 unsigned int buffer_size
;
87 struct sh_qspi_target
{
93 static const struct sh_qspi_target target_devices
[] = {
94 /* name, tap_idcode, io_base */
95 { "SH QSPI", 0x4ba00477, 0xe6b10000 },
99 static int sh_qspi_init(struct flash_bank
*bank
)
101 struct target
*target
= bank
->target
;
102 struct sh_qspi_flash_bank
*info
= bank
->driver_priv
;
106 /* QSPI initialize */
107 /* Set master mode only */
108 ret
= target_write_u8(target
, info
->io_base
+ SH_QSPI_SPCR
, SPCR_MSTR
);
112 /* Set SSL signal level */
113 ret
= target_write_u8(target
, info
->io_base
+ SH_QSPI_SSLP
, 0x00);
117 /* Set MOSI signal value when transfer is in idle state */
118 ret
= target_write_u8(target
, info
->io_base
+ SH_QSPI_SPPCR
,
119 SPPCR_IO3FV
| SPPCR_IO2FV
);
123 /* Set bit rate. See 58.3.8 Quad Serial Peripheral Interface */
124 ret
= target_write_u8(target
, info
->io_base
+ SH_QSPI_SPBR
, 0x01);
128 /* Disable Dummy Data Transmission */
129 ret
= target_write_u8(target
, info
->io_base
+ SH_QSPI_SPDCR
, 0x00);
133 /* Set clock delay value */
134 ret
= target_write_u8(target
, info
->io_base
+ SH_QSPI_SPCKD
, 0x00);
138 /* Set SSL negation delay value */
139 ret
= target_write_u8(target
, info
->io_base
+ SH_QSPI_SSLND
, 0x00);
143 /* Set next-access delay value */
144 ret
= target_write_u8(target
, info
->io_base
+ SH_QSPI_SPND
, 0x00);
148 /* Set equence command */
149 ret
= target_write_u16(target
, info
->io_base
+ SH_QSPI_SPCMD0
,
154 /* Reset transfer and receive Buffer */
155 ret
= target_read_u8(target
, info
->io_base
+ SH_QSPI_SPBFCR
, &val
);
159 val
|= SPBFCR_TXRST
| SPBFCR_RXRST
;
161 ret
= target_write_u8(target
, info
->io_base
+ SH_QSPI_SPBFCR
, val
);
165 /* Clear transfer and receive Buffer control bit */
166 ret
= target_read_u8(target
, info
->io_base
+ SH_QSPI_SPBFCR
, &val
);
170 val
&= ~(SPBFCR_TXRST
| SPBFCR_RXRST
);
172 ret
= target_write_u8(target
, info
->io_base
+ SH_QSPI_SPBFCR
, val
);
176 /* Set equence control method. Use equence0 only */
177 ret
= target_write_u8(target
, info
->io_base
+ SH_QSPI_SPSCR
, 0x00);
181 /* Enable SPI function */
182 ret
= target_read_u8(target
, info
->io_base
+ SH_QSPI_SPCR
, &val
);
188 return target_write_u8(target
, info
->io_base
+ SH_QSPI_SPCR
, val
);
191 static int sh_qspi_cs_activate(struct flash_bank
*bank
)
193 struct target
*target
= bank
->target
;
194 struct sh_qspi_flash_bank
*info
= bank
->driver_priv
;
198 /* Set master mode only */
199 ret
= target_write_u8(target
, info
->io_base
+ SH_QSPI_SPCR
, SPCR_MSTR
);
204 ret
= target_write_u16(target
, info
->io_base
+ SH_QSPI_SPCMD0
,
209 /* Reset transfer and receive Buffer */
210 ret
= target_read_u8(target
, info
->io_base
+ SH_QSPI_SPBFCR
, &val
);
214 val
|= SPBFCR_TXRST
| SPBFCR_RXRST
;
216 ret
= target_write_u8(target
, info
->io_base
+ SH_QSPI_SPBFCR
, val
);
220 /* Clear transfer and receive Buffer control bit */
221 ret
= target_read_u8(target
, info
->io_base
+ SH_QSPI_SPBFCR
, &val
);
225 val
&= ~(SPBFCR_TXRST
| SPBFCR_RXRST
);
227 ret
= target_write_u8(target
, info
->io_base
+ SH_QSPI_SPBFCR
, val
);
231 /* Set equence control method. Use equence0 only */
232 ret
= target_write_u8(target
, info
->io_base
+ SH_QSPI_SPSCR
, 0x00);
236 /* Enable SPI function */
237 ret
= target_read_u8(target
, info
->io_base
+ SH_QSPI_SPCR
, &val
);
243 return target_write_u8(target
, info
->io_base
+ SH_QSPI_SPCR
, val
);
246 static int sh_qspi_cs_deactivate(struct flash_bank
*bank
)
248 struct target
*target
= bank
->target
;
249 struct sh_qspi_flash_bank
*info
= bank
->driver_priv
;
253 /* Disable SPI Function */
254 ret
= target_read_u8(target
, info
->io_base
+ SH_QSPI_SPCR
, &val
);
260 return target_write_u8(target
, info
->io_base
+ SH_QSPI_SPCR
, val
);
263 static int sh_qspi_wait_for_bit(struct flash_bank
*bank
, uint8_t reg
,
264 uint32_t mask
, bool set
,
265 unsigned long timeout
)
267 struct target
*target
= bank
->target
;
268 struct sh_qspi_flash_bank
*info
= bank
->driver_priv
;
273 endtime
= timeval_ms() + timeout
;
275 ret
= target_read_u8(target
, info
->io_base
+ reg
, &val
);
282 if ((val
& mask
) == mask
)
286 } while (timeval_ms() < endtime
);
288 LOG_ERROR("timeout");
289 return ERROR_TIMEOUT_REACHED
;
292 static int sh_qspi_xfer_common(struct flash_bank
*bank
,
293 const uint8_t *dout
, unsigned int outlen
,
294 uint8_t *din
, unsigned int inlen
,
295 bool xfer_start
, bool xfer_end
)
297 struct target
*target
= bank
->target
;
298 struct sh_qspi_flash_bank
*info
= bank
->driver_priv
;
299 uint8_t tdata
, rdata
;
301 unsigned int nbyte
= outlen
+ inlen
;
305 ret
= sh_qspi_cs_activate(bank
);
309 ret
= target_write_u32(target
, info
->io_base
+ SH_QSPI_SPBMUL0
,
314 ret
= target_read_u8(target
, info
->io_base
+ SH_QSPI_SPBFCR
,
319 val
&= ~(SPBFCR_TXTRG
| SPBFCR_RXTRG
);
321 ret
= target_write_u8(target
, info
->io_base
+ SH_QSPI_SPBFCR
,
328 ret
= sh_qspi_wait_for_bit(bank
, SH_QSPI_SPSR
, SPSR_SPTEF
,
333 tdata
= outlen
? *dout
++ : 0;
334 ret
= target_write_u8(target
, info
->io_base
+ SH_QSPI_SPDR
,
339 ret
= sh_qspi_wait_for_bit(bank
, SH_QSPI_SPSR
, SPSR_SPRFF
,
344 ret
= target_read_u8(target
, info
->io_base
+ SH_QSPI_SPDR
,
348 if (!outlen
&& inlen
) {
360 return sh_qspi_cs_deactivate(bank
);
365 /* Send "write enable" command to SPI flash chip. */
366 static int sh_qspi_write_enable(struct flash_bank
*bank
)
368 uint8_t dout
= SPIFLASH_WRITE_ENABLE
;
370 return sh_qspi_xfer_common(bank
, &dout
, 1, NULL
, 0, 1, 1);
373 /* Read the status register of the external SPI flash chip. */
374 static int read_status_reg(struct flash_bank
*bank
, uint32_t *status
)
376 uint8_t dout
= SPIFLASH_READ_STATUS
;
380 ret
= sh_qspi_xfer_common(bank
, &dout
, 1, &din
, 1, 1, 1);
384 *status
= din
& 0xff;
389 /* check for WIP (write in progress) bit in status register */
391 static int wait_till_ready(struct flash_bank
*bank
, int timeout
)
397 endtime
= timeval_ms() + timeout
;
399 /* read flash status register */
400 ret
= read_status_reg(bank
, &status
);
404 if ((status
& SPIFLASH_BSY_BIT
) == 0)
407 } while (timeval_ms() < endtime
);
409 LOG_ERROR("timeout");
410 return ERROR_TIMEOUT_REACHED
;
413 static int sh_qspi_erase_sector(struct flash_bank
*bank
, int sector
)
415 struct sh_qspi_flash_bank
*info
= bank
->driver_priv
;
416 bool addr4b
= info
->dev
->size_in_bytes
> (1UL << 24);
417 uint32_t address
= (sector
* info
->dev
->sectorsize
) <<
420 info
->dev
->erase_cmd
,
421 (address
>> 24) & 0xff, (address
>> 16) & 0xff,
422 (address
>> 8) & 0xff, (address
>> 0) & 0xff
424 unsigned int doutlen
= addr4b
? 5 : 4;
428 ret
= sh_qspi_write_enable(bank
);
433 ret
= sh_qspi_xfer_common(bank
, dout
, doutlen
, NULL
, 0, 1, 1);
437 /* Poll status register */
438 return wait_till_ready(bank
, 3000);
441 static int sh_qspi_erase(struct flash_bank
*bank
, unsigned int first
,
444 struct target
*target
= bank
->target
;
445 struct sh_qspi_flash_bank
*info
= bank
->driver_priv
;
446 int retval
= ERROR_OK
;
448 LOG_DEBUG("%s: from sector %u to sector %u", __func__
, first
, last
);
450 if (target
->state
!= TARGET_HALTED
) {
451 LOG_ERROR("Target not halted");
452 return ERROR_TARGET_NOT_HALTED
;
455 if ((last
< first
) || (last
>= bank
->num_sectors
)) {
456 LOG_ERROR("Flash sector invalid");
457 return ERROR_FLASH_SECTOR_INVALID
;
461 LOG_ERROR("Flash bank not probed");
462 return ERROR_FLASH_BANK_NOT_PROBED
;
465 if (info
->dev
->erase_cmd
== 0x00)
466 return ERROR_FLASH_OPER_UNSUPPORTED
;
468 for (unsigned int sector
= first
; sector
<= last
; sector
++) {
469 if (bank
->sectors
[sector
].is_protected
) {
470 LOG_ERROR("Flash sector %u protected", sector
);
475 for (unsigned int sector
= first
; sector
<= last
; sector
++) {
476 retval
= sh_qspi_erase_sector(bank
, sector
);
477 if (retval
!= ERROR_OK
)
485 static int sh_qspi_write(struct flash_bank
*bank
, const uint8_t *buffer
,
486 uint32_t offset
, uint32_t count
)
488 struct target
*target
= bank
->target
;
489 struct sh_qspi_flash_bank
*info
= bank
->driver_priv
;
490 struct reg_param reg_params
[4];
491 struct arm_algorithm arm_algo
;
492 uint32_t io_base
= (uint32_t)(info
->io_base
);
493 uint32_t src_base
= (uint32_t)(info
->source
->address
);
495 bool addr4b
= !!(info
->dev
->size_in_bytes
> (1UL << 24));
498 LOG_DEBUG("%s: offset=0x%08" PRIx32
" count=0x%08" PRIx32
,
499 __func__
, offset
, count
);
501 if (target
->state
!= TARGET_HALTED
) {
502 LOG_ERROR("Target not halted");
503 return ERROR_TARGET_NOT_HALTED
;
506 if (offset
+ count
> bank
->size
) {
507 LOG_WARNING("Write pasts end of flash. Extra data discarded.");
508 count
= bank
->size
- offset
;
512 LOG_ERROR("sh_qspi_write_page: unaligned write address: %08" PRIx32
,
517 /* Check sector protection */
518 for (unsigned int sector
= 0; sector
< bank
->num_sectors
; sector
++) {
519 /* Start offset in or before this sector? */
520 /* End offset in or behind this sector? */
521 struct flash_sector
*bs
= &bank
->sectors
[sector
];
523 if ((offset
< (bs
->offset
+ bs
->size
)) &&
524 ((offset
+ count
- 1) >= bs
->offset
) &&
526 LOG_ERROR("Flash sector %u protected", sector
);
531 LOG_DEBUG("%s: offset=0x%08" PRIx32
" count=0x%08" PRIx32
,
532 __func__
, offset
, count
);
534 if (target
->state
!= TARGET_HALTED
) {
535 LOG_ERROR("Target not halted");
536 return ERROR_TARGET_NOT_HALTED
;
539 if (offset
+ count
> bank
->size
) {
540 LOG_WARNING("Reads past end of flash. Extra data discarded.");
541 count
= bank
->size
- offset
;
544 arm_algo
.common_magic
= ARM_COMMON_MAGIC
;
545 arm_algo
.core_mode
= ARM_MODE_SVC
;
546 arm_algo
.core_state
= ARM_STATE_ARM
;
548 init_reg_param(®_params
[0], "r0", 32, PARAM_OUT
);
549 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
550 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
);
551 init_reg_param(®_params
[3], "r3", 32, PARAM_OUT
);
554 chunk
= (count
> info
->buffer_size
) ?
555 info
->buffer_size
: count
;
557 target_write_buffer(target
, info
->source
->address
,
560 buf_set_u32(reg_params
[0].value
, 0, 32, io_base
);
561 buf_set_u32(reg_params
[1].value
, 0, 32, src_base
);
562 buf_set_u32(reg_params
[2].value
, 0, 32,
563 (1 << 31) | (addr4b
<< 30) |
564 (info
->dev
->pprog_cmd
<< 20) | chunk
);
565 buf_set_u32(reg_params
[3].value
, 0, 32, offset
);
567 ret
= target_run_algorithm(target
, 0, NULL
, 4, reg_params
,
568 info
->io_algorithm
->address
,
569 0, 10000, &arm_algo
);
570 if (ret
!= ERROR_OK
) {
571 LOG_ERROR("error executing SH QSPI flash IO algorithm");
572 ret
= ERROR_FLASH_OPERATION_FAILED
;
581 destroy_reg_param(®_params
[0]);
582 destroy_reg_param(®_params
[1]);
583 destroy_reg_param(®_params
[2]);
584 destroy_reg_param(®_params
[3]);
589 static int sh_qspi_read(struct flash_bank
*bank
, uint8_t *buffer
,
590 uint32_t offset
, uint32_t count
)
592 struct target
*target
= bank
->target
;
593 struct sh_qspi_flash_bank
*info
= bank
->driver_priv
;
594 struct reg_param reg_params
[4];
595 struct arm_algorithm arm_algo
;
596 uint32_t io_base
= (uint32_t)(info
->io_base
);
597 uint32_t src_base
= (uint32_t)(info
->source
->address
);
599 bool addr4b
= !!(info
->dev
->size_in_bytes
> (1UL << 24));
602 LOG_DEBUG("%s: offset=0x%08" PRIx32
" count=0x%08" PRIx32
,
603 __func__
, offset
, count
);
605 if (target
->state
!= TARGET_HALTED
) {
606 LOG_ERROR("Target not halted");
607 return ERROR_TARGET_NOT_HALTED
;
610 if (offset
+ count
> bank
->size
) {
611 LOG_WARNING("Reads past end of flash. Extra data discarded.");
612 count
= bank
->size
- offset
;
615 arm_algo
.common_magic
= ARM_COMMON_MAGIC
;
616 arm_algo
.core_mode
= ARM_MODE_SVC
;
617 arm_algo
.core_state
= ARM_STATE_ARM
;
619 init_reg_param(®_params
[0], "r0", 32, PARAM_OUT
);
620 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
621 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
);
622 init_reg_param(®_params
[3], "r3", 32, PARAM_OUT
);
625 chunk
= (count
> info
->buffer_size
) ?
626 info
->buffer_size
: count
;
628 buf_set_u32(reg_params
[0].value
, 0, 32, io_base
);
629 buf_set_u32(reg_params
[1].value
, 0, 32, src_base
);
630 buf_set_u32(reg_params
[2].value
, 0, 32,
631 (addr4b
<< 30) | (info
->dev
->read_cmd
<< 20) |
633 buf_set_u32(reg_params
[3].value
, 0, 32, offset
);
635 ret
= target_run_algorithm(target
, 0, NULL
, 4, reg_params
,
636 info
->io_algorithm
->address
,
637 0, 10000, &arm_algo
);
638 if (ret
!= ERROR_OK
) {
639 LOG_ERROR("error executing SH QSPI flash IO algorithm");
640 ret
= ERROR_FLASH_OPERATION_FAILED
;
644 target_read_buffer(target
, info
->source
->address
,
652 destroy_reg_param(®_params
[0]);
653 destroy_reg_param(®_params
[1]);
654 destroy_reg_param(®_params
[2]);
655 destroy_reg_param(®_params
[3]);
660 /* Return ID of flash device */
661 static int read_flash_id(struct flash_bank
*bank
, uint32_t *id
)
663 struct target
*target
= bank
->target
;
664 uint8_t dout
= SPIFLASH_READ_ID
;
665 uint8_t din
[3] = { 0, 0, 0 };
668 if (target
->state
!= TARGET_HALTED
) {
669 LOG_ERROR("Target not halted");
670 return ERROR_TARGET_NOT_HALTED
;
673 ret
= sh_qspi_xfer_common(bank
, &dout
, 1, din
, 3, 1, 1);
677 *id
= (din
[0] << 0) | (din
[1] << 8) | (din
[2] << 16);
679 if (*id
== 0xffffff) {
680 LOG_ERROR("No SPI flash found");
687 static int sh_qspi_protect(struct flash_bank
*bank
, int set
,
688 unsigned int first
, unsigned int last
)
690 for (unsigned int sector
= first
; sector
<= last
; sector
++)
691 bank
->sectors
[sector
].is_protected
= set
;
696 static int sh_qspi_upload_helper(struct flash_bank
*bank
)
698 struct target
*target
= bank
->target
;
699 struct sh_qspi_flash_bank
*info
= bank
->driver_priv
;
701 /* see contrib/loaders/flash/sh_qspi.s for src */
702 static const uint8_t sh_qspi_io_code
[] = {
703 #include "../../../contrib/loaders/flash/sh_qspi/sh_qspi.inc"
707 target_free_working_area(target
, info
->source
);
708 target_free_working_area(target
, info
->io_algorithm
);
710 /* FIXME: Working areas are allocated during flash probe
711 * and eventual target_free_all_working_areas() called in case
712 * of target reset or run is not handled at all.
713 * Not a big problem if area backp is off.
715 /* flash write code */
716 if (target_alloc_working_area(target
, sizeof(sh_qspi_io_code
),
717 &info
->io_algorithm
) != ERROR_OK
) {
718 LOG_WARNING("no working area available, can't do block memory writes");
719 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
722 target_write_buffer(target
, info
->io_algorithm
->address
,
723 sizeof(sh_qspi_io_code
), sh_qspi_io_code
);
726 * Try to allocate as big work area buffer as possible, start
727 * with 32 kiB and count down. If there is less than 256 Bytes
728 * of work area available, abort.
730 info
->buffer_size
= 32768;
732 ret
= target_alloc_working_area_try(target
, info
->buffer_size
,
737 info
->buffer_size
/= 2;
738 if (info
->buffer_size
<= 256) {
739 target_free_working_area(target
, info
->io_algorithm
);
741 LOG_WARNING("no large enough working area available, can't do block memory writes");
742 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
749 static int sh_qspi_probe(struct flash_bank
*bank
)
751 struct target
*target
= bank
->target
;
752 struct sh_qspi_flash_bank
*info
= bank
->driver_priv
;
753 struct flash_sector
*sectors
;
754 uint32_t id
= 0; /* silence uninitialized warning */
756 const struct sh_qspi_target
*target_device
;
762 info
->probed
= false;
764 for (target_device
= target_devices
; target_device
->name
;
766 if (target_device
->tap_idcode
== target
->tap
->idcode
)
768 if (!target_device
->name
) {
769 LOG_ERROR("Device ID 0x%" PRIx32
" is not known",
770 target
->tap
->idcode
);
774 info
->io_base
= target_device
->io_base
;
776 LOG_DEBUG("Found device %s at address " TARGET_ADDR_FMT
,
777 target_device
->name
, bank
->base
);
779 ret
= sh_qspi_upload_helper(bank
);
783 ret
= sh_qspi_init(bank
);
787 ret
= read_flash_id(bank
, &id
);
792 for (const struct flash_device
*p
= flash_devices
; p
->name
; p
++)
793 if (p
->device_id
== id
) {
799 LOG_ERROR("Unknown flash device (ID 0x%08" PRIx32
")", id
);
803 LOG_INFO("Found flash device \'%s\' (ID 0x%08" PRIx32
")",
804 info
->dev
->name
, info
->dev
->device_id
);
806 /* Set correct size value */
807 bank
->size
= info
->dev
->size_in_bytes
;
808 if (bank
->size
<= (1UL << 16))
809 LOG_WARNING("device needs 2-byte addresses - not implemented");
811 /* if no sectors, treat whole bank as single sector */
812 sectorsize
= info
->dev
->sectorsize
?
813 info
->dev
->sectorsize
:
814 info
->dev
->size_in_bytes
;
816 /* create and fill sectors array */
817 bank
->num_sectors
= info
->dev
->size_in_bytes
/ sectorsize
;
818 sectors
= calloc(1, sizeof(*sectors
) * bank
->num_sectors
);
820 LOG_ERROR("not enough memory");
824 for (unsigned int sector
= 0; sector
< bank
->num_sectors
; sector
++) {
825 sectors
[sector
].offset
= sector
* sectorsize
;
826 sectors
[sector
].size
= sectorsize
;
827 sectors
[sector
].is_erased
= 0;
828 sectors
[sector
].is_protected
= 0;
831 bank
->sectors
= sectors
;
836 static int sh_qspi_auto_probe(struct flash_bank
*bank
)
838 struct sh_qspi_flash_bank
*info
= bank
->driver_priv
;
843 return sh_qspi_probe(bank
);
846 static int sh_qspi_flash_blank_check(struct flash_bank
*bank
)
848 /* Not implemented */
852 static int sh_qspi_protect_check(struct flash_bank
*bank
)
854 /* Not implemented */
858 static int sh_qspi_get_info(struct flash_bank
*bank
, struct command_invocation
*cmd
)
860 struct sh_qspi_flash_bank
*info
= bank
->driver_priv
;
863 command_print_sameline(cmd
, "\nSH QSPI flash bank not probed yet\n");
867 command_print_sameline(cmd
, "\nSH QSPI flash information:\n"
868 " Device \'%s\' (ID 0x%08" PRIx32
")\n",
869 info
->dev
->name
, info
->dev
->device_id
);
874 FLASH_BANK_COMMAND_HANDLER(sh_qspi_flash_bank_command
)
876 struct sh_qspi_flash_bank
*info
;
878 LOG_DEBUG("%s", __func__
);
880 if (CMD_ARGC
< 6 || CMD_ARGC
> 7)
881 return ERROR_COMMAND_SYNTAX_ERROR
;
883 if ((CMD_ARGC
== 7) && strcmp(CMD_ARGV
[6], "cs0")) {
884 LOG_ERROR("Unknown arg: %s", CMD_ARGV
[6]);
885 return ERROR_COMMAND_SYNTAX_ERROR
;
888 info
= calloc(1, sizeof(struct sh_qspi_flash_bank
));
890 LOG_ERROR("not enough memory");
894 bank
->driver_priv
= info
;
899 const struct flash_driver sh_qspi_flash
= {
901 .flash_bank_command
= sh_qspi_flash_bank_command
,
902 .erase
= sh_qspi_erase
,
903 .protect
= sh_qspi_protect
,
904 .write
= sh_qspi_write
,
905 .read
= sh_qspi_read
,
906 .probe
= sh_qspi_probe
,
907 .auto_probe
= sh_qspi_auto_probe
,
908 .erase_check
= sh_qspi_flash_blank_check
,
909 .protect_check
= sh_qspi_protect_check
,
910 .info
= sh_qspi_get_info
,
911 .free_driver_priv
= default_flash_free_driver_priv
,
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