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openocd: src: fix incorrect SPDX tags
[openocd.git] / src / flash / nor / stm32f1x.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2011 by Andreas Fritiofson *
9 * andreas.fritiofson@gmail.com *
10 *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 ***************************************************************************/
24
25 #ifdef HAVE_CONFIG_H
26 #include "config.h"
27 #endif
28
29 #include <string.h>
30
31 #include "imp.h"
32 #include <helper/binarybuffer.h>
33 #include <target/algorithm.h>
34 #include <target/cortex_m.h>
35
36 /* stm32x register locations */
37
38 #define FLASH_REG_BASE_B0 0x40022000
39 #define FLASH_REG_BASE_B1 0x40022040
40
41 #define STM32_FLASH_ACR 0x00
42 #define STM32_FLASH_KEYR 0x04
43 #define STM32_FLASH_OPTKEYR 0x08
44 #define STM32_FLASH_SR 0x0C
45 #define STM32_FLASH_CR 0x10
46 #define STM32_FLASH_AR 0x14
47 #define STM32_FLASH_OBR 0x1C
48 #define STM32_FLASH_WRPR 0x20
49
50 /* TODO: Check if code using these really should be hard coded to bank 0.
51 * There are valid cases, on dual flash devices the protection of the
52 * second bank is done on the bank0 reg's. */
53 #define STM32_FLASH_ACR_B0 0x40022000
54 #define STM32_FLASH_KEYR_B0 0x40022004
55 #define STM32_FLASH_OPTKEYR_B0 0x40022008
56 #define STM32_FLASH_SR_B0 0x4002200C
57 #define STM32_FLASH_CR_B0 0x40022010
58 #define STM32_FLASH_AR_B0 0x40022014
59 #define STM32_FLASH_OBR_B0 0x4002201C
60 #define STM32_FLASH_WRPR_B0 0x40022020
61
62 /* option byte location */
63
64 #define STM32_OB_RDP 0x1FFFF800
65 #define STM32_OB_USER 0x1FFFF802
66 #define STM32_OB_DATA0 0x1FFFF804
67 #define STM32_OB_DATA1 0x1FFFF806
68 #define STM32_OB_WRP0 0x1FFFF808
69 #define STM32_OB_WRP1 0x1FFFF80A
70 #define STM32_OB_WRP2 0x1FFFF80C
71 #define STM32_OB_WRP3 0x1FFFF80E
72
73 /* FLASH_CR register bits */
74
75 #define FLASH_PG (1 << 0)
76 #define FLASH_PER (1 << 1)
77 #define FLASH_MER (1 << 2)
78 #define FLASH_OPTPG (1 << 4)
79 #define FLASH_OPTER (1 << 5)
80 #define FLASH_STRT (1 << 6)
81 #define FLASH_LOCK (1 << 7)
82 #define FLASH_OPTWRE (1 << 9)
83 #define FLASH_OBL_LAUNCH (1 << 13) /* except stm32f1x series */
84
85 /* FLASH_SR register bits */
86
87 #define FLASH_BSY (1 << 0)
88 #define FLASH_PGERR (1 << 2)
89 #define FLASH_WRPRTERR (1 << 4)
90 #define FLASH_EOP (1 << 5)
91
92 /* STM32_FLASH_OBR bit definitions (reading) */
93
94 #define OPT_ERROR 0
95 #define OPT_READOUT 1
96 #define OPT_RDWDGSW 2
97 #define OPT_RDRSTSTOP 3
98 #define OPT_RDRSTSTDBY 4
99 #define OPT_BFB2 5 /* dual flash bank only */
100
101 /* register unlock keys */
102
103 #define KEY1 0x45670123
104 #define KEY2 0xCDEF89AB
105
106 /* timeout values */
107
108 #define FLASH_WRITE_TIMEOUT 10
109 #define FLASH_ERASE_TIMEOUT 100
110
111 struct stm32x_options {
112 uint8_t rdp;
113 uint8_t user;
114 uint16_t data;
115 uint32_t protection;
116 };
117
118 struct stm32x_flash_bank {
119 struct stm32x_options option_bytes;
120 int ppage_size;
121 bool probed;
122
123 bool has_dual_banks;
124 /* used to access dual flash bank stm32xl */
125 bool can_load_options;
126 uint32_t register_base;
127 uint8_t default_rdp;
128 int user_data_offset;
129 int option_offset;
130 uint32_t user_bank_size;
131 };
132
133 static int stm32x_mass_erase(struct flash_bank *bank);
134 static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
135 uint32_t address, uint32_t hwords_count);
136
137 /* flash bank stm32x <base> <size> 0 0 <target#>
138 */
139 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
140 {
141 struct stm32x_flash_bank *stm32x_info;
142
143 if (CMD_ARGC < 6)
144 return ERROR_COMMAND_SYNTAX_ERROR;
145
146 stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
147
148 bank->driver_priv = stm32x_info;
149 stm32x_info->probed = false;
150 stm32x_info->has_dual_banks = false;
151 stm32x_info->can_load_options = false;
152 stm32x_info->register_base = FLASH_REG_BASE_B0;
153 stm32x_info->user_bank_size = bank->size;
154
155 /* The flash write must be aligned to a halfword boundary */
156 bank->write_start_alignment = bank->write_end_alignment = 2;
157
158 return ERROR_OK;
159 }
160
161 static inline int stm32x_get_flash_reg(struct flash_bank *bank, uint32_t reg)
162 {
163 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
164 return reg + stm32x_info->register_base;
165 }
166
167 static inline int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
168 {
169 struct target *target = bank->target;
170 return target_read_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), status);
171 }
172
173 static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
174 {
175 struct target *target = bank->target;
176 uint32_t status;
177 int retval = ERROR_OK;
178
179 /* wait for busy to clear */
180 for (;;) {
181 retval = stm32x_get_flash_status(bank, &status);
182 if (retval != ERROR_OK)
183 return retval;
184 LOG_DEBUG("status: 0x%" PRIx32 "", status);
185 if ((status & FLASH_BSY) == 0)
186 break;
187 if (timeout-- <= 0) {
188 LOG_ERROR("timed out waiting for flash");
189 return ERROR_FLASH_BUSY;
190 }
191 alive_sleep(1);
192 }
193
194 if (status & FLASH_WRPRTERR) {
195 LOG_ERROR("stm32x device protected");
196 retval = ERROR_FLASH_PROTECTED;
197 }
198
199 if (status & FLASH_PGERR) {
200 LOG_ERROR("stm32x device programming failed / flash not erased");
201 retval = ERROR_FLASH_OPERATION_FAILED;
202 }
203
204 /* Clear but report errors */
205 if (status & (FLASH_WRPRTERR | FLASH_PGERR)) {
206 /* If this operation fails, we ignore it and report the original
207 * retval
208 */
209 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR),
210 FLASH_WRPRTERR | FLASH_PGERR);
211 }
212 return retval;
213 }
214
215 static int stm32x_check_operation_supported(struct flash_bank *bank)
216 {
217 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
218
219 /* if we have a dual flash bank device then
220 * we need to perform option byte stuff on bank0 only */
221 if (stm32x_info->register_base != FLASH_REG_BASE_B0) {
222 LOG_ERROR("Option byte operations must use bank 0");
223 return ERROR_FLASH_OPERATION_FAILED;
224 }
225
226 return ERROR_OK;
227 }
228
229 static int stm32x_read_options(struct flash_bank *bank)
230 {
231 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
232 struct target *target = bank->target;
233 uint32_t option_bytes;
234 int retval;
235
236 /* read user and read protection option bytes, user data option bytes */
237 retval = target_read_u32(target, STM32_FLASH_OBR_B0, &option_bytes);
238 if (retval != ERROR_OK)
239 return retval;
240
241 stm32x_info->option_bytes.rdp = (option_bytes & (1 << OPT_READOUT)) ? 0 : stm32x_info->default_rdp;
242 stm32x_info->option_bytes.user = (option_bytes >> stm32x_info->option_offset >> 2) & 0xff;
243 stm32x_info->option_bytes.data = (option_bytes >> stm32x_info->user_data_offset) & 0xffff;
244
245 /* read write protection option bytes */
246 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &stm32x_info->option_bytes.protection);
247 if (retval != ERROR_OK)
248 return retval;
249
250 return ERROR_OK;
251 }
252
253 static int stm32x_erase_options(struct flash_bank *bank)
254 {
255 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
256 struct target *target = bank->target;
257
258 /* read current options */
259 stm32x_read_options(bank);
260
261 /* unlock flash registers */
262 int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
263 if (retval != ERROR_OK)
264 return retval;
265 retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
266 if (retval != ERROR_OK)
267 goto flash_lock;
268
269 /* unlock option flash registers */
270 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
271 if (retval != ERROR_OK)
272 goto flash_lock;
273 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
274 if (retval != ERROR_OK)
275 goto flash_lock;
276
277 /* erase option bytes */
278 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_OPTWRE);
279 if (retval != ERROR_OK)
280 goto flash_lock;
281 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_STRT | FLASH_OPTWRE);
282 if (retval != ERROR_OK)
283 goto flash_lock;
284
285 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
286 if (retval != ERROR_OK)
287 goto flash_lock;
288
289 /* clear read protection option byte
290 * this will also force a device unlock if set */
291 stm32x_info->option_bytes.rdp = stm32x_info->default_rdp;
292
293 return ERROR_OK;
294
295 flash_lock:
296 target_write_u32(target, STM32_FLASH_CR_B0, FLASH_LOCK);
297 return retval;
298 }
299
300 static int stm32x_write_options(struct flash_bank *bank)
301 {
302 struct stm32x_flash_bank *stm32x_info = NULL;
303 struct target *target = bank->target;
304
305 stm32x_info = bank->driver_priv;
306
307 /* unlock flash registers */
308 int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
309 if (retval != ERROR_OK)
310 return retval;
311 retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
312 if (retval != ERROR_OK)
313 goto flash_lock;
314
315 /* unlock option flash registers */
316 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
317 if (retval != ERROR_OK)
318 goto flash_lock;
319 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
320 if (retval != ERROR_OK)
321 goto flash_lock;
322
323 /* program option bytes */
324 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTPG | FLASH_OPTWRE);
325 if (retval != ERROR_OK)
326 goto flash_lock;
327
328 uint8_t opt_bytes[16];
329
330 target_buffer_set_u16(target, opt_bytes, stm32x_info->option_bytes.rdp);
331 target_buffer_set_u16(target, opt_bytes + 2, stm32x_info->option_bytes.user);
332 target_buffer_set_u16(target, opt_bytes + 4, stm32x_info->option_bytes.data & 0xff);
333 target_buffer_set_u16(target, opt_bytes + 6, (stm32x_info->option_bytes.data >> 8) & 0xff);
334 target_buffer_set_u16(target, opt_bytes + 8, stm32x_info->option_bytes.protection & 0xff);
335 target_buffer_set_u16(target, opt_bytes + 10, (stm32x_info->option_bytes.protection >> 8) & 0xff);
336 target_buffer_set_u16(target, opt_bytes + 12, (stm32x_info->option_bytes.protection >> 16) & 0xff);
337 target_buffer_set_u16(target, opt_bytes + 14, (stm32x_info->option_bytes.protection >> 24) & 0xff);
338
339 /* Block write is preferred in favour of operation with ancient ST-Link
340 * firmwares without 16-bit memory access. See
341 * 480: flash: stm32f1x: write option bytes using the loader
342 * https://review.openocd.org/c/openocd/+/480
343 */
344 retval = stm32x_write_block(bank, opt_bytes, STM32_OB_RDP, sizeof(opt_bytes) / 2);
345
346 flash_lock:
347 {
348 int retval2 = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_LOCK);
349 if (retval == ERROR_OK)
350 retval = retval2;
351 }
352 return retval;
353 }
354
355 static int stm32x_protect_check(struct flash_bank *bank)
356 {
357 struct target *target = bank->target;
358 uint32_t protection;
359
360 int retval = stm32x_check_operation_supported(bank);
361 if (retval != ERROR_OK)
362 return retval;
363
364 /* medium density - each bit refers to a 4 sector protection block
365 * high density - each bit refers to a 2 sector protection block
366 * bit 31 refers to all remaining sectors in a bank */
367 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
368 if (retval != ERROR_OK)
369 return retval;
370
371 for (unsigned int i = 0; i < bank->num_prot_blocks; i++)
372 bank->prot_blocks[i].is_protected = (protection & (1 << i)) ? 0 : 1;
373
374 return ERROR_OK;
375 }
376
377 static int stm32x_erase(struct flash_bank *bank, unsigned int first,
378 unsigned int last)
379 {
380 struct target *target = bank->target;
381
382 if (bank->target->state != TARGET_HALTED) {
383 LOG_ERROR("Target not halted");
384 return ERROR_TARGET_NOT_HALTED;
385 }
386
387 if ((first == 0) && (last == (bank->num_sectors - 1)))
388 return stm32x_mass_erase(bank);
389
390 /* unlock flash registers */
391 int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
392 if (retval != ERROR_OK)
393 return retval;
394 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
395 if (retval != ERROR_OK)
396 goto flash_lock;
397
398 for (unsigned int i = first; i <= last; i++) {
399 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER);
400 if (retval != ERROR_OK)
401 goto flash_lock;
402 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_AR),
403 bank->base + bank->sectors[i].offset);
404 if (retval != ERROR_OK)
405 goto flash_lock;
406 retval = target_write_u32(target,
407 stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER | FLASH_STRT);
408 if (retval != ERROR_OK)
409 goto flash_lock;
410
411 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
412 if (retval != ERROR_OK)
413 goto flash_lock;
414 }
415
416 flash_lock:
417 {
418 int retval2 = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
419 if (retval == ERROR_OK)
420 retval = retval2;
421 }
422 return retval;
423 }
424
425 static int stm32x_protect(struct flash_bank *bank, int set, unsigned int first,
426 unsigned int last)
427 {
428 struct target *target = bank->target;
429 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
430
431 if (target->state != TARGET_HALTED) {
432 LOG_ERROR("Target not halted");
433 return ERROR_TARGET_NOT_HALTED;
434 }
435
436 int retval = stm32x_check_operation_supported(bank);
437 if (retval != ERROR_OK)
438 return retval;
439
440 retval = stm32x_erase_options(bank);
441 if (retval != ERROR_OK) {
442 LOG_ERROR("stm32x failed to erase options");
443 return retval;
444 }
445
446 for (unsigned int i = first; i <= last; i++) {
447 if (set)
448 stm32x_info->option_bytes.protection &= ~(1 << i);
449 else
450 stm32x_info->option_bytes.protection |= (1 << i);
451 }
452
453 return stm32x_write_options(bank);
454 }
455
456 static int stm32x_write_block_async(struct flash_bank *bank, const uint8_t *buffer,
457 uint32_t address, uint32_t hwords_count)
458 {
459 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
460 struct target *target = bank->target;
461 uint32_t buffer_size;
462 struct working_area *write_algorithm;
463 struct working_area *source;
464 struct armv7m_algorithm armv7m_info;
465 int retval;
466
467 static const uint8_t stm32x_flash_write_code[] = {
468 #include "../../../contrib/loaders/flash/stm32/stm32f1x.inc"
469 };
470
471 /* flash write code */
472 if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
473 &write_algorithm) != ERROR_OK) {
474 LOG_WARNING("no working area available, can't do block memory writes");
475 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
476 }
477
478 retval = target_write_buffer(target, write_algorithm->address,
479 sizeof(stm32x_flash_write_code), stm32x_flash_write_code);
480 if (retval != ERROR_OK) {
481 target_free_working_area(target, write_algorithm);
482 return retval;
483 }
484
485 /* memory buffer */
486 buffer_size = target_get_working_area_avail(target);
487 buffer_size = MIN(hwords_count * 2, MAX(buffer_size, 256));
488 /* Normally we allocate all available working area.
489 * MIN shrinks buffer_size if the size of the written block is smaller.
490 * MAX prevents using async algo if the available working area is smaller
491 * than 256, the following allocation fails with
492 * ERROR_TARGET_RESOURCE_NOT_AVAILABLE and slow flashing takes place.
493 */
494
495 retval = target_alloc_working_area(target, buffer_size, &source);
496 /* Allocated size is always 32-bit word aligned */
497 if (retval != ERROR_OK) {
498 target_free_working_area(target, write_algorithm);
499 LOG_WARNING("no large enough working area available, can't do block memory writes");
500 /* target_alloc_working_area() may return ERROR_FAIL if area backup fails:
501 * convert any error to ERROR_TARGET_RESOURCE_NOT_AVAILABLE
502 */
503 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
504 }
505
506 struct reg_param reg_params[5];
507
508 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* flash base (in), status (out) */
509 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* count (halfword-16bit) */
510 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT); /* buffer start */
511 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT); /* buffer end */
512 init_reg_param(&reg_params[4], "r4", 32, PARAM_IN_OUT); /* target address */
513
514 buf_set_u32(reg_params[0].value, 0, 32, stm32x_info->register_base);
515 buf_set_u32(reg_params[1].value, 0, 32, hwords_count);
516 buf_set_u32(reg_params[2].value, 0, 32, source->address);
517 buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
518 buf_set_u32(reg_params[4].value, 0, 32, address);
519
520 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
521 armv7m_info.core_mode = ARM_MODE_THREAD;
522
523 retval = target_run_flash_async_algorithm(target, buffer, hwords_count, 2,
524 0, NULL,
525 ARRAY_SIZE(reg_params), reg_params,
526 source->address, source->size,
527 write_algorithm->address, 0,
528 &armv7m_info);
529
530 if (retval == ERROR_FLASH_OPERATION_FAILED) {
531 /* Actually we just need to check for programming errors
532 * stm32x_wait_status_busy also reports error and clears status bits.
533 *
534 * Target algo returns flash status in r0 only if properly finished.
535 * It is safer to re-read status register.
536 */
537 int retval2 = stm32x_wait_status_busy(bank, 5);
538 if (retval2 != ERROR_OK)
539 retval = retval2;
540
541 LOG_ERROR("flash write failed just before address 0x%"PRIx32,
542 buf_get_u32(reg_params[4].value, 0, 32));
543 }
544
545 for (unsigned int i = 0; i < ARRAY_SIZE(reg_params); i++)
546 destroy_reg_param(&reg_params[i]);
547
548 target_free_working_area(target, source);
549 target_free_working_area(target, write_algorithm);
550
551 return retval;
552 }
553
554 static int stm32x_write_block_riscv(struct flash_bank *bank, const uint8_t *buffer,
555 uint32_t address, uint32_t hwords_count)
556 {
557 struct target *target = bank->target;
558 uint32_t buffer_size;
559 struct working_area *write_algorithm;
560 struct working_area *source;
561 static const uint8_t gd32vf103_flash_write_code[] = {
562 #include "../../../contrib/loaders/flash/gd32vf103/gd32vf103.inc"
563 };
564
565 /* flash write code */
566 if (target_alloc_working_area(target, sizeof(gd32vf103_flash_write_code),
567 &write_algorithm) != ERROR_OK) {
568 LOG_WARNING("no working area available, can't do block memory writes");
569 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
570 }
571
572 int retval = target_write_buffer(target, write_algorithm->address,
573 sizeof(gd32vf103_flash_write_code), gd32vf103_flash_write_code);
574 if (retval != ERROR_OK) {
575 target_free_working_area(target, write_algorithm);
576 return retval;
577 }
578
579 /* memory buffer */
580 buffer_size = target_get_working_area_avail(target);
581 buffer_size = MIN(hwords_count * 2, MAX(buffer_size, 256));
582
583 retval = target_alloc_working_area(target, buffer_size, &source);
584 /* Allocated size is always word aligned */
585 if (retval != ERROR_OK) {
586 target_free_working_area(target, write_algorithm);
587 LOG_WARNING("no large enough working area available, can't do block memory writes");
588 /* target_alloc_working_area() may return ERROR_FAIL if area backup fails:
589 * convert any error to ERROR_TARGET_RESOURCE_NOT_AVAILABLE
590 */
591 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
592 }
593
594 struct reg_param reg_params[4];
595
596 init_reg_param(&reg_params[0], "a0", 32, PARAM_OUT); /* poiner to FLASH_SR */
597 init_reg_param(&reg_params[1], "a1", 32, PARAM_OUT); /* count (halfword-16bit) */
598 init_reg_param(&reg_params[2], "a2", 32, PARAM_OUT); /* buffer start */
599 init_reg_param(&reg_params[3], "a3", 32, PARAM_IN_OUT); /* target address */
600
601 while (hwords_count > 0) {
602 uint32_t thisrun_hwords = source->size / 2;
603
604 /* Limit to the amount of data we actually want to write */
605 if (thisrun_hwords > hwords_count)
606 thisrun_hwords = hwords_count;
607
608 /* Write data to buffer */
609 retval = target_write_buffer(target, source->address,
610 thisrun_hwords * 2, buffer);
611 if (retval != ERROR_OK)
612 break;
613
614 buf_set_u32(reg_params[0].value, 0, 32, stm32x_get_flash_reg(bank, STM32_FLASH_SR));
615 buf_set_u32(reg_params[1].value, 0, 32, thisrun_hwords);
616 buf_set_u32(reg_params[2].value, 0, 32, source->address);
617 buf_set_u32(reg_params[3].value, 0, 32, address);
618
619 retval = target_run_algorithm(target,
620 0, NULL,
621 ARRAY_SIZE(reg_params), reg_params,
622 write_algorithm->address,
623 write_algorithm->address + sizeof(gd32vf103_flash_write_code) - 4,
624 10000, NULL);
625
626 if (retval != ERROR_OK) {
627 LOG_ERROR("Failed to execute algorithm at 0x%" TARGET_PRIxADDR ": %d",
628 write_algorithm->address, retval);
629 break;
630 }
631
632 /* Actually we just need to check for programming errors
633 * stm32x_wait_status_busy also reports error and clears status bits
634 */
635 retval = stm32x_wait_status_busy(bank, 5);
636 if (retval != ERROR_OK) {
637 LOG_ERROR("flash write failed at address 0x%"PRIx32,
638 buf_get_u32(reg_params[3].value, 0, 32));
639 break;
640 }
641
642 /* Update counters */
643 buffer += thisrun_hwords * 2;
644 address += thisrun_hwords * 2;
645 hwords_count -= thisrun_hwords;
646 }
647
648 for (unsigned int i = 0; i < ARRAY_SIZE(reg_params); i++)
649 destroy_reg_param(&reg_params[i]);
650
651 target_free_working_area(target, source);
652 target_free_working_area(target, write_algorithm);
653
654 return retval;
655 }
656
657 /** Writes a block to flash either using target algorithm
658 * or use fallback, host controlled halfword-by-halfword access.
659 * Flash controller must be unlocked before this call.
660 */
661 static int stm32x_write_block(struct flash_bank *bank,
662 const uint8_t *buffer, uint32_t address, uint32_t hwords_count)
663 {
664 struct target *target = bank->target;
665
666 /* The flash write must be aligned to a halfword boundary.
667 * The flash infrastructure ensures it, do just a security check
668 */
669 assert(address % 2 == 0);
670
671 int retval;
672 struct arm *arm = target_to_arm(target);
673 if (is_arm(arm)) {
674 /* try using a block write - on ARM architecture or... */
675 retval = stm32x_write_block_async(bank, buffer, address, hwords_count);
676 } else {
677 /* ... RISC-V architecture */
678 retval = stm32x_write_block_riscv(bank, buffer, address, hwords_count);
679 }
680
681 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
682 /* if block write failed (no sufficient working area),
683 * we use normal (slow) single halfword accesses */
684 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
685
686 while (hwords_count > 0) {
687 retval = target_write_memory(target, address, 2, 1, buffer);
688 if (retval != ERROR_OK)
689 return retval;
690
691 retval = stm32x_wait_status_busy(bank, 5);
692 if (retval != ERROR_OK)
693 return retval;
694
695 hwords_count--;
696 buffer += 2;
697 address += 2;
698 }
699 }
700 return retval;
701 }
702
703 static int stm32x_write(struct flash_bank *bank, const uint8_t *buffer,
704 uint32_t offset, uint32_t count)
705 {
706 struct target *target = bank->target;
707
708 if (bank->target->state != TARGET_HALTED) {
709 LOG_ERROR("Target not halted");
710 return ERROR_TARGET_NOT_HALTED;
711 }
712
713 /* The flash write must be aligned to a halfword boundary.
714 * The flash infrastructure ensures it, do just a security check
715 */
716 assert(offset % 2 == 0);
717 assert(count % 2 == 0);
718
719 int retval, retval2;
720
721 /* unlock flash registers */
722 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
723 if (retval != ERROR_OK)
724 return retval;
725 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
726 if (retval != ERROR_OK)
727 goto reset_pg_and_lock;
728
729 /* enable flash programming */
730 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PG);
731 if (retval != ERROR_OK)
732 goto reset_pg_and_lock;
733
734 /* write to flash */
735 retval = stm32x_write_block(bank, buffer, bank->base + offset, count / 2);
736
737 reset_pg_and_lock:
738 retval2 = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
739 if (retval == ERROR_OK)
740 retval = retval2;
741
742 return retval;
743 }
744
745 struct stm32x_property_addr {
746 uint32_t device_id;
747 uint32_t flash_size;
748 };
749
750 static int stm32x_get_property_addr(struct target *target, struct stm32x_property_addr *addr)
751 {
752 if (!target_was_examined(target)) {
753 LOG_ERROR("Target not examined yet");
754 return ERROR_TARGET_NOT_EXAMINED;
755 }
756
757 switch (cortex_m_get_partno_safe(target)) {
758 case CORTEX_M0_PARTNO: /* STM32F0x devices */
759 addr->device_id = 0x40015800;
760 addr->flash_size = 0x1FFFF7CC;
761 return ERROR_OK;
762 case CORTEX_M3_PARTNO: /* STM32F1x devices */
763 addr->device_id = 0xE0042000;
764 addr->flash_size = 0x1FFFF7E0;
765 return ERROR_OK;
766 case CORTEX_M4_PARTNO: /* STM32F3x devices */
767 addr->device_id = 0xE0042000;
768 addr->flash_size = 0x1FFFF7CC;
769 return ERROR_OK;
770 case CORTEX_M23_PARTNO: /* GD32E23x devices */
771 addr->device_id = 0x40015800;
772 addr->flash_size = 0x1FFFF7E0;
773 return ERROR_OK;
774 case CORTEX_M_PARTNO_INVALID:
775 /* Check for GD32VF103 with RISC-V CPU */
776 if (strcmp(target_type_name(target), "riscv") == 0
777 && target_address_bits(target) == 32) {
778 /* There is nothing like arm common_magic in riscv_info_t
779 * check text name of target and if target is 32-bit
780 */
781 addr->device_id = 0xE0042000;
782 addr->flash_size = 0x1FFFF7E0;
783 return ERROR_OK;
784 }
785 /* fallthrough */
786 default:
787 LOG_ERROR("Cannot identify target as a stm32x");
788 return ERROR_FAIL;
789 }
790 }
791
792 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id)
793 {
794 struct target *target = bank->target;
795 struct stm32x_property_addr addr;
796
797 int retval = stm32x_get_property_addr(target, &addr);
798 if (retval != ERROR_OK)
799 return retval;
800
801 return target_read_u32(target, addr.device_id, device_id);
802 }
803
804 static int stm32x_get_flash_size(struct flash_bank *bank, uint16_t *flash_size_in_kb)
805 {
806 struct target *target = bank->target;
807 struct stm32x_property_addr addr;
808
809 int retval = stm32x_get_property_addr(target, &addr);
810 if (retval != ERROR_OK)
811 return retval;
812
813 return target_read_u16(target, addr.flash_size, flash_size_in_kb);
814 }
815
816 static int stm32x_probe(struct flash_bank *bank)
817 {
818 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
819 uint16_t flash_size_in_kb;
820 uint16_t max_flash_size_in_kb;
821 uint32_t dbgmcu_idcode;
822 int page_size;
823 uint32_t base_address = 0x08000000;
824
825 stm32x_info->probed = false;
826 stm32x_info->register_base = FLASH_REG_BASE_B0;
827 stm32x_info->user_data_offset = 10;
828 stm32x_info->option_offset = 0;
829
830 /* default factory read protection level 0 */
831 stm32x_info->default_rdp = 0xA5;
832
833 /* read stm32 device id register */
834 int retval = stm32x_get_device_id(bank, &dbgmcu_idcode);
835 if (retval != ERROR_OK)
836 return retval;
837
838 LOG_INFO("device id = 0x%08" PRIx32 "", dbgmcu_idcode);
839
840 uint16_t device_id = dbgmcu_idcode & 0xfff;
841 uint16_t rev_id = dbgmcu_idcode >> 16;
842
843 /* set page size, protection granularity and max flash size depending on family */
844 switch (device_id) {
845 case 0x440: /* stm32f05x */
846 page_size = 1024;
847 stm32x_info->ppage_size = 4;
848 max_flash_size_in_kb = 64;
849 stm32x_info->user_data_offset = 16;
850 stm32x_info->option_offset = 6;
851 stm32x_info->default_rdp = 0xAA;
852 stm32x_info->can_load_options = true;
853 break;
854 case 0x444: /* stm32f03x */
855 case 0x445: /* stm32f04x */
856 page_size = 1024;
857 stm32x_info->ppage_size = 4;
858 max_flash_size_in_kb = 32;
859 stm32x_info->user_data_offset = 16;
860 stm32x_info->option_offset = 6;
861 stm32x_info->default_rdp = 0xAA;
862 stm32x_info->can_load_options = true;
863 break;
864 case 0x448: /* stm32f07x */
865 page_size = 2048;
866 stm32x_info->ppage_size = 4;
867 max_flash_size_in_kb = 128;
868 stm32x_info->user_data_offset = 16;
869 stm32x_info->option_offset = 6;
870 stm32x_info->default_rdp = 0xAA;
871 stm32x_info->can_load_options = true;
872 break;
873 case 0x442: /* stm32f09x */
874 page_size = 2048;
875 stm32x_info->ppage_size = 4;
876 max_flash_size_in_kb = 256;
877 stm32x_info->user_data_offset = 16;
878 stm32x_info->option_offset = 6;
879 stm32x_info->default_rdp = 0xAA;
880 stm32x_info->can_load_options = true;
881 break;
882 case 0x410: /* stm32f1x medium-density */
883 page_size = 1024;
884 stm32x_info->ppage_size = 4;
885 max_flash_size_in_kb = 128;
886 /* GigaDevice GD32F1x0 & GD32F3x0 & GD32E23x series devices
887 share DEV_ID with STM32F101/2/3 medium-density line,
888 however they use a REV_ID different from any STM32 device.
889 The main difference is another offset of user option bits
890 (like WDG_SW, nRST_STOP, nRST_STDBY) in option byte register
891 (FLASH_OBR/FMC_OBSTAT 0x4002201C).
892 This caused problems e.g. during flash block programming
893 because of unexpected active hardware watchog. */
894 switch (rev_id) {
895 case 0x1303: /* gd32f1x0 */
896 stm32x_info->user_data_offset = 16;
897 stm32x_info->option_offset = 6;
898 max_flash_size_in_kb = 64;
899 stm32x_info->can_load_options = true;
900 break;
901 case 0x1704: /* gd32f3x0 */
902 stm32x_info->user_data_offset = 16;
903 stm32x_info->option_offset = 6;
904 stm32x_info->can_load_options = true;
905 break;
906 case 0x1906: /* gd32vf103 */
907 break;
908 case 0x1909: /* gd32e23x */
909 stm32x_info->user_data_offset = 16;
910 stm32x_info->option_offset = 6;
911 max_flash_size_in_kb = 64;
912 stm32x_info->can_load_options = true;
913 break;
914 }
915 break;
916 case 0x412: /* stm32f1x low-density */
917 page_size = 1024;
918 stm32x_info->ppage_size = 4;
919 max_flash_size_in_kb = 32;
920 break;
921 case 0x414: /* stm32f1x high-density */
922 page_size = 2048;
923 stm32x_info->ppage_size = 2;
924 max_flash_size_in_kb = 512;
925 break;
926 case 0x418: /* stm32f1x connectivity */
927 page_size = 2048;
928 stm32x_info->ppage_size = 2;
929 max_flash_size_in_kb = 256;
930 break;
931 case 0x430: /* stm32f1 XL-density (dual flash banks) */
932 page_size = 2048;
933 stm32x_info->ppage_size = 2;
934 max_flash_size_in_kb = 1024;
935 stm32x_info->has_dual_banks = true;
936 break;
937 case 0x420: /* stm32f100xx low- and medium-density value line */
938 page_size = 1024;
939 stm32x_info->ppage_size = 4;
940 max_flash_size_in_kb = 128;
941 break;
942 case 0x428: /* stm32f100xx high-density value line */
943 page_size = 2048;
944 stm32x_info->ppage_size = 4;
945 max_flash_size_in_kb = 512;
946 break;
947 case 0x422: /* stm32f302/3xb/c */
948 page_size = 2048;
949 stm32x_info->ppage_size = 2;
950 max_flash_size_in_kb = 256;
951 stm32x_info->user_data_offset = 16;
952 stm32x_info->option_offset = 6;
953 stm32x_info->default_rdp = 0xAA;
954 stm32x_info->can_load_options = true;
955 break;
956 case 0x446: /* stm32f303xD/E */
957 page_size = 2048;
958 stm32x_info->ppage_size = 2;
959 max_flash_size_in_kb = 512;
960 stm32x_info->user_data_offset = 16;
961 stm32x_info->option_offset = 6;
962 stm32x_info->default_rdp = 0xAA;
963 stm32x_info->can_load_options = true;
964 break;
965 case 0x432: /* stm32f37x */
966 page_size = 2048;
967 stm32x_info->ppage_size = 2;
968 max_flash_size_in_kb = 256;
969 stm32x_info->user_data_offset = 16;
970 stm32x_info->option_offset = 6;
971 stm32x_info->default_rdp = 0xAA;
972 stm32x_info->can_load_options = true;
973 break;
974 case 0x438: /* stm32f33x */
975 case 0x439: /* stm32f302x6/8 */
976 page_size = 2048;
977 stm32x_info->ppage_size = 2;
978 max_flash_size_in_kb = 64;
979 stm32x_info->user_data_offset = 16;
980 stm32x_info->option_offset = 6;
981 stm32x_info->default_rdp = 0xAA;
982 stm32x_info->can_load_options = true;
983 break;
984 default:
985 LOG_WARNING("Cannot identify target as a STM32 family.");
986 return ERROR_FAIL;
987 }
988
989 /* get flash size from target. */
990 retval = stm32x_get_flash_size(bank, &flash_size_in_kb);
991
992 /* failed reading flash size or flash size invalid (early silicon),
993 * default to max target family */
994 if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0) {
995 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
996 max_flash_size_in_kb);
997 flash_size_in_kb = max_flash_size_in_kb;
998 }
999
1000 if (stm32x_info->has_dual_banks) {
1001 /* split reported size into matching bank */
1002 if (bank->base != 0x08080000) {
1003 /* bank 0 will be fixed 512k */
1004 flash_size_in_kb = 512;
1005 } else {
1006 flash_size_in_kb -= 512;
1007 /* bank1 also uses a register offset */
1008 stm32x_info->register_base = FLASH_REG_BASE_B1;
1009 base_address = 0x08080000;
1010 }
1011 }
1012
1013 /* if the user sets the size manually then ignore the probed value
1014 * this allows us to work around devices that have a invalid flash size register value */
1015 if (stm32x_info->user_bank_size) {
1016 LOG_INFO("ignoring flash probed value, using configured bank size");
1017 flash_size_in_kb = stm32x_info->user_bank_size / 1024;
1018 }
1019
1020 LOG_INFO("flash size = %dkbytes", flash_size_in_kb);
1021
1022 /* did we assign flash size? */
1023 assert(flash_size_in_kb != 0xffff);
1024
1025 /* calculate numbers of pages */
1026 int num_pages = flash_size_in_kb * 1024 / page_size;
1027
1028 /* check that calculation result makes sense */
1029 assert(num_pages > 0);
1030
1031 free(bank->sectors);
1032 bank->sectors = NULL;
1033
1034 free(bank->prot_blocks);
1035 bank->prot_blocks = NULL;
1036
1037 bank->base = base_address;
1038 bank->size = (num_pages * page_size);
1039
1040 bank->num_sectors = num_pages;
1041 bank->sectors = alloc_block_array(0, page_size, num_pages);
1042 if (!bank->sectors)
1043 return ERROR_FAIL;
1044
1045 /* calculate number of write protection blocks */
1046 int num_prot_blocks = num_pages / stm32x_info->ppage_size;
1047 if (num_prot_blocks > 32)
1048 num_prot_blocks = 32;
1049
1050 bank->num_prot_blocks = num_prot_blocks;
1051 bank->prot_blocks = alloc_block_array(0, stm32x_info->ppage_size * page_size, num_prot_blocks);
1052 if (!bank->prot_blocks)
1053 return ERROR_FAIL;
1054
1055 if (num_prot_blocks == 32)
1056 bank->prot_blocks[31].size = (num_pages - (31 * stm32x_info->ppage_size)) * page_size;
1057
1058 stm32x_info->probed = true;
1059
1060 return ERROR_OK;
1061 }
1062
1063 static int stm32x_auto_probe(struct flash_bank *bank)
1064 {
1065 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
1066 if (stm32x_info->probed)
1067 return ERROR_OK;
1068 return stm32x_probe(bank);
1069 }
1070
1071 #if 0
1072 COMMAND_HANDLER(stm32x_handle_part_id_command)
1073 {
1074 return ERROR_OK;
1075 }
1076 #endif
1077
1078 static const char *get_stm32f0_revision(uint16_t rev_id)
1079 {
1080 const char *rev_str = NULL;
1081
1082 switch (rev_id) {
1083 case 0x1000:
1084 rev_str = "1.0";
1085 break;
1086 case 0x2000:
1087 rev_str = "2.0";
1088 break;
1089 }
1090 return rev_str;
1091 }
1092
1093 static int get_stm32x_info(struct flash_bank *bank, struct command_invocation *cmd)
1094 {
1095 uint32_t dbgmcu_idcode;
1096
1097 /* read stm32 device id register */
1098 int retval = stm32x_get_device_id(bank, &dbgmcu_idcode);
1099 if (retval != ERROR_OK)
1100 return retval;
1101
1102 uint16_t device_id = dbgmcu_idcode & 0xfff;
1103 uint16_t rev_id = dbgmcu_idcode >> 16;
1104 const char *device_str;
1105 const char *rev_str = NULL;
1106
1107 switch (device_id) {
1108 case 0x410:
1109 device_str = "STM32F10x (Medium Density)";
1110
1111 switch (rev_id) {
1112 case 0x0000:
1113 rev_str = "A";
1114 break;
1115
1116 case 0x1303: /* gd32f1x0 */
1117 device_str = "GD32F1x0";
1118 break;
1119
1120 case 0x1704: /* gd32f3x0 */
1121 device_str = "GD32F3x0";
1122 break;
1123
1124 case 0x1906:
1125 device_str = "GD32VF103";
1126 break;
1127
1128 case 0x1909: /* gd32e23x */
1129 device_str = "GD32E23x";
1130 break;
1131
1132 case 0x2000:
1133 rev_str = "B";
1134 break;
1135
1136 case 0x2001:
1137 rev_str = "Z";
1138 break;
1139
1140 case 0x2003:
1141 rev_str = "Y";
1142 break;
1143 }
1144 break;
1145
1146 case 0x412:
1147 device_str = "STM32F10x (Low Density)";
1148
1149 switch (rev_id) {
1150 case 0x1000:
1151 rev_str = "A";
1152 break;
1153 }
1154 break;
1155
1156 case 0x414:
1157 device_str = "STM32F10x (High Density)";
1158
1159 switch (rev_id) {
1160 case 0x1000:
1161 rev_str = "A";
1162 break;
1163
1164 case 0x1001:
1165 rev_str = "Z";
1166 break;
1167
1168 case 0x1003:
1169 rev_str = "Y";
1170 break;
1171 }
1172 break;
1173
1174 case 0x418:
1175 device_str = "STM32F10x (Connectivity)";
1176
1177 switch (rev_id) {
1178 case 0x1000:
1179 rev_str = "A";
1180 break;
1181
1182 case 0x1001:
1183 rev_str = "Z";
1184 break;
1185 }
1186 break;
1187
1188 case 0x420:
1189 device_str = "STM32F100 (Low/Medium Density)";
1190
1191 switch (rev_id) {
1192 case 0x1000:
1193 rev_str = "A";
1194 break;
1195
1196 case 0x1001:
1197 rev_str = "Z";
1198 break;
1199 }
1200 break;
1201
1202 case 0x422:
1203 device_str = "STM32F302xB/C";
1204
1205 switch (rev_id) {
1206 case 0x1000:
1207 rev_str = "A";
1208 break;
1209
1210 case 0x1001:
1211 rev_str = "Z";
1212 break;
1213
1214 case 0x1003:
1215 rev_str = "Y";
1216 break;
1217
1218 case 0x2000:
1219 rev_str = "B";
1220 break;
1221 }
1222 break;
1223
1224 case 0x428:
1225 device_str = "STM32F100 (High Density)";
1226
1227 switch (rev_id) {
1228 case 0x1000:
1229 rev_str = "A";
1230 break;
1231
1232 case 0x1001:
1233 rev_str = "Z";
1234 break;
1235 }
1236 break;
1237
1238 case 0x430:
1239 device_str = "STM32F10x (XL Density)";
1240
1241 switch (rev_id) {
1242 case 0x1000:
1243 rev_str = "A";
1244 break;
1245 }
1246 break;
1247
1248 case 0x432:
1249 device_str = "STM32F37x";
1250
1251 switch (rev_id) {
1252 case 0x1000:
1253 rev_str = "A";
1254 break;
1255
1256 case 0x2000:
1257 rev_str = "B";
1258 break;
1259 }
1260 break;
1261
1262 case 0x438:
1263 device_str = "STM32F33x";
1264
1265 switch (rev_id) {
1266 case 0x1000:
1267 rev_str = "A";
1268 break;
1269 }
1270 break;
1271
1272 case 0x439:
1273 device_str = "STM32F302x6/8";
1274
1275 switch (rev_id) {
1276 case 0x1000:
1277 rev_str = "A";
1278 break;
1279
1280 case 0x1001:
1281 rev_str = "Z";
1282 break;
1283 }
1284 break;
1285
1286 case 0x444:
1287 device_str = "STM32F03x";
1288 rev_str = get_stm32f0_revision(rev_id);
1289 break;
1290
1291 case 0x440:
1292 device_str = "STM32F05x";
1293 rev_str = get_stm32f0_revision(rev_id);
1294 break;
1295
1296 case 0x445:
1297 device_str = "STM32F04x";
1298 rev_str = get_stm32f0_revision(rev_id);
1299 break;
1300
1301 case 0x446:
1302 device_str = "STM32F303xD/E";
1303 switch (rev_id) {
1304 case 0x1000:
1305 rev_str = "A";
1306 break;
1307 }
1308 break;
1309
1310 case 0x448:
1311 device_str = "STM32F07x";
1312 rev_str = get_stm32f0_revision(rev_id);
1313 break;
1314
1315 case 0x442:
1316 device_str = "STM32F09x";
1317 rev_str = get_stm32f0_revision(rev_id);
1318 break;
1319
1320 default:
1321 command_print_sameline(cmd, "Cannot identify target as a STM32F0/1/3\n");
1322 return ERROR_FAIL;
1323 }
1324
1325 if (rev_str)
1326 command_print_sameline(cmd, "%s - Rev: %s", device_str, rev_str);
1327 else
1328 command_print_sameline(cmd, "%s - Rev: unknown (0x%04x)", device_str, rev_id);
1329
1330 return ERROR_OK;
1331 }
1332
1333 COMMAND_HANDLER(stm32x_handle_lock_command)
1334 {
1335 struct target *target = NULL;
1336 struct stm32x_flash_bank *stm32x_info = NULL;
1337
1338 if (CMD_ARGC < 1)
1339 return ERROR_COMMAND_SYNTAX_ERROR;
1340
1341 struct flash_bank *bank;
1342 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1343 if (retval != ERROR_OK)
1344 return retval;
1345
1346 stm32x_info = bank->driver_priv;
1347
1348 target = bank->target;
1349
1350 if (target->state != TARGET_HALTED) {
1351 LOG_ERROR("Target not halted");
1352 return ERROR_TARGET_NOT_HALTED;
1353 }
1354
1355 retval = stm32x_check_operation_supported(bank);
1356 if (retval != ERROR_OK)
1357 return retval;
1358
1359 if (stm32x_erase_options(bank) != ERROR_OK) {
1360 command_print(CMD, "stm32x failed to erase options");
1361 return ERROR_OK;
1362 }
1363
1364 /* set readout protection */
1365 stm32x_info->option_bytes.rdp = 0;
1366
1367 if (stm32x_write_options(bank) != ERROR_OK) {
1368 command_print(CMD, "stm32x failed to lock device");
1369 return ERROR_OK;
1370 }
1371
1372 command_print(CMD, "stm32x locked");
1373
1374 return ERROR_OK;
1375 }
1376
1377 COMMAND_HANDLER(stm32x_handle_unlock_command)
1378 {
1379 struct target *target = NULL;
1380
1381 if (CMD_ARGC < 1)
1382 return ERROR_COMMAND_SYNTAX_ERROR;
1383
1384 struct flash_bank *bank;
1385 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1386 if (retval != ERROR_OK)
1387 return retval;
1388
1389 target = bank->target;
1390
1391 if (target->state != TARGET_HALTED) {
1392 LOG_ERROR("Target not halted");
1393 return ERROR_TARGET_NOT_HALTED;
1394 }
1395
1396 retval = stm32x_check_operation_supported(bank);
1397 if (retval != ERROR_OK)
1398 return retval;
1399
1400 if (stm32x_erase_options(bank) != ERROR_OK) {
1401 command_print(CMD, "stm32x failed to erase options");
1402 return ERROR_OK;
1403 }
1404
1405 if (stm32x_write_options(bank) != ERROR_OK) {
1406 command_print(CMD, "stm32x failed to unlock device");
1407 return ERROR_OK;
1408 }
1409
1410 command_print(CMD, "stm32x unlocked.\n"
1411 "INFO: a reset or power cycle is required "
1412 "for the new settings to take effect.");
1413
1414 return ERROR_OK;
1415 }
1416
1417 COMMAND_HANDLER(stm32x_handle_options_read_command)
1418 {
1419 uint32_t optionbyte, protection;
1420 struct target *target = NULL;
1421 struct stm32x_flash_bank *stm32x_info = NULL;
1422
1423 if (CMD_ARGC < 1)
1424 return ERROR_COMMAND_SYNTAX_ERROR;
1425
1426 struct flash_bank *bank;
1427 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1428 if (retval != ERROR_OK)
1429 return retval;
1430
1431 stm32x_info = bank->driver_priv;
1432
1433 target = bank->target;
1434
1435 if (target->state != TARGET_HALTED) {
1436 LOG_ERROR("Target not halted");
1437 return ERROR_TARGET_NOT_HALTED;
1438 }
1439
1440 retval = stm32x_check_operation_supported(bank);
1441 if (retval != ERROR_OK)
1442 return retval;
1443
1444 retval = target_read_u32(target, STM32_FLASH_OBR_B0, &optionbyte);
1445 if (retval != ERROR_OK)
1446 return retval;
1447
1448 uint16_t user_data = optionbyte >> stm32x_info->user_data_offset;
1449
1450 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
1451 if (retval != ERROR_OK)
1452 return retval;
1453
1454 if (optionbyte & (1 << OPT_ERROR))
1455 command_print(CMD, "option byte complement error");
1456
1457 command_print(CMD, "option byte register = 0x%" PRIx32 "", optionbyte);
1458 command_print(CMD, "write protection register = 0x%" PRIx32 "", protection);
1459
1460 command_print(CMD, "read protection: %s",
1461 (optionbyte & (1 << OPT_READOUT)) ? "on" : "off");
1462
1463 /* user option bytes are offset depending on variant */
1464 optionbyte >>= stm32x_info->option_offset;
1465
1466 command_print(CMD, "watchdog: %sware",
1467 (optionbyte & (1 << OPT_RDWDGSW)) ? "soft" : "hard");
1468
1469 command_print(CMD, "stop mode: %sreset generated upon entry",
1470 (optionbyte & (1 << OPT_RDRSTSTOP)) ? "no " : "");
1471
1472 command_print(CMD, "standby mode: %sreset generated upon entry",
1473 (optionbyte & (1 << OPT_RDRSTSTDBY)) ? "no " : "");
1474
1475 if (stm32x_info->has_dual_banks)
1476 command_print(CMD, "boot: bank %d", (optionbyte & (1 << OPT_BFB2)) ? 0 : 1);
1477
1478 command_print(CMD, "user data = 0x%02" PRIx16 "", user_data);
1479
1480 return ERROR_OK;
1481 }
1482
1483 COMMAND_HANDLER(stm32x_handle_options_write_command)
1484 {
1485 struct target *target = NULL;
1486 struct stm32x_flash_bank *stm32x_info = NULL;
1487 uint8_t optionbyte;
1488 uint16_t useropt;
1489
1490 if (CMD_ARGC < 2)
1491 return ERROR_COMMAND_SYNTAX_ERROR;
1492
1493 struct flash_bank *bank;
1494 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1495 if (retval != ERROR_OK)
1496 return retval;
1497
1498 stm32x_info = bank->driver_priv;
1499
1500 target = bank->target;
1501
1502 if (target->state != TARGET_HALTED) {
1503 LOG_ERROR("Target not halted");
1504 return ERROR_TARGET_NOT_HALTED;
1505 }
1506
1507 retval = stm32x_check_operation_supported(bank);
1508 if (retval != ERROR_OK)
1509 return retval;
1510
1511 retval = stm32x_read_options(bank);
1512 if (retval != ERROR_OK)
1513 return retval;
1514
1515 /* start with current options */
1516 optionbyte = stm32x_info->option_bytes.user;
1517 useropt = stm32x_info->option_bytes.data;
1518
1519 /* skip over flash bank */
1520 CMD_ARGC--;
1521 CMD_ARGV++;
1522
1523 while (CMD_ARGC) {
1524 if (strcmp("SWWDG", CMD_ARGV[0]) == 0)
1525 optionbyte |= (1 << 0);
1526 else if (strcmp("HWWDG", CMD_ARGV[0]) == 0)
1527 optionbyte &= ~(1 << 0);
1528 else if (strcmp("NORSTSTOP", CMD_ARGV[0]) == 0)
1529 optionbyte |= (1 << 1);
1530 else if (strcmp("RSTSTOP", CMD_ARGV[0]) == 0)
1531 optionbyte &= ~(1 << 1);
1532 else if (strcmp("NORSTSTNDBY", CMD_ARGV[0]) == 0)
1533 optionbyte |= (1 << 2);
1534 else if (strcmp("RSTSTNDBY", CMD_ARGV[0]) == 0)
1535 optionbyte &= ~(1 << 2);
1536 else if (strcmp("USEROPT", CMD_ARGV[0]) == 0) {
1537 if (CMD_ARGC < 2)
1538 return ERROR_COMMAND_SYNTAX_ERROR;
1539 COMMAND_PARSE_NUMBER(u16, CMD_ARGV[1], useropt);
1540 CMD_ARGC--;
1541 CMD_ARGV++;
1542 } else if (stm32x_info->has_dual_banks) {
1543 if (strcmp("BOOT0", CMD_ARGV[0]) == 0)
1544 optionbyte |= (1 << 3);
1545 else if (strcmp("BOOT1", CMD_ARGV[0]) == 0)
1546 optionbyte &= ~(1 << 3);
1547 else
1548 return ERROR_COMMAND_SYNTAX_ERROR;
1549 } else
1550 return ERROR_COMMAND_SYNTAX_ERROR;
1551 CMD_ARGC--;
1552 CMD_ARGV++;
1553 }
1554
1555 if (stm32x_erase_options(bank) != ERROR_OK) {
1556 command_print(CMD, "stm32x failed to erase options");
1557 return ERROR_OK;
1558 }
1559
1560 stm32x_info->option_bytes.user = optionbyte;
1561 stm32x_info->option_bytes.data = useropt;
1562
1563 if (stm32x_write_options(bank) != ERROR_OK) {
1564 command_print(CMD, "stm32x failed to write options");
1565 return ERROR_OK;
1566 }
1567
1568 command_print(CMD, "stm32x write options complete.\n"
1569 "INFO: %spower cycle is required "
1570 "for the new settings to take effect.",
1571 stm32x_info->can_load_options
1572 ? "'stm32f1x options_load' command or " : "");
1573
1574 return ERROR_OK;
1575 }
1576
1577 COMMAND_HANDLER(stm32x_handle_options_load_command)
1578 {
1579 if (CMD_ARGC < 1)
1580 return ERROR_COMMAND_SYNTAX_ERROR;
1581
1582 struct flash_bank *bank;
1583 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1584 if (retval != ERROR_OK)
1585 return retval;
1586
1587 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
1588
1589 if (!stm32x_info->can_load_options) {
1590 LOG_ERROR("Command not applicable to stm32f1x devices - power cycle is "
1591 "required instead.");
1592 return ERROR_FAIL;
1593 }
1594
1595 struct target *target = bank->target;
1596
1597 if (target->state != TARGET_HALTED) {
1598 LOG_ERROR("Target not halted");
1599 return ERROR_TARGET_NOT_HALTED;
1600 }
1601
1602 retval = stm32x_check_operation_supported(bank);
1603 if (retval != ERROR_OK)
1604 return retval;
1605
1606 /* unlock option flash registers */
1607 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
1608 if (retval != ERROR_OK)
1609 return retval;
1610 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
1611 if (retval != ERROR_OK) {
1612 (void)target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
1613 return retval;
1614 }
1615
1616 /* force re-load of option bytes - generates software reset */
1617 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_OBL_LAUNCH);
1618 if (retval != ERROR_OK)
1619 return retval;
1620
1621 return ERROR_OK;
1622 }
1623
1624 static int stm32x_mass_erase(struct flash_bank *bank)
1625 {
1626 struct target *target = bank->target;
1627
1628 if (target->state != TARGET_HALTED) {
1629 LOG_ERROR("Target not halted");
1630 return ERROR_TARGET_NOT_HALTED;
1631 }
1632
1633 /* unlock option flash registers */
1634 int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
1635 if (retval != ERROR_OK)
1636 return retval;
1637 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
1638 if (retval != ERROR_OK)
1639 goto flash_lock;
1640
1641 /* mass erase flash memory */
1642 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_MER);
1643 if (retval != ERROR_OK)
1644 goto flash_lock;
1645 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR),
1646 FLASH_MER | FLASH_STRT);
1647 if (retval != ERROR_OK)
1648 goto flash_lock;
1649
1650 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
1651
1652 flash_lock:
1653 {
1654 int retval2 = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
1655 if (retval == ERROR_OK)
1656 retval = retval2;
1657 }
1658 return retval;
1659 }
1660
1661 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
1662 {
1663 if (CMD_ARGC < 1)
1664 return ERROR_COMMAND_SYNTAX_ERROR;
1665
1666 struct flash_bank *bank;
1667 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1668 if (retval != ERROR_OK)
1669 return retval;
1670
1671 retval = stm32x_mass_erase(bank);
1672 if (retval == ERROR_OK)
1673 command_print(CMD, "stm32x mass erase complete");
1674 else
1675 command_print(CMD, "stm32x mass erase failed");
1676
1677 return retval;
1678 }
1679
1680 static const struct command_registration stm32f1x_exec_command_handlers[] = {
1681 {
1682 .name = "lock",
1683 .handler = stm32x_handle_lock_command,
1684 .mode = COMMAND_EXEC,
1685 .usage = "bank_id",
1686 .help = "Lock entire flash device.",
1687 },
1688 {
1689 .name = "unlock",
1690 .handler = stm32x_handle_unlock_command,
1691 .mode = COMMAND_EXEC,
1692 .usage = "bank_id",
1693 .help = "Unlock entire protected flash device.",
1694 },
1695 {
1696 .name = "mass_erase",
1697 .handler = stm32x_handle_mass_erase_command,
1698 .mode = COMMAND_EXEC,
1699 .usage = "bank_id",
1700 .help = "Erase entire flash device.",
1701 },
1702 {
1703 .name = "options_read",
1704 .handler = stm32x_handle_options_read_command,
1705 .mode = COMMAND_EXEC,
1706 .usage = "bank_id",
1707 .help = "Read and display device option bytes.",
1708 },
1709 {
1710 .name = "options_write",
1711 .handler = stm32x_handle_options_write_command,
1712 .mode = COMMAND_EXEC,
1713 .usage = "bank_id ('SWWDG'|'HWWDG') "
1714 "('RSTSTNDBY'|'NORSTSTNDBY') "
1715 "('RSTSTOP'|'NORSTSTOP') ('USEROPT' user_data)",
1716 .help = "Replace bits in device option bytes.",
1717 },
1718 {
1719 .name = "options_load",
1720 .handler = stm32x_handle_options_load_command,
1721 .mode = COMMAND_EXEC,
1722 .usage = "bank_id",
1723 .help = "Force re-load of device option bytes.",
1724 },
1725 COMMAND_REGISTRATION_DONE
1726 };
1727
1728 static const struct command_registration stm32f1x_command_handlers[] = {
1729 {
1730 .name = "stm32f1x",
1731 .mode = COMMAND_ANY,
1732 .help = "stm32f1x flash command group",
1733 .usage = "",
1734 .chain = stm32f1x_exec_command_handlers,
1735 },
1736 COMMAND_REGISTRATION_DONE
1737 };
1738
1739 const struct flash_driver stm32f1x_flash = {
1740 .name = "stm32f1x",
1741 .commands = stm32f1x_command_handlers,
1742 .flash_bank_command = stm32x_flash_bank_command,
1743 .erase = stm32x_erase,
1744 .protect = stm32x_protect,
1745 .write = stm32x_write,
1746 .read = default_flash_read,
1747 .probe = stm32x_probe,
1748 .auto_probe = stm32x_auto_probe,
1749 .erase_check = default_flash_blank_check,
1750 .protect_check = stm32x_protect_check,
1751 .info = get_stm32x_info,
1752 .free_driver_priv = default_flash_free_driver_priv,
1753 };
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