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Add stm32f0x probe and info working
[openocd.git] / src / flash / nor / stm32f1x.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2011 by Andreas Fritiofson *
9 * andreas.fritiofson@gmail.com *
10 *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
26
27 #ifdef HAVE_CONFIG_H
28 #include "config.h"
29 #endif
30
31 #include "imp.h"
32 #include <helper/binarybuffer.h>
33 #include <target/algorithm.h>
34 #include <target/armv7m.h>
35
36 /* stm32x register locations */
37
38 #define FLASH_REG_BASE_B0 0x40022000
39 #define FLASH_REG_BASE_B1 0x40022040
40
41 #define STM32_FLASH_ACR 0x00
42 #define STM32_FLASH_KEYR 0x04
43 #define STM32_FLASH_OPTKEYR 0x08
44 #define STM32_FLASH_SR 0x0C
45 #define STM32_FLASH_CR 0x10
46 #define STM32_FLASH_AR 0x14
47 #define STM32_FLASH_OBR 0x1C
48 #define STM32_FLASH_WRPR 0x20
49
50 /* TODO: Check if code using these really should be hard coded to bank 0.
51 * There are valid cases, on dual flash devices the protection of the
52 * second bank is done on the bank0 reg's. */
53 #define STM32_FLASH_ACR_B0 0x40022000
54 #define STM32_FLASH_KEYR_B0 0x40022004
55 #define STM32_FLASH_OPTKEYR_B0 0x40022008
56 #define STM32_FLASH_SR_B0 0x4002200C
57 #define STM32_FLASH_CR_B0 0x40022010
58 #define STM32_FLASH_AR_B0 0x40022014
59 #define STM32_FLASH_OBR_B0 0x4002201C
60 #define STM32_FLASH_WRPR_B0 0x40022020
61
62 /* option byte location */
63
64 #define STM32_OB_RDP 0x1FFFF800
65 #define STM32_OB_USER 0x1FFFF802
66 #define STM32_OB_DATA0 0x1FFFF804
67 #define STM32_OB_DATA1 0x1FFFF806
68 #define STM32_OB_WRP0 0x1FFFF808
69 #define STM32_OB_WRP1 0x1FFFF80A
70 #define STM32_OB_WRP2 0x1FFFF80C
71 #define STM32_OB_WRP3 0x1FFFF80E
72
73 /* FLASH_CR register bits */
74
75 #define FLASH_PG (1 << 0)
76 #define FLASH_PER (1 << 1)
77 #define FLASH_MER (1 << 2)
78 #define FLASH_OPTPG (1 << 4)
79 #define FLASH_OPTER (1 << 5)
80 #define FLASH_STRT (1 << 6)
81 #define FLASH_LOCK (1 << 7)
82 #define FLASH_OPTWRE (1 << 9)
83
84 /* FLASH_SR register bits */
85
86 #define FLASH_BSY (1 << 0)
87 #define FLASH_PGERR (1 << 2)
88 #define FLASH_WRPRTERR (1 << 4)
89 #define FLASH_EOP (1 << 5)
90
91 /* STM32_FLASH_OBR bit definitions (reading) */
92
93 #define OPT_ERROR 0
94 #define OPT_READOUT 1
95 #define OPT_RDWDGSW 2
96 #define OPT_RDRSTSTOP 3
97 #define OPT_RDRSTSTDBY 4
98 #define OPT_BFB2 5 /* dual flash bank only */
99
100 /* register unlock keys */
101
102 #define KEY1 0x45670123
103 #define KEY2 0xCDEF89AB
104
105 struct stm32x_options {
106 uint16_t RDP;
107 uint16_t user_options;
108 uint16_t protection[4];
109 };
110
111 struct stm32x_flash_bank {
112 struct stm32x_options option_bytes;
113 struct working_area *write_algorithm;
114 int ppage_size;
115 int probed;
116
117 bool has_dual_banks;
118 /* used to access dual flash bank stm32xl */
119 uint32_t register_base;
120 };
121
122 static int stm32x_mass_erase(struct flash_bank *bank);
123 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id);
124
125 /* flash bank stm32x <base> <size> 0 0 <target#>
126 */
127 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
128 {
129 struct stm32x_flash_bank *stm32x_info;
130
131 if (CMD_ARGC < 6)
132 return ERROR_COMMAND_SYNTAX_ERROR;
133
134 stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
135
136 bank->driver_priv = stm32x_info;
137 stm32x_info->write_algorithm = NULL;
138 stm32x_info->probed = 0;
139 stm32x_info->has_dual_banks = false;
140 stm32x_info->register_base = FLASH_REG_BASE_B0;
141
142 return ERROR_OK;
143 }
144
145 static inline int stm32x_get_flash_reg(struct flash_bank *bank, uint32_t reg)
146 {
147 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
148 return reg + stm32x_info->register_base;
149 }
150
151 static inline int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
152 {
153 struct target *target = bank->target;
154 return target_read_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), status);
155 }
156
157 static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
158 {
159 struct target *target = bank->target;
160 uint32_t status;
161 int retval = ERROR_OK;
162
163 /* wait for busy to clear */
164 for (;;) {
165 retval = stm32x_get_flash_status(bank, &status);
166 if (retval != ERROR_OK)
167 return retval;
168 LOG_DEBUG("status: 0x%" PRIx32 "", status);
169 if ((status & FLASH_BSY) == 0)
170 break;
171 if (timeout-- <= 0) {
172 LOG_ERROR("timed out waiting for flash");
173 return ERROR_FAIL;
174 }
175 alive_sleep(1);
176 }
177
178 if (status & FLASH_WRPRTERR) {
179 LOG_ERROR("stm32x device protected");
180 retval = ERROR_FAIL;
181 }
182
183 if (status & FLASH_PGERR) {
184 LOG_ERROR("stm32x device programming failed");
185 retval = ERROR_FAIL;
186 }
187
188 /* Clear but report errors */
189 if (status & (FLASH_WRPRTERR | FLASH_PGERR)) {
190 /* If this operation fails, we ignore it and report the original
191 * retval
192 */
193 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR),
194 FLASH_WRPRTERR | FLASH_PGERR);
195 }
196 return retval;
197 }
198
199 int stm32x_check_operation_supported(struct flash_bank *bank)
200 {
201 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
202
203 /* if we have a dual flash bank device then
204 * we need to perform option byte stuff on bank0 only */
205 if (stm32x_info->register_base != FLASH_REG_BASE_B0) {
206 LOG_ERROR("Option Byte Operation's must use bank0");
207 return ERROR_FLASH_OPERATION_FAILED;
208 }
209
210 return ERROR_OK;
211 }
212
213 static int stm32x_read_options(struct flash_bank *bank)
214 {
215 uint32_t optiondata;
216 struct stm32x_flash_bank *stm32x_info = NULL;
217 struct target *target = bank->target;
218
219 stm32x_info = bank->driver_priv;
220
221 /* read current option bytes */
222 int retval = target_read_u32(target, STM32_FLASH_OBR_B0, &optiondata);
223 if (retval != ERROR_OK)
224 return retval;
225
226 stm32x_info->option_bytes.user_options = (uint16_t)0xFFF8 | ((optiondata >> 2) & 0x07);
227 stm32x_info->option_bytes.RDP = (optiondata & (1 << OPT_READOUT)) ? 0xFFFF : 0x5AA5;
228
229 if (optiondata & (1 << OPT_READOUT))
230 LOG_INFO("Device Security Bit Set");
231
232 /* each bit refers to a 4bank protection */
233 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &optiondata);
234 if (retval != ERROR_OK)
235 return retval;
236
237 stm32x_info->option_bytes.protection[0] = (uint16_t)optiondata;
238 stm32x_info->option_bytes.protection[1] = (uint16_t)(optiondata >> 8);
239 stm32x_info->option_bytes.protection[2] = (uint16_t)(optiondata >> 16);
240 stm32x_info->option_bytes.protection[3] = (uint16_t)(optiondata >> 24);
241
242 return ERROR_OK;
243 }
244
245 static int stm32x_erase_options(struct flash_bank *bank)
246 {
247 struct stm32x_flash_bank *stm32x_info = NULL;
248 struct target *target = bank->target;
249
250 stm32x_info = bank->driver_priv;
251
252 /* read current options */
253 stm32x_read_options(bank);
254
255 /* unlock flash registers */
256 int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
257 if (retval != ERROR_OK)
258 return retval;
259
260 retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
261 if (retval != ERROR_OK)
262 return retval;
263
264 /* unlock option flash registers */
265 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
266 if (retval != ERROR_OK)
267 return retval;
268 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
269 if (retval != ERROR_OK)
270 return retval;
271
272 /* erase option bytes */
273 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_OPTWRE);
274 if (retval != ERROR_OK)
275 return retval;
276 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_STRT | FLASH_OPTWRE);
277 if (retval != ERROR_OK)
278 return retval;
279
280 retval = stm32x_wait_status_busy(bank, 10);
281 if (retval != ERROR_OK)
282 return retval;
283
284 /* clear readout protection and complementary option bytes
285 * this will also force a device unlock if set */
286 stm32x_info->option_bytes.RDP = 0x5AA5;
287
288 return ERROR_OK;
289 }
290
291 static int stm32x_write_options(struct flash_bank *bank)
292 {
293 struct stm32x_flash_bank *stm32x_info = NULL;
294 struct target *target = bank->target;
295
296 stm32x_info = bank->driver_priv;
297
298 /* unlock flash registers */
299 int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
300 if (retval != ERROR_OK)
301 return retval;
302 retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
303 if (retval != ERROR_OK)
304 return retval;
305
306 /* unlock option flash registers */
307 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
308 if (retval != ERROR_OK)
309 return retval;
310 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
311 if (retval != ERROR_OK)
312 return retval;
313
314 /* program option bytes */
315 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTPG | FLASH_OPTWRE);
316 if (retval != ERROR_OK)
317 return retval;
318
319 /* write user option byte */
320 retval = target_write_u16(target, STM32_OB_USER, stm32x_info->option_bytes.user_options);
321 if (retval != ERROR_OK)
322 return retval;
323
324 retval = stm32x_wait_status_busy(bank, 10);
325 if (retval != ERROR_OK)
326 return retval;
327
328 /* write protection byte 1 */
329 retval = target_write_u16(target, STM32_OB_WRP0, stm32x_info->option_bytes.protection[0]);
330 if (retval != ERROR_OK)
331 return retval;
332
333 retval = stm32x_wait_status_busy(bank, 10);
334 if (retval != ERROR_OK)
335 return retval;
336
337 /* write protection byte 2 */
338 retval = target_write_u16(target, STM32_OB_WRP1, stm32x_info->option_bytes.protection[1]);
339 if (retval != ERROR_OK)
340 return retval;
341
342 retval = stm32x_wait_status_busy(bank, 10);
343 if (retval != ERROR_OK)
344 return retval;
345
346 /* write protection byte 3 */
347 retval = target_write_u16(target, STM32_OB_WRP2, stm32x_info->option_bytes.protection[2]);
348 if (retval != ERROR_OK)
349 return retval;
350
351 retval = stm32x_wait_status_busy(bank, 10);
352 if (retval != ERROR_OK)
353 return retval;
354
355 /* write protection byte 4 */
356 retval = target_write_u16(target, STM32_OB_WRP3, stm32x_info->option_bytes.protection[3]);
357 if (retval != ERROR_OK)
358 return retval;
359
360 retval = stm32x_wait_status_busy(bank, 10);
361 if (retval != ERROR_OK)
362 return retval;
363
364 /* write readout protection bit */
365 retval = target_write_u16(target, STM32_OB_RDP, stm32x_info->option_bytes.RDP);
366 if (retval != ERROR_OK)
367 return retval;
368
369 retval = stm32x_wait_status_busy(bank, 10);
370 if (retval != ERROR_OK)
371 return retval;
372
373 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_LOCK);
374 if (retval != ERROR_OK)
375 return retval;
376
377 return ERROR_OK;
378 }
379
380 static int stm32x_protect_check(struct flash_bank *bank)
381 {
382 struct target *target = bank->target;
383 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
384
385 uint32_t protection;
386 int i, s;
387 int num_bits;
388 int set;
389
390 if (target->state != TARGET_HALTED) {
391 LOG_ERROR("Target not halted");
392 return ERROR_TARGET_NOT_HALTED;
393 }
394
395 int retval = stm32x_check_operation_supported(bank);
396 if (ERROR_OK != retval)
397 return retval;
398
399 /* medium density - each bit refers to a 4bank protection
400 * high density - each bit refers to a 2bank protection */
401 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
402 if (retval != ERROR_OK)
403 return retval;
404
405 /* medium density - each protection bit is for 4 * 1K pages
406 * high density - each protection bit is for 2 * 2K pages */
407 num_bits = (bank->num_sectors / stm32x_info->ppage_size);
408
409 if (stm32x_info->ppage_size == 2) {
410 /* high density flash/connectivity line protection */
411
412 set = 1;
413
414 if (protection & (1 << 31))
415 set = 0;
416
417 /* bit 31 controls sector 62 - 255 protection for high density
418 * bit 31 controls sector 62 - 127 protection for connectivity line */
419 for (s = 62; s < bank->num_sectors; s++)
420 bank->sectors[s].is_protected = set;
421
422 if (bank->num_sectors > 61)
423 num_bits = 31;
424
425 for (i = 0; i < num_bits; i++) {
426 set = 1;
427
428 if (protection & (1 << i))
429 set = 0;
430
431 for (s = 0; s < stm32x_info->ppage_size; s++)
432 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
433 }
434 } else {
435 /* low/medium density flash protection */
436 for (i = 0; i < num_bits; i++) {
437 set = 1;
438
439 if (protection & (1 << i))
440 set = 0;
441
442 for (s = 0; s < stm32x_info->ppage_size; s++)
443 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
444 }
445 }
446
447 return ERROR_OK;
448 }
449
450 static int stm32x_erase(struct flash_bank *bank, int first, int last)
451 {
452 struct target *target = bank->target;
453 int i;
454
455 if (bank->target->state != TARGET_HALTED) {
456 LOG_ERROR("Target not halted");
457 return ERROR_TARGET_NOT_HALTED;
458 }
459
460 if ((first == 0) && (last == (bank->num_sectors - 1)))
461 return stm32x_mass_erase(bank);
462
463 /* unlock flash registers */
464 int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
465 if (retval != ERROR_OK)
466 return retval;
467 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
468 if (retval != ERROR_OK)
469 return retval;
470
471 for (i = first; i <= last; i++) {
472 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER);
473 if (retval != ERROR_OK)
474 return retval;
475 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_AR),
476 bank->base + bank->sectors[i].offset);
477 if (retval != ERROR_OK)
478 return retval;
479 retval = target_write_u32(target,
480 stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER | FLASH_STRT);
481 if (retval != ERROR_OK)
482 return retval;
483
484 retval = stm32x_wait_status_busy(bank, 100);
485 if (retval != ERROR_OK)
486 return retval;
487
488 bank->sectors[i].is_erased = 1;
489 }
490
491 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
492 if (retval != ERROR_OK)
493 return retval;
494
495 return ERROR_OK;
496 }
497
498 static int stm32x_protect(struct flash_bank *bank, int set, int first, int last)
499 {
500 struct stm32x_flash_bank *stm32x_info = NULL;
501 struct target *target = bank->target;
502 uint16_t prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
503 int i, reg, bit;
504 int status;
505 uint32_t protection;
506
507 stm32x_info = bank->driver_priv;
508
509 if (target->state != TARGET_HALTED) {
510 LOG_ERROR("Target not halted");
511 return ERROR_TARGET_NOT_HALTED;
512 }
513
514 int retval = stm32x_check_operation_supported(bank);
515 if (ERROR_OK != retval)
516 return retval;
517
518 if ((first % stm32x_info->ppage_size) != 0) {
519 LOG_WARNING("aligned start protect sector to a %d sector boundary",
520 stm32x_info->ppage_size);
521 first = first - (first % stm32x_info->ppage_size);
522 }
523 if (((last + 1) % stm32x_info->ppage_size) != 0) {
524 LOG_WARNING("aligned end protect sector to a %d sector boundary",
525 stm32x_info->ppage_size);
526 last++;
527 last = last - (last % stm32x_info->ppage_size);
528 last--;
529 }
530
531 /* medium density - each bit refers to a 4bank protection
532 * high density - each bit refers to a 2bank protection */
533 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
534 if (retval != ERROR_OK)
535 return retval;
536
537 prot_reg[0] = (uint16_t)protection;
538 prot_reg[1] = (uint16_t)(protection >> 8);
539 prot_reg[2] = (uint16_t)(protection >> 16);
540 prot_reg[3] = (uint16_t)(protection >> 24);
541
542 if (stm32x_info->ppage_size == 2) {
543 /* high density flash */
544
545 /* bit 7 controls sector 62 - 255 protection */
546 if (last > 61) {
547 if (set)
548 prot_reg[3] &= ~(1 << 7);
549 else
550 prot_reg[3] |= (1 << 7);
551 }
552
553 if (first > 61)
554 first = 62;
555 if (last > 61)
556 last = 61;
557
558 for (i = first; i <= last; i++) {
559 reg = (i / stm32x_info->ppage_size) / 8;
560 bit = (i / stm32x_info->ppage_size) - (reg * 8);
561
562 if (set)
563 prot_reg[reg] &= ~(1 << bit);
564 else
565 prot_reg[reg] |= (1 << bit);
566 }
567 } else {
568 /* medium density flash */
569 for (i = first; i <= last; i++) {
570 reg = (i / stm32x_info->ppage_size) / 8;
571 bit = (i / stm32x_info->ppage_size) - (reg * 8);
572
573 if (set)
574 prot_reg[reg] &= ~(1 << bit);
575 else
576 prot_reg[reg] |= (1 << bit);
577 }
578 }
579
580 status = stm32x_erase_options(bank);
581 if (status != ERROR_OK)
582 return status;
583
584 stm32x_info->option_bytes.protection[0] = prot_reg[0];
585 stm32x_info->option_bytes.protection[1] = prot_reg[1];
586 stm32x_info->option_bytes.protection[2] = prot_reg[2];
587 stm32x_info->option_bytes.protection[3] = prot_reg[3];
588
589 return stm32x_write_options(bank);
590 }
591
592 static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer,
593 uint32_t offset, uint32_t count)
594 {
595 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
596 struct target *target = bank->target;
597 uint32_t buffer_size = 16384;
598 struct working_area *source;
599 uint32_t address = bank->base + offset;
600 struct reg_param reg_params[5];
601 struct armv7m_algorithm armv7m_info;
602 int retval = ERROR_OK;
603
604 /* see contrib/loaders/flash/stm32f1x.S for src */
605
606 static const uint8_t stm32x_flash_write_code[] = {
607 /* #define STM32_FLASH_CR_OFFSET 0x10 */
608 /* #define STM32_FLASH_SR_OFFSET 0x0C */
609 /* wait_fifo: */
610 0x16, 0x68, /* ldr r6, [r2, #0] */
611 0x00, 0x2e, /* cmp r6, #0 */
612 0x1a, 0xd0, /* beq exit */
613 0x55, 0x68, /* ldr r5, [r2, #4] */
614 0xb5, 0x42, /* cmp r5, r6 */
615 0xf9, 0xd0, /* beq wait_fifo */
616 0x01, 0x26, /* movs r6, #1 */
617 0x06, 0x61, /* str r6, [r0, #STM32_FLASH_CR_OFFSET] */
618 0x2e, 0x88, /* ldrh r6, [r5, #0] */
619 0x26, 0x80, /* strh r6, [r4, #0] */
620 0x02, 0x35, /* adds r5, #2 */
621 0x02, 0x34, /* adds r4, #2 */
622 /* busy: */
623 0xc6, 0x68, /* ldr r6, [r0, #STM32_FLASH_SR_OFFSET] */
624 0x01, 0x27, /* movs r7, #1 */
625 0x3e, 0x42, /* tst r6, r7 */
626 0xfb, 0xd1, /* bne busy */
627 0x14, 0x27, /* movs r7, #0x14 */
628 0x3e, 0x42, /* tst r6, r7 */
629 0x08, 0xd1, /* bne error */
630 0x9d, 0x42, /* cmp r5, r3 */
631 0x01, 0xd3, /* bcc no_wrap */
632 0x15, 0x46, /* mov r5, r2 */
633 0x08, 0x35, /* adds r5, #8 */
634 /* no_wrap: */
635 0x55, 0x60, /* str r5, [r2, #4] */
636 0x01, 0x39, /* subs r1, r1, #1 */
637 0x00, 0x29, /* cmp r1, #0 */
638 0x02, 0xd0, /* beq exit */
639 0xe3, 0xe7, /* b wait_fifo */
640 /* error: */
641 0x00, 0x20, /* movs r0, #0 */
642 0x50, 0x60, /* str r0, [r2, #4] */
643 /* exit: */
644 0x30, 0x46, /* mov r0, r6 */
645 0x00, 0xbe, /* bkpt #0 */
646 };
647
648 /* flash write code */
649 if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
650 &stm32x_info->write_algorithm) != ERROR_OK) {
651 LOG_WARNING("no working area available, can't do block memory writes");
652 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
653 };
654
655 retval = target_write_buffer(target, stm32x_info->write_algorithm->address,
656 sizeof(stm32x_flash_write_code), (uint8_t *)stm32x_flash_write_code);
657 if (retval != ERROR_OK)
658 return retval;
659
660 /* memory buffer */
661 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
662 buffer_size /= 2;
663 buffer_size &= ~3UL; /* Make sure it's 4 byte aligned */
664 if (buffer_size <= 256) {
665 /* if we already allocated the writing code, but failed to get a
666 * buffer, free the algorithm */
667 if (stm32x_info->write_algorithm)
668 target_free_working_area(target, stm32x_info->write_algorithm);
669
670 LOG_WARNING("no large enough working area available, can't do block memory writes");
671 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
672 }
673 };
674
675 /* Set up working area. First word is write pointer, second word is read pointer,
676 * rest is fifo data area. */
677 uint32_t wp_addr = source->address;
678 uint32_t rp_addr = source->address + 4;
679 uint32_t fifo_start_addr = source->address + 8;
680 uint32_t fifo_end_addr = source->address + source->size;
681
682 uint32_t wp = fifo_start_addr;
683 uint32_t rp = fifo_start_addr;
684
685 retval = target_write_u32(target, wp_addr, wp);
686 if (retval != ERROR_OK)
687 return retval;
688 retval = target_write_u32(target, rp_addr, rp);
689 if (retval != ERROR_OK)
690 return retval;
691
692 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* flash base (in), status (out) */
693 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* count (halfword-16bit) */
694 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT); /* buffer start */
695 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT); /* buffer end */
696 init_reg_param(&reg_params[4], "r4", 32, PARAM_IN_OUT); /* target address */
697
698 buf_set_u32(reg_params[0].value, 0, 32, stm32x_info->register_base);
699 buf_set_u32(reg_params[1].value, 0, 32, count);
700 buf_set_u32(reg_params[2].value, 0, 32, source->address);
701 buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
702 buf_set_u32(reg_params[4].value, 0, 32, address);
703
704 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
705 armv7m_info.core_mode = ARMV7M_MODE_ANY;
706
707 /* Start up algorithm on target and let it idle while writing the first chunk */
708 retval = target_start_algorithm(target, 0, NULL, 5, reg_params,
709 stm32x_info->write_algorithm->address,
710 0,
711 &armv7m_info);
712 if (retval != ERROR_OK) {
713 LOG_ERROR("error starting stm32x flash write algorithm");
714 goto cleanup;
715 }
716
717 while (count > 0) {
718 retval = target_read_u32(target, rp_addr, &rp);
719 if (retval != ERROR_OK) {
720 LOG_ERROR("failed to get read pointer");
721 break;
722 }
723
724 LOG_DEBUG("count 0x%"PRIx32" wp 0x%"PRIx32" rp 0x%"PRIx32, count, wp, rp);
725
726 if (rp == 0) {
727 LOG_ERROR("flash write algorithm aborted by target");
728 retval = ERROR_FLASH_OPERATION_FAILED;
729 break;
730 }
731
732 if ((rp & 1) || rp < fifo_start_addr || rp >= fifo_end_addr) {
733 LOG_ERROR("corrupted fifo read pointer 0x%"PRIx32, rp);
734 break;
735 }
736
737 /* Count the number of bytes available in the fifo without
738 * crossing the wrap around. Make sure to not fill it completely,
739 * because that would make wp == rp and that's the empty condition. */
740 uint32_t thisrun_bytes;
741 if (rp > wp)
742 thisrun_bytes = rp - wp - 2;
743 else if (rp > fifo_start_addr)
744 thisrun_bytes = fifo_end_addr - wp;
745 else
746 thisrun_bytes = fifo_end_addr - wp - 2;
747
748 if (thisrun_bytes == 0) {
749 /* Throttle polling a bit if transfer is (much) faster than flash
750 * programming. The exact delay shouldn't matter as long as it's
751 * less than buffer size / flash speed. This is very unlikely to
752 * run when using high latency connections such as USB. */
753 alive_sleep(10);
754 continue;
755 }
756
757 /* Limit to the amount of data we actually want to write */
758 if (thisrun_bytes > count * 2)
759 thisrun_bytes = count * 2;
760
761 /* Write data to fifo */
762 retval = target_write_buffer(target, wp, thisrun_bytes, buffer);
763 if (retval != ERROR_OK)
764 break;
765
766 /* Update counters and wrap write pointer */
767 buffer += thisrun_bytes;
768 count -= thisrun_bytes / 2;
769 wp += thisrun_bytes;
770 if (wp >= fifo_end_addr)
771 wp = fifo_start_addr;
772
773 /* Store updated write pointer to target */
774 retval = target_write_u32(target, wp_addr, wp);
775 if (retval != ERROR_OK)
776 break;
777 }
778
779 if (retval != ERROR_OK) {
780 /* abort flash write algorithm on target */
781 target_write_u32(target, wp_addr, 0);
782 }
783
784 int retval2 = target_wait_algorithm(target, 0, NULL, 5, reg_params,
785 0, 10000, &armv7m_info);
786 if (retval2 != ERROR_OK) {
787 LOG_ERROR("error waiting for stm32x flash write algorithm");
788 retval = retval2;
789 }
790
791 if (retval == ERROR_FLASH_OPERATION_FAILED) {
792 LOG_ERROR("flash write failed at address 0x%"PRIx32,
793 buf_get_u32(reg_params[4].value, 0, 32));
794
795 if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_PGERR) {
796 LOG_ERROR("flash memory not erased before writing");
797 /* Clear but report errors */
798 target_write_u32(target, STM32_FLASH_SR_B0, FLASH_PGERR);
799 }
800
801 if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_WRPRTERR) {
802 LOG_ERROR("flash memory write protected");
803 /* Clear but report errors */
804 target_write_u32(target, STM32_FLASH_SR_B0, FLASH_WRPRTERR);
805 }
806 }
807
808 cleanup:
809 target_free_working_area(target, source);
810 target_free_working_area(target, stm32x_info->write_algorithm);
811
812 destroy_reg_param(&reg_params[0]);
813 destroy_reg_param(&reg_params[1]);
814 destroy_reg_param(&reg_params[2]);
815 destroy_reg_param(&reg_params[3]);
816 destroy_reg_param(&reg_params[4]);
817
818 return retval;
819 }
820
821 static int stm32x_write(struct flash_bank *bank, uint8_t *buffer,
822 uint32_t offset, uint32_t count)
823 {
824 struct target *target = bank->target;
825 uint32_t words_remaining = (count / 2);
826 uint32_t bytes_remaining = (count & 0x00000001);
827 uint32_t address = bank->base + offset;
828 uint32_t bytes_written = 0;
829 int retval;
830
831 if (bank->target->state != TARGET_HALTED) {
832 LOG_ERROR("Target not halted");
833 return ERROR_TARGET_NOT_HALTED;
834 }
835
836 if (offset & 0x1) {
837 LOG_WARNING("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
838 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
839 }
840
841 /* unlock flash registers */
842 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
843 if (retval != ERROR_OK)
844 return retval;
845 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
846 if (retval != ERROR_OK)
847 return retval;
848
849 /* multiple half words (2-byte) to be programmed? */
850 if (words_remaining > 0) {
851 /* try using a block write */
852 retval = stm32x_write_block(bank, buffer, offset, words_remaining);
853 if (retval != ERROR_OK) {
854 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
855 /* if block write failed (no sufficient working area),
856 * we use normal (slow) single dword accesses */
857 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
858 }
859 } else {
860 buffer += words_remaining * 2;
861 address += words_remaining * 2;
862 words_remaining = 0;
863 }
864 }
865
866 if ((retval != ERROR_OK) && (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE))
867 return retval;
868
869 while (words_remaining > 0) {
870 uint16_t value;
871 memcpy(&value, buffer + bytes_written, sizeof(uint16_t));
872
873 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PG);
874 if (retval != ERROR_OK)
875 return retval;
876 retval = target_write_u16(target, address, value);
877 if (retval != ERROR_OK)
878 return retval;
879
880 retval = stm32x_wait_status_busy(bank, 5);
881 if (retval != ERROR_OK)
882 return retval;
883
884 bytes_written += 2;
885 words_remaining--;
886 address += 2;
887 }
888
889 if (bytes_remaining) {
890 uint16_t value = 0xffff;
891 memcpy(&value, buffer + bytes_written, bytes_remaining);
892
893 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PG);
894 if (retval != ERROR_OK)
895 return retval;
896 retval = target_write_u16(target, address, value);
897 if (retval != ERROR_OK)
898 return retval;
899
900 retval = stm32x_wait_status_busy(bank, 5);
901 if (retval != ERROR_OK)
902 return retval;
903 }
904
905 return target_write_u32(target, STM32_FLASH_CR_B0, FLASH_LOCK);
906 }
907
908 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id)
909 {
910 /* This check the device CPUID core register to detect
911 * the M0 from the M3 devices. */
912
913 struct target *target = bank->target;
914 uint32_t cpuid, device_id_register = 0;
915
916 /* Get the CPUID from the ARM Core
917 * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0432c/DDI0432C_cortex_m0_r0p0_trm.pdf 4.2.1 */
918 int retval = target_read_u32(target, 0xE000ED00, &cpuid);
919 if (retval != ERROR_OK)
920 return retval;
921
922 if (((cpuid >> 4) & 0xFFF) == 0xC20) {
923 /* 0xC20 is M0 devices */
924 device_id_register = 0x40015800;
925 } else if (((cpuid >> 4) & 0xFFF) == 0xC23) {
926 /* 0xC23 is M3 devices */
927 device_id_register = 0xE0042000;
928 } else {
929 LOG_ERROR("Cannot identify target as a stm32x");
930 return ERROR_FAIL;
931 }
932
933 /* read stm32 device id register */
934 retval = target_read_u32(target, device_id_register, device_id);
935 if (retval != ERROR_OK)
936 return retval;
937
938 return retval;
939 }
940
941 static int stm32x_probe(struct flash_bank *bank)
942 {
943 struct target *target = bank->target;
944 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
945 int i;
946 uint16_t flash_size_in_kb;
947 uint32_t device_id;
948 int page_size;
949 uint32_t base_address = 0x08000000;
950
951
952 stm32x_info->probed = 0;
953 stm32x_info->register_base = FLASH_REG_BASE_B0;
954
955 /* read stm32 device id register */
956 int retval = stm32x_get_device_id(bank, &device_id);
957 if (retval != ERROR_OK)
958 return retval;
959
960 LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
961
962 /* get flash size from target. */
963 retval = target_read_u16(target, 0x1FFFF7E0, &flash_size_in_kb);
964 if (retval != ERROR_OK) {
965 LOG_WARNING("failed reading flash size, default to max target family");
966 /* failed reading flash size, default to max target family */
967 flash_size_in_kb = 0xffff;
968 }
969
970 if ((device_id & 0xfff) == 0x410) {
971 /* medium density - we have 1k pages
972 * 4 pages for a protection area */
973 page_size = 1024;
974 stm32x_info->ppage_size = 4;
975
976 /* check for early silicon */
977 if (flash_size_in_kb == 0xffff) {
978 /* number of sectors incorrect on revA */
979 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 128k flash");
980 flash_size_in_kb = 128;
981 }
982 } else if ((device_id & 0xfff) == 0x412) {
983 /* low density - we have 1k pages
984 * 4 pages for a protection area */
985 page_size = 1024;
986 stm32x_info->ppage_size = 4;
987
988 /* check for early silicon */
989 if (flash_size_in_kb == 0xffff) {
990 /* number of sectors incorrect on revA */
991 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 32k flash");
992 flash_size_in_kb = 32;
993 }
994 } else if ((device_id & 0xfff) == 0x414) {
995 /* high density - we have 2k pages
996 * 2 pages for a protection area */
997 page_size = 2048;
998 stm32x_info->ppage_size = 2;
999
1000 /* check for early silicon */
1001 if (flash_size_in_kb == 0xffff) {
1002 /* number of sectors incorrect on revZ */
1003 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 512k flash");
1004 flash_size_in_kb = 512;
1005 }
1006 } else if ((device_id & 0xfff) == 0x418) {
1007 /* connectivity line density - we have 2k pages
1008 * 2 pages for a protection area */
1009 page_size = 2048;
1010 stm32x_info->ppage_size = 2;
1011
1012 /* check for early silicon */
1013 if (flash_size_in_kb == 0xffff) {
1014 /* number of sectors incorrect on revZ */
1015 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 256k flash");
1016 flash_size_in_kb = 256;
1017 }
1018 } else if ((device_id & 0xfff) == 0x420) {
1019 /* value line density - we have 1k pages
1020 * 4 pages for a protection area */
1021 page_size = 1024;
1022 stm32x_info->ppage_size = 4;
1023
1024 /* check for early silicon */
1025 if (flash_size_in_kb == 0xffff) {
1026 /* number of sectors may be incorrrect on early silicon */
1027 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 128k flash");
1028 flash_size_in_kb = 128;
1029 }
1030 } else if ((device_id & 0xfff) == 0x428) {
1031 /* value line High density - we have 2k pages
1032 * 4 pages for a protection area */
1033 page_size = 2048;
1034 stm32x_info->ppage_size = 4;
1035
1036 /* check for early silicon */
1037 if (flash_size_in_kb == 0xffff) {
1038 /* number of sectors may be incorrrect on early silicon */
1039 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 128k flash");
1040 flash_size_in_kb = 128;
1041 }
1042 } else if ((device_id & 0xfff) == 0x430) {
1043 /* xl line density - we have 2k pages
1044 * 2 pages for a protection area */
1045 page_size = 2048;
1046 stm32x_info->ppage_size = 2;
1047 stm32x_info->has_dual_banks = true;
1048
1049 /* check for early silicon */
1050 if (flash_size_in_kb == 0xffff) {
1051 /* number of sectors may be incorrrect on early silicon */
1052 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 1024k flash");
1053 flash_size_in_kb = 1024;
1054 }
1055
1056 /* split reported size into matching bank */
1057 if (bank->base != 0x08080000) {
1058 /* bank 0 will be fixed 512k */
1059 flash_size_in_kb = 512;
1060 } else {
1061 flash_size_in_kb -= 512;
1062 /* bank1 also uses a register offset */
1063 stm32x_info->register_base = FLASH_REG_BASE_B1;
1064 base_address = 0x08080000;
1065 }
1066 } else if ((device_id & 0xfff) == 0x440) {
1067 /* stm32f0x - we have 1k pages
1068 * 4 pages for a protection area */
1069 page_size = 1024;
1070 stm32x_info->ppage_size = 4;
1071
1072 /* check for early silicon */
1073 if (flash_size_in_kb == 0xffff) {
1074 /* number of sectors incorrect on revZ */
1075 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 64k flash");
1076 flash_size_in_kb = 64;
1077 }
1078 } else {
1079 LOG_WARNING("Cannot identify target as a STM32 family.");
1080 return ERROR_FAIL;
1081 }
1082
1083 LOG_INFO("flash size = %dkbytes", flash_size_in_kb);
1084
1085 /* did we assign flash size? */
1086 assert(flash_size_in_kb != 0xffff);
1087
1088 /* calculate numbers of pages */
1089 int num_pages = flash_size_in_kb * 1024 / page_size;
1090
1091 /* check that calculation result makes sense */
1092 assert(num_pages > 0);
1093
1094 if (bank->sectors) {
1095 free(bank->sectors);
1096 bank->sectors = NULL;
1097 }
1098
1099 bank->base = base_address;
1100 bank->size = (num_pages * page_size);
1101 bank->num_sectors = num_pages;
1102 bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
1103
1104 for (i = 0; i < num_pages; i++) {
1105 bank->sectors[i].offset = i * page_size;
1106 bank->sectors[i].size = page_size;
1107 bank->sectors[i].is_erased = -1;
1108 bank->sectors[i].is_protected = 1;
1109 }
1110
1111 stm32x_info->probed = 1;
1112
1113 return ERROR_OK;
1114 }
1115
1116 static int stm32x_auto_probe(struct flash_bank *bank)
1117 {
1118 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
1119 if (stm32x_info->probed)
1120 return ERROR_OK;
1121 return stm32x_probe(bank);
1122 }
1123
1124 #if 0
1125 COMMAND_HANDLER(stm32x_handle_part_id_command)
1126 {
1127 return ERROR_OK;
1128 }
1129 #endif
1130
1131 static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
1132 {
1133 uint32_t device_id;
1134 int printed;
1135
1136 /* read stm32 device id register */
1137 int retval = stm32x_get_device_id(bank, &device_id);
1138 if (retval != ERROR_OK)
1139 return retval;
1140
1141 if ((device_id & 0xfff) == 0x410) {
1142 printed = snprintf(buf, buf_size, "stm32x (Medium Density) - Rev: ");
1143 buf += printed;
1144 buf_size -= printed;
1145
1146 switch (device_id >> 16) {
1147 case 0x0000:
1148 snprintf(buf, buf_size, "A");
1149 break;
1150
1151 case 0x2000:
1152 snprintf(buf, buf_size, "B");
1153 break;
1154
1155 case 0x2001:
1156 snprintf(buf, buf_size, "Z");
1157 break;
1158
1159 case 0x2003:
1160 snprintf(buf, buf_size, "Y");
1161 break;
1162
1163 default:
1164 snprintf(buf, buf_size, "unknown");
1165 break;
1166 }
1167 } else if ((device_id & 0xfff) == 0x412) {
1168 printed = snprintf(buf, buf_size, "stm32x (Low Density) - Rev: ");
1169 buf += printed;
1170 buf_size -= printed;
1171
1172 switch (device_id >> 16) {
1173 case 0x1000:
1174 snprintf(buf, buf_size, "A");
1175 break;
1176
1177 default:
1178 snprintf(buf, buf_size, "unknown");
1179 break;
1180 }
1181 } else if ((device_id & 0xfff) == 0x414) {
1182 printed = snprintf(buf, buf_size, "stm32x (High Density) - Rev: ");
1183 buf += printed;
1184 buf_size -= printed;
1185
1186 switch (device_id >> 16) {
1187 case 0x1000:
1188 snprintf(buf, buf_size, "A");
1189 break;
1190
1191 case 0x1001:
1192 snprintf(buf, buf_size, "Z");
1193 break;
1194
1195 default:
1196 snprintf(buf, buf_size, "unknown");
1197 break;
1198 }
1199 } else if ((device_id & 0xfff) == 0x418) {
1200 printed = snprintf(buf, buf_size, "stm32x (Connectivity) - Rev: ");
1201 buf += printed;
1202 buf_size -= printed;
1203
1204 switch (device_id >> 16) {
1205 case 0x1000:
1206 snprintf(buf, buf_size, "A");
1207 break;
1208
1209 case 0x1001:
1210 snprintf(buf, buf_size, "Z");
1211 break;
1212
1213 default:
1214 snprintf(buf, buf_size, "unknown");
1215 break;
1216 }
1217 } else if ((device_id & 0xfff) == 0x420) {
1218 printed = snprintf(buf, buf_size, "stm32x (Value) - Rev: ");
1219 buf += printed;
1220 buf_size -= printed;
1221
1222 switch (device_id >> 16) {
1223 case 0x1000:
1224 snprintf(buf, buf_size, "A");
1225 break;
1226
1227 case 0x1001:
1228 snprintf(buf, buf_size, "Z");
1229 break;
1230
1231 default:
1232 snprintf(buf, buf_size, "unknown");
1233 break;
1234 }
1235 } else if ((device_id & 0xfff) == 0x428) {
1236 printed = snprintf(buf, buf_size, "stm32x (Value HD) - Rev: ");
1237 buf += printed;
1238 buf_size -= printed;
1239
1240 switch (device_id >> 16) {
1241 case 0x1000:
1242 snprintf(buf, buf_size, "A");
1243 break;
1244
1245 case 0x1001:
1246 snprintf(buf, buf_size, "Z");
1247 break;
1248
1249 default:
1250 snprintf(buf, buf_size, "unknown");
1251 break;
1252 }
1253 } else if ((device_id & 0xfff) == 0x430) {
1254 printed = snprintf(buf, buf_size, "stm32x (XL) - Rev: ");
1255 buf += printed;
1256 buf_size -= printed;
1257
1258 switch (device_id >> 16) {
1259 case 0x1000:
1260 snprintf(buf, buf_size, "A");
1261 break;
1262
1263 default:
1264 snprintf(buf, buf_size, "unknown");
1265 break;
1266 }
1267 } else if ((device_id & 0xfff) == 0x440) {
1268 printed = snprintf(buf, buf_size, "stm32f0x - Rev: ");
1269 buf += printed;
1270 buf_size -= printed;
1271
1272 switch (device_id >> 16) {
1273 case 0x1000:
1274 snprintf(buf, buf_size, "A");
1275 break;
1276
1277 default:
1278 snprintf(buf, buf_size, "unknown");
1279 break;
1280 }
1281 } else {
1282 snprintf(buf, buf_size, "Cannot identify target as a stm32x\n");
1283 return ERROR_FAIL;
1284 }
1285
1286 return ERROR_OK;
1287 }
1288
1289 COMMAND_HANDLER(stm32x_handle_lock_command)
1290 {
1291 struct target *target = NULL;
1292 struct stm32x_flash_bank *stm32x_info = NULL;
1293
1294 if (CMD_ARGC < 1)
1295 return ERROR_COMMAND_SYNTAX_ERROR;
1296
1297 struct flash_bank *bank;
1298 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1299 if (ERROR_OK != retval)
1300 return retval;
1301
1302 stm32x_info = bank->driver_priv;
1303
1304 target = bank->target;
1305
1306 if (target->state != TARGET_HALTED) {
1307 LOG_ERROR("Target not halted");
1308 return ERROR_TARGET_NOT_HALTED;
1309 }
1310
1311 retval = stm32x_check_operation_supported(bank);
1312 if (ERROR_OK != retval)
1313 return retval;
1314
1315 if (stm32x_erase_options(bank) != ERROR_OK) {
1316 command_print(CMD_CTX, "stm32x failed to erase options");
1317 return ERROR_OK;
1318 }
1319
1320 /* set readout protection */
1321 stm32x_info->option_bytes.RDP = 0;
1322
1323 if (stm32x_write_options(bank) != ERROR_OK) {
1324 command_print(CMD_CTX, "stm32x failed to lock device");
1325 return ERROR_OK;
1326 }
1327
1328 command_print(CMD_CTX, "stm32x locked");
1329
1330 return ERROR_OK;
1331 }
1332
1333 COMMAND_HANDLER(stm32x_handle_unlock_command)
1334 {
1335 struct target *target = NULL;
1336
1337 if (CMD_ARGC < 1)
1338 return ERROR_COMMAND_SYNTAX_ERROR;
1339
1340 struct flash_bank *bank;
1341 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1342 if (ERROR_OK != retval)
1343 return retval;
1344
1345 target = bank->target;
1346
1347 if (target->state != TARGET_HALTED) {
1348 LOG_ERROR("Target not halted");
1349 return ERROR_TARGET_NOT_HALTED;
1350 }
1351
1352 retval = stm32x_check_operation_supported(bank);
1353 if (ERROR_OK != retval)
1354 return retval;
1355
1356 if (stm32x_erase_options(bank) != ERROR_OK) {
1357 command_print(CMD_CTX, "stm32x failed to unlock device");
1358 return ERROR_OK;
1359 }
1360
1361 if (stm32x_write_options(bank) != ERROR_OK) {
1362 command_print(CMD_CTX, "stm32x failed to lock device");
1363 return ERROR_OK;
1364 }
1365
1366 command_print(CMD_CTX, "stm32x unlocked.\n"
1367 "INFO: a reset or power cycle is required "
1368 "for the new settings to take effect.");
1369
1370 return ERROR_OK;
1371 }
1372
1373 COMMAND_HANDLER(stm32x_handle_options_read_command)
1374 {
1375 uint32_t optionbyte;
1376 struct target *target = NULL;
1377 struct stm32x_flash_bank *stm32x_info = NULL;
1378
1379 if (CMD_ARGC < 1)
1380 return ERROR_COMMAND_SYNTAX_ERROR;
1381
1382 struct flash_bank *bank;
1383 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1384 if (ERROR_OK != retval)
1385 return retval;
1386
1387 stm32x_info = bank->driver_priv;
1388
1389 target = bank->target;
1390
1391 if (target->state != TARGET_HALTED) {
1392 LOG_ERROR("Target not halted");
1393 return ERROR_TARGET_NOT_HALTED;
1394 }
1395
1396 retval = stm32x_check_operation_supported(bank);
1397 if (ERROR_OK != retval)
1398 return retval;
1399
1400 retval = target_read_u32(target, STM32_FLASH_OBR_B0, &optionbyte);
1401 if (retval != ERROR_OK)
1402 return retval;
1403 command_print(CMD_CTX, "Option Byte: 0x%" PRIx32 "", optionbyte);
1404
1405 if (buf_get_u32((uint8_t *)&optionbyte, OPT_ERROR, 1))
1406 command_print(CMD_CTX, "Option Byte Complement Error");
1407
1408 if (buf_get_u32((uint8_t *)&optionbyte, OPT_READOUT, 1))
1409 command_print(CMD_CTX, "Readout Protection On");
1410 else
1411 command_print(CMD_CTX, "Readout Protection Off");
1412
1413 if (buf_get_u32((uint8_t *)&optionbyte, OPT_RDWDGSW, 1))
1414 command_print(CMD_CTX, "Software Watchdog");
1415 else
1416 command_print(CMD_CTX, "Hardware Watchdog");
1417
1418 if (buf_get_u32((uint8_t *)&optionbyte, OPT_RDRSTSTOP, 1))
1419 command_print(CMD_CTX, "Stop: No reset generated");
1420 else
1421 command_print(CMD_CTX, "Stop: Reset generated");
1422
1423 if (buf_get_u32((uint8_t *)&optionbyte, OPT_RDRSTSTDBY, 1))
1424 command_print(CMD_CTX, "Standby: No reset generated");
1425 else
1426 command_print(CMD_CTX, "Standby: Reset generated");
1427
1428 if (stm32x_info->has_dual_banks) {
1429 if (buf_get_u32((uint8_t *)&optionbyte, OPT_BFB2, 1))
1430 command_print(CMD_CTX, "Boot: Bank 0");
1431 else
1432 command_print(CMD_CTX, "Boot: Bank 1");
1433 }
1434
1435 return ERROR_OK;
1436 }
1437
1438 COMMAND_HANDLER(stm32x_handle_options_write_command)
1439 {
1440 struct target *target = NULL;
1441 struct stm32x_flash_bank *stm32x_info = NULL;
1442 uint16_t optionbyte = 0xF8;
1443
1444 if (CMD_ARGC < 4)
1445 return ERROR_COMMAND_SYNTAX_ERROR;
1446
1447 struct flash_bank *bank;
1448 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1449 if (ERROR_OK != retval)
1450 return retval;
1451
1452 stm32x_info = bank->driver_priv;
1453
1454 target = bank->target;
1455
1456 if (target->state != TARGET_HALTED) {
1457 LOG_ERROR("Target not halted");
1458 return ERROR_TARGET_NOT_HALTED;
1459 }
1460
1461 retval = stm32x_check_operation_supported(bank);
1462 if (ERROR_OK != retval)
1463 return retval;
1464
1465 /* REVISIT: ignores some options which we will display...
1466 * and doesn't insist on the specified syntax.
1467 */
1468
1469 /* OPT_RDWDGSW */
1470 if (strcmp(CMD_ARGV[1], "SWWDG") == 0)
1471 optionbyte |= (1 << 0);
1472 else /* REVISIT must be "HWWDG" then ... */
1473 optionbyte &= ~(1 << 0);
1474
1475 /* OPT_RDRSTSTOP */
1476 if (strcmp(CMD_ARGV[2], "NORSTSTOP") == 0)
1477 optionbyte |= (1 << 1);
1478 else /* REVISIT must be "RSTSTNDBY" then ... */
1479 optionbyte &= ~(1 << 1);
1480
1481 /* OPT_RDRSTSTDBY */
1482 if (strcmp(CMD_ARGV[3], "NORSTSTNDBY") == 0)
1483 optionbyte |= (1 << 2);
1484 else /* REVISIT must be "RSTSTOP" then ... */
1485 optionbyte &= ~(1 << 2);
1486
1487 if (CMD_ARGC > 4 && stm32x_info->has_dual_banks) {
1488 /* OPT_BFB2 */
1489 if (strcmp(CMD_ARGV[4], "BOOT0") == 0)
1490 optionbyte |= (1 << 3);
1491 else
1492 optionbyte &= ~(1 << 3);
1493 }
1494
1495 if (stm32x_erase_options(bank) != ERROR_OK) {
1496 command_print(CMD_CTX, "stm32x failed to erase options");
1497 return ERROR_OK;
1498 }
1499
1500 stm32x_info->option_bytes.user_options = optionbyte;
1501
1502 if (stm32x_write_options(bank) != ERROR_OK) {
1503 command_print(CMD_CTX, "stm32x failed to write options");
1504 return ERROR_OK;
1505 }
1506
1507 command_print(CMD_CTX, "stm32x write options complete.\n"
1508 "INFO: a reset or power cycle is required "
1509 "for the new settings to take effect.");
1510
1511 return ERROR_OK;
1512 }
1513
1514 static int stm32x_mass_erase(struct flash_bank *bank)
1515 {
1516 struct target *target = bank->target;
1517
1518 if (target->state != TARGET_HALTED) {
1519 LOG_ERROR("Target not halted");
1520 return ERROR_TARGET_NOT_HALTED;
1521 }
1522
1523 /* unlock option flash registers */
1524 int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
1525 if (retval != ERROR_OK)
1526 return retval;
1527 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
1528 if (retval != ERROR_OK)
1529 return retval;
1530
1531 /* mass erase flash memory */
1532 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_MER);
1533 if (retval != ERROR_OK)
1534 return retval;
1535 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR),
1536 FLASH_MER | FLASH_STRT);
1537 if (retval != ERROR_OK)
1538 return retval;
1539
1540 retval = stm32x_wait_status_busy(bank, 100);
1541 if (retval != ERROR_OK)
1542 return retval;
1543
1544 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
1545 if (retval != ERROR_OK)
1546 return retval;
1547
1548 return ERROR_OK;
1549 }
1550
1551 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
1552 {
1553 int i;
1554
1555 if (CMD_ARGC < 1)
1556 return ERROR_COMMAND_SYNTAX_ERROR;
1557
1558 struct flash_bank *bank;
1559 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1560 if (ERROR_OK != retval)
1561 return retval;
1562
1563 retval = stm32x_mass_erase(bank);
1564 if (retval == ERROR_OK) {
1565 /* set all sectors as erased */
1566 for (i = 0; i < bank->num_sectors; i++)
1567 bank->sectors[i].is_erased = 1;
1568
1569 command_print(CMD_CTX, "stm32x mass erase complete");
1570 } else
1571 command_print(CMD_CTX, "stm32x mass erase failed");
1572
1573 return retval;
1574 }
1575
1576 static const struct command_registration stm32x_exec_command_handlers[] = {
1577 {
1578 .name = "lock",
1579 .handler = stm32x_handle_lock_command,
1580 .mode = COMMAND_EXEC,
1581 .usage = "bank_id",
1582 .help = "Lock entire flash device.",
1583 },
1584 {
1585 .name = "unlock",
1586 .handler = stm32x_handle_unlock_command,
1587 .mode = COMMAND_EXEC,
1588 .usage = "bank_id",
1589 .help = "Unlock entire protected flash device.",
1590 },
1591 {
1592 .name = "mass_erase",
1593 .handler = stm32x_handle_mass_erase_command,
1594 .mode = COMMAND_EXEC,
1595 .usage = "bank_id",
1596 .help = "Erase entire flash device.",
1597 },
1598 {
1599 .name = "options_read",
1600 .handler = stm32x_handle_options_read_command,
1601 .mode = COMMAND_EXEC,
1602 .usage = "bank_id",
1603 .help = "Read and display device option byte.",
1604 },
1605 {
1606 .name = "options_write",
1607 .handler = stm32x_handle_options_write_command,
1608 .mode = COMMAND_EXEC,
1609 .usage = "bank_id ('SWWDG'|'HWWDG') "
1610 "('RSTSTNDBY'|'NORSTSTNDBY') "
1611 "('RSTSTOP'|'NORSTSTOP')",
1612 .help = "Replace bits in device option byte.",
1613 },
1614 COMMAND_REGISTRATION_DONE
1615 };
1616
1617 static const struct command_registration stm32x_command_handlers[] = {
1618 {
1619 .name = "stm32f1x",
1620 .mode = COMMAND_ANY,
1621 .help = "stm32f1x flash command group",
1622 .usage = "",
1623 .chain = stm32x_exec_command_handlers,
1624 },
1625 COMMAND_REGISTRATION_DONE
1626 };
1627
1628 struct flash_driver stm32f1x_flash = {
1629 .name = "stm32f1x",
1630 .commands = stm32x_command_handlers,
1631 .flash_bank_command = stm32x_flash_bank_command,
1632 .erase = stm32x_erase,
1633 .protect = stm32x_protect,
1634 .write = stm32x_write,
1635 .read = default_flash_read,
1636 .probe = stm32x_probe,
1637 .auto_probe = stm32x_auto_probe,
1638 .erase_check = default_flash_mem_blank_check,
1639 .protect_check = stm32x_protect_check,
1640 .info = get_stm32x_info,
1641 };
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