1 /***************************************************************************
2 * Copyright (C) 2017 by STMicroelectronics *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
16 ***************************************************************************/
22 #include <helper/binarybuffer.h>
23 #include <target/algorithm.h>
24 #include <target/armv7m.h>
27 /* Erase time can be as high as 1000ms, 10x this and it's toast... */
28 #define FLASH_ERASE_TIMEOUT 10000
29 #define FLASH_WRITE_TIMEOUT 5
32 /* Same Flash registers for both banks, */
33 /* access depends on Flash Base address */
34 #define FLASH_ACR 0x00
35 #define FLASH_KEYR 0x04
36 #define FLASH_OPTKEYR 0x08
39 #define FLASH_CCR 0x14
40 #define FLASH_OPTCR 0x18
41 #define FLASH_OPTSR_CUR 0x1C
42 #define FLASH_OPTSR_PRG 0x20
43 #define FLASH_OPTCCR 0x24
44 #define FLASH_WPSN_CUR 0x38
45 #define FLASH_WPSN_PRG 0x3C
48 /* FLASH_CR register bits */
49 #define FLASH_LOCK (1 << 0)
50 #define FLASH_PG (1 << 1)
51 #define FLASH_SER (1 << 2)
52 #define FLASH_BER (1 << 3)
53 #define FLASH_PSIZE_8 (0 << 4)
54 #define FLASH_PSIZE_16 (1 << 4)
55 #define FLASH_PSIZE_32 (2 << 4)
56 #define FLASH_PSIZE_64 (3 << 4)
57 #define FLASH_FW (1 << 6)
58 #define FLASH_START (1 << 7)
60 /* FLASH_SR register bits */
61 #define FLASH_BSY (1 << 0) /* Operation in progress */
62 #define FLASH_QW (1 << 2) /* Operation queue in progress */
63 #define FLASH_WRPERR (1 << 17) /* Write protection error */
64 #define FLASH_PGSERR (1 << 18) /* Programming sequence error */
65 #define FLASH_STRBERR (1 << 19) /* Strobe error */
66 #define FLASH_INCERR (1 << 21) /* Inconsistency error */
67 #define FLASH_OPERR (1 << 22) /* Operation error */
68 #define FLASH_RDPERR (1 << 23) /* Read Protection error */
69 #define FLASH_RDSERR (1 << 24) /* Secure Protection error */
70 #define FLASH_SNECCERR (1 << 25) /* Single ECC error */
71 #define FLASH_DBECCERR (1 << 26) /* Double ECC error */
73 #define FLASH_ERROR (FLASH_WRPERR | FLASH_PGSERR | FLASH_STRBERR | FLASH_INCERR | FLASH_OPERR | \
74 FLASH_RDPERR | FLASH_RDSERR | FLASH_SNECCERR | FLASH_DBECCERR)
76 /* FLASH_OPTCR register bits */
77 #define OPT_LOCK (1 << 0)
78 #define OPT_START (1 << 1)
80 /* FLASH_OPTSR register bits */
81 #define OPT_BSY (1 << 0)
83 #define OPT_RDP_MASK (0xff << OPT_RDP_POS)
84 #define OPT_OPTCHANGEERR (1 << 30)
86 /* FLASH_OPTCCR register bits */
87 #define OPT_CLR_OPTCHANGEERR (1 << 30)
89 /* register unlock keys */
90 #define KEY1 0x45670123
91 #define KEY2 0xCDEF89AB
93 /* option register unlock key */
94 #define OPTKEY1 0x08192A3B
95 #define OPTKEY2 0x4C5D6E7F
97 #define DBGMCU_IDCODE_REGISTER 0x5C001000
98 #define FLASH_BANK0_ADDRESS 0x08000000
99 #define FLASH_BANK1_ADDRESS 0x08100000
100 #define FLASH_REG_BASE_B0 0x52002000
101 #define FLASH_REG_BASE_B1 0x52002100
103 struct stm32h7x_rev
{
108 /* stm32h7x_part_info permits the store each device information and specificities.
109 * the default unit is byte unless the suffix '_kb' is used. */
111 struct stm32h7x_part_info
{
113 const char *device_str
;
114 const struct stm32h7x_rev
*revs
;
116 unsigned int page_size_kb
;
117 unsigned int block_size
; /* flash write word size in bytes */
118 uint16_t max_flash_size_kb
;
119 uint8_t has_dual_bank
;
120 uint16_t max_bank_size_kb
; /* Used when has_dual_bank is true */
121 uint32_t flash_regs_base
; /* Flash controller registers location */
122 uint32_t fsize_addr
; /* Location of FSIZE register */
123 uint32_t wps_group_size
; /* write protection group sectors' count */
125 /* function to compute flash_cr register values */
126 uint32_t (*compute_flash_cr
)(uint32_t cmd
, int snb
);
129 struct stm32h7x_flash_bank
{
132 uint32_t user_bank_size
;
133 uint32_t flash_regs_base
; /* Address of flash reg controller */
134 const struct stm32h7x_part_info
*part_info
;
137 enum stm32h7x_opt_rdp
{
143 static const struct stm32h7x_rev stm32_450_revs
[] = {
144 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x1003, "Y" }, { 0x2001, "X" }, { 0x2003, "V" },
147 static const struct stm32h7x_rev stm32_480_revs
[] = {
151 static uint32_t stm32x_compute_flash_cr_450(uint32_t cmd
, int snb
)
153 return cmd
| (snb
<< 8);
156 static uint32_t stm32x_compute_flash_cr_480(uint32_t cmd
, int snb
)
158 /* save FW and START bits, to be right shifted by 2 bits later */
159 const uint32_t tmp
= cmd
& (FLASH_FW
| FLASH_START
);
161 /* mask parallelism (ignored), FW and START bits */
162 cmd
&= ~(FLASH_PSIZE_64
| FLASH_FW
| FLASH_START
);
164 return cmd
| (tmp
>> 2) | (snb
<< 6);
167 static const struct stm32h7x_part_info stm32h7x_parts
[] = {
170 .revs
= stm32_450_revs
,
171 .num_revs
= ARRAY_SIZE(stm32_450_revs
),
172 .device_str
= "STM32H74x/75x",
175 .max_flash_size_kb
= 2048,
176 .max_bank_size_kb
= 1024,
178 .flash_regs_base
= FLASH_REG_BASE_B0
,
179 .fsize_addr
= 0x1FF1E880,
182 .compute_flash_cr
= stm32x_compute_flash_cr_450
,
186 .revs
= stm32_480_revs
,
187 .num_revs
= ARRAY_SIZE(stm32_480_revs
),
188 .device_str
= "STM32H7Ax/7Bx",
191 .max_flash_size_kb
= 2048,
192 .max_bank_size_kb
= 1024,
194 .flash_regs_base
= FLASH_REG_BASE_B0
,
195 .fsize_addr
= 0x08FFF80C,
197 .wps_mask
= 0xFFFFFFFF,
198 .compute_flash_cr
= stm32x_compute_flash_cr_480
,
202 /* flash bank stm32x <base> <size> 0 0 <target#> */
204 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command
)
206 struct stm32h7x_flash_bank
*stm32x_info
;
209 return ERROR_COMMAND_SYNTAX_ERROR
;
211 stm32x_info
= malloc(sizeof(struct stm32h7x_flash_bank
));
212 bank
->driver_priv
= stm32x_info
;
214 stm32x_info
->probed
= false;
215 stm32x_info
->user_bank_size
= bank
->size
;
220 static inline uint32_t stm32x_get_flash_reg(struct flash_bank
*bank
, uint32_t reg_offset
)
222 struct stm32h7x_flash_bank
*stm32x_info
= bank
->driver_priv
;
223 return reg_offset
+ stm32x_info
->flash_regs_base
;
226 static inline int stm32x_read_flash_reg(struct flash_bank
*bank
, uint32_t reg_offset
, uint32_t *value
)
228 uint32_t reg_addr
= stm32x_get_flash_reg(bank
, reg_offset
);
229 int retval
= target_read_u32(bank
->target
, reg_addr
, value
);
231 if (retval
!= ERROR_OK
)
232 LOG_ERROR("error while reading from address 0x%" PRIx32
, reg_addr
);
237 static inline int stm32x_write_flash_reg(struct flash_bank
*bank
, uint32_t reg_offset
, uint32_t value
)
239 uint32_t reg_addr
= stm32x_get_flash_reg(bank
, reg_offset
);
240 int retval
= target_write_u32(bank
->target
, reg_addr
, value
);
242 if (retval
!= ERROR_OK
)
243 LOG_ERROR("error while writing to address 0x%" PRIx32
, reg_addr
);
248 static inline int stm32x_get_flash_status(struct flash_bank
*bank
, uint32_t *status
)
250 return stm32x_read_flash_reg(bank
, FLASH_SR
, status
);
253 static int stm32x_wait_flash_op_queue(struct flash_bank
*bank
, int timeout
)
258 /* wait for flash operations completion */
260 retval
= stm32x_get_flash_status(bank
, &status
);
261 if (retval
!= ERROR_OK
)
264 if ((status
& FLASH_QW
) == 0)
267 if (timeout
-- <= 0) {
268 LOG_ERROR("wait_flash_op_queue, time out expired, status: 0x%" PRIx32
"", status
);
274 if (status
& FLASH_WRPERR
) {
275 LOG_ERROR("wait_flash_op_queue, WRPERR detected");
279 /* Clear error + EOP flags but report errors */
280 if (status
& FLASH_ERROR
) {
281 if (retval
== ERROR_OK
)
283 /* If this operation fails, we ignore it and report the original retval */
284 stm32x_write_flash_reg(bank
, FLASH_CCR
, status
);
289 static int stm32x_unlock_reg(struct flash_bank
*bank
)
293 /* first check if not already unlocked
294 * otherwise writing on FLASH_KEYR will fail
296 int retval
= stm32x_read_flash_reg(bank
, FLASH_CR
, &ctrl
);
297 if (retval
!= ERROR_OK
)
300 if ((ctrl
& FLASH_LOCK
) == 0)
303 /* unlock flash registers for bank */
304 retval
= stm32x_write_flash_reg(bank
, FLASH_KEYR
, KEY1
);
305 if (retval
!= ERROR_OK
)
308 retval
= stm32x_write_flash_reg(bank
, FLASH_KEYR
, KEY2
);
309 if (retval
!= ERROR_OK
)
312 retval
= stm32x_read_flash_reg(bank
, FLASH_CR
, &ctrl
);
313 if (retval
!= ERROR_OK
)
316 if (ctrl
& FLASH_LOCK
) {
317 LOG_ERROR("flash not unlocked STM32_FLASH_CRx: %" PRIx32
, ctrl
);
318 return ERROR_TARGET_FAILURE
;
323 static int stm32x_unlock_option_reg(struct flash_bank
*bank
)
327 int retval
= stm32x_read_flash_reg(bank
, FLASH_OPTCR
, &ctrl
);
328 if (retval
!= ERROR_OK
)
331 if ((ctrl
& OPT_LOCK
) == 0)
334 /* unlock option registers */
335 retval
= stm32x_write_flash_reg(bank
, FLASH_OPTKEYR
, OPTKEY1
);
336 if (retval
!= ERROR_OK
)
339 retval
= stm32x_write_flash_reg(bank
, FLASH_OPTKEYR
, OPTKEY2
);
340 if (retval
!= ERROR_OK
)
343 retval
= stm32x_read_flash_reg(bank
, FLASH_OPTCR
, &ctrl
);
344 if (retval
!= ERROR_OK
)
347 if (ctrl
& OPT_LOCK
) {
348 LOG_ERROR("options not unlocked STM32_FLASH_OPTCR: %" PRIx32
, ctrl
);
349 return ERROR_TARGET_FAILURE
;
355 static inline int stm32x_lock_reg(struct flash_bank
*bank
)
357 return stm32x_write_flash_reg(bank
, FLASH_CR
, FLASH_LOCK
);
360 static inline int stm32x_lock_option_reg(struct flash_bank
*bank
)
362 return stm32x_write_flash_reg(bank
, FLASH_OPTCR
, OPT_LOCK
);
365 static int stm32x_write_option(struct flash_bank
*bank
, uint32_t reg_offset
, uint32_t value
)
369 /* unlock option bytes for modification */
370 retval
= stm32x_unlock_option_reg(bank
);
371 if (retval
!= ERROR_OK
)
372 goto flash_options_lock
;
374 /* write option bytes */
375 retval
= stm32x_write_flash_reg(bank
, reg_offset
, value
);
376 if (retval
!= ERROR_OK
)
377 goto flash_options_lock
;
379 /* Remove OPT error flag before programming */
380 retval
= stm32x_write_flash_reg(bank
, FLASH_OPTCCR
, OPT_CLR_OPTCHANGEERR
);
381 if (retval
!= ERROR_OK
)
382 goto flash_options_lock
;
384 /* start programming cycle */
385 retval
= stm32x_write_flash_reg(bank
, FLASH_OPTCR
, OPT_START
);
386 if (retval
!= ERROR_OK
)
387 goto flash_options_lock
;
389 /* wait for completion */
390 int timeout
= FLASH_ERASE_TIMEOUT
;
393 retval
= stm32x_read_flash_reg(bank
, FLASH_OPTSR_CUR
, &status
);
394 if (retval
!= ERROR_OK
) {
395 LOG_ERROR("stm32x_options_program: failed to read FLASH_OPTSR_CUR");
396 goto flash_options_lock
;
398 if ((status
& OPT_BSY
) == 0)
401 if (timeout
-- <= 0) {
402 LOG_ERROR("waiting for OBL launch, time out expired, OPTSR: 0x%" PRIx32
"", status
);
404 goto flash_options_lock
;
409 /* check for failure */
410 if (status
& OPT_OPTCHANGEERR
) {
411 LOG_ERROR("error changing option bytes (OPTCHANGEERR=1)");
412 retval
= ERROR_FLASH_OPERATION_FAILED
;
416 retval2
= stm32x_lock_option_reg(bank
);
417 if (retval2
!= ERROR_OK
)
418 LOG_ERROR("error during the lock of flash options");
420 return (retval
== ERROR_OK
) ? retval2
: retval
;
423 static int stm32x_modify_option(struct flash_bank
*bank
, uint32_t reg_offset
, uint32_t value
, uint32_t mask
)
427 int retval
= stm32x_read_flash_reg(bank
, reg_offset
, &data
);
428 if (retval
!= ERROR_OK
)
431 data
= (data
& ~mask
) | (value
& mask
);
433 return stm32x_write_option(bank
, reg_offset
, data
);
436 static int stm32x_protect_check(struct flash_bank
*bank
)
440 /* read 'write protection' settings */
441 int retval
= stm32x_read_flash_reg(bank
, FLASH_WPSN_CUR
, &protection
);
442 if (retval
!= ERROR_OK
) {
443 LOG_DEBUG("unable to read WPSN_CUR register");
447 for (int i
= 0; i
< bank
->num_prot_blocks
; i
++)
448 bank
->prot_blocks
[i
].is_protected
= protection
& (1 << i
) ? 0 : 1;
453 static int stm32x_erase(struct flash_bank
*bank
, int first
, int last
)
455 struct stm32h7x_flash_bank
*stm32x_info
= bank
->driver_priv
;
458 assert(first
< bank
->num_sectors
);
459 assert(last
< bank
->num_sectors
);
461 if (bank
->target
->state
!= TARGET_HALTED
)
462 return ERROR_TARGET_NOT_HALTED
;
464 retval
= stm32x_unlock_reg(bank
);
465 if (retval
!= ERROR_OK
)
470 To erase a sector, follow the procedure below:
471 1. Check that no Flash memory operation is ongoing by checking the QW bit in the
473 2. Set the SER bit and select the sector
474 you wish to erase (SNB) in the FLASH_CR register
475 3. Set the STRT bit in the FLASH_CR register
476 4. Wait for flash operations completion
478 for (int i
= first
; i
<= last
; i
++) {
479 LOG_DEBUG("erase sector %d", i
);
480 retval
= stm32x_write_flash_reg(bank
, FLASH_CR
,
481 stm32x_info
->part_info
->compute_flash_cr(FLASH_SER
| FLASH_PSIZE_64
, i
));
482 if (retval
!= ERROR_OK
) {
483 LOG_ERROR("Error erase sector %d", i
);
486 retval
= stm32x_write_flash_reg(bank
, FLASH_CR
,
487 stm32x_info
->part_info
->compute_flash_cr(FLASH_SER
| FLASH_PSIZE_64
| FLASH_START
, i
));
488 if (retval
!= ERROR_OK
) {
489 LOG_ERROR("Error erase sector %d", i
);
492 retval
= stm32x_wait_flash_op_queue(bank
, FLASH_ERASE_TIMEOUT
);
494 if (retval
!= ERROR_OK
) {
495 LOG_ERROR("erase time-out or operation error sector %d", i
);
498 bank
->sectors
[i
].is_erased
= 1;
502 retval2
= stm32x_lock_reg(bank
);
503 if (retval2
!= ERROR_OK
)
504 LOG_ERROR("error during the lock of flash");
506 return (retval
== ERROR_OK
) ? retval2
: retval
;
509 static int stm32x_protect(struct flash_bank
*bank
, int set
, int first
, int last
)
511 struct target
*target
= bank
->target
;
514 if (target
->state
!= TARGET_HALTED
) {
515 LOG_ERROR("Target not halted");
516 return ERROR_TARGET_NOT_HALTED
;
519 /* read 'write protection' settings */
520 int retval
= stm32x_read_flash_reg(bank
, FLASH_WPSN_CUR
, &protection
);
521 if (retval
!= ERROR_OK
) {
522 LOG_DEBUG("unable to read WPSN_CUR register");
526 for (int i
= first
; i
<= last
; i
++) {
528 protection
&= ~(1 << i
);
530 protection
|= (1 << i
);
533 /* apply WRPSN mask */
536 LOG_DEBUG("stm32x_protect, option_bytes written WPSN 0x%" PRIx32
, protection
);
538 /* apply new option value */
539 return stm32x_write_option(bank
, FLASH_WPSN_PRG
, protection
);
542 static int stm32x_write_block(struct flash_bank
*bank
, const uint8_t *buffer
,
543 uint32_t offset
, uint32_t count
)
545 struct target
*target
= bank
->target
;
546 struct stm32h7x_flash_bank
*stm32x_info
= bank
->driver_priv
;
548 * If the size of the data part of the buffer is not a multiple of .block_size, we get
549 * "corrupted fifo read" pointer in target_run_flash_async_algorithm()
551 uint32_t data_size
= 512 * stm32x_info
->part_info
->block_size
;
552 uint32_t buffer_size
= 8 + data_size
;
553 struct working_area
*write_algorithm
;
554 struct working_area
*source
;
555 uint32_t address
= bank
->base
+ offset
;
556 struct reg_param reg_params
[6];
557 struct armv7m_algorithm armv7m_info
;
558 int retval
= ERROR_OK
;
560 static const uint8_t stm32x_flash_write_code
[] = {
561 #include "../../../contrib/loaders/flash/stm32/stm32h7x.inc"
564 if (target_alloc_working_area(target
, sizeof(stm32x_flash_write_code
),
565 &write_algorithm
) != ERROR_OK
) {
566 LOG_WARNING("no working area available, can't do block memory writes");
567 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
570 retval
= target_write_buffer(target
, write_algorithm
->address
,
571 sizeof(stm32x_flash_write_code
),
572 stm32x_flash_write_code
);
573 if (retval
!= ERROR_OK
) {
574 target_free_working_area(target
, write_algorithm
);
579 while (target_alloc_working_area_try(target
, buffer_size
, &source
) != ERROR_OK
) {
581 buffer_size
= 8 + data_size
;
582 if (data_size
<= 256) {
583 /* we already allocated the writing code, but failed to get a
584 * buffer, free the algorithm */
585 target_free_working_area(target
, write_algorithm
);
587 LOG_WARNING("no large enough working area available, can't do block memory writes");
588 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
592 LOG_DEBUG("target_alloc_working_area_try : buffer_size -> 0x%" PRIx32
, buffer_size
);
594 armv7m_info
.common_magic
= ARMV7M_COMMON_MAGIC
;
595 armv7m_info
.core_mode
= ARM_MODE_THREAD
;
597 init_reg_param(®_params
[0], "r0", 32, PARAM_IN_OUT
); /* buffer start, status (out) */
598 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
); /* buffer end */
599 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
); /* target address */
600 init_reg_param(®_params
[3], "r3", 32, PARAM_OUT
); /* count of words (word size = .block_size (bytes) */
601 init_reg_param(®_params
[4], "r4", 32, PARAM_OUT
); /* word size in bytes */
602 init_reg_param(®_params
[5], "r5", 32, PARAM_OUT
); /* flash reg base */
604 buf_set_u32(reg_params
[0].value
, 0, 32, source
->address
);
605 buf_set_u32(reg_params
[1].value
, 0, 32, source
->address
+ source
->size
);
606 buf_set_u32(reg_params
[2].value
, 0, 32, address
);
607 buf_set_u32(reg_params
[3].value
, 0, 32, count
);
608 buf_set_u32(reg_params
[4].value
, 0, 32, stm32x_info
->part_info
->block_size
);
609 buf_set_u32(reg_params
[5].value
, 0, 32, stm32x_info
->flash_regs_base
);
611 retval
= target_run_flash_async_algorithm(target
,
614 stm32x_info
->part_info
->block_size
,
616 ARRAY_SIZE(reg_params
), reg_params
,
617 source
->address
, source
->size
,
618 write_algorithm
->address
, 0,
621 if (retval
== ERROR_FLASH_OPERATION_FAILED
) {
622 LOG_ERROR("error executing stm32h7x flash write algorithm");
624 uint32_t flash_sr
= buf_get_u32(reg_params
[0].value
, 0, 32);
626 if (flash_sr
& FLASH_WRPERR
)
627 LOG_ERROR("flash memory write protected");
629 if ((flash_sr
& FLASH_ERROR
) != 0) {
630 LOG_ERROR("flash write failed, FLASH_SR = %08" PRIx32
, flash_sr
);
631 /* Clear error + EOP flags but report errors */
632 stm32x_write_flash_reg(bank
, FLASH_CCR
, flash_sr
);
637 target_free_working_area(target
, source
);
638 target_free_working_area(target
, write_algorithm
);
640 destroy_reg_param(®_params
[0]);
641 destroy_reg_param(®_params
[1]);
642 destroy_reg_param(®_params
[2]);
643 destroy_reg_param(®_params
[3]);
644 destroy_reg_param(®_params
[4]);
645 destroy_reg_param(®_params
[5]);
649 static int stm32x_write(struct flash_bank
*bank
, const uint8_t *buffer
,
650 uint32_t offset
, uint32_t count
)
652 struct target
*target
= bank
->target
;
653 struct stm32h7x_flash_bank
*stm32x_info
= bank
->driver_priv
;
654 uint32_t address
= bank
->base
+ offset
;
657 if (bank
->target
->state
!= TARGET_HALTED
) {
658 LOG_ERROR("Target not halted");
659 return ERROR_TARGET_NOT_HALTED
;
662 /* should be enforced via bank->write_start_alignment */
663 assert(!(offset
% stm32x_info
->part_info
->block_size
));
665 /* should be enforced via bank->write_end_alignment */
666 assert(!(count
% stm32x_info
->part_info
->block_size
));
668 retval
= stm32x_unlock_reg(bank
);
669 if (retval
!= ERROR_OK
)
672 uint32_t blocks_remaining
= count
/ stm32x_info
->part_info
->block_size
;
674 /* multiple words (n * .block_size) to be programmed in block */
675 if (blocks_remaining
) {
676 retval
= stm32x_write_block(bank
, buffer
, offset
, blocks_remaining
);
677 if (retval
!= ERROR_OK
) {
678 if (retval
== ERROR_TARGET_RESOURCE_NOT_AVAILABLE
) {
679 /* if block write failed (no sufficient working area),
680 * we use normal (slow) dword accesses */
681 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
684 buffer
+= blocks_remaining
* stm32x_info
->part_info
->block_size
;
685 address
+= blocks_remaining
* stm32x_info
->part_info
->block_size
;
686 blocks_remaining
= 0;
688 if ((retval
!= ERROR_OK
) && (retval
!= ERROR_TARGET_RESOURCE_NOT_AVAILABLE
))
694 The Flash memory programming sequence is as follows:
695 1. Check that no main Flash memory operation is ongoing by checking the QW bit in the
697 2. Set the PG bit in the FLASH_CR register
698 3. 8 x Word access (or Force Write FW)
699 4. Wait for flash operations completion
701 while (blocks_remaining
> 0) {
702 retval
= stm32x_write_flash_reg(bank
, FLASH_CR
,
703 stm32x_info
->part_info
->compute_flash_cr(FLASH_PG
| FLASH_PSIZE_64
, 0));
704 if (retval
!= ERROR_OK
)
707 retval
= target_write_buffer(target
, address
, stm32x_info
->part_info
->block_size
, buffer
);
708 if (retval
!= ERROR_OK
)
711 retval
= stm32x_wait_flash_op_queue(bank
, FLASH_WRITE_TIMEOUT
);
712 if (retval
!= ERROR_OK
)
715 buffer
+= stm32x_info
->part_info
->block_size
;
716 address
+= stm32x_info
->part_info
->block_size
;
721 retval2
= stm32x_lock_reg(bank
);
722 if (retval2
!= ERROR_OK
)
723 LOG_ERROR("error during the lock of flash");
725 return (retval
== ERROR_OK
) ? retval2
: retval
;
728 static int stm32x_read_id_code(struct flash_bank
*bank
, uint32_t *id
)
730 /* read stm32 device id register */
731 int retval
= target_read_u32(bank
->target
, DBGMCU_IDCODE_REGISTER
, id
);
732 if (retval
!= ERROR_OK
)
737 static int stm32x_probe(struct flash_bank
*bank
)
739 struct target
*target
= bank
->target
;
740 struct stm32h7x_flash_bank
*stm32x_info
= bank
->driver_priv
;
741 uint16_t flash_size_in_kb
;
744 stm32x_info
->probed
= false;
745 stm32x_info
->part_info
= NULL
;
747 int retval
= stm32x_read_id_code(bank
, &stm32x_info
->idcode
);
748 if (retval
!= ERROR_OK
)
751 LOG_DEBUG("device id = 0x%08" PRIx32
"", stm32x_info
->idcode
);
753 device_id
= stm32x_info
->idcode
& 0xfff;
755 for (unsigned int n
= 0; n
< ARRAY_SIZE(stm32h7x_parts
); n
++) {
756 if (device_id
== stm32h7x_parts
[n
].id
)
757 stm32x_info
->part_info
= &stm32h7x_parts
[n
];
759 if (!stm32x_info
->part_info
) {
760 LOG_WARNING("Cannot identify target as a STM32H7xx family.");
763 LOG_INFO("Device: %s", stm32x_info
->part_info
->device_str
);
766 /* update the address of controller from data base */
767 stm32x_info
->flash_regs_base
= stm32x_info
->part_info
->flash_regs_base
;
769 /* get flash size from target */
770 retval
= target_read_u16(target
, stm32x_info
->part_info
->fsize_addr
, &flash_size_in_kb
);
771 if (retval
!= ERROR_OK
) {
772 /* read error when device has invalid value, set max flash size */
773 flash_size_in_kb
= stm32x_info
->part_info
->max_flash_size_kb
;
775 LOG_INFO("flash size probed value %d", flash_size_in_kb
);
780 /* setup bank size */
781 const uint32_t bank1_base
= FLASH_BANK0_ADDRESS
;
782 const uint32_t bank2_base
= bank1_base
+ stm32x_info
->part_info
->max_bank_size_kb
* 1024;
783 bool has_dual_bank
= stm32x_info
->part_info
->has_dual_bank
;
788 /* For STM32H74x/75x and STM32H7Ax/Bx
789 * - STM32H7xxxI devices contains dual bank, 1 Mbyte each
790 * - STM32H7xxxG devices contains dual bank, 512 Kbyte each
791 * - STM32H7xxxB devices contains single bank, 128 Kbyte
792 * - the second bank starts always from 0x08100000
794 if (flash_size_in_kb
== 128)
795 has_dual_bank
= false;
797 /* flash size is 2M or 1M */
798 flash_size_in_kb
/= 2;
801 LOG_ERROR("unsupported device");
806 LOG_INFO("STM32H7 flash has dual banks");
807 if (bank
->base
!= bank1_base
&& bank
->base
!= bank2_base
) {
808 LOG_ERROR("STM32H7 flash bank base address config is incorrect. "
809 TARGET_ADDR_FMT
" but should rather be 0x%" PRIx32
" or 0x%" PRIx32
,
810 bank
->base
, bank1_base
, bank2_base
);
814 LOG_INFO("STM32H7 flash has a single bank");
815 if (bank
->base
== bank2_base
) {
816 LOG_ERROR("this device has a single bank only");
818 } else if (bank
->base
!= bank1_base
) {
819 LOG_ERROR("STM32H7 flash bank base address config is incorrect. "
820 TARGET_ADDR_FMT
" but should be 0x%" PRIx32
,
821 bank
->base
, bank1_base
);
826 LOG_INFO("Bank (%d) size is %d kb, base address is 0x%" PRIx32
,
827 bank
->bank_number
, flash_size_in_kb
, (uint32_t) bank
->base
);
829 /* if the user sets the size manually then ignore the probed value
830 * this allows us to work around devices that have an invalid flash size register value */
831 if (stm32x_info
->user_bank_size
) {
832 LOG_INFO("ignoring flash probed value, using configured bank size");
833 flash_size_in_kb
= stm32x_info
->user_bank_size
/ 1024;
834 } else if (flash_size_in_kb
== 0xffff) {
836 flash_size_in_kb
= stm32x_info
->part_info
->max_flash_size_kb
;
839 /* did we assign flash size? */
840 assert(flash_size_in_kb
!= 0xffff);
841 bank
->size
= flash_size_in_kb
* 1024;
842 bank
->write_start_alignment
= stm32x_info
->part_info
->block_size
;
843 bank
->write_end_alignment
= stm32x_info
->part_info
->block_size
;
846 bank
->num_sectors
= flash_size_in_kb
/ stm32x_info
->part_info
->page_size_kb
;
847 assert(bank
->num_sectors
> 0);
852 bank
->sectors
= alloc_block_array(0, stm32x_info
->part_info
->page_size_kb
* 1024,
855 if (bank
->sectors
== NULL
) {
856 LOG_ERROR("failed to allocate bank sectors");
860 /* setup protection blocks */
861 const uint32_t wpsn
= stm32x_info
->part_info
->wps_group_size
;
862 assert(bank
->num_sectors
% wpsn
== 0);
864 bank
->num_prot_blocks
= bank
->num_sectors
/ wpsn
;
865 assert(bank
->num_prot_blocks
> 0);
867 if (bank
->prot_blocks
)
868 free(bank
->prot_blocks
);
870 bank
->prot_blocks
= alloc_block_array(0, stm32x_info
->part_info
->page_size_kb
* wpsn
* 1024,
871 bank
->num_prot_blocks
);
873 if (bank
->prot_blocks
== NULL
) {
874 LOG_ERROR("failed to allocate bank prot_block");
878 stm32x_info
->probed
= 1;
882 static int stm32x_auto_probe(struct flash_bank
*bank
)
884 struct stm32h7x_flash_bank
*stm32x_info
= bank
->driver_priv
;
886 if (stm32x_info
->probed
)
889 return stm32x_probe(bank
);
892 /* This method must return a string displaying information about the bank */
893 static int stm32x_get_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
895 struct stm32h7x_flash_bank
*stm32x_info
= bank
->driver_priv
;
896 const struct stm32h7x_part_info
*info
= stm32x_info
->part_info
;
898 if (!stm32x_info
->probed
) {
899 int retval
= stm32x_probe(bank
);
900 if (retval
!= ERROR_OK
) {
901 snprintf(buf
, buf_size
, "Unable to find bank information.");
907 const char *rev_str
= NULL
;
908 uint16_t rev_id
= stm32x_info
->idcode
>> 16;
910 for (unsigned int i
= 0; i
< info
->num_revs
; i
++)
911 if (rev_id
== info
->revs
[i
].rev
)
912 rev_str
= info
->revs
[i
].str
;
914 if (rev_str
!= NULL
) {
915 snprintf(buf
, buf_size
, "%s - Rev: %s",
916 stm32x_info
->part_info
->device_str
, rev_str
);
918 snprintf(buf
, buf_size
,
919 "%s - Rev: unknown (0x%04x)",
920 stm32x_info
->part_info
->device_str
, rev_id
);
923 snprintf(buf
, buf_size
, "Cannot identify target as a STM32H7x");
929 static int stm32x_set_rdp(struct flash_bank
*bank
, enum stm32h7x_opt_rdp new_rdp
)
931 struct target
*target
= bank
->target
;
932 uint32_t optsr
, cur_rdp
;
935 if (target
->state
!= TARGET_HALTED
) {
936 LOG_ERROR("Target not halted");
937 return ERROR_TARGET_NOT_HALTED
;
940 retval
= stm32x_read_flash_reg(bank
, FLASH_OPTSR_PRG
, &optsr
);
942 if (retval
!= ERROR_OK
) {
943 LOG_DEBUG("unable to read FLASH_OPTSR_PRG register");
947 /* get current RDP, and check if there is a change */
948 cur_rdp
= (optsr
& OPT_RDP_MASK
) >> OPT_RDP_POS
;
949 if (new_rdp
== cur_rdp
) {
950 LOG_INFO("the requested RDP value is already programmed");
956 LOG_WARNING("unlocking the entire flash device");
959 LOG_WARNING("locking the entire flash device");
962 LOG_WARNING("locking the entire flash device, irreversible");
967 optsr
= (optsr
& ~OPT_RDP_MASK
) | (new_rdp
<< OPT_RDP_POS
);
969 /* apply new option value */
970 return stm32x_write_option(bank
, FLASH_OPTSR_PRG
, optsr
);
973 COMMAND_HANDLER(stm32x_handle_lock_command
)
976 return ERROR_COMMAND_SYNTAX_ERROR
;
978 struct flash_bank
*bank
;
979 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
980 if (ERROR_OK
!= retval
)
983 retval
= stm32x_set_rdp(bank
, OPT_RDP_L1
);
985 if (retval
!= ERROR_OK
)
986 command_print(CMD
, "%s failed to lock device", bank
->driver
->name
);
988 command_print(CMD
, "%s locked", bank
->driver
->name
);
993 COMMAND_HANDLER(stm32x_handle_unlock_command
)
996 return ERROR_COMMAND_SYNTAX_ERROR
;
998 struct flash_bank
*bank
;
999 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1000 if (ERROR_OK
!= retval
)
1003 retval
= stm32x_set_rdp(bank
, OPT_RDP_L0
);
1005 if (retval
!= ERROR_OK
)
1006 command_print(CMD
, "%s failed to unlock device", bank
->driver
->name
);
1008 command_print(CMD
, "%s unlocked", bank
->driver
->name
);
1013 static int stm32x_mass_erase(struct flash_bank
*bank
)
1015 int retval
, retval2
;
1016 struct target
*target
= bank
->target
;
1017 struct stm32h7x_flash_bank
*stm32x_info
= bank
->driver_priv
;
1019 if (target
->state
!= TARGET_HALTED
) {
1020 LOG_ERROR("Target not halted");
1021 return ERROR_TARGET_NOT_HALTED
;
1024 retval
= stm32x_unlock_reg(bank
);
1025 if (retval
!= ERROR_OK
)
1028 /* mass erase flash memory bank */
1029 retval
= stm32x_write_flash_reg(bank
, FLASH_CR
,
1030 stm32x_info
->part_info
->compute_flash_cr(FLASH_BER
| FLASH_PSIZE_64
, 0));
1031 if (retval
!= ERROR_OK
)
1034 retval
= stm32x_write_flash_reg(bank
, FLASH_CR
,
1035 stm32x_info
->part_info
->compute_flash_cr(FLASH_BER
| FLASH_PSIZE_64
| FLASH_START
, 0));
1036 if (retval
!= ERROR_OK
)
1039 retval
= stm32x_wait_flash_op_queue(bank
, 30000);
1040 if (retval
!= ERROR_OK
)
1044 retval2
= stm32x_lock_reg(bank
);
1045 if (retval2
!= ERROR_OK
)
1046 LOG_ERROR("error during the lock of flash");
1048 return (retval
== ERROR_OK
) ? retval2
: retval
;
1051 COMMAND_HANDLER(stm32x_handle_mass_erase_command
)
1054 command_print(CMD
, "stm32h7x mass_erase <bank>");
1055 return ERROR_COMMAND_SYNTAX_ERROR
;
1058 struct flash_bank
*bank
;
1059 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1060 if (ERROR_OK
!= retval
)
1063 retval
= stm32x_mass_erase(bank
);
1064 if (retval
== ERROR_OK
) {
1065 /* set all sectors as erased */
1066 for (int i
= 0; i
< bank
->num_sectors
; i
++)
1067 bank
->sectors
[i
].is_erased
= 1;
1069 command_print(CMD
, "stm32h7x mass erase complete");
1071 command_print(CMD
, "stm32h7x mass erase failed");
1077 COMMAND_HANDLER(stm32x_handle_option_read_command
)
1080 command_print(CMD
, "stm32h7x option_read <bank> <option_reg offset>");
1081 return ERROR_COMMAND_SYNTAX_ERROR
;
1084 struct flash_bank
*bank
;
1085 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1086 if (ERROR_OK
!= retval
)
1089 uint32_t reg_offset
, value
;
1091 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], reg_offset
);
1092 retval
= stm32x_read_flash_reg(bank
, reg_offset
, &value
);
1093 if (ERROR_OK
!= retval
)
1096 command_print(CMD
, "Option Register: <0x%" PRIx32
"> = 0x%" PRIx32
"",
1097 stm32x_get_flash_reg(bank
, reg_offset
), value
);
1102 COMMAND_HANDLER(stm32x_handle_option_write_command
)
1105 command_print(CMD
, "stm32h7x option_write <bank> <option_reg offset> <value> [mask]");
1106 return ERROR_COMMAND_SYNTAX_ERROR
;
1109 struct flash_bank
*bank
;
1110 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1111 if (ERROR_OK
!= retval
)
1114 uint32_t reg_offset
, value
, mask
= 0xffffffff;
1116 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], reg_offset
);
1117 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[2], value
);
1119 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[3], mask
);
1121 return stm32x_modify_option(bank
, reg_offset
, value
, mask
);
1124 static const struct command_registration stm32x_exec_command_handlers
[] = {
1127 .handler
= stm32x_handle_lock_command
,
1128 .mode
= COMMAND_EXEC
,
1130 .help
= "Lock entire flash device.",
1134 .handler
= stm32x_handle_unlock_command
,
1135 .mode
= COMMAND_EXEC
,
1137 .help
= "Unlock entire protected flash device.",
1140 .name
= "mass_erase",
1141 .handler
= stm32x_handle_mass_erase_command
,
1142 .mode
= COMMAND_EXEC
,
1144 .help
= "Erase entire flash device.",
1147 .name
= "option_read",
1148 .handler
= stm32x_handle_option_read_command
,
1149 .mode
= COMMAND_EXEC
,
1150 .usage
= "bank_id reg_offset",
1151 .help
= "Read and display device option bytes.",
1154 .name
= "option_write",
1155 .handler
= stm32x_handle_option_write_command
,
1156 .mode
= COMMAND_EXEC
,
1157 .usage
= "bank_id reg_offset value [mask]",
1158 .help
= "Write device option bit fields with provided value.",
1160 COMMAND_REGISTRATION_DONE
1163 static const struct command_registration stm32x_command_handlers
[] = {
1166 .mode
= COMMAND_ANY
,
1167 .help
= "stm32h7x flash command group",
1169 .chain
= stm32x_exec_command_handlers
,
1171 COMMAND_REGISTRATION_DONE
1174 const struct flash_driver stm32h7x_flash
= {
1176 .commands
= stm32x_command_handlers
,
1177 .flash_bank_command
= stm32x_flash_bank_command
,
1178 .erase
= stm32x_erase
,
1179 .protect
= stm32x_protect
,
1180 .write
= stm32x_write
,
1181 .read
= default_flash_read
,
1182 .probe
= stm32x_probe
,
1183 .auto_probe
= stm32x_auto_probe
,
1184 .erase_check
= default_flash_blank_check
,
1185 .protect_check
= stm32x_protect_check
,
1186 .info
= stm32x_get_info
,
1187 .free_driver_priv
= default_flash_free_driver_priv
,
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