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flash/nor/stm32l4x: Add revision 'Z' for STM32L552/562 devices
[openocd.git] / src / flash / nor / stm32l4x.c
1 // SPDX-License-Identifier: GPL-2.0-or-later
2
3 /***************************************************************************
4 * Copyright (C) 2015 by Uwe Bonnes *
5 * bon@elektron.ikp.physik.tu-darmstadt.de *
6 * *
7 * Copyright (C) 2019 by Tarek Bochkati for STMicroelectronics *
8 * tarek.bouchkati@gmail.com *
9 ***************************************************************************/
10
11 #ifdef HAVE_CONFIG_H
12 #include "config.h"
13 #endif
14
15 #include "imp.h"
16 #include <helper/align.h>
17 #include <helper/binarybuffer.h>
18 #include <helper/bits.h>
19 #include <target/algorithm.h>
20 #include <target/arm_adi_v5.h>
21 #include <target/cortex_m.h>
22 #include "stm32l4x.h"
23
24 /* STM32L4xxx series for reference.
25 *
26 * RM0351 (STM32L4x5/STM32L4x6)
27 * http://www.st.com/resource/en/reference_manual/dm00083560.pdf
28 *
29 * RM0394 (STM32L43x/44x/45x/46x)
30 * http://www.st.com/resource/en/reference_manual/dm00151940.pdf
31 *
32 * RM0432 (STM32L4R/4Sxx)
33 * http://www.st.com/resource/en/reference_manual/dm00310109.pdf
34 *
35 * STM32L476RG Datasheet (for erase timing)
36 * http://www.st.com/resource/en/datasheet/stm32l476rg.pdf
37 *
38 * The RM0351 devices have normally two banks, but on 512 and 256 kiB devices
39 * an option byte is available to map all sectors to the first bank.
40 * Both STM32 banks are treated as one OpenOCD bank, as other STM32 devices
41 * handlers do!
42 *
43 * RM0394 devices have a single bank only.
44 *
45 * RM0432 devices have single and dual bank operating modes.
46 * - for STM32L4R/Sxx the FLASH size is 2Mbyte or 1Mbyte.
47 * - for STM32L4P/Q5x the FLASH size is 1Mbyte or 512Kbyte.
48 * Bank page (sector) size is 4Kbyte (dual mode) or 8Kbyte (single mode).
49 *
50 * Bank mode is controlled by two different bits in option bytes register.
51 * - for STM32L4R/Sxx
52 * In 2M FLASH devices bit 22 (DBANK) controls Dual Bank mode.
53 * In 1M FLASH devices bit 21 (DB1M) controls Dual Bank mode.
54 * - for STM32L4P5/Q5x
55 * In 1M FLASH devices bit 22 (DBANK) controls Dual Bank mode.
56 * In 512K FLASH devices bit 21 (DB512K) controls Dual Bank mode.
57 */
58
59 /* STM32WBxxx series for reference.
60 *
61 * RM0434 (STM32WB55/WB35x)
62 * http://www.st.com/resource/en/reference_manual/dm00318631.pdf
63 *
64 * RM0471 (STM32WB50/WB30x)
65 * http://www.st.com/resource/en/reference_manual/dm00622834.pdf
66 *
67 * RM0473 (STM32WB15x)
68 * http://www.st.com/resource/en/reference_manual/dm00649196.pdf
69 *
70 * RM0478 (STM32WB10x)
71 * http://www.st.com/resource/en/reference_manual/dm00689203.pdf
72 */
73
74 /* STM32WLxxx series for reference.
75 *
76 * RM0461 (STM32WLEx)
77 * http://www.st.com/resource/en/reference_manual/dm00530369.pdf
78 *
79 * RM0453 (STM32WL5x)
80 * http://www.st.com/resource/en/reference_manual/dm00451556.pdf
81 */
82
83 /* STM32G0xxx series for reference.
84 *
85 * RM0444 (STM32G0x1)
86 * http://www.st.com/resource/en/reference_manual/dm00371828.pdf
87 *
88 * RM0454 (STM32G0x0)
89 * http://www.st.com/resource/en/reference_manual/dm00463896.pdf
90 */
91
92 /* STM32G4xxx series for reference.
93 *
94 * RM0440 (STM32G43x/44x/47x/48x/49x/4Ax)
95 * http://www.st.com/resource/en/reference_manual/dm00355726.pdf
96 *
97 * Cat. 2 devices have single bank only, page size is 2kByte.
98 *
99 * Cat. 3 devices have single and dual bank operating modes,
100 * Page size is 2kByte (dual mode) or 4kByte (single mode).
101 *
102 * Bank mode is controlled by bit 22 (DBANK) in option bytes register.
103 * Both banks are treated as a single OpenOCD bank.
104 *
105 * Cat. 4 devices have single bank only, page size is 2kByte.
106 */
107
108 /* STM32L5xxx series for reference.
109 *
110 * RM0428 (STM32L552xx/STM32L562xx)
111 * http://www.st.com/resource/en/reference_manual/dm00346336.pdf
112 */
113
114 /* Erase time can be as high as 25ms, 10x this and assume it's toast... */
115
116 #define FLASH_ERASE_TIMEOUT 250
117 #define FLASH_WRITE_TIMEOUT 50
118
119
120 /* relevant STM32L4 flags ****************************************************/
121 #define F_NONE 0
122 /* this flag indicates if the device flash is with dual bank architecture */
123 #define F_HAS_DUAL_BANK BIT(0)
124 /* this flags is used for dual bank devices only, it indicates if the
125 * 4 WRPxx are usable if the device is configured in single-bank mode */
126 #define F_USE_ALL_WRPXX BIT(1)
127 /* this flag indicates if the device embeds a TrustZone security feature */
128 #define F_HAS_TZ BIT(2)
129 /* this flag indicates if the device has the same flash registers as STM32L5 */
130 #define F_HAS_L5_FLASH_REGS BIT(3)
131 /* this flag indicates that programming should be done in quad-word
132 * the default programming word size is double-word */
133 #define F_QUAD_WORD_PROG BIT(4)
134 /* end of STM32L4 flags ******************************************************/
135
136
137 enum stm32l4_flash_reg_index {
138 STM32_FLASH_ACR_INDEX,
139 STM32_FLASH_KEYR_INDEX,
140 STM32_FLASH_OPTKEYR_INDEX,
141 STM32_FLASH_SR_INDEX,
142 STM32_FLASH_CR_INDEX,
143 /* for some devices like STM32WL5x, the CPU2 have a dedicated C2CR register w/o LOCKs,
144 * so it uses the C2CR for flash operations and CR for checking locks and locking */
145 STM32_FLASH_CR_WLK_INDEX, /* FLASH_CR_WITH_LOCK */
146 STM32_FLASH_OPTR_INDEX,
147 STM32_FLASH_WRP1AR_INDEX,
148 STM32_FLASH_WRP1BR_INDEX,
149 STM32_FLASH_WRP2AR_INDEX,
150 STM32_FLASH_WRP2BR_INDEX,
151 STM32_FLASH_REG_INDEX_NUM,
152 };
153
154 enum stm32l4_rdp {
155 RDP_LEVEL_0 = 0xAA,
156 RDP_LEVEL_0_5 = 0x55, /* for devices with TrustZone enabled */
157 RDP_LEVEL_1 = 0x00,
158 RDP_LEVEL_2 = 0xCC
159 };
160
161 static const uint32_t stm32l4_flash_regs[STM32_FLASH_REG_INDEX_NUM] = {
162 [STM32_FLASH_ACR_INDEX] = 0x000,
163 [STM32_FLASH_KEYR_INDEX] = 0x008,
164 [STM32_FLASH_OPTKEYR_INDEX] = 0x00C,
165 [STM32_FLASH_SR_INDEX] = 0x010,
166 [STM32_FLASH_CR_INDEX] = 0x014,
167 [STM32_FLASH_OPTR_INDEX] = 0x020,
168 [STM32_FLASH_WRP1AR_INDEX] = 0x02C,
169 [STM32_FLASH_WRP1BR_INDEX] = 0x030,
170 [STM32_FLASH_WRP2AR_INDEX] = 0x04C,
171 [STM32_FLASH_WRP2BR_INDEX] = 0x050,
172 };
173
174 static const uint32_t stm32wl_cpu2_flash_regs[STM32_FLASH_REG_INDEX_NUM] = {
175 [STM32_FLASH_ACR_INDEX] = 0x000,
176 [STM32_FLASH_KEYR_INDEX] = 0x008,
177 [STM32_FLASH_OPTKEYR_INDEX] = 0x010,
178 [STM32_FLASH_SR_INDEX] = 0x060,
179 [STM32_FLASH_CR_INDEX] = 0x064,
180 [STM32_FLASH_CR_WLK_INDEX] = 0x014,
181 [STM32_FLASH_OPTR_INDEX] = 0x020,
182 [STM32_FLASH_WRP1AR_INDEX] = 0x02C,
183 [STM32_FLASH_WRP1BR_INDEX] = 0x030,
184 };
185
186 static const uint32_t stm32l5_ns_flash_regs[STM32_FLASH_REG_INDEX_NUM] = {
187 [STM32_FLASH_ACR_INDEX] = 0x000,
188 [STM32_FLASH_KEYR_INDEX] = 0x008, /* NSKEYR */
189 [STM32_FLASH_OPTKEYR_INDEX] = 0x010,
190 [STM32_FLASH_SR_INDEX] = 0x020, /* NSSR */
191 [STM32_FLASH_CR_INDEX] = 0x028, /* NSCR */
192 [STM32_FLASH_OPTR_INDEX] = 0x040,
193 [STM32_FLASH_WRP1AR_INDEX] = 0x058,
194 [STM32_FLASH_WRP1BR_INDEX] = 0x05C,
195 [STM32_FLASH_WRP2AR_INDEX] = 0x068,
196 [STM32_FLASH_WRP2BR_INDEX] = 0x06C,
197 };
198
199 static const uint32_t stm32l5_s_flash_regs[STM32_FLASH_REG_INDEX_NUM] = {
200 [STM32_FLASH_ACR_INDEX] = 0x000,
201 [STM32_FLASH_KEYR_INDEX] = 0x00C, /* SECKEYR */
202 [STM32_FLASH_OPTKEYR_INDEX] = 0x010,
203 [STM32_FLASH_SR_INDEX] = 0x024, /* SECSR */
204 [STM32_FLASH_CR_INDEX] = 0x02C, /* SECCR */
205 [STM32_FLASH_OPTR_INDEX] = 0x040,
206 [STM32_FLASH_WRP1AR_INDEX] = 0x058,
207 [STM32_FLASH_WRP1BR_INDEX] = 0x05C,
208 [STM32_FLASH_WRP2AR_INDEX] = 0x068,
209 [STM32_FLASH_WRP2BR_INDEX] = 0x06C,
210 };
211
212 struct stm32l4_rev {
213 const uint16_t rev;
214 const char *str;
215 };
216
217 struct stm32l4_part_info {
218 uint16_t id;
219 const char *device_str;
220 const struct stm32l4_rev *revs;
221 const size_t num_revs;
222 const uint16_t max_flash_size_kb;
223 const uint32_t flags; /* one bit per feature, see STM32L4 flags: macros F_XXX */
224 const uint32_t flash_regs_base;
225 const uint32_t fsize_addr;
226 const uint32_t otp_base;
227 const uint32_t otp_size;
228 };
229
230 struct stm32l4_flash_bank {
231 bool probed;
232 uint32_t idcode;
233 unsigned int bank1_sectors;
234 bool dual_bank_mode;
235 int hole_sectors;
236 uint32_t user_bank_size;
237 uint32_t data_width;
238 uint32_t cr_bker_mask;
239 uint32_t sr_bsy_mask;
240 uint32_t wrpxxr_mask;
241 const struct stm32l4_part_info *part_info;
242 uint32_t flash_regs_base;
243 const uint32_t *flash_regs;
244 bool otp_enabled;
245 enum stm32l4_rdp rdp;
246 bool tzen;
247 uint32_t optr;
248 };
249
250 enum stm32_bank_id {
251 STM32_BANK1,
252 STM32_BANK2,
253 STM32_ALL_BANKS
254 };
255
256 struct stm32l4_wrp {
257 enum stm32l4_flash_reg_index reg_idx;
258 uint32_t value;
259 bool used;
260 int first;
261 int last;
262 int offset;
263 };
264
265 /* human readable list of families this drivers supports (sorted alphabetically) */
266 static const char *device_families = "STM32G0/G4/L4/L4+/L5/U5/WB/WL";
267
268 static const struct stm32l4_rev stm32l47_l48xx_revs[] = {
269 { 0x1000, "1" }, { 0x1001, "2" }, { 0x1003, "3" }, { 0x1007, "4" }
270 };
271
272 static const struct stm32l4_rev stm32l43_l44xx_revs[] = {
273 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
274 };
275
276 static const struct stm32l4_rev stm32g05_g06xx_revs[] = {
277 { 0x1000, "A" },
278 };
279
280 static const struct stm32l4_rev stm32_g07_g08xx_revs[] = {
281 { 0x1000, "A/Z" } /* A and Z, no typo in RM! */, { 0x2000, "B" },
282 };
283
284 static const struct stm32l4_rev stm32l49_l4axx_revs[] = {
285 { 0x1000, "A" }, { 0x2000, "B" },
286 };
287
288 static const struct stm32l4_rev stm32l45_l46xx_revs[] = {
289 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
290 };
291
292 static const struct stm32l4_rev stm32l41_l42xx_revs[] = {
293 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
294 };
295
296 static const struct stm32l4_rev stm32g03_g04xx_revs[] = {
297 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2000, "B" },
298 };
299
300 static const struct stm32l4_rev stm32g0b_g0cxx_revs[] = {
301 { 0x1000, "A" },
302 };
303
304 static const struct stm32l4_rev stm32g43_g44xx_revs[] = {
305 { 0x1000, "A" }, { 0x2000, "B" }, { 0x2001, "Z" },
306 };
307
308 static const struct stm32l4_rev stm32g47_g48xx_revs[] = {
309 { 0x1000, "A" }, { 0x2000, "B" }, { 0x2001, "Z" },
310 };
311
312 static const struct stm32l4_rev stm32l4r_l4sxx_revs[] = {
313 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x1003, "Y" }, { 0x100F, "W" },
314 };
315
316 static const struct stm32l4_rev stm32l4p_l4qxx_revs[] = {
317 { 0x1001, "Z" },
318 };
319
320 static const struct stm32l4_rev stm32l55_l56xx_revs[] = {
321 { 0x1000, "A" }, { 0x2000, "B" }, { 0x2001, "Z" },
322 };
323
324 static const struct stm32l4_rev stm32g49_g4axx_revs[] = {
325 { 0x1000, "A" },
326 };
327
328 static const struct stm32l4_rev stm32u57_u58xx_revs[] = {
329 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x1003, "Y" }, { 0x2000, "B" },
330 { 0x2001, "X" }, { 0x3000, "C" },
331 };
332
333 static const struct stm32l4_rev stm32wb1xx_revs[] = {
334 { 0x1000, "A" }, { 0x2000, "B" },
335 };
336
337 static const struct stm32l4_rev stm32wb5xx_revs[] = {
338 { 0x2001, "2.1" },
339 };
340
341 static const struct stm32l4_rev stm32wb3xx_revs[] = {
342 { 0x1000, "A" },
343 };
344
345 static const struct stm32l4_rev stm32wle_wl5xx_revs[] = {
346 { 0x1000, "1.0" },
347 };
348
349 static const struct stm32l4_part_info stm32l4_parts[] = {
350 {
351 .id = DEVID_STM32L47_L48XX,
352 .revs = stm32l47_l48xx_revs,
353 .num_revs = ARRAY_SIZE(stm32l47_l48xx_revs),
354 .device_str = "STM32L47/L48xx",
355 .max_flash_size_kb = 1024,
356 .flags = F_HAS_DUAL_BANK,
357 .flash_regs_base = 0x40022000,
358 .fsize_addr = 0x1FFF75E0,
359 .otp_base = 0x1FFF7000,
360 .otp_size = 1024,
361 },
362 {
363 .id = DEVID_STM32L43_L44XX,
364 .revs = stm32l43_l44xx_revs,
365 .num_revs = ARRAY_SIZE(stm32l43_l44xx_revs),
366 .device_str = "STM32L43/L44xx",
367 .max_flash_size_kb = 256,
368 .flags = F_NONE,
369 .flash_regs_base = 0x40022000,
370 .fsize_addr = 0x1FFF75E0,
371 .otp_base = 0x1FFF7000,
372 .otp_size = 1024,
373 },
374 {
375 .id = DEVID_STM32G05_G06XX,
376 .revs = stm32g05_g06xx_revs,
377 .num_revs = ARRAY_SIZE(stm32g05_g06xx_revs),
378 .device_str = "STM32G05/G06xx",
379 .max_flash_size_kb = 64,
380 .flags = F_NONE,
381 .flash_regs_base = 0x40022000,
382 .fsize_addr = 0x1FFF75E0,
383 .otp_base = 0x1FFF7000,
384 .otp_size = 1024,
385 },
386 {
387 .id = DEVID_STM32G07_G08XX,
388 .revs = stm32_g07_g08xx_revs,
389 .num_revs = ARRAY_SIZE(stm32_g07_g08xx_revs),
390 .device_str = "STM32G07/G08xx",
391 .max_flash_size_kb = 128,
392 .flags = F_NONE,
393 .flash_regs_base = 0x40022000,
394 .fsize_addr = 0x1FFF75E0,
395 .otp_base = 0x1FFF7000,
396 .otp_size = 1024,
397 },
398 {
399 .id = DEVID_STM32L49_L4AXX,
400 .revs = stm32l49_l4axx_revs,
401 .num_revs = ARRAY_SIZE(stm32l49_l4axx_revs),
402 .device_str = "STM32L49/L4Axx",
403 .max_flash_size_kb = 1024,
404 .flags = F_HAS_DUAL_BANK,
405 .flash_regs_base = 0x40022000,
406 .fsize_addr = 0x1FFF75E0,
407 .otp_base = 0x1FFF7000,
408 .otp_size = 1024,
409 },
410 {
411 .id = DEVID_STM32L45_L46XX,
412 .revs = stm32l45_l46xx_revs,
413 .num_revs = ARRAY_SIZE(stm32l45_l46xx_revs),
414 .device_str = "STM32L45/L46xx",
415 .max_flash_size_kb = 512,
416 .flags = F_NONE,
417 .flash_regs_base = 0x40022000,
418 .fsize_addr = 0x1FFF75E0,
419 .otp_base = 0x1FFF7000,
420 .otp_size = 1024,
421 },
422 {
423 .id = DEVID_STM32L41_L42XX,
424 .revs = stm32l41_l42xx_revs,
425 .num_revs = ARRAY_SIZE(stm32l41_l42xx_revs),
426 .device_str = "STM32L41/L42xx",
427 .max_flash_size_kb = 128,
428 .flags = F_NONE,
429 .flash_regs_base = 0x40022000,
430 .fsize_addr = 0x1FFF75E0,
431 .otp_base = 0x1FFF7000,
432 .otp_size = 1024,
433 },
434 {
435 .id = DEVID_STM32G03_G04XX,
436 .revs = stm32g03_g04xx_revs,
437 .num_revs = ARRAY_SIZE(stm32g03_g04xx_revs),
438 .device_str = "STM32G03x/G04xx",
439 .max_flash_size_kb = 64,
440 .flags = F_NONE,
441 .flash_regs_base = 0x40022000,
442 .fsize_addr = 0x1FFF75E0,
443 .otp_base = 0x1FFF7000,
444 .otp_size = 1024,
445 },
446 {
447 .id = DEVID_STM32G0B_G0CXX,
448 .revs = stm32g0b_g0cxx_revs,
449 .num_revs = ARRAY_SIZE(stm32g0b_g0cxx_revs),
450 .device_str = "STM32G0B/G0Cx",
451 .max_flash_size_kb = 512,
452 .flags = F_HAS_DUAL_BANK,
453 .flash_regs_base = 0x40022000,
454 .fsize_addr = 0x1FFF75E0,
455 .otp_base = 0x1FFF7000,
456 .otp_size = 1024,
457 },
458 {
459 .id = DEVID_STM32G43_G44XX,
460 .revs = stm32g43_g44xx_revs,
461 .num_revs = ARRAY_SIZE(stm32g43_g44xx_revs),
462 .device_str = "STM32G43/G44xx",
463 .max_flash_size_kb = 128,
464 .flags = F_NONE,
465 .flash_regs_base = 0x40022000,
466 .fsize_addr = 0x1FFF75E0,
467 .otp_base = 0x1FFF7000,
468 .otp_size = 1024,
469 },
470 {
471 .id = DEVID_STM32G47_G48XX,
472 .revs = stm32g47_g48xx_revs,
473 .num_revs = ARRAY_SIZE(stm32g47_g48xx_revs),
474 .device_str = "STM32G47/G48xx",
475 .max_flash_size_kb = 512,
476 .flags = F_HAS_DUAL_BANK | F_USE_ALL_WRPXX,
477 .flash_regs_base = 0x40022000,
478 .fsize_addr = 0x1FFF75E0,
479 .otp_base = 0x1FFF7000,
480 .otp_size = 1024,
481 },
482 {
483 .id = DEVID_STM32L4R_L4SXX,
484 .revs = stm32l4r_l4sxx_revs,
485 .num_revs = ARRAY_SIZE(stm32l4r_l4sxx_revs),
486 .device_str = "STM32L4R/L4Sxx",
487 .max_flash_size_kb = 2048,
488 .flags = F_HAS_DUAL_BANK | F_USE_ALL_WRPXX,
489 .flash_regs_base = 0x40022000,
490 .fsize_addr = 0x1FFF75E0,
491 .otp_base = 0x1FFF7000,
492 .otp_size = 1024,
493 },
494 {
495 .id = DEVID_STM32L4P_L4QXX,
496 .revs = stm32l4p_l4qxx_revs,
497 .num_revs = ARRAY_SIZE(stm32l4p_l4qxx_revs),
498 .device_str = "STM32L4P/L4Qxx",
499 .max_flash_size_kb = 1024,
500 .flags = F_HAS_DUAL_BANK | F_USE_ALL_WRPXX,
501 .flash_regs_base = 0x40022000,
502 .fsize_addr = 0x1FFF75E0,
503 .otp_base = 0x1FFF7000,
504 .otp_size = 1024,
505 },
506 {
507 .id = DEVID_STM32L55_L56XX,
508 .revs = stm32l55_l56xx_revs,
509 .num_revs = ARRAY_SIZE(stm32l55_l56xx_revs),
510 .device_str = "STM32L55/L56xx",
511 .max_flash_size_kb = 512,
512 .flags = F_HAS_DUAL_BANK | F_USE_ALL_WRPXX | F_HAS_TZ | F_HAS_L5_FLASH_REGS,
513 .flash_regs_base = 0x40022000,
514 .fsize_addr = 0x0BFA05E0,
515 .otp_base = 0x0BFA0000,
516 .otp_size = 512,
517 },
518 {
519 .id = DEVID_STM32G49_G4AXX,
520 .revs = stm32g49_g4axx_revs,
521 .num_revs = ARRAY_SIZE(stm32g49_g4axx_revs),
522 .device_str = "STM32G49/G4Axx",
523 .max_flash_size_kb = 512,
524 .flags = F_NONE,
525 .flash_regs_base = 0x40022000,
526 .fsize_addr = 0x1FFF75E0,
527 .otp_base = 0x1FFF7000,
528 .otp_size = 1024,
529 },
530 {
531 .id = DEVID_STM32U57_U58XX,
532 .revs = stm32u57_u58xx_revs,
533 .num_revs = ARRAY_SIZE(stm32u57_u58xx_revs),
534 .device_str = "STM32U57/U58xx",
535 .max_flash_size_kb = 2048,
536 .flags = F_HAS_DUAL_BANK | F_QUAD_WORD_PROG | F_HAS_TZ | F_HAS_L5_FLASH_REGS,
537 .flash_regs_base = 0x40022000,
538 .fsize_addr = 0x0BFA07A0,
539 .otp_base = 0x0BFA0000,
540 .otp_size = 512,
541 },
542 {
543 .id = DEVID_STM32WB1XX,
544 .revs = stm32wb1xx_revs,
545 .num_revs = ARRAY_SIZE(stm32wb1xx_revs),
546 .device_str = "STM32WB1x",
547 .max_flash_size_kb = 320,
548 .flags = F_NONE,
549 .flash_regs_base = 0x58004000,
550 .fsize_addr = 0x1FFF75E0,
551 .otp_base = 0x1FFF7000,
552 .otp_size = 1024,
553 },
554 {
555 .id = DEVID_STM32WB5XX,
556 .revs = stm32wb5xx_revs,
557 .num_revs = ARRAY_SIZE(stm32wb5xx_revs),
558 .device_str = "STM32WB5x",
559 .max_flash_size_kb = 1024,
560 .flags = F_NONE,
561 .flash_regs_base = 0x58004000,
562 .fsize_addr = 0x1FFF75E0,
563 .otp_base = 0x1FFF7000,
564 .otp_size = 1024,
565 },
566 {
567 .id = DEVID_STM32WB3XX,
568 .revs = stm32wb3xx_revs,
569 .num_revs = ARRAY_SIZE(stm32wb3xx_revs),
570 .device_str = "STM32WB3x",
571 .max_flash_size_kb = 512,
572 .flags = F_NONE,
573 .flash_regs_base = 0x58004000,
574 .fsize_addr = 0x1FFF75E0,
575 .otp_base = 0x1FFF7000,
576 .otp_size = 1024,
577 },
578 {
579 .id = DEVID_STM32WLE_WL5XX,
580 .revs = stm32wle_wl5xx_revs,
581 .num_revs = ARRAY_SIZE(stm32wle_wl5xx_revs),
582 .device_str = "STM32WLE/WL5x",
583 .max_flash_size_kb = 256,
584 .flags = F_NONE,
585 .flash_regs_base = 0x58004000,
586 .fsize_addr = 0x1FFF75E0,
587 .otp_base = 0x1FFF7000,
588 .otp_size = 1024,
589 },
590 };
591
592 /* flash bank stm32l4x <base> <size> 0 0 <target#> */
593 FLASH_BANK_COMMAND_HANDLER(stm32l4_flash_bank_command)
594 {
595 struct stm32l4_flash_bank *stm32l4_info;
596
597 if (CMD_ARGC < 6)
598 return ERROR_COMMAND_SYNTAX_ERROR;
599
600 /* fix-up bank base address: 0 is used for normal flash memory */
601 if (bank->base == 0)
602 bank->base = STM32_FLASH_BANK_BASE;
603
604 stm32l4_info = calloc(1, sizeof(struct stm32l4_flash_bank));
605 if (!stm32l4_info)
606 return ERROR_FAIL; /* Checkme: What better error to use?*/
607 bank->driver_priv = stm32l4_info;
608
609 stm32l4_info->probed = false;
610 stm32l4_info->otp_enabled = false;
611 stm32l4_info->user_bank_size = bank->size;
612
613 return ERROR_OK;
614 }
615
616 /* bitmap helper extension */
617 struct range {
618 unsigned int start;
619 unsigned int end;
620 };
621
622 static void bitmap_to_ranges(unsigned long *bitmap, unsigned int nbits,
623 struct range *ranges, unsigned int *ranges_count) {
624 *ranges_count = 0;
625 bool last_bit = 0, cur_bit;
626 for (unsigned int i = 0; i < nbits; i++) {
627 cur_bit = test_bit(i, bitmap);
628
629 if (cur_bit && !last_bit) {
630 (*ranges_count)++;
631 ranges[*ranges_count - 1].start = i;
632 ranges[*ranges_count - 1].end = i;
633 } else if (cur_bit && last_bit) {
634 /* update (increment) the end this range */
635 ranges[*ranges_count - 1].end = i;
636 }
637
638 last_bit = cur_bit;
639 }
640 }
641
642 static inline int range_print_one(struct range *range, char *str)
643 {
644 if (range->start == range->end)
645 return sprintf(str, "[%d]", range->start);
646
647 return sprintf(str, "[%d,%d]", range->start, range->end);
648 }
649
650 static char *range_print_alloc(struct range *ranges, unsigned int ranges_count)
651 {
652 /* each range will be printed like the following: [start,end]
653 * start and end, both are unsigned int, an unsigned int takes 10 characters max
654 * plus 3 characters for '[', ',' and ']'
655 * thus means each range can take maximum 23 character
656 * after each range we add a ' ' as separator and finally we need the '\0'
657 * if the ranges_count is zero we reserve one char for '\0' to return an empty string */
658 char *str = calloc(1, ranges_count * (24 * sizeof(char)) + 1);
659 char *ptr = str;
660
661 for (unsigned int i = 0; i < ranges_count; i++) {
662 ptr += range_print_one(&(ranges[i]), ptr);
663
664 if (i < ranges_count - 1)
665 *(ptr++) = ' ';
666 }
667
668 return str;
669 }
670
671 /* end of bitmap helper extension */
672
673 static inline bool stm32l4_is_otp(struct flash_bank *bank)
674 {
675 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
676 return bank->base == stm32l4_info->part_info->otp_base;
677 }
678
679 static int stm32l4_otp_enable(struct flash_bank *bank, bool enable)
680 {
681 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
682
683 if (!stm32l4_is_otp(bank))
684 return ERROR_FAIL;
685
686 char *op_str = enable ? "enabled" : "disabled";
687
688 LOG_INFO("OTP memory (bank #%d) is %s%s for write commands",
689 bank->bank_number,
690 stm32l4_info->otp_enabled == enable ? "already " : "",
691 op_str);
692
693 stm32l4_info->otp_enabled = enable;
694
695 return ERROR_OK;
696 }
697
698 static inline bool stm32l4_otp_is_enabled(struct flash_bank *bank)
699 {
700 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
701 return stm32l4_info->otp_enabled;
702 }
703
704 static void stm32l4_sync_rdp_tzen(struct flash_bank *bank)
705 {
706 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
707
708 bool tzen = false;
709
710 if (stm32l4_info->part_info->flags & F_HAS_TZ)
711 tzen = (stm32l4_info->optr & FLASH_TZEN) != 0;
712
713 uint32_t rdp = stm32l4_info->optr & FLASH_RDP_MASK;
714
715 /* for devices without TrustZone:
716 * RDP level 0 and 2 values are to 0xAA and 0xCC
717 * Any other value corresponds to RDP level 1
718 * for devices with TrusZone:
719 * RDP level 0 and 2 values are 0xAA and 0xCC
720 * RDP level 0.5 value is 0x55 only if TZEN = 1
721 * Any other value corresponds to RDP level 1, including 0x55 if TZEN = 0
722 */
723
724 if (rdp != RDP_LEVEL_0 && rdp != RDP_LEVEL_2) {
725 if (!tzen || (tzen && rdp != RDP_LEVEL_0_5))
726 rdp = RDP_LEVEL_1;
727 }
728
729 stm32l4_info->tzen = tzen;
730 stm32l4_info->rdp = rdp;
731 }
732
733 static inline uint32_t stm32l4_get_flash_reg(struct flash_bank *bank, uint32_t reg_offset)
734 {
735 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
736 return stm32l4_info->flash_regs_base + reg_offset;
737 }
738
739 static inline uint32_t stm32l4_get_flash_reg_by_index(struct flash_bank *bank,
740 enum stm32l4_flash_reg_index reg_index)
741 {
742 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
743 return stm32l4_get_flash_reg(bank, stm32l4_info->flash_regs[reg_index]);
744 }
745
746 static inline int stm32l4_read_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t *value)
747 {
748 return target_read_u32(bank->target, stm32l4_get_flash_reg(bank, reg_offset), value);
749 }
750
751 static inline int stm32l4_read_flash_reg_by_index(struct flash_bank *bank,
752 enum stm32l4_flash_reg_index reg_index, uint32_t *value)
753 {
754 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
755 return stm32l4_read_flash_reg(bank, stm32l4_info->flash_regs[reg_index], value);
756 }
757
758 static inline int stm32l4_write_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t value)
759 {
760 return target_write_u32(bank->target, stm32l4_get_flash_reg(bank, reg_offset), value);
761 }
762
763 static inline int stm32l4_write_flash_reg_by_index(struct flash_bank *bank,
764 enum stm32l4_flash_reg_index reg_index, uint32_t value)
765 {
766 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
767 return stm32l4_write_flash_reg(bank, stm32l4_info->flash_regs[reg_index], value);
768 }
769
770 static int stm32l4_wait_status_busy(struct flash_bank *bank, int timeout)
771 {
772 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
773 uint32_t status;
774 int retval = ERROR_OK;
775
776 /* wait for busy to clear */
777 for (;;) {
778 retval = stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_SR_INDEX, &status);
779 if (retval != ERROR_OK)
780 return retval;
781 LOG_DEBUG("status: 0x%" PRIx32 "", status);
782 if ((status & stm32l4_info->sr_bsy_mask) == 0)
783 break;
784 if (timeout-- <= 0) {
785 LOG_ERROR("timed out waiting for flash");
786 return ERROR_FAIL;
787 }
788 alive_sleep(1);
789 }
790
791 if (status & FLASH_WRPERR) {
792 LOG_ERROR("stm32x device protected");
793 retval = ERROR_FAIL;
794 }
795
796 /* Clear but report errors */
797 if (status & FLASH_ERROR) {
798 if (retval == ERROR_OK)
799 retval = ERROR_FAIL;
800 /* If this operation fails, we ignore it and report the original
801 * retval
802 */
803 stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_SR_INDEX, status & FLASH_ERROR);
804 }
805
806 return retval;
807 }
808
809 /** set all FLASH_SECBB registers to the same value */
810 static int stm32l4_set_secbb(struct flash_bank *bank, uint32_t value)
811 {
812 /* This function should be used only with device with TrustZone, do just a security check */
813 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
814 assert(stm32l4_info->part_info->flags & F_HAS_TZ);
815
816 /* based on RM0438 Rev6 for STM32L5x devices:
817 * to modify a page block-based security attribution, it is recommended to
818 * 1- check that no flash operation is ongoing on the related page
819 * 2- add ISB instruction after modifying the page security attribute in SECBBxRy
820 * this step is not need in case of JTAG direct access
821 */
822 int retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
823 if (retval != ERROR_OK)
824 return retval;
825
826 /* write SECBBxRy registers */
827 LOG_DEBUG("setting secure block-based areas registers (SECBBxRy) to 0x%08x", value);
828
829 const uint8_t secbb_regs[] = {
830 FLASH_SECBB1(1), FLASH_SECBB1(2), FLASH_SECBB1(3), FLASH_SECBB1(4), /* bank 1 SECBB register offsets */
831 FLASH_SECBB2(1), FLASH_SECBB2(2), FLASH_SECBB2(3), FLASH_SECBB2(4) /* bank 2 SECBB register offsets */
832 };
833
834
835 unsigned int num_secbb_regs = ARRAY_SIZE(secbb_regs);
836
837 /* in single bank mode, it's useless to modify FLASH_SECBB2Rx registers
838 * then consider only the first half of secbb_regs
839 */
840 if (!stm32l4_info->dual_bank_mode)
841 num_secbb_regs /= 2;
842
843 for (unsigned int i = 0; i < num_secbb_regs; i++) {
844 retval = stm32l4_write_flash_reg(bank, secbb_regs[i], value);
845 if (retval != ERROR_OK)
846 return retval;
847 }
848
849 return ERROR_OK;
850 }
851
852 static inline int stm32l4_get_flash_cr_with_lock_index(struct flash_bank *bank)
853 {
854 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
855 return (stm32l4_info->flash_regs[STM32_FLASH_CR_WLK_INDEX]) ?
856 STM32_FLASH_CR_WLK_INDEX : STM32_FLASH_CR_INDEX;
857 }
858
859 static int stm32l4_unlock_reg(struct flash_bank *bank)
860 {
861 const uint32_t flash_cr_index = stm32l4_get_flash_cr_with_lock_index(bank);
862 uint32_t ctrl;
863
864 /* first check if not already unlocked
865 * otherwise writing on STM32_FLASH_KEYR will fail
866 */
867 int retval = stm32l4_read_flash_reg_by_index(bank, flash_cr_index, &ctrl);
868 if (retval != ERROR_OK)
869 return retval;
870
871 if ((ctrl & FLASH_LOCK) == 0)
872 return ERROR_OK;
873
874 /* unlock flash registers */
875 retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_KEYR_INDEX, KEY1);
876 if (retval != ERROR_OK)
877 return retval;
878
879 retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_KEYR_INDEX, KEY2);
880 if (retval != ERROR_OK)
881 return retval;
882
883 retval = stm32l4_read_flash_reg_by_index(bank, flash_cr_index, &ctrl);
884 if (retval != ERROR_OK)
885 return retval;
886
887 if (ctrl & FLASH_LOCK) {
888 LOG_ERROR("flash not unlocked STM32_FLASH_CR: %" PRIx32, ctrl);
889 return ERROR_TARGET_FAILURE;
890 }
891
892 return ERROR_OK;
893 }
894
895 static int stm32l4_unlock_option_reg(struct flash_bank *bank)
896 {
897 const uint32_t flash_cr_index = stm32l4_get_flash_cr_with_lock_index(bank);
898 uint32_t ctrl;
899
900 int retval = stm32l4_read_flash_reg_by_index(bank, flash_cr_index, &ctrl);
901 if (retval != ERROR_OK)
902 return retval;
903
904 if ((ctrl & FLASH_OPTLOCK) == 0)
905 return ERROR_OK;
906
907 /* unlock option registers */
908 retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_OPTKEYR_INDEX, OPTKEY1);
909 if (retval != ERROR_OK)
910 return retval;
911
912 retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_OPTKEYR_INDEX, OPTKEY2);
913 if (retval != ERROR_OK)
914 return retval;
915
916 retval = stm32l4_read_flash_reg_by_index(bank, flash_cr_index, &ctrl);
917 if (retval != ERROR_OK)
918 return retval;
919
920 if (ctrl & FLASH_OPTLOCK) {
921 LOG_ERROR("options not unlocked STM32_FLASH_CR: %" PRIx32, ctrl);
922 return ERROR_TARGET_FAILURE;
923 }
924
925 return ERROR_OK;
926 }
927
928 static int stm32l4_perform_obl_launch(struct flash_bank *bank)
929 {
930 int retval, retval2;
931
932 retval = stm32l4_unlock_reg(bank);
933 if (retval != ERROR_OK)
934 goto err_lock;
935
936 retval = stm32l4_unlock_option_reg(bank);
937 if (retval != ERROR_OK)
938 goto err_lock;
939
940 /* Set OBL_LAUNCH bit in CR -> system reset and option bytes reload,
941 * but the RMs explicitly do *NOT* list this as power-on reset cause, and:
942 * "Note: If the read protection is set while the debugger is still
943 * connected through JTAG/SWD, apply a POR (power-on reset) instead of a system reset."
944 */
945
946 /* "Setting OBL_LAUNCH generates a reset so the option byte loading is performed under system reset" */
947 /* Due to this reset ST-Link reports an SWD_DP_ERROR, despite the write was successful,
948 * then just ignore the returned value */
949 stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, FLASH_OBL_LAUNCH);
950
951 /* Need to re-probe after change */
952 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
953 stm32l4_info->probed = false;
954
955 err_lock:
956 retval2 = stm32l4_write_flash_reg_by_index(bank, stm32l4_get_flash_cr_with_lock_index(bank),
957 FLASH_LOCK | FLASH_OPTLOCK);
958
959 if (retval != ERROR_OK)
960 return retval;
961
962 return retval2;
963 }
964
965 static int stm32l4_write_option(struct flash_bank *bank, uint32_t reg_offset,
966 uint32_t value, uint32_t mask)
967 {
968 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
969 uint32_t optiondata;
970 int retval, retval2;
971
972 retval = stm32l4_read_flash_reg(bank, reg_offset, &optiondata);
973 if (retval != ERROR_OK)
974 return retval;
975
976 /* for STM32L5 and similar devices, use always non-secure
977 * registers for option bytes programming */
978 const uint32_t *saved_flash_regs = stm32l4_info->flash_regs;
979 if (stm32l4_info->part_info->flags & F_HAS_L5_FLASH_REGS)
980 stm32l4_info->flash_regs = stm32l5_ns_flash_regs;
981
982 retval = stm32l4_unlock_reg(bank);
983 if (retval != ERROR_OK)
984 goto err_lock;
985
986 retval = stm32l4_unlock_option_reg(bank);
987 if (retval != ERROR_OK)
988 goto err_lock;
989
990 optiondata = (optiondata & ~mask) | (value & mask);
991
992 retval = stm32l4_write_flash_reg(bank, reg_offset, optiondata);
993 if (retval != ERROR_OK)
994 goto err_lock;
995
996 retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, FLASH_OPTSTRT);
997 if (retval != ERROR_OK)
998 goto err_lock;
999
1000 retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
1001
1002 err_lock:
1003 retval2 = stm32l4_write_flash_reg_by_index(bank, stm32l4_get_flash_cr_with_lock_index(bank),
1004 FLASH_LOCK | FLASH_OPTLOCK);
1005 stm32l4_info->flash_regs = saved_flash_regs;
1006
1007 if (retval != ERROR_OK)
1008 return retval;
1009
1010 return retval2;
1011 }
1012
1013 static int stm32l4_get_one_wrpxy(struct flash_bank *bank, struct stm32l4_wrp *wrpxy,
1014 enum stm32l4_flash_reg_index reg_idx, int offset)
1015 {
1016 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1017 int ret;
1018
1019 wrpxy->reg_idx = reg_idx;
1020 wrpxy->offset = offset;
1021
1022 ret = stm32l4_read_flash_reg_by_index(bank, wrpxy->reg_idx , &wrpxy->value);
1023 if (ret != ERROR_OK)
1024 return ret;
1025
1026 wrpxy->first = (wrpxy->value & stm32l4_info->wrpxxr_mask) + wrpxy->offset;
1027 wrpxy->last = ((wrpxy->value >> 16) & stm32l4_info->wrpxxr_mask) + wrpxy->offset;
1028 wrpxy->used = wrpxy->first <= wrpxy->last;
1029
1030 return ERROR_OK;
1031 }
1032
1033 static int stm32l4_get_all_wrpxy(struct flash_bank *bank, enum stm32_bank_id dev_bank_id,
1034 struct stm32l4_wrp *wrpxy, unsigned int *n_wrp)
1035 {
1036 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1037 int ret;
1038
1039 *n_wrp = 0;
1040
1041 /* for single bank devices there is 2 WRP regions.
1042 * for dual bank devices there is 2 WRP regions per bank,
1043 * if configured as single bank only 2 WRP are usable
1044 * except for STM32L4R/S/P/Q, G4 cat3, L5 ... all 4 WRP are usable
1045 * note: this should be revised, if a device will have the SWAP banks option
1046 */
1047
1048 int wrp2y_sectors_offset = -1; /* -1 : unused */
1049
1050 /* if bank_id is BANK1 or ALL_BANKS */
1051 if (dev_bank_id != STM32_BANK2) {
1052 /* get FLASH_WRP1AR */
1053 ret = stm32l4_get_one_wrpxy(bank, &wrpxy[(*n_wrp)++], STM32_FLASH_WRP1AR_INDEX, 0);
1054 if (ret != ERROR_OK)
1055 return ret;
1056
1057 /* get WRP1BR */
1058 ret = stm32l4_get_one_wrpxy(bank, &wrpxy[(*n_wrp)++], STM32_FLASH_WRP1BR_INDEX, 0);
1059 if (ret != ERROR_OK)
1060 return ret;
1061
1062 /* for some devices (like STM32L4R/S) in single-bank mode, the 4 WRPxx are usable */
1063 if ((stm32l4_info->part_info->flags & F_USE_ALL_WRPXX) && !stm32l4_info->dual_bank_mode)
1064 wrp2y_sectors_offset = 0;
1065 }
1066
1067 /* if bank_id is BANK2 or ALL_BANKS */
1068 if (dev_bank_id != STM32_BANK1 && stm32l4_info->dual_bank_mode)
1069 wrp2y_sectors_offset = stm32l4_info->bank1_sectors;
1070
1071 if (wrp2y_sectors_offset >= 0) {
1072 /* get WRP2AR */
1073 ret = stm32l4_get_one_wrpxy(bank, &wrpxy[(*n_wrp)++], STM32_FLASH_WRP2AR_INDEX, wrp2y_sectors_offset);
1074 if (ret != ERROR_OK)
1075 return ret;
1076
1077 /* get WRP2BR */
1078 ret = stm32l4_get_one_wrpxy(bank, &wrpxy[(*n_wrp)++], STM32_FLASH_WRP2BR_INDEX, wrp2y_sectors_offset);
1079 if (ret != ERROR_OK)
1080 return ret;
1081 }
1082
1083 return ERROR_OK;
1084 }
1085
1086 static int stm32l4_write_one_wrpxy(struct flash_bank *bank, struct stm32l4_wrp *wrpxy)
1087 {
1088 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1089
1090 int wrp_start = wrpxy->first - wrpxy->offset;
1091 int wrp_end = wrpxy->last - wrpxy->offset;
1092
1093 uint32_t wrp_value = (wrp_start & stm32l4_info->wrpxxr_mask) | ((wrp_end & stm32l4_info->wrpxxr_mask) << 16);
1094
1095 return stm32l4_write_option(bank, stm32l4_info->flash_regs[wrpxy->reg_idx], wrp_value, 0xffffffff);
1096 }
1097
1098 static int stm32l4_write_all_wrpxy(struct flash_bank *bank, struct stm32l4_wrp *wrpxy, unsigned int n_wrp)
1099 {
1100 int ret;
1101
1102 for (unsigned int i = 0; i < n_wrp; i++) {
1103 ret = stm32l4_write_one_wrpxy(bank, &wrpxy[i]);
1104 if (ret != ERROR_OK)
1105 return ret;
1106 }
1107
1108 return ERROR_OK;
1109 }
1110
1111 static int stm32l4_protect_check(struct flash_bank *bank)
1112 {
1113 unsigned int n_wrp;
1114 struct stm32l4_wrp wrpxy[4];
1115
1116 int ret = stm32l4_get_all_wrpxy(bank, STM32_ALL_BANKS, wrpxy, &n_wrp);
1117 if (ret != ERROR_OK)
1118 return ret;
1119
1120 /* initialize all sectors as unprotected */
1121 for (unsigned int i = 0; i < bank->num_sectors; i++)
1122 bank->sectors[i].is_protected = 0;
1123
1124 /* now check WRPxy and mark the protected sectors */
1125 for (unsigned int i = 0; i < n_wrp; i++) {
1126 if (wrpxy[i].used) {
1127 for (int s = wrpxy[i].first; s <= wrpxy[i].last; s++)
1128 bank->sectors[s].is_protected = 1;
1129 }
1130 }
1131
1132 return ERROR_OK;
1133 }
1134
1135 static int stm32l4_erase(struct flash_bank *bank, unsigned int first,
1136 unsigned int last)
1137 {
1138 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1139 int retval, retval2;
1140
1141 assert((first <= last) && (last < bank->num_sectors));
1142
1143 if (stm32l4_is_otp(bank)) {
1144 LOG_ERROR("cannot erase OTP memory");
1145 return ERROR_FLASH_OPER_UNSUPPORTED;
1146 }
1147
1148 if (bank->target->state != TARGET_HALTED) {
1149 LOG_ERROR("Target not halted");
1150 return ERROR_TARGET_NOT_HALTED;
1151 }
1152
1153 if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
1154 /* set all FLASH pages as secure */
1155 retval = stm32l4_set_secbb(bank, FLASH_SECBB_SECURE);
1156 if (retval != ERROR_OK) {
1157 /* restore all FLASH pages as non-secure */
1158 stm32l4_set_secbb(bank, FLASH_SECBB_NON_SECURE); /* ignore the return value */
1159 return retval;
1160 }
1161 }
1162
1163 retval = stm32l4_unlock_reg(bank);
1164 if (retval != ERROR_OK)
1165 goto err_lock;
1166
1167 /*
1168 Sector Erase
1169 To erase a sector, follow the procedure below:
1170 1. Check that no Flash memory operation is ongoing by
1171 checking the BSY bit in the FLASH_SR register
1172 2. Set the PER bit and select the page and bank
1173 you wish to erase in the FLASH_CR register
1174 3. Set the STRT bit in the FLASH_CR register
1175 4. Wait for the BSY bit to be cleared
1176 */
1177
1178 for (unsigned int i = first; i <= last; i++) {
1179 uint32_t erase_flags;
1180 erase_flags = FLASH_PER | FLASH_STRT;
1181
1182 if (i >= stm32l4_info->bank1_sectors) {
1183 uint8_t snb;
1184 snb = i - stm32l4_info->bank1_sectors;
1185 erase_flags |= snb << FLASH_PAGE_SHIFT | stm32l4_info->cr_bker_mask;
1186 } else
1187 erase_flags |= i << FLASH_PAGE_SHIFT;
1188 retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, erase_flags);
1189 if (retval != ERROR_OK)
1190 break;
1191
1192 retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
1193 if (retval != ERROR_OK)
1194 break;
1195 }
1196
1197 err_lock:
1198 retval2 = stm32l4_write_flash_reg_by_index(bank, stm32l4_get_flash_cr_with_lock_index(bank), FLASH_LOCK);
1199
1200 if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
1201 /* restore all FLASH pages as non-secure */
1202 int retval3 = stm32l4_set_secbb(bank, FLASH_SECBB_NON_SECURE);
1203 if (retval3 != ERROR_OK)
1204 return retval3;
1205 }
1206
1207 if (retval != ERROR_OK)
1208 return retval;
1209
1210 return retval2;
1211 }
1212
1213 static int stm32l4_protect_same_bank(struct flash_bank *bank, enum stm32_bank_id bank_id, int set,
1214 unsigned int first, unsigned int last)
1215 {
1216 unsigned int i;
1217
1218 /* check if the desired protection is already configured */
1219 for (i = first; i <= last; i++) {
1220 if (bank->sectors[i].is_protected != set)
1221 break;
1222 else if (i == last) {
1223 LOG_INFO("The specified sectors are already %s", set ? "protected" : "unprotected");
1224 return ERROR_OK;
1225 }
1226 }
1227
1228 /* all sectors from first to last (or part of them) could have different
1229 * protection other than the requested */
1230 unsigned int n_wrp;
1231 struct stm32l4_wrp wrpxy[4];
1232
1233 int ret = stm32l4_get_all_wrpxy(bank, bank_id, wrpxy, &n_wrp);
1234 if (ret != ERROR_OK)
1235 return ret;
1236
1237 /* use bitmap and range helpers to optimize the WRP usage */
1238 DECLARE_BITMAP(pages, bank->num_sectors);
1239 bitmap_zero(pages, bank->num_sectors);
1240
1241 for (i = 0; i < n_wrp; i++) {
1242 if (wrpxy[i].used) {
1243 for (int p = wrpxy[i].first; p <= wrpxy[i].last; p++)
1244 set_bit(p, pages);
1245 }
1246 }
1247
1248 /* we have at most 'n_wrp' WRP areas
1249 * add one range if the user is trying to protect a fifth range */
1250 struct range ranges[n_wrp + 1];
1251 unsigned int ranges_count = 0;
1252
1253 bitmap_to_ranges(pages, bank->num_sectors, ranges, &ranges_count);
1254
1255 /* pretty-print the currently protected ranges */
1256 if (ranges_count > 0) {
1257 char *ranges_str = range_print_alloc(ranges, ranges_count);
1258 LOG_DEBUG("current protected areas: %s", ranges_str);
1259 free(ranges_str);
1260 } else
1261 LOG_DEBUG("current protected areas: none");
1262
1263 if (set) { /* flash protect */
1264 for (i = first; i <= last; i++)
1265 set_bit(i, pages);
1266 } else { /* flash unprotect */
1267 for (i = first; i <= last; i++)
1268 clear_bit(i, pages);
1269 }
1270
1271 /* check the ranges_count after the user request */
1272 bitmap_to_ranges(pages, bank->num_sectors, ranges, &ranges_count);
1273
1274 /* pretty-print the requested areas for protection */
1275 if (ranges_count > 0) {
1276 char *ranges_str = range_print_alloc(ranges, ranges_count);
1277 LOG_DEBUG("requested areas for protection: %s", ranges_str);
1278 free(ranges_str);
1279 } else
1280 LOG_DEBUG("requested areas for protection: none");
1281
1282 if (ranges_count > n_wrp) {
1283 LOG_ERROR("cannot set the requested protection "
1284 "(only %u write protection areas are available)" , n_wrp);
1285 return ERROR_FAIL;
1286 }
1287
1288 /* re-init all WRPxy as disabled (first > last)*/
1289 for (i = 0; i < n_wrp; i++) {
1290 wrpxy[i].first = wrpxy[i].offset + 1;
1291 wrpxy[i].last = wrpxy[i].offset;
1292 }
1293
1294 /* then configure WRPxy areas */
1295 for (i = 0; i < ranges_count; i++) {
1296 wrpxy[i].first = ranges[i].start;
1297 wrpxy[i].last = ranges[i].end;
1298 }
1299
1300 /* finally write WRPxy registers */
1301 return stm32l4_write_all_wrpxy(bank, wrpxy, n_wrp);
1302 }
1303
1304 static int stm32l4_protect(struct flash_bank *bank, int set, unsigned int first, unsigned int last)
1305 {
1306 struct target *target = bank->target;
1307 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1308
1309 if (stm32l4_is_otp(bank)) {
1310 LOG_ERROR("cannot protect/unprotect OTP memory");
1311 return ERROR_FLASH_OPER_UNSUPPORTED;
1312 }
1313
1314 if (target->state != TARGET_HALTED) {
1315 LOG_ERROR("Target not halted");
1316 return ERROR_TARGET_NOT_HALTED;
1317 }
1318
1319 /* refresh the sectors' protection */
1320 int ret = stm32l4_protect_check(bank);
1321 if (ret != ERROR_OK)
1322 return ret;
1323
1324 /* the requested sectors could be located into bank1 and/or bank2 */
1325 if (last < stm32l4_info->bank1_sectors) {
1326 return stm32l4_protect_same_bank(bank, STM32_BANK1, set, first, last);
1327 } else if (first >= stm32l4_info->bank1_sectors) {
1328 return stm32l4_protect_same_bank(bank, STM32_BANK2, set, first, last);
1329 } else {
1330 ret = stm32l4_protect_same_bank(bank, STM32_BANK1, set, first, stm32l4_info->bank1_sectors - 1);
1331 if (ret != ERROR_OK)
1332 return ret;
1333
1334 return stm32l4_protect_same_bank(bank, STM32_BANK2, set, stm32l4_info->bank1_sectors, last);
1335 }
1336 }
1337
1338 /* count is the size divided by stm32l4_info->data_width */
1339 static int stm32l4_write_block(struct flash_bank *bank, const uint8_t *buffer,
1340 uint32_t offset, uint32_t count)
1341 {
1342 struct target *target = bank->target;
1343 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1344 struct working_area *write_algorithm;
1345 struct working_area *source;
1346 uint32_t address = bank->base + offset;
1347 struct reg_param reg_params[5];
1348 struct armv7m_algorithm armv7m_info;
1349 int retval = ERROR_OK;
1350
1351 static const uint8_t stm32l4_flash_write_code[] = {
1352 #include "../../../contrib/loaders/flash/stm32/stm32l4x.inc"
1353 };
1354
1355 if (target_alloc_working_area(target, sizeof(stm32l4_flash_write_code),
1356 &write_algorithm) != ERROR_OK) {
1357 LOG_WARNING("no working area available, can't do block memory writes");
1358 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1359 }
1360
1361 retval = target_write_buffer(target, write_algorithm->address,
1362 sizeof(stm32l4_flash_write_code),
1363 stm32l4_flash_write_code);
1364 if (retval != ERROR_OK) {
1365 target_free_working_area(target, write_algorithm);
1366 return retval;
1367 }
1368
1369 /* data_width should be multiple of double-word */
1370 assert(stm32l4_info->data_width % 8 == 0);
1371 const size_t extra_size = sizeof(struct stm32l4_work_area);
1372 uint32_t buffer_size = target_get_working_area_avail(target) - extra_size;
1373 /* buffer_size should be multiple of stm32l4_info->data_width */
1374 buffer_size &= ~(stm32l4_info->data_width - 1);
1375
1376 if (buffer_size < 256) {
1377 LOG_WARNING("large enough working area not available, can't do block memory writes");
1378 target_free_working_area(target, write_algorithm);
1379 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1380 } else if (buffer_size > 16384) {
1381 /* probably won't benefit from more than 16k ... */
1382 buffer_size = 16384;
1383 }
1384
1385 if (target_alloc_working_area_try(target, buffer_size + extra_size, &source) != ERROR_OK) {
1386 LOG_ERROR("allocating working area failed");
1387 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1388 }
1389
1390 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
1391 armv7m_info.core_mode = ARM_MODE_THREAD;
1392
1393 /* contrib/loaders/flash/stm32/stm32l4x.c:write() arguments */
1394 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* stm32l4_work_area ptr , status (out) */
1395 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* buffer end */
1396 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT); /* target address */
1397 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT); /* count (of stm32l4_info->data_width) */
1398
1399 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1400 buf_set_u32(reg_params[1].value, 0, 32, source->address + source->size);
1401 buf_set_u32(reg_params[2].value, 0, 32, address);
1402 buf_set_u32(reg_params[3].value, 0, 32, count);
1403
1404 /* write algo stack pointer */
1405 init_reg_param(&reg_params[4], "sp", 32, PARAM_OUT);
1406 buf_set_u32(reg_params[4].value, 0, 32, source->address +
1407 offsetof(struct stm32l4_work_area, stack) + LDR_STACK_SIZE);
1408
1409 struct stm32l4_loader_params loader_extra_params;
1410
1411 target_buffer_set_u32(target, (uint8_t *) &loader_extra_params.flash_sr_addr,
1412 stm32l4_get_flash_reg_by_index(bank, STM32_FLASH_SR_INDEX));
1413 target_buffer_set_u32(target, (uint8_t *) &loader_extra_params.flash_cr_addr,
1414 stm32l4_get_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX));
1415 target_buffer_set_u32(target, (uint8_t *) &loader_extra_params.flash_word_size,
1416 stm32l4_info->data_width);
1417 target_buffer_set_u32(target, (uint8_t *) &loader_extra_params.flash_sr_bsy_mask,
1418 stm32l4_info->sr_bsy_mask);
1419
1420 retval = target_write_buffer(target, source->address, sizeof(loader_extra_params),
1421 (uint8_t *) &loader_extra_params);
1422 if (retval != ERROR_OK)
1423 return retval;
1424
1425 retval = target_run_flash_async_algorithm(target, buffer, count, stm32l4_info->data_width,
1426 0, NULL,
1427 ARRAY_SIZE(reg_params), reg_params,
1428 source->address + offsetof(struct stm32l4_work_area, fifo),
1429 source->size - offsetof(struct stm32l4_work_area, fifo),
1430 write_algorithm->address, 0,
1431 &armv7m_info);
1432
1433 if (retval == ERROR_FLASH_OPERATION_FAILED) {
1434 LOG_ERROR("error executing stm32l4 flash write algorithm");
1435
1436 uint32_t error;
1437 stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_SR_INDEX, &error);
1438 error &= FLASH_ERROR;
1439
1440 if (error & FLASH_WRPERR)
1441 LOG_ERROR("flash memory write protected");
1442
1443 if (error != 0) {
1444 LOG_ERROR("flash write failed = %08" PRIx32, error);
1445 /* Clear but report errors */
1446 stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_SR_INDEX, error);
1447 retval = ERROR_FAIL;
1448 }
1449 }
1450
1451 target_free_working_area(target, source);
1452 target_free_working_area(target, write_algorithm);
1453
1454 destroy_reg_param(&reg_params[0]);
1455 destroy_reg_param(&reg_params[1]);
1456 destroy_reg_param(&reg_params[2]);
1457 destroy_reg_param(&reg_params[3]);
1458 destroy_reg_param(&reg_params[4]);
1459
1460 return retval;
1461 }
1462
1463 /* count is the size divided by stm32l4_info->data_width */
1464 static int stm32l4_write_block_without_loader(struct flash_bank *bank, const uint8_t *buffer,
1465 uint32_t offset, uint32_t count)
1466 {
1467 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1468 struct target *target = bank->target;
1469 uint32_t address = bank->base + offset;
1470 int retval = ERROR_OK;
1471
1472 /* wait for BSY bit */
1473 retval = stm32l4_wait_status_busy(bank, FLASH_WRITE_TIMEOUT);
1474 if (retval != ERROR_OK)
1475 return retval;
1476
1477 /* set PG in FLASH_CR */
1478 retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, FLASH_PG);
1479 if (retval != ERROR_OK)
1480 return retval;
1481
1482
1483 /* write directly to flash memory */
1484 const uint8_t *src = buffer;
1485 const uint32_t data_width_in_words = stm32l4_info->data_width / 4;
1486 while (count--) {
1487 retval = target_write_memory(target, address, 4, data_width_in_words, src);
1488 if (retval != ERROR_OK)
1489 return retval;
1490
1491 /* wait for BSY bit */
1492 retval = stm32l4_wait_status_busy(bank, FLASH_WRITE_TIMEOUT);
1493 if (retval != ERROR_OK)
1494 return retval;
1495
1496 src += stm32l4_info->data_width;
1497 address += stm32l4_info->data_width;
1498 }
1499
1500 /* reset PG in FLASH_CR */
1501 retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, 0);
1502 if (retval != ERROR_OK)
1503 return retval;
1504
1505 return retval;
1506 }
1507
1508 static int stm32l4_write(struct flash_bank *bank, const uint8_t *buffer,
1509 uint32_t offset, uint32_t count)
1510 {
1511 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1512 int retval = ERROR_OK, retval2;
1513
1514 if (stm32l4_is_otp(bank) && !stm32l4_otp_is_enabled(bank)) {
1515 LOG_ERROR("OTP memory is disabled for write commands");
1516 return ERROR_FAIL;
1517 }
1518
1519 if (bank->target->state != TARGET_HALTED) {
1520 LOG_ERROR("Target not halted");
1521 return ERROR_TARGET_NOT_HALTED;
1522 }
1523
1524 /* ensure that stm32l4_info->data_width is 'at least' a multiple of dword */
1525 assert(stm32l4_info->data_width % 8 == 0);
1526
1527 /* The flash write must be aligned to the 'stm32l4_info->data_width' boundary.
1528 * The flash infrastructure ensures it, do just a security check */
1529 assert(offset % stm32l4_info->data_width == 0);
1530 assert(count % stm32l4_info->data_width == 0);
1531
1532 /* STM32G4xxx Cat. 3 devices may have gaps between banks, check whether
1533 * data to be written does not go into a gap:
1534 * suppose buffer is fully contained in bank from sector 0 to sector
1535 * num->sectors - 1 and sectors are ordered according to offset
1536 */
1537 struct flash_sector *head = &bank->sectors[0];
1538 struct flash_sector *tail = &bank->sectors[bank->num_sectors - 1];
1539
1540 while ((head < tail) && (offset >= (head + 1)->offset)) {
1541 /* buffer does not intersect head nor gap behind head */
1542 head++;
1543 }
1544
1545 while ((head < tail) && (offset + count <= (tail - 1)->offset + (tail - 1)->size)) {
1546 /* buffer does not intersect tail nor gap before tail */
1547 --tail;
1548 }
1549
1550 LOG_DEBUG("data: 0x%08" PRIx32 " - 0x%08" PRIx32 ", sectors: 0x%08" PRIx32 " - 0x%08" PRIx32,
1551 offset, offset + count - 1, head->offset, tail->offset + tail->size - 1);
1552
1553 /* Now check that there is no gap from head to tail, this should work
1554 * even for multiple or non-symmetric gaps
1555 */
1556 while (head < tail) {
1557 if (head->offset + head->size != (head + 1)->offset) {
1558 LOG_ERROR("write into gap from " TARGET_ADDR_FMT " to " TARGET_ADDR_FMT,
1559 bank->base + head->offset + head->size,
1560 bank->base + (head + 1)->offset - 1);
1561 retval = ERROR_FLASH_DST_OUT_OF_BANK;
1562 }
1563 head++;
1564 }
1565
1566 if (retval != ERROR_OK)
1567 return retval;
1568
1569 if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
1570 /* set all FLASH pages as secure */
1571 retval = stm32l4_set_secbb(bank, FLASH_SECBB_SECURE);
1572 if (retval != ERROR_OK) {
1573 /* restore all FLASH pages as non-secure */
1574 stm32l4_set_secbb(bank, FLASH_SECBB_NON_SECURE); /* ignore the return value */
1575 return retval;
1576 }
1577 }
1578
1579 retval = stm32l4_unlock_reg(bank);
1580 if (retval != ERROR_OK)
1581 goto err_lock;
1582
1583
1584 /* For TrustZone enabled devices, when TZEN is set and RDP level is 0.5,
1585 * the debug is possible only in non-secure state.
1586 * Thus means the flashloader will run in non-secure mode,
1587 * and the workarea need to be in non-secure RAM */
1588 if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0_5))
1589 LOG_WARNING("RDP = 0x55, the work-area should be in non-secure RAM (check SAU partitioning)");
1590
1591 /* first try to write using the loader, for better performance */
1592 retval = stm32l4_write_block(bank, buffer, offset,
1593 count / stm32l4_info->data_width);
1594
1595 /* if resources are not available write without a loader */
1596 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
1597 LOG_WARNING("falling back to programming without a flash loader (slower)");
1598 retval = stm32l4_write_block_without_loader(bank, buffer, offset,
1599 count / stm32l4_info->data_width);
1600 }
1601
1602 err_lock:
1603 retval2 = stm32l4_write_flash_reg_by_index(bank, stm32l4_get_flash_cr_with_lock_index(bank), FLASH_LOCK);
1604
1605 if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
1606 /* restore all FLASH pages as non-secure */
1607 int retval3 = stm32l4_set_secbb(bank, FLASH_SECBB_NON_SECURE);
1608 if (retval3 != ERROR_OK)
1609 return retval3;
1610 }
1611
1612 if (retval != ERROR_OK) {
1613 LOG_ERROR("block write failed");
1614 return retval;
1615 }
1616 return retval2;
1617 }
1618
1619 static int stm32l4_read_idcode(struct flash_bank *bank, uint32_t *id)
1620 {
1621 int retval = ERROR_OK;
1622 struct target *target = bank->target;
1623
1624 /* try reading possible IDCODE registers, in the following order */
1625 uint32_t dbgmcu_idcode[] = {DBGMCU_IDCODE_L4_G4, DBGMCU_IDCODE_G0, DBGMCU_IDCODE_L5};
1626
1627 for (unsigned int i = 0; i < ARRAY_SIZE(dbgmcu_idcode); i++) {
1628 retval = target_read_u32(target, dbgmcu_idcode[i], id);
1629 if ((retval == ERROR_OK) && ((*id & 0xfff) != 0) && ((*id & 0xfff) != 0xfff))
1630 return ERROR_OK;
1631 }
1632
1633 /* Workaround for STM32WL5x devices:
1634 * DBGMCU_IDCODE cannot be read using CPU1 (Cortex-M0+) at AP1,
1635 * to solve this read the UID64 (IEEE 64-bit unique device ID register) */
1636
1637 struct armv7m_common *armv7m = target_to_armv7m_safe(target);
1638 if (!armv7m) {
1639 LOG_ERROR("Flash requires Cortex-M target");
1640 return ERROR_TARGET_INVALID;
1641 }
1642
1643 /* CPU2 (Cortex-M0+) is supported only with non-hla adapters because it is on AP1.
1644 * Using HLA adapters armv7m.debug_ap is null, and checking ap_num triggers a segfault */
1645 if (cortex_m_get_partno_safe(target) == CORTEX_M0P_PARTNO &&
1646 armv7m->debug_ap && armv7m->debug_ap->ap_num == 1) {
1647 uint32_t uid64_ids;
1648
1649 /* UID64 is contains
1650 * - Bits 63:32 : DEVNUM (unique device number, different for each individual device)
1651 * - Bits 31:08 : STID (company ID) = 0x0080E1
1652 * - Bits 07:00 : DEVID (device ID) = 0x15
1653 *
1654 * read only the fixed values {STID,DEVID} from UID64_IDS to identify the device as STM32WLx
1655 */
1656 retval = target_read_u32(target, UID64_IDS, &uid64_ids);
1657 if (retval == ERROR_OK && uid64_ids == UID64_IDS_STM32WL) {
1658 /* force the DEV_ID to DEVID_STM32WLE_WL5XX and the REV_ID to unknown */
1659 *id = DEVID_STM32WLE_WL5XX;
1660 return ERROR_OK;
1661 }
1662 }
1663
1664 LOG_ERROR("can't get the device id");
1665 return (retval == ERROR_OK) ? ERROR_FAIL : retval;
1666 }
1667
1668 static const char *get_stm32l4_rev_str(struct flash_bank *bank)
1669 {
1670 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1671 const struct stm32l4_part_info *part_info = stm32l4_info->part_info;
1672 assert(part_info);
1673
1674 const uint16_t rev_id = stm32l4_info->idcode >> 16;
1675 for (unsigned int i = 0; i < part_info->num_revs; i++) {
1676 if (rev_id == part_info->revs[i].rev)
1677 return part_info->revs[i].str;
1678 }
1679 return "'unknown'";
1680 }
1681
1682 static const char *get_stm32l4_bank_type_str(struct flash_bank *bank)
1683 {
1684 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1685 assert(stm32l4_info->part_info);
1686 return stm32l4_is_otp(bank) ? "OTP" :
1687 stm32l4_info->dual_bank_mode ? "Flash dual" :
1688 "Flash single";
1689 }
1690
1691 static int stm32l4_probe(struct flash_bank *bank)
1692 {
1693 struct target *target = bank->target;
1694 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1695 const struct stm32l4_part_info *part_info;
1696 uint16_t flash_size_kb = 0xffff;
1697
1698 if (!target_was_examined(target)) {
1699 LOG_ERROR("Target not examined yet");
1700 return ERROR_TARGET_NOT_EXAMINED;
1701 }
1702
1703 struct armv7m_common *armv7m = target_to_armv7m_safe(target);
1704 if (!armv7m) {
1705 LOG_ERROR("Flash requires Cortex-M target");
1706 return ERROR_TARGET_INVALID;
1707 }
1708
1709 stm32l4_info->probed = false;
1710
1711 /* read stm32 device id registers */
1712 int retval = stm32l4_read_idcode(bank, &stm32l4_info->idcode);
1713 if (retval != ERROR_OK)
1714 return retval;
1715
1716 const uint32_t device_id = stm32l4_info->idcode & 0xFFF;
1717
1718 for (unsigned int n = 0; n < ARRAY_SIZE(stm32l4_parts); n++) {
1719 if (device_id == stm32l4_parts[n].id) {
1720 stm32l4_info->part_info = &stm32l4_parts[n];
1721 break;
1722 }
1723 }
1724
1725 if (!stm32l4_info->part_info) {
1726 LOG_WARNING("Cannot identify target as an %s family device.", device_families);
1727 return ERROR_FAIL;
1728 }
1729
1730 part_info = stm32l4_info->part_info;
1731 const char *rev_str = get_stm32l4_rev_str(bank);
1732 const uint16_t rev_id = stm32l4_info->idcode >> 16;
1733
1734 LOG_INFO("device idcode = 0x%08" PRIx32 " (%s - Rev %s : 0x%04x)",
1735 stm32l4_info->idcode, part_info->device_str, rev_str, rev_id);
1736
1737 stm32l4_info->flash_regs_base = stm32l4_info->part_info->flash_regs_base;
1738 stm32l4_info->data_width = (part_info->flags & F_QUAD_WORD_PROG) ? 16 : 8;
1739 stm32l4_info->cr_bker_mask = FLASH_BKER;
1740 stm32l4_info->sr_bsy_mask = FLASH_BSY;
1741
1742 /* Set flash write alignment boundaries.
1743 * Ask the flash infrastructure to ensure required alignment */
1744 bank->write_start_alignment = stm32l4_info->data_width;
1745 bank->write_end_alignment = stm32l4_info->data_width;
1746
1747 /* Initialize the flash registers layout */
1748 if (part_info->flags & F_HAS_L5_FLASH_REGS)
1749 stm32l4_info->flash_regs = stm32l5_ns_flash_regs;
1750 else
1751 stm32l4_info->flash_regs = stm32l4_flash_regs;
1752
1753 /* read flash option register */
1754 retval = stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_OPTR_INDEX, &stm32l4_info->optr);
1755 if (retval != ERROR_OK)
1756 return retval;
1757
1758 stm32l4_sync_rdp_tzen(bank);
1759
1760 /* for devices with TrustZone, use flash secure registers when TZEN=1 and RDP is LEVEL_0 */
1761 if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
1762 if (part_info->flags & F_HAS_L5_FLASH_REGS) {
1763 stm32l4_info->flash_regs_base |= STM32L5_REGS_SEC_OFFSET;
1764 stm32l4_info->flash_regs = stm32l5_s_flash_regs;
1765 } else {
1766 LOG_ERROR("BUG: device supported incomplete");
1767 return ERROR_NOT_IMPLEMENTED;
1768 }
1769 }
1770
1771 if (part_info->flags & F_HAS_TZ)
1772 LOG_INFO("TZEN = %d : TrustZone %s by option bytes",
1773 stm32l4_info->tzen,
1774 stm32l4_info->tzen ? "enabled" : "disabled");
1775
1776 LOG_INFO("RDP level %s (0x%02X)",
1777 stm32l4_info->rdp == RDP_LEVEL_0 ? "0" : stm32l4_info->rdp == RDP_LEVEL_0_5 ? "0.5" : "1",
1778 stm32l4_info->rdp);
1779
1780 if (stm32l4_is_otp(bank)) {
1781 bank->size = part_info->otp_size;
1782
1783 LOG_INFO("OTP size is %d bytes, base address is " TARGET_ADDR_FMT, bank->size, bank->base);
1784
1785 /* OTP memory is considered as one sector */
1786 free(bank->sectors);
1787 bank->num_sectors = 1;
1788 bank->sectors = alloc_block_array(0, part_info->otp_size, 1);
1789
1790 if (!bank->sectors) {
1791 LOG_ERROR("failed to allocate bank sectors");
1792 return ERROR_FAIL;
1793 }
1794
1795 stm32l4_info->probed = true;
1796 return ERROR_OK;
1797 } else if (bank->base != STM32_FLASH_BANK_BASE && bank->base != STM32_FLASH_S_BANK_BASE) {
1798 LOG_ERROR("invalid bank base address");
1799 return ERROR_FAIL;
1800 }
1801
1802 /* get flash size from target. */
1803 retval = target_read_u16(target, part_info->fsize_addr, &flash_size_kb);
1804
1805 /* failed reading flash size or flash size invalid (early silicon),
1806 * default to max target family */
1807 if (retval != ERROR_OK || flash_size_kb == 0xffff || flash_size_kb == 0
1808 || flash_size_kb > part_info->max_flash_size_kb) {
1809 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
1810 part_info->max_flash_size_kb);
1811 flash_size_kb = part_info->max_flash_size_kb;
1812 }
1813
1814 /* if the user sets the size manually then ignore the probed value
1815 * this allows us to work around devices that have a invalid flash size register value */
1816 if (stm32l4_info->user_bank_size) {
1817 LOG_WARNING("overriding size register by configured bank size - MAY CAUSE TROUBLE");
1818 flash_size_kb = stm32l4_info->user_bank_size / 1024;
1819 }
1820
1821 LOG_INFO("flash size = %d KiB", flash_size_kb);
1822
1823 /* did we assign a flash size? */
1824 assert((flash_size_kb != 0xffff) && flash_size_kb);
1825
1826 const bool is_max_flash_size = flash_size_kb == stm32l4_info->part_info->max_flash_size_kb;
1827
1828 stm32l4_info->bank1_sectors = 0;
1829 stm32l4_info->hole_sectors = 0;
1830
1831 int num_pages = 0;
1832 int page_size_kb = 0;
1833
1834 stm32l4_info->dual_bank_mode = false;
1835
1836 switch (device_id) {
1837 case DEVID_STM32L47_L48XX:
1838 case DEVID_STM32L49_L4AXX:
1839 /* if flash size is max (1M) the device is always dual bank
1840 * STM32L47/L48xx: has variants with 512K
1841 * STM32L49/L4Axx: has variants with 512 and 256
1842 * for these variants:
1843 * if DUAL_BANK = 0 -> single bank
1844 * else -> dual bank without gap
1845 * note: the page size is invariant
1846 */
1847 page_size_kb = 2;
1848 num_pages = flash_size_kb / page_size_kb;
1849 stm32l4_info->bank1_sectors = num_pages;
1850
1851 /* check DUAL_BANK option bit if the flash is less than 1M */
1852 if (is_max_flash_size || (stm32l4_info->optr & FLASH_L4_DUAL_BANK)) {
1853 stm32l4_info->dual_bank_mode = true;
1854 stm32l4_info->bank1_sectors = num_pages / 2;
1855 }
1856 break;
1857 case DEVID_STM32L43_L44XX:
1858 case DEVID_STM32G05_G06XX:
1859 case DEVID_STM32G07_G08XX:
1860 case DEVID_STM32L45_L46XX:
1861 case DEVID_STM32L41_L42XX:
1862 case DEVID_STM32G03_G04XX:
1863 case DEVID_STM32G43_G44XX:
1864 case DEVID_STM32G49_G4AXX:
1865 case DEVID_STM32WB1XX:
1866 /* single bank flash */
1867 page_size_kb = 2;
1868 num_pages = flash_size_kb / page_size_kb;
1869 stm32l4_info->bank1_sectors = num_pages;
1870 break;
1871 case DEVID_STM32G0B_G0CXX:
1872 /* single/dual bank depending on DUAL_BANK option bit */
1873 page_size_kb = 2;
1874 num_pages = flash_size_kb / page_size_kb;
1875 stm32l4_info->bank1_sectors = num_pages;
1876 stm32l4_info->cr_bker_mask = FLASH_BKER_G0;
1877
1878 /* check DUAL_BANK bit */
1879 if (stm32l4_info->optr & FLASH_G0_DUAL_BANK) {
1880 stm32l4_info->sr_bsy_mask = FLASH_BSY | FLASH_BSY2;
1881 stm32l4_info->dual_bank_mode = true;
1882 stm32l4_info->bank1_sectors = num_pages / 2;
1883 }
1884 break;
1885 case DEVID_STM32G47_G48XX:
1886 /* STM32G47/8 can be single/dual bank:
1887 * if DUAL_BANK = 0 -> single bank
1888 * else -> dual bank WITH gap
1889 */
1890 page_size_kb = 4;
1891 num_pages = flash_size_kb / page_size_kb;
1892 stm32l4_info->bank1_sectors = num_pages;
1893 if (stm32l4_info->optr & FLASH_G4_DUAL_BANK) {
1894 stm32l4_info->dual_bank_mode = true;
1895 page_size_kb = 2;
1896 num_pages = flash_size_kb / page_size_kb;
1897 stm32l4_info->bank1_sectors = num_pages / 2;
1898
1899 /* for devices with trimmed flash, there is a gap between both banks */
1900 stm32l4_info->hole_sectors =
1901 (part_info->max_flash_size_kb - flash_size_kb) / (2 * page_size_kb);
1902 }
1903 break;
1904 case DEVID_STM32L4R_L4SXX:
1905 case DEVID_STM32L4P_L4QXX:
1906 /* STM32L4R/S can be single/dual bank:
1907 * if size = 2M check DBANK bit
1908 * if size = 1M check DB1M bit
1909 * STM32L4P/Q can be single/dual bank
1910 * if size = 1M check DBANK bit
1911 * if size = 512K check DB512K bit (same as DB1M bit)
1912 */
1913 page_size_kb = 8;
1914 num_pages = flash_size_kb / page_size_kb;
1915 stm32l4_info->bank1_sectors = num_pages;
1916 if ((is_max_flash_size && (stm32l4_info->optr & FLASH_L4R_DBANK)) ||
1917 (!is_max_flash_size && (stm32l4_info->optr & FLASH_LRR_DB1M))) {
1918 stm32l4_info->dual_bank_mode = true;
1919 page_size_kb = 4;
1920 num_pages = flash_size_kb / page_size_kb;
1921 stm32l4_info->bank1_sectors = num_pages / 2;
1922 }
1923 break;
1924 case DEVID_STM32L55_L56XX:
1925 /* STM32L55/L56xx can be single/dual bank:
1926 * if size = 512K check DBANK bit
1927 * if size = 256K check DB256K bit
1928 *
1929 * default page size is 4kb, if DBANK = 1, the page size is 2kb.
1930 */
1931
1932 page_size_kb = (stm32l4_info->optr & FLASH_L5_DBANK) ? 2 : 4;
1933 num_pages = flash_size_kb / page_size_kb;
1934 stm32l4_info->bank1_sectors = num_pages;
1935
1936 if ((is_max_flash_size && (stm32l4_info->optr & FLASH_L5_DBANK)) ||
1937 (!is_max_flash_size && (stm32l4_info->optr & FLASH_L5_DB256))) {
1938 stm32l4_info->dual_bank_mode = true;
1939 stm32l4_info->bank1_sectors = num_pages / 2;
1940 }
1941 break;
1942 case DEVID_STM32U57_U58XX:
1943 /* if flash size is max (2M) the device is always dual bank
1944 * otherwise check DUALBANK
1945 */
1946 page_size_kb = 8;
1947 num_pages = flash_size_kb / page_size_kb;
1948 stm32l4_info->bank1_sectors = num_pages;
1949 if (is_max_flash_size || (stm32l4_info->optr & FLASH_U5_DUALBANK)) {
1950 stm32l4_info->dual_bank_mode = true;
1951 stm32l4_info->bank1_sectors = num_pages / 2;
1952 }
1953 break;
1954 case DEVID_STM32WB5XX:
1955 case DEVID_STM32WB3XX:
1956 /* single bank flash */
1957 page_size_kb = 4;
1958 num_pages = flash_size_kb / page_size_kb;
1959 stm32l4_info->bank1_sectors = num_pages;
1960 break;
1961 case DEVID_STM32WLE_WL5XX:
1962 /* single bank flash */
1963 page_size_kb = 2;
1964 num_pages = flash_size_kb / page_size_kb;
1965 stm32l4_info->bank1_sectors = num_pages;
1966
1967 /* CPU2 (Cortex-M0+) is supported only with non-hla adapters because it is on AP1.
1968 * Using HLA adapters armv7m->debug_ap is null, and checking ap_num triggers a segfault */
1969 if (armv7m->debug_ap && armv7m->debug_ap->ap_num == 1)
1970 stm32l4_info->flash_regs = stm32wl_cpu2_flash_regs;
1971 break;
1972 default:
1973 LOG_ERROR("unsupported device");
1974 return ERROR_FAIL;
1975 }
1976
1977 /* ensure that at least there is 1 flash sector / page */
1978 if (num_pages == 0) {
1979 if (stm32l4_info->user_bank_size)
1980 LOG_ERROR("The specified flash size is less than page size");
1981
1982 LOG_ERROR("Flash pages count cannot be zero");
1983 return ERROR_FAIL;
1984 }
1985
1986 LOG_INFO("flash mode : %s-bank", stm32l4_info->dual_bank_mode ? "dual" : "single");
1987
1988 const int gap_size_kb = stm32l4_info->hole_sectors * page_size_kb;
1989
1990 if (gap_size_kb != 0) {
1991 LOG_INFO("gap detected from 0x%08x to 0x%08x",
1992 STM32_FLASH_BANK_BASE + stm32l4_info->bank1_sectors
1993 * page_size_kb * 1024,
1994 STM32_FLASH_BANK_BASE + (stm32l4_info->bank1_sectors
1995 * page_size_kb + gap_size_kb) * 1024 - 1);
1996 }
1997
1998 /* number of significant bits in WRPxxR differs per device,
1999 * always right adjusted, on some devices non-implemented
2000 * bits read as '0', on others as '1' ...
2001 * notably G4 Cat. 2 implement only 6 bits, contradicting the RM
2002 */
2003
2004 /* use *max_flash_size* instead of actual size as the trimmed versions
2005 * certainly use the same number of bits
2006 */
2007 uint32_t max_pages = stm32l4_info->part_info->max_flash_size_kb / page_size_kb;
2008
2009 /* in dual bank mode number of pages is doubled, but extra bit is bank selection */
2010 stm32l4_info->wrpxxr_mask = ((max_pages >> (stm32l4_info->dual_bank_mode ? 1 : 0)) - 1);
2011 assert((stm32l4_info->wrpxxr_mask & 0xFFFF0000) == 0);
2012 LOG_DEBUG("WRPxxR mask 0x%04" PRIx16, (uint16_t)stm32l4_info->wrpxxr_mask);
2013
2014 free(bank->sectors);
2015
2016 bank->size = (flash_size_kb + gap_size_kb) * 1024;
2017 bank->num_sectors = num_pages;
2018 bank->sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
2019 if (!bank->sectors) {
2020 LOG_ERROR("failed to allocate bank sectors");
2021 return ERROR_FAIL;
2022 }
2023
2024 for (unsigned int i = 0; i < bank->num_sectors; i++) {
2025 bank->sectors[i].offset = i * page_size_kb * 1024;
2026 /* in dual bank configuration, if there is a gap between banks
2027 * we fix up the sector offset to consider this gap */
2028 if (i >= stm32l4_info->bank1_sectors && stm32l4_info->hole_sectors)
2029 bank->sectors[i].offset += gap_size_kb * 1024;
2030 bank->sectors[i].size = page_size_kb * 1024;
2031 bank->sectors[i].is_erased = -1;
2032 bank->sectors[i].is_protected = 1;
2033 }
2034
2035 stm32l4_info->probed = true;
2036 return ERROR_OK;
2037 }
2038
2039 static int stm32l4_auto_probe(struct flash_bank *bank)
2040 {
2041 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
2042 if (stm32l4_info->probed) {
2043 uint32_t optr_cur;
2044
2045 /* save flash_regs_base */
2046 uint32_t saved_flash_regs_base = stm32l4_info->flash_regs_base;
2047
2048 /* for devices with TrustZone, use NS flash registers to read OPTR */
2049 if (stm32l4_info->part_info->flags & F_HAS_L5_FLASH_REGS)
2050 stm32l4_info->flash_regs_base &= ~STM32L5_REGS_SEC_OFFSET;
2051
2052 /* read flash option register and re-probe if optr value is changed */
2053 int retval = stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_OPTR_INDEX, &optr_cur);
2054
2055 /* restore saved flash_regs_base */
2056 stm32l4_info->flash_regs_base = saved_flash_regs_base;
2057
2058 if (retval != ERROR_OK)
2059 return retval;
2060
2061 if (stm32l4_info->optr == optr_cur)
2062 return ERROR_OK;
2063 }
2064
2065 return stm32l4_probe(bank);
2066 }
2067
2068 static int get_stm32l4_info(struct flash_bank *bank, struct command_invocation *cmd)
2069 {
2070 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
2071 const struct stm32l4_part_info *part_info = stm32l4_info->part_info;
2072
2073 if (part_info) {
2074 const uint16_t rev_id = stm32l4_info->idcode >> 16;
2075 command_print_sameline(cmd, "%s - Rev %s : 0x%04x", part_info->device_str,
2076 get_stm32l4_rev_str(bank), rev_id);
2077 if (stm32l4_info->probed)
2078 command_print_sameline(cmd, " - %s-bank", get_stm32l4_bank_type_str(bank));
2079 } else {
2080 command_print_sameline(cmd, "Cannot identify target as an %s device", device_families);
2081 }
2082
2083 return ERROR_OK;
2084 }
2085
2086 static int stm32l4_mass_erase(struct flash_bank *bank)
2087 {
2088 int retval, retval2;
2089 struct target *target = bank->target;
2090 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
2091
2092 if (stm32l4_is_otp(bank)) {
2093 LOG_ERROR("cannot erase OTP memory");
2094 return ERROR_FLASH_OPER_UNSUPPORTED;
2095 }
2096
2097 uint32_t action = FLASH_MER1;
2098
2099 if (stm32l4_info->part_info->flags & F_HAS_DUAL_BANK)
2100 action |= FLASH_MER2;
2101
2102 if (target->state != TARGET_HALTED) {
2103 LOG_ERROR("Target not halted");
2104 return ERROR_TARGET_NOT_HALTED;
2105 }
2106
2107 if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
2108 /* set all FLASH pages as secure */
2109 retval = stm32l4_set_secbb(bank, FLASH_SECBB_SECURE);
2110 if (retval != ERROR_OK) {
2111 /* restore all FLASH pages as non-secure */
2112 stm32l4_set_secbb(bank, FLASH_SECBB_NON_SECURE); /* ignore the return value */
2113 return retval;
2114 }
2115 }
2116
2117 retval = stm32l4_unlock_reg(bank);
2118 if (retval != ERROR_OK)
2119 goto err_lock;
2120
2121 /* mass erase flash memory */
2122 retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT / 10);
2123 if (retval != ERROR_OK)
2124 goto err_lock;
2125
2126 retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, action);
2127 if (retval != ERROR_OK)
2128 goto err_lock;
2129
2130 retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, action | FLASH_STRT);
2131 if (retval != ERROR_OK)
2132 goto err_lock;
2133
2134 retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
2135
2136 err_lock:
2137 retval2 = stm32l4_write_flash_reg_by_index(bank, stm32l4_get_flash_cr_with_lock_index(bank), FLASH_LOCK);
2138
2139 if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
2140 /* restore all FLASH pages as non-secure */
2141 int retval3 = stm32l4_set_secbb(bank, FLASH_SECBB_NON_SECURE);
2142 if (retval3 != ERROR_OK)
2143 return retval3;
2144 }
2145
2146 if (retval != ERROR_OK)
2147 return retval;
2148
2149 return retval2;
2150 }
2151
2152 COMMAND_HANDLER(stm32l4_handle_mass_erase_command)
2153 {
2154 if (CMD_ARGC < 1) {
2155 command_print(CMD, "stm32l4x mass_erase <STM32L4 bank>");
2156 return ERROR_COMMAND_SYNTAX_ERROR;
2157 }
2158
2159 struct flash_bank *bank;
2160 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2161 if (retval != ERROR_OK)
2162 return retval;
2163
2164 retval = stm32l4_mass_erase(bank);
2165 if (retval == ERROR_OK)
2166 command_print(CMD, "stm32l4x mass erase complete");
2167 else
2168 command_print(CMD, "stm32l4x mass erase failed");
2169
2170 return retval;
2171 }
2172
2173 COMMAND_HANDLER(stm32l4_handle_option_read_command)
2174 {
2175 if (CMD_ARGC < 2) {
2176 command_print(CMD, "stm32l4x option_read <STM32L4 bank> <option_reg offset>");
2177 return ERROR_COMMAND_SYNTAX_ERROR;
2178 }
2179
2180 struct flash_bank *bank;
2181 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2182 if (retval != ERROR_OK)
2183 return retval;
2184
2185 uint32_t reg_offset, reg_addr;
2186 uint32_t value = 0;
2187
2188 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], reg_offset);
2189 reg_addr = stm32l4_get_flash_reg(bank, reg_offset);
2190
2191 retval = stm32l4_read_flash_reg(bank, reg_offset, &value);
2192 if (retval != ERROR_OK)
2193 return retval;
2194
2195 command_print(CMD, "Option Register: <0x%" PRIx32 "> = 0x%" PRIx32 "", reg_addr, value);
2196
2197 return retval;
2198 }
2199
2200 COMMAND_HANDLER(stm32l4_handle_option_write_command)
2201 {
2202 if (CMD_ARGC < 3) {
2203 command_print(CMD, "stm32l4x option_write <STM32L4 bank> <option_reg offset> <value> [mask]");
2204 return ERROR_COMMAND_SYNTAX_ERROR;
2205 }
2206
2207 struct flash_bank *bank;
2208 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2209 if (retval != ERROR_OK)
2210 return retval;
2211
2212 uint32_t reg_offset;
2213 uint32_t value = 0;
2214 uint32_t mask = 0xFFFFFFFF;
2215
2216 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], reg_offset);
2217 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value);
2218
2219 if (CMD_ARGC > 3)
2220 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[3], mask);
2221
2222 command_print(CMD, "%s Option written.\n"
2223 "INFO: a reset or power cycle is required "
2224 "for the new settings to take effect.", bank->driver->name);
2225
2226 retval = stm32l4_write_option(bank, reg_offset, value, mask);
2227 return retval;
2228 }
2229
2230 COMMAND_HANDLER(stm32l4_handle_trustzone_command)
2231 {
2232 if (CMD_ARGC < 1 || CMD_ARGC > 2)
2233 return ERROR_COMMAND_SYNTAX_ERROR;
2234
2235 struct flash_bank *bank;
2236 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2237 if (retval != ERROR_OK)
2238 return retval;
2239
2240 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
2241 if (!(stm32l4_info->part_info->flags & F_HAS_TZ)) {
2242 LOG_ERROR("This device does not have a TrustZone");
2243 return ERROR_FAIL;
2244 }
2245
2246 retval = stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_OPTR_INDEX, &stm32l4_info->optr);
2247 if (retval != ERROR_OK)
2248 return retval;
2249
2250 stm32l4_sync_rdp_tzen(bank);
2251
2252 if (CMD_ARGC == 1) {
2253 /* only display the TZEN value */
2254 LOG_INFO("Global TrustZone Security is %s", stm32l4_info->tzen ? "enabled" : "disabled");
2255 return ERROR_OK;
2256 }
2257
2258 bool new_tzen;
2259 COMMAND_PARSE_ENABLE(CMD_ARGV[1], new_tzen);
2260
2261 if (new_tzen == stm32l4_info->tzen) {
2262 LOG_INFO("The requested TZEN is already programmed");
2263 return ERROR_OK;
2264 }
2265
2266 if (new_tzen) {
2267 if (stm32l4_info->rdp != RDP_LEVEL_0) {
2268 LOG_ERROR("TZEN can be set only when RDP level is 0");
2269 return ERROR_FAIL;
2270 }
2271 retval = stm32l4_write_option(bank, stm32l4_info->flash_regs[STM32_FLASH_OPTR_INDEX],
2272 FLASH_TZEN, FLASH_TZEN);
2273 } else {
2274 /* Deactivation of TZEN (from 1 to 0) is only possible when the RDP is
2275 * changing to level 0 (from level 1 to level 0 or from level 0.5 to level 0). */
2276 if (stm32l4_info->rdp != RDP_LEVEL_1 && stm32l4_info->rdp != RDP_LEVEL_0_5) {
2277 LOG_ERROR("Deactivation of TZEN is only possible when the RDP is changing to level 0");
2278 return ERROR_FAIL;
2279 }
2280
2281 retval = stm32l4_write_option(bank, stm32l4_info->flash_regs[STM32_FLASH_OPTR_INDEX],
2282 RDP_LEVEL_0, FLASH_RDP_MASK | FLASH_TZEN);
2283 }
2284
2285 if (retval != ERROR_OK)
2286 return retval;
2287
2288 return stm32l4_perform_obl_launch(bank);
2289 }
2290
2291 COMMAND_HANDLER(stm32l4_handle_option_load_command)
2292 {
2293 if (CMD_ARGC != 1)
2294 return ERROR_COMMAND_SYNTAX_ERROR;
2295
2296 struct flash_bank *bank;
2297 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2298 if (retval != ERROR_OK)
2299 return retval;
2300
2301 retval = stm32l4_perform_obl_launch(bank);
2302 if (retval != ERROR_OK) {
2303 command_print(CMD, "stm32l4x option load failed");
2304 return retval;
2305 }
2306
2307
2308 command_print(CMD, "stm32l4x option load completed. Power-on reset might be required");
2309
2310 return ERROR_OK;
2311 }
2312
2313 COMMAND_HANDLER(stm32l4_handle_lock_command)
2314 {
2315 struct target *target = NULL;
2316
2317 if (CMD_ARGC < 1)
2318 return ERROR_COMMAND_SYNTAX_ERROR;
2319
2320 struct flash_bank *bank;
2321 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2322 if (retval != ERROR_OK)
2323 return retval;
2324
2325 if (stm32l4_is_otp(bank)) {
2326 LOG_ERROR("cannot lock/unlock OTP memory");
2327 return ERROR_FLASH_OPER_UNSUPPORTED;
2328 }
2329
2330 target = bank->target;
2331
2332 if (target->state != TARGET_HALTED) {
2333 LOG_ERROR("Target not halted");
2334 return ERROR_TARGET_NOT_HALTED;
2335 }
2336
2337 /* set readout protection level 1 by erasing the RDP option byte */
2338 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
2339 if (stm32l4_write_option(bank, stm32l4_info->flash_regs[STM32_FLASH_OPTR_INDEX],
2340 RDP_LEVEL_1, FLASH_RDP_MASK) != ERROR_OK) {
2341 command_print(CMD, "%s failed to lock device", bank->driver->name);
2342 return ERROR_OK;
2343 }
2344
2345 return ERROR_OK;
2346 }
2347
2348 COMMAND_HANDLER(stm32l4_handle_unlock_command)
2349 {
2350 struct target *target = NULL;
2351
2352 if (CMD_ARGC < 1)
2353 return ERROR_COMMAND_SYNTAX_ERROR;
2354
2355 struct flash_bank *bank;
2356 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2357 if (retval != ERROR_OK)
2358 return retval;
2359
2360 if (stm32l4_is_otp(bank)) {
2361 LOG_ERROR("cannot lock/unlock OTP memory");
2362 return ERROR_FLASH_OPER_UNSUPPORTED;
2363 }
2364
2365 target = bank->target;
2366
2367 if (target->state != TARGET_HALTED) {
2368 LOG_ERROR("Target not halted");
2369 return ERROR_TARGET_NOT_HALTED;
2370 }
2371
2372 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
2373 if (stm32l4_write_option(bank, stm32l4_info->flash_regs[STM32_FLASH_OPTR_INDEX],
2374 RDP_LEVEL_0, FLASH_RDP_MASK) != ERROR_OK) {
2375 command_print(CMD, "%s failed to unlock device", bank->driver->name);
2376 return ERROR_OK;
2377 }
2378
2379 return ERROR_OK;
2380 }
2381
2382 COMMAND_HANDLER(stm32l4_handle_wrp_info_command)
2383 {
2384 if (CMD_ARGC < 1 || CMD_ARGC > 2)
2385 return ERROR_COMMAND_SYNTAX_ERROR;
2386
2387 struct flash_bank *bank;
2388 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2389 if (retval != ERROR_OK)
2390 return retval;
2391
2392 if (stm32l4_is_otp(bank)) {
2393 LOG_ERROR("OTP memory does not have write protection areas");
2394 return ERROR_FLASH_OPER_UNSUPPORTED;
2395 }
2396
2397 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
2398 enum stm32_bank_id dev_bank_id = STM32_ALL_BANKS;
2399 if (CMD_ARGC == 2) {
2400 if (strcmp(CMD_ARGV[1], "bank1") == 0)
2401 dev_bank_id = STM32_BANK1;
2402 else if (strcmp(CMD_ARGV[1], "bank2") == 0)
2403 dev_bank_id = STM32_BANK2;
2404 else
2405 return ERROR_COMMAND_ARGUMENT_INVALID;
2406 }
2407
2408 if (dev_bank_id == STM32_BANK2) {
2409 if (!(stm32l4_info->part_info->flags & F_HAS_DUAL_BANK)) {
2410 LOG_ERROR("this device has no second bank");
2411 return ERROR_FAIL;
2412 } else if (!stm32l4_info->dual_bank_mode) {
2413 LOG_ERROR("this device is configured in single bank mode");
2414 return ERROR_FAIL;
2415 }
2416 }
2417
2418 int ret;
2419 unsigned int n_wrp, i;
2420 struct stm32l4_wrp wrpxy[4];
2421
2422 ret = stm32l4_get_all_wrpxy(bank, dev_bank_id, wrpxy, &n_wrp);
2423 if (ret != ERROR_OK)
2424 return ret;
2425
2426 /* use bitmap and range helpers to better describe protected areas */
2427 DECLARE_BITMAP(pages, bank->num_sectors);
2428 bitmap_zero(pages, bank->num_sectors);
2429
2430 for (i = 0; i < n_wrp; i++) {
2431 if (wrpxy[i].used) {
2432 for (int p = wrpxy[i].first; p <= wrpxy[i].last; p++)
2433 set_bit(p, pages);
2434 }
2435 }
2436
2437 /* we have at most 'n_wrp' WRP areas */
2438 struct range ranges[n_wrp];
2439 unsigned int ranges_count = 0;
2440
2441 bitmap_to_ranges(pages, bank->num_sectors, ranges, &ranges_count);
2442
2443 if (ranges_count > 0) {
2444 /* pretty-print the protected ranges */
2445 char *ranges_str = range_print_alloc(ranges, ranges_count);
2446 command_print(CMD, "protected areas: %s", ranges_str);
2447 free(ranges_str);
2448 } else
2449 command_print(CMD, "no protected areas");
2450
2451 return ERROR_OK;
2452 }
2453
2454 COMMAND_HANDLER(stm32l4_handle_otp_command)
2455 {
2456 if (CMD_ARGC < 2)
2457 return ERROR_COMMAND_SYNTAX_ERROR;
2458
2459 struct flash_bank *bank;
2460 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2461 if (retval != ERROR_OK)
2462 return retval;
2463
2464 if (!stm32l4_is_otp(bank)) {
2465 command_print(CMD, "the specified bank is not an OTP memory");
2466 return ERROR_FAIL;
2467 }
2468 if (strcmp(CMD_ARGV[1], "enable") == 0)
2469 stm32l4_otp_enable(bank, true);
2470 else if (strcmp(CMD_ARGV[1], "disable") == 0)
2471 stm32l4_otp_enable(bank, false);
2472 else if (strcmp(CMD_ARGV[1], "show") == 0)
2473 command_print(CMD, "OTP memory bank #%d is %s for write commands.",
2474 bank->bank_number, stm32l4_otp_is_enabled(bank) ? "enabled" : "disabled");
2475 else
2476 return ERROR_COMMAND_SYNTAX_ERROR;
2477
2478 return ERROR_OK;
2479 }
2480
2481 static const struct command_registration stm32l4_exec_command_handlers[] = {
2482 {
2483 .name = "lock",
2484 .handler = stm32l4_handle_lock_command,
2485 .mode = COMMAND_EXEC,
2486 .usage = "bank_id",
2487 .help = "Lock entire flash device.",
2488 },
2489 {
2490 .name = "unlock",
2491 .handler = stm32l4_handle_unlock_command,
2492 .mode = COMMAND_EXEC,
2493 .usage = "bank_id",
2494 .help = "Unlock entire protected flash device.",
2495 },
2496 {
2497 .name = "mass_erase",
2498 .handler = stm32l4_handle_mass_erase_command,
2499 .mode = COMMAND_EXEC,
2500 .usage = "bank_id",
2501 .help = "Erase entire flash device.",
2502 },
2503 {
2504 .name = "option_read",
2505 .handler = stm32l4_handle_option_read_command,
2506 .mode = COMMAND_EXEC,
2507 .usage = "bank_id reg_offset",
2508 .help = "Read & Display device option bytes.",
2509 },
2510 {
2511 .name = "option_write",
2512 .handler = stm32l4_handle_option_write_command,
2513 .mode = COMMAND_EXEC,
2514 .usage = "bank_id reg_offset value mask",
2515 .help = "Write device option bit fields with provided value.",
2516 },
2517 {
2518 .name = "trustzone",
2519 .handler = stm32l4_handle_trustzone_command,
2520 .mode = COMMAND_EXEC,
2521 .usage = "<bank_id> [enable|disable]",
2522 .help = "Configure TrustZone security",
2523 },
2524 {
2525 .name = "wrp_info",
2526 .handler = stm32l4_handle_wrp_info_command,
2527 .mode = COMMAND_EXEC,
2528 .usage = "bank_id [bank1|bank2]",
2529 .help = "list the protected areas using WRP",
2530 },
2531 {
2532 .name = "option_load",
2533 .handler = stm32l4_handle_option_load_command,
2534 .mode = COMMAND_EXEC,
2535 .usage = "bank_id",
2536 .help = "Force re-load of device options (will cause device reset).",
2537 },
2538 {
2539 .name = "otp",
2540 .handler = stm32l4_handle_otp_command,
2541 .mode = COMMAND_EXEC,
2542 .usage = "<bank_id> <enable|disable|show>",
2543 .help = "OTP (One Time Programmable) memory write enable/disable",
2544 },
2545 COMMAND_REGISTRATION_DONE
2546 };
2547
2548 static const struct command_registration stm32l4_command_handlers[] = {
2549 {
2550 .name = "stm32l4x",
2551 .mode = COMMAND_ANY,
2552 .help = "stm32l4x flash command group",
2553 .usage = "",
2554 .chain = stm32l4_exec_command_handlers,
2555 },
2556 COMMAND_REGISTRATION_DONE
2557 };
2558
2559 const struct flash_driver stm32l4x_flash = {
2560 .name = "stm32l4x",
2561 .commands = stm32l4_command_handlers,
2562 .flash_bank_command = stm32l4_flash_bank_command,
2563 .erase = stm32l4_erase,
2564 .protect = stm32l4_protect,
2565 .write = stm32l4_write,
2566 .read = default_flash_read,
2567 .probe = stm32l4_probe,
2568 .auto_probe = stm32l4_auto_probe,
2569 .erase_check = default_flash_blank_check,
2570 .protect_check = stm32l4_protect_check,
2571 .info = get_stm32l4_info,
2572 .free_driver_priv = default_flash_free_driver_priv,
2573 };
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