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flash/nor/stm32l4x: Fix check for number of arguments
[openocd.git] / src / flash / nor / stm32l4x.c
1 /***************************************************************************
2 * Copyright (C) 2015 by Uwe Bonnes *
3 * bon@elektron.ikp.physik.tu-darmstadt.de *
4 * *
5 * Copyright (C) 2019 by Tarek Bochkati for STMicroelectronics *
6 * tarek.bouchkati@gmail.com *
7 * *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
12 * *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
17 * *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
20 ***************************************************************************/
21
22 #ifdef HAVE_CONFIG_H
23 #include "config.h"
24 #endif
25
26 #include "imp.h"
27 #include <helper/binarybuffer.h>
28 #include <target/algorithm.h>
29 #include <target/armv7m.h>
30 #include "bits.h"
31 #include "stm32l4x.h"
32
33 /* STM32L4xxx series for reference.
34 *
35 * RM0351 (STM32L4x5/STM32L4x6)
36 * http://www.st.com/resource/en/reference_manual/dm00083560.pdf
37 *
38 * RM0394 (STM32L43x/44x/45x/46x)
39 * http://www.st.com/resource/en/reference_manual/dm00151940.pdf
40 *
41 * RM0432 (STM32L4R/4Sxx)
42 * http://www.st.com/resource/en/reference_manual/dm00310109.pdf
43 *
44 * STM32L476RG Datasheet (for erase timing)
45 * http://www.st.com/resource/en/datasheet/stm32l476rg.pdf
46 *
47 * The RM0351 devices have normally two banks, but on 512 and 256 kiB devices
48 * an option byte is available to map all sectors to the first bank.
49 * Both STM32 banks are treated as one OpenOCD bank, as other STM32 devices
50 * handlers do!
51 *
52 * RM0394 devices have a single bank only.
53 *
54 * RM0432 devices have single and dual bank operating modes.
55 * - for STM32L4R/Sxx the FLASH size is 2Mbyte or 1Mbyte.
56 * - for STM32L4P/Q5x the FLASH size is 1Mbyte or 512Kbyte.
57 * Bank page (sector) size is 4Kbyte (dual mode) or 8Kbyte (single mode).
58 *
59 * Bank mode is controlled by two different bits in option bytes register.
60 * - for STM32L4R/Sxx
61 * In 2M FLASH devices bit 22 (DBANK) controls Dual Bank mode.
62 * In 1M FLASH devices bit 21 (DB1M) controls Dual Bank mode.
63 * - for STM32L4P5/Q5x
64 * In 1M FLASH devices bit 22 (DBANK) controls Dual Bank mode.
65 * In 512K FLASH devices bit 21 (DB512K) controls Dual Bank mode.
66 *
67 */
68
69 /* STM32WBxxx series for reference.
70 *
71 * RM0434 (STM32WB55)
72 * http://www.st.com/resource/en/reference_manual/dm00318631.pdf
73 *
74 * RM0471 (STM32WB50)
75 * http://www.st.com/resource/en/reference_manual/dm00622834.pdf
76 */
77
78 /* STM32WLxxx series for reference.
79 *
80 * RM0461 (STM32WLEx)
81 * http://www.st.com/resource/en/reference_manual/dm00530369.pdf
82 */
83
84 /*
85 * STM32G0xxx series for reference.
86 *
87 * RM0444 (STM32G0x1)
88 * http://www.st.com/resource/en/reference_manual/dm00371828.pdf
89 *
90 * RM0454 (STM32G0x0)
91 * http://www.st.com/resource/en/reference_manual/dm00463896.pdf
92 */
93
94 /*
95 * STM32G4xxx series for reference.
96 *
97 * RM0440 (STM32G43x/44x/47x/48x)
98 * http://www.st.com/resource/en/reference_manual/dm00355726.pdf
99 *
100 * Cat. 2 devices have single bank only, page size is 2kByte.
101 *
102 * Cat. 3 devices have single and dual bank operating modes,
103 * Page size is 2kByte (dual mode) or 4kByte (single mode).
104 *
105 * Bank mode is controlled by bit 22 (DBANK) in option bytes register.
106 * Both banks are treated as a single OpenOCD bank.
107 */
108
109 /* Erase time can be as high as 25ms, 10x this and assume it's toast... */
110
111 #define FLASH_ERASE_TIMEOUT 250
112
113 struct stm32l4_rev {
114 const uint16_t rev;
115 const char *str;
116 };
117
118 struct stm32l4_part_info {
119 uint16_t id;
120 const char *device_str;
121 const struct stm32l4_rev *revs;
122 const size_t num_revs;
123 const uint16_t max_flash_size_kb;
124 const bool has_dual_bank;
125 const uint32_t flash_regs_base;
126 const uint32_t fsize_addr;
127 };
128
129 struct stm32l4_flash_bank {
130 bool probed;
131 uint32_t idcode;
132 int bank1_sectors;
133 bool dual_bank_mode;
134 int hole_sectors;
135 uint32_t user_bank_size;
136 uint32_t wrpxxr_mask;
137 const struct stm32l4_part_info *part_info;
138 };
139
140 /* human readable list of families this drivers supports */
141 static const char *device_families = "STM32L4/L4+/WB/WL/G4/G0";
142
143 static const struct stm32l4_rev stm32_415_revs[] = {
144 { 0x1000, "1" }, { 0x1001, "2" }, { 0x1003, "3" }, { 0x1007, "4" }
145 };
146
147 static const struct stm32l4_rev stm32_435_revs[] = {
148 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
149 };
150
151 static const struct stm32l4_rev stm32_460_revs[] = {
152 { 0x1000, "A/Z" } /* A and Z, no typo in RM! */, { 0x2000, "B" },
153 };
154
155 static const struct stm32l4_rev stm32_461_revs[] = {
156 { 0x1000, "A" }, { 0x2000, "B" },
157 };
158
159 static const struct stm32l4_rev stm32_462_revs[] = {
160 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
161 };
162
163 static const struct stm32l4_rev stm32_464_revs[] = {
164 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
165 };
166
167 static const struct stm32l4_rev stm32_466_revs[] = {
168 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2000, "B" },
169 };
170
171 static const struct stm32l4_rev stm32_468_revs[] = {
172 { 0x1000, "A" }, { 0x2000, "B" }, { 0x2001, "Z" },
173 };
174
175 static const struct stm32l4_rev stm32_469_revs[] = {
176 { 0x1000, "A" }, { 0x2000, "B" }, { 0x2001, "Z" },
177 };
178
179 static const struct stm32l4_rev stm32_470_revs[] = {
180 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x1003, "Y" }, { 0x100F, "W" },
181 };
182
183 static const struct stm32l4_rev stm32_471_revs[] = {
184 { 0x1001, "Z" },
185 };
186
187 static const struct stm32l4_rev stm32_495_revs[] = {
188 { 0x2001, "2.1" },
189 };
190
191 static const struct stm32l4_rev stm32_496_revs[] = {
192 { 0x1000, "A" },
193 };
194
195 static const struct stm32l4_rev stm32_497_revs[] = {
196 { 0x1000, "1.0" },
197 };
198
199 static const struct stm32l4_part_info stm32l4_parts[] = {
200 {
201 .id = 0x415,
202 .revs = stm32_415_revs,
203 .num_revs = ARRAY_SIZE(stm32_415_revs),
204 .device_str = "STM32L47/L48xx",
205 .max_flash_size_kb = 1024,
206 .has_dual_bank = true,
207 .flash_regs_base = 0x40022000,
208 .fsize_addr = 0x1FFF75E0,
209 },
210 {
211 .id = 0x435,
212 .revs = stm32_435_revs,
213 .num_revs = ARRAY_SIZE(stm32_435_revs),
214 .device_str = "STM32L43/L44xx",
215 .max_flash_size_kb = 256,
216 .has_dual_bank = false,
217 .flash_regs_base = 0x40022000,
218 .fsize_addr = 0x1FFF75E0,
219 },
220 {
221 .id = 0x460,
222 .revs = stm32_460_revs,
223 .num_revs = ARRAY_SIZE(stm32_460_revs),
224 .device_str = "STM32G07/G08xx",
225 .max_flash_size_kb = 128,
226 .has_dual_bank = false,
227 .flash_regs_base = 0x40022000,
228 .fsize_addr = 0x1FFF75E0,
229 },
230 {
231 .id = 0x461,
232 .revs = stm32_461_revs,
233 .num_revs = ARRAY_SIZE(stm32_461_revs),
234 .device_str = "STM32L49/L4Axx",
235 .max_flash_size_kb = 1024,
236 .has_dual_bank = true,
237 .flash_regs_base = 0x40022000,
238 .fsize_addr = 0x1FFF75E0,
239 },
240 {
241 .id = 0x462,
242 .revs = stm32_462_revs,
243 .num_revs = ARRAY_SIZE(stm32_462_revs),
244 .device_str = "STM32L45/L46xx",
245 .max_flash_size_kb = 512,
246 .has_dual_bank = false,
247 .flash_regs_base = 0x40022000,
248 .fsize_addr = 0x1FFF75E0,
249 },
250 {
251 .id = 0x464,
252 .revs = stm32_464_revs,
253 .num_revs = ARRAY_SIZE(stm32_464_revs),
254 .device_str = "STM32L41/L42xx",
255 .max_flash_size_kb = 128,
256 .has_dual_bank = false,
257 .flash_regs_base = 0x40022000,
258 .fsize_addr = 0x1FFF75E0,
259 },
260 {
261 .id = 0x466,
262 .revs = stm32_466_revs,
263 .num_revs = ARRAY_SIZE(stm32_466_revs),
264 .device_str = "STM32G03/G04xx",
265 .max_flash_size_kb = 64,
266 .has_dual_bank = false,
267 .flash_regs_base = 0x40022000,
268 .fsize_addr = 0x1FFF75E0,
269 },
270 {
271 .id = 0x468,
272 .revs = stm32_468_revs,
273 .num_revs = ARRAY_SIZE(stm32_468_revs),
274 .device_str = "STM32G43/G44xx",
275 .max_flash_size_kb = 128,
276 .has_dual_bank = false,
277 .flash_regs_base = 0x40022000,
278 .fsize_addr = 0x1FFF75E0,
279 },
280 {
281 .id = 0x469,
282 .revs = stm32_469_revs,
283 .num_revs = ARRAY_SIZE(stm32_469_revs),
284 .device_str = "STM32G47/G48xx",
285 .max_flash_size_kb = 512,
286 .has_dual_bank = true,
287 .flash_regs_base = 0x40022000,
288 .fsize_addr = 0x1FFF75E0,
289 },
290 {
291 .id = 0x470,
292 .revs = stm32_470_revs,
293 .num_revs = ARRAY_SIZE(stm32_470_revs),
294 .device_str = "STM32L4R/L4Sxx",
295 .max_flash_size_kb = 2048,
296 .has_dual_bank = true,
297 .flash_regs_base = 0x40022000,
298 .fsize_addr = 0x1FFF75E0,
299 },
300 {
301 .id = 0x471,
302 .revs = stm32_471_revs,
303 .num_revs = ARRAY_SIZE(stm32_471_revs),
304 .device_str = "STM32L4P5/L4Q5x",
305 .max_flash_size_kb = 1024,
306 .has_dual_bank = true,
307 .flash_regs_base = 0x40022000,
308 .fsize_addr = 0x1FFF75E0,
309 },
310 {
311 .id = 0x495,
312 .revs = stm32_495_revs,
313 .num_revs = ARRAY_SIZE(stm32_495_revs),
314 .device_str = "STM32WB5x",
315 .max_flash_size_kb = 1024,
316 .has_dual_bank = false,
317 .flash_regs_base = 0x58004000,
318 .fsize_addr = 0x1FFF75E0,
319 },
320 {
321 .id = 0x496,
322 .revs = stm32_496_revs,
323 .num_revs = ARRAY_SIZE(stm32_496_revs),
324 .device_str = "STM32WB3x",
325 .max_flash_size_kb = 512,
326 .has_dual_bank = false,
327 .flash_regs_base = 0x58004000,
328 .fsize_addr = 0x1FFF75E0,
329 },
330 {
331 .id = 0x497,
332 .revs = stm32_497_revs,
333 .num_revs = ARRAY_SIZE(stm32_497_revs),
334 .device_str = "STM32WLEx",
335 .max_flash_size_kb = 256,
336 .has_dual_bank = false,
337 .flash_regs_base = 0x58004000,
338 .fsize_addr = 0x1FFF75E0,
339 },
340 };
341
342 /* flash bank stm32l4x <base> <size> 0 0 <target#> */
343 FLASH_BANK_COMMAND_HANDLER(stm32l4_flash_bank_command)
344 {
345 struct stm32l4_flash_bank *stm32l4_info;
346
347 if (CMD_ARGC < 6)
348 return ERROR_COMMAND_SYNTAX_ERROR;
349
350 stm32l4_info = malloc(sizeof(struct stm32l4_flash_bank));
351 if (!stm32l4_info)
352 return ERROR_FAIL; /* Checkme: What better error to use?*/
353 bank->driver_priv = stm32l4_info;
354
355 /* The flash write must be aligned to a double word (8-bytes) boundary.
356 * Ask the flash infrastructure to ensure required alignment */
357 bank->write_start_alignment = bank->write_end_alignment = 8;
358
359 stm32l4_info->probed = false;
360 stm32l4_info->user_bank_size = bank->size;
361
362 return ERROR_OK;
363 }
364
365 static inline uint32_t stm32l4_get_flash_reg(struct flash_bank *bank, uint32_t reg_offset)
366 {
367 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
368 return stm32l4_info->part_info->flash_regs_base + reg_offset;
369 }
370
371 static inline int stm32l4_read_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t *value)
372 {
373 return target_read_u32(bank->target, stm32l4_get_flash_reg(bank, reg_offset), value);
374 }
375
376 static inline int stm32l4_write_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t value)
377 {
378 return target_write_u32(bank->target, stm32l4_get_flash_reg(bank, reg_offset), value);
379 }
380
381 static int stm32l4_wait_status_busy(struct flash_bank *bank, int timeout)
382 {
383 uint32_t status;
384 int retval = ERROR_OK;
385
386 /* wait for busy to clear */
387 for (;;) {
388 retval = stm32l4_read_flash_reg(bank, STM32_FLASH_SR, &status);
389 if (retval != ERROR_OK)
390 return retval;
391 LOG_DEBUG("status: 0x%" PRIx32 "", status);
392 if ((status & FLASH_BSY) == 0)
393 break;
394 if (timeout-- <= 0) {
395 LOG_ERROR("timed out waiting for flash");
396 return ERROR_FAIL;
397 }
398 alive_sleep(1);
399 }
400
401
402 if (status & FLASH_WRPERR) {
403 LOG_ERROR("stm32x device protected");
404 retval = ERROR_FAIL;
405 }
406
407 /* Clear but report errors */
408 if (status & FLASH_ERROR) {
409 if (retval == ERROR_OK)
410 retval = ERROR_FAIL;
411 /* If this operation fails, we ignore it and report the original
412 * retval
413 */
414 stm32l4_write_flash_reg(bank, STM32_FLASH_SR, status & FLASH_ERROR);
415 }
416
417 return retval;
418 }
419
420 static int stm32l4_unlock_reg(struct flash_bank *bank)
421 {
422 uint32_t ctrl;
423
424 /* first check if not already unlocked
425 * otherwise writing on STM32_FLASH_KEYR will fail
426 */
427 int retval = stm32l4_read_flash_reg(bank, STM32_FLASH_CR, &ctrl);
428 if (retval != ERROR_OK)
429 return retval;
430
431 if ((ctrl & FLASH_LOCK) == 0)
432 return ERROR_OK;
433
434 /* unlock flash registers */
435 retval = stm32l4_write_flash_reg(bank, STM32_FLASH_KEYR, KEY1);
436 if (retval != ERROR_OK)
437 return retval;
438
439 retval = stm32l4_write_flash_reg(bank, STM32_FLASH_KEYR, KEY2);
440 if (retval != ERROR_OK)
441 return retval;
442
443 retval = stm32l4_read_flash_reg(bank, STM32_FLASH_CR, &ctrl);
444 if (retval != ERROR_OK)
445 return retval;
446
447 if (ctrl & FLASH_LOCK) {
448 LOG_ERROR("flash not unlocked STM32_FLASH_CR: %" PRIx32, ctrl);
449 return ERROR_TARGET_FAILURE;
450 }
451
452 return ERROR_OK;
453 }
454
455 static int stm32l4_unlock_option_reg(struct flash_bank *bank)
456 {
457 uint32_t ctrl;
458
459 int retval = stm32l4_read_flash_reg(bank, STM32_FLASH_CR, &ctrl);
460 if (retval != ERROR_OK)
461 return retval;
462
463 if ((ctrl & FLASH_OPTLOCK) == 0)
464 return ERROR_OK;
465
466 /* unlock option registers */
467 retval = stm32l4_write_flash_reg(bank, STM32_FLASH_OPTKEYR, OPTKEY1);
468 if (retval != ERROR_OK)
469 return retval;
470
471 retval = stm32l4_write_flash_reg(bank, STM32_FLASH_OPTKEYR, OPTKEY2);
472 if (retval != ERROR_OK)
473 return retval;
474
475 retval = stm32l4_read_flash_reg(bank, STM32_FLASH_CR, &ctrl);
476 if (retval != ERROR_OK)
477 return retval;
478
479 if (ctrl & FLASH_OPTLOCK) {
480 LOG_ERROR("options not unlocked STM32_FLASH_CR: %" PRIx32, ctrl);
481 return ERROR_TARGET_FAILURE;
482 }
483
484 return ERROR_OK;
485 }
486
487 static int stm32l4_write_option(struct flash_bank *bank, uint32_t reg_offset,
488 uint32_t value, uint32_t mask)
489 {
490 uint32_t optiondata;
491 int retval, retval2;
492
493 retval = stm32l4_read_flash_reg(bank, reg_offset, &optiondata);
494 if (retval != ERROR_OK)
495 return retval;
496
497 retval = stm32l4_unlock_reg(bank);
498 if (retval != ERROR_OK)
499 goto err_lock;
500
501 retval = stm32l4_unlock_option_reg(bank);
502 if (retval != ERROR_OK)
503 goto err_lock;
504
505 optiondata = (optiondata & ~mask) | (value & mask);
506
507 retval = stm32l4_write_flash_reg(bank, reg_offset, optiondata);
508 if (retval != ERROR_OK)
509 goto err_lock;
510
511 retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, FLASH_OPTSTRT);
512 if (retval != ERROR_OK)
513 goto err_lock;
514
515 retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
516
517 err_lock:
518 retval2 = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, FLASH_LOCK | FLASH_OPTLOCK);
519
520 if (retval != ERROR_OK)
521 return retval;
522
523 return retval2;
524 }
525
526 static int stm32l4_protect_check(struct flash_bank *bank)
527 {
528 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
529
530 uint32_t wrp1ar, wrp1br, wrp2ar, wrp2br;
531 stm32l4_read_flash_reg(bank, STM32_FLASH_WRP1AR, &wrp1ar);
532 stm32l4_read_flash_reg(bank, STM32_FLASH_WRP1BR, &wrp1br);
533 if (stm32l4_info->part_info->has_dual_bank) {
534 stm32l4_read_flash_reg(bank, STM32_FLASH_WRP2AR, &wrp2ar);
535 stm32l4_read_flash_reg(bank, STM32_FLASH_WRP2BR, &wrp2br);
536 } else {
537 /* prevent unintialized errors */
538 wrp2ar = 0;
539 wrp2br = 0;
540 }
541
542 const uint8_t wrp1a_start = wrp1ar & stm32l4_info->wrpxxr_mask;
543 const uint8_t wrp1a_end = (wrp1ar >> 16) & stm32l4_info->wrpxxr_mask;
544 const uint8_t wrp1b_start = wrp1br & stm32l4_info->wrpxxr_mask;
545 const uint8_t wrp1b_end = (wrp1br >> 16) & stm32l4_info->wrpxxr_mask;
546 const uint8_t wrp2a_start = wrp2ar & stm32l4_info->wrpxxr_mask;
547 const uint8_t wrp2a_end = (wrp2ar >> 16) & stm32l4_info->wrpxxr_mask;
548 const uint8_t wrp2b_start = wrp2br & stm32l4_info->wrpxxr_mask;
549 const uint8_t wrp2b_end = (wrp2br >> 16) & stm32l4_info->wrpxxr_mask;
550
551 for (int i = 0; i < bank->num_sectors; i++) {
552 if (i < stm32l4_info->bank1_sectors) {
553 if (((i >= wrp1a_start) &&
554 (i <= wrp1a_end)) ||
555 ((i >= wrp1b_start) &&
556 (i <= wrp1b_end)))
557 bank->sectors[i].is_protected = 1;
558 else
559 bank->sectors[i].is_protected = 0;
560 } else {
561 assert(stm32l4_info->part_info->has_dual_bank == true);
562 uint8_t snb;
563 snb = i - stm32l4_info->bank1_sectors;
564 if (((snb >= wrp2a_start) &&
565 (snb <= wrp2a_end)) ||
566 ((snb >= wrp2b_start) &&
567 (snb <= wrp2b_end)))
568 bank->sectors[i].is_protected = 1;
569 else
570 bank->sectors[i].is_protected = 0;
571 }
572 }
573 return ERROR_OK;
574 }
575
576 static int stm32l4_erase(struct flash_bank *bank, int first, int last)
577 {
578 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
579 int i;
580 int retval, retval2;
581
582 assert((0 <= first) && (first <= last) && (last < bank->num_sectors));
583
584 if (bank->target->state != TARGET_HALTED) {
585 LOG_ERROR("Target not halted");
586 return ERROR_TARGET_NOT_HALTED;
587 }
588
589 retval = stm32l4_unlock_reg(bank);
590 if (retval != ERROR_OK)
591 goto err_lock;
592
593 /*
594 Sector Erase
595 To erase a sector, follow the procedure below:
596 1. Check that no Flash memory operation is ongoing by
597 checking the BSY bit in the FLASH_SR register
598 2. Set the PER bit and select the page and bank
599 you wish to erase in the FLASH_CR register
600 3. Set the STRT bit in the FLASH_CR register
601 4. Wait for the BSY bit to be cleared
602 */
603
604 for (i = first; i <= last; i++) {
605 uint32_t erase_flags;
606 erase_flags = FLASH_PER | FLASH_STRT;
607
608 if (i >= stm32l4_info->bank1_sectors) {
609 uint8_t snb;
610 snb = i - stm32l4_info->bank1_sectors;
611 erase_flags |= snb << FLASH_PAGE_SHIFT | FLASH_CR_BKER;
612 } else
613 erase_flags |= i << FLASH_PAGE_SHIFT;
614 retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, erase_flags);
615 if (retval != ERROR_OK)
616 break;
617
618 retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
619 if (retval != ERROR_OK)
620 break;
621
622 bank->sectors[i].is_erased = 1;
623 }
624
625 err_lock:
626 retval2 = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, FLASH_LOCK);
627
628 if (retval != ERROR_OK)
629 return retval;
630
631 return retval2;
632 }
633
634 static int stm32l4_protect(struct flash_bank *bank, int set, int first, int last)
635 {
636 struct target *target = bank->target;
637 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
638
639 if (target->state != TARGET_HALTED) {
640 LOG_ERROR("Target not halted");
641 return ERROR_TARGET_NOT_HALTED;
642 }
643
644 int ret = ERROR_OK;
645 /* Bank 2 */
646 uint32_t reg_value = 0xFF; /* Default to bank un-protected */
647 if (last >= stm32l4_info->bank1_sectors) {
648 if (set == 1) {
649 uint8_t begin = first > stm32l4_info->bank1_sectors ? first : 0x00;
650 reg_value = ((last & 0xFF) << 16) | begin;
651 }
652
653 ret = stm32l4_write_option(bank, STM32_FLASH_WRP2AR, reg_value, 0xffffffff);
654 }
655 /* Bank 1 */
656 reg_value = 0xFF; /* Default to bank un-protected */
657 if (first < stm32l4_info->bank1_sectors) {
658 if (set == 1) {
659 uint8_t end = last >= stm32l4_info->bank1_sectors ? 0xFF : last;
660 reg_value = (end << 16) | (first & 0xFF);
661 }
662
663 ret = stm32l4_write_option(bank, STM32_FLASH_WRP1AR, reg_value, 0xffffffff);
664 }
665
666 return ret;
667 }
668
669 /* Count is in double-words */
670 static int stm32l4_write_block(struct flash_bank *bank, const uint8_t *buffer,
671 uint32_t offset, uint32_t count)
672 {
673 struct target *target = bank->target;
674 uint32_t buffer_size;
675 struct working_area *write_algorithm;
676 struct working_area *source;
677 uint32_t address = bank->base + offset;
678 struct reg_param reg_params[6];
679 struct armv7m_algorithm armv7m_info;
680 int retval = ERROR_OK;
681
682 static const uint8_t stm32l4_flash_write_code[] = {
683 #include "../../../contrib/loaders/flash/stm32/stm32l4x.inc"
684 };
685
686 if (target_alloc_working_area(target, sizeof(stm32l4_flash_write_code),
687 &write_algorithm) != ERROR_OK) {
688 LOG_WARNING("no working area available, can't do block memory writes");
689 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
690 }
691
692 retval = target_write_buffer(target, write_algorithm->address,
693 sizeof(stm32l4_flash_write_code),
694 stm32l4_flash_write_code);
695 if (retval != ERROR_OK) {
696 target_free_working_area(target, write_algorithm);
697 return retval;
698 }
699
700 /* memory buffer, size *must* be multiple of dword plus one dword for rp and one for wp */
701 buffer_size = target_get_working_area_avail(target) & ~(2 * sizeof(uint32_t) - 1);
702 if (buffer_size < 256) {
703 LOG_WARNING("large enough working area not available, can't do block memory writes");
704 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
705 } else if (buffer_size > 16384) {
706 /* probably won't benefit from more than 16k ... */
707 buffer_size = 16384;
708 }
709
710 if (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
711 LOG_ERROR("allocating working area failed");
712 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
713 }
714
715 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
716 armv7m_info.core_mode = ARM_MODE_THREAD;
717
718 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* buffer start, status (out) */
719 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* buffer end */
720 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT); /* target address */
721 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT); /* count (double word-64bit) */
722 init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT); /* flash status register */
723 init_reg_param(&reg_params[5], "r5", 32, PARAM_OUT); /* flash control register */
724
725 buf_set_u32(reg_params[0].value, 0, 32, source->address);
726 buf_set_u32(reg_params[1].value, 0, 32, source->address + source->size);
727 buf_set_u32(reg_params[2].value, 0, 32, address);
728 buf_set_u32(reg_params[3].value, 0, 32, count);
729 buf_set_u32(reg_params[4].value, 0, 32, stm32l4_get_flash_reg(bank, STM32_FLASH_SR));
730 buf_set_u32(reg_params[5].value, 0, 32, stm32l4_get_flash_reg(bank, STM32_FLASH_CR));
731
732 retval = target_run_flash_async_algorithm(target, buffer, count, 8,
733 0, NULL,
734 ARRAY_SIZE(reg_params), reg_params,
735 source->address, source->size,
736 write_algorithm->address, 0,
737 &armv7m_info);
738
739 if (retval == ERROR_FLASH_OPERATION_FAILED) {
740 LOG_ERROR("error executing stm32l4 flash write algorithm");
741
742 uint32_t error = buf_get_u32(reg_params[0].value, 0, 32) & FLASH_ERROR;
743
744 if (error & FLASH_WRPERR)
745 LOG_ERROR("flash memory write protected");
746
747 if (error != 0) {
748 LOG_ERROR("flash write failed = %08" PRIx32, error);
749 /* Clear but report errors */
750 stm32l4_write_flash_reg(bank, STM32_FLASH_SR, error);
751 retval = ERROR_FAIL;
752 }
753 }
754
755 target_free_working_area(target, source);
756 target_free_working_area(target, write_algorithm);
757
758 destroy_reg_param(&reg_params[0]);
759 destroy_reg_param(&reg_params[1]);
760 destroy_reg_param(&reg_params[2]);
761 destroy_reg_param(&reg_params[3]);
762 destroy_reg_param(&reg_params[4]);
763 destroy_reg_param(&reg_params[5]);
764
765 return retval;
766 }
767
768 static int stm32l4_write(struct flash_bank *bank, const uint8_t *buffer,
769 uint32_t offset, uint32_t count)
770 {
771 int retval = ERROR_OK, retval2;
772
773 if (bank->target->state != TARGET_HALTED) {
774 LOG_ERROR("Target not halted");
775 return ERROR_TARGET_NOT_HALTED;
776 }
777
778 /* The flash write must be aligned to a double word (8-bytes) boundary.
779 * The flash infrastructure ensures it, do just a security check */
780 assert(offset % 8 == 0);
781 assert(count % 8 == 0);
782
783 /* STM32G4xxx Cat. 3 devices may have gaps between banks, check whether
784 * data to be written does not go into a gap:
785 * suppose buffer is fully contained in bank from sector 0 to sector
786 * num->sectors - 1 and sectors are ordered according to offset
787 */
788 struct flash_sector *head = &bank->sectors[0];
789 struct flash_sector *tail = &bank->sectors[bank->num_sectors - 1];
790
791 while ((head < tail) && (offset >= (head + 1)->offset)) {
792 /* buffer does not intersect head nor gap behind head */
793 head++;
794 }
795
796 while ((head < tail) && (offset + count <= (tail - 1)->offset + (tail - 1)->size)) {
797 /* buffer does not intersect tail nor gap before tail */
798 --tail;
799 }
800
801 LOG_DEBUG("data: 0x%08" PRIx32 " - 0x%08" PRIx32 ", sectors: 0x%08" PRIx32 " - 0x%08" PRIx32,
802 offset, offset + count - 1, head->offset, tail->offset + tail->size - 1);
803
804 /* Now check that there is no gap from head to tail, this should work
805 * even for multiple or non-symmetric gaps
806 */
807 while (head < tail) {
808 if (head->offset + head->size != (head + 1)->offset) {
809 LOG_ERROR("write into gap from " TARGET_ADDR_FMT " to " TARGET_ADDR_FMT,
810 bank->base + head->offset + head->size,
811 bank->base + (head + 1)->offset - 1);
812 retval = ERROR_FLASH_DST_OUT_OF_BANK;
813 }
814 head++;
815 }
816
817 if (retval != ERROR_OK)
818 return retval;
819
820 retval = stm32l4_unlock_reg(bank);
821 if (retval != ERROR_OK)
822 goto err_lock;
823
824 retval = stm32l4_write_block(bank, buffer, offset, count / 8);
825
826 err_lock:
827 retval2 = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, FLASH_LOCK);
828
829 if (retval != ERROR_OK) {
830 LOG_ERROR("block write failed");
831 return retval;
832 }
833 return retval2;
834 }
835
836 static int stm32l4_read_idcode(struct flash_bank *bank, uint32_t *id)
837 {
838 int retval;
839
840 /* try stm32l4/l4+/wb/g4 id register first, then stm32g0 id register */
841 retval = target_read_u32(bank->target, DBGMCU_IDCODE_L4_G4, id);
842 if ((retval != ERROR_OK) || ((*id & 0xfff) == 0) || ((*id & 0xfff) == 0xfff)) {
843 retval = target_read_u32(bank->target, DBGMCU_IDCODE_G0, id);
844 if ((retval != ERROR_OK) || ((*id & 0xfff) == 0) || ((*id & 0xfff) == 0xfff)) {
845 LOG_ERROR("can't get device id");
846 return (retval == ERROR_OK) ? ERROR_FAIL : retval;
847 }
848 }
849
850 return retval;
851 }
852
853 static int stm32l4_probe(struct flash_bank *bank)
854 {
855 struct target *target = bank->target;
856 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
857 const struct stm32l4_part_info *part_info;
858 uint16_t flash_size_kb = 0xffff;
859 uint32_t device_id;
860 uint32_t options;
861
862 stm32l4_info->probed = false;
863
864 /* read stm32 device id registers */
865 int retval = stm32l4_read_idcode(bank, &stm32l4_info->idcode);
866 if (retval != ERROR_OK)
867 return retval;
868
869 device_id = stm32l4_info->idcode & 0xFFF;
870
871 for (unsigned int n = 0; n < ARRAY_SIZE(stm32l4_parts); n++) {
872 if (device_id == stm32l4_parts[n].id)
873 stm32l4_info->part_info = &stm32l4_parts[n];
874 }
875
876 if (!stm32l4_info->part_info) {
877 LOG_WARNING("Cannot identify target as an %s family device.", device_families);
878 return ERROR_FAIL;
879 }
880
881 part_info = stm32l4_info->part_info;
882
883 char device_info[1024];
884 retval = bank->driver->info(bank, device_info, sizeof(device_info));
885 if (retval != ERROR_OK)
886 return retval;
887
888 LOG_INFO("device idcode = 0x%08" PRIx32 " (%s)", stm32l4_info->idcode, device_info);
889
890 /* get flash size from target. */
891 retval = target_read_u16(target, part_info->fsize_addr, &flash_size_kb);
892
893 /* failed reading flash size or flash size invalid (early silicon),
894 * default to max target family */
895 if (retval != ERROR_OK || flash_size_kb == 0xffff || flash_size_kb == 0
896 || flash_size_kb > part_info->max_flash_size_kb) {
897 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
898 part_info->max_flash_size_kb);
899 flash_size_kb = part_info->max_flash_size_kb;
900 }
901
902 /* if the user sets the size manually then ignore the probed value
903 * this allows us to work around devices that have a invalid flash size register value */
904 if (stm32l4_info->user_bank_size) {
905 LOG_WARNING("overriding size register by configured bank size - MAY CAUSE TROUBLE");
906 flash_size_kb = stm32l4_info->user_bank_size / 1024;
907 }
908
909 LOG_INFO("flash size = %dkbytes", flash_size_kb);
910
911 /* did we assign a flash size? */
912 assert((flash_size_kb != 0xffff) && flash_size_kb);
913
914 /* read flash option register */
915 retval = stm32l4_read_flash_reg(bank, STM32_FLASH_OPTR, &options);
916 if (retval != ERROR_OK)
917 return retval;
918
919 stm32l4_info->bank1_sectors = 0;
920 stm32l4_info->hole_sectors = 0;
921
922 int num_pages = 0;
923 int page_size_kb = 0;
924
925 stm32l4_info->dual_bank_mode = false;
926
927 switch (device_id) {
928 case 0x415: /* STM32L47/L48xx */
929 case 0x461: /* STM32L49/L4Axx */
930 /* if flash size is max (1M) the device is always dual bank
931 * 0x415: has variants with 512K
932 * 0x461: has variants with 512 and 256
933 * for these variants:
934 * if DUAL_BANK = 0 -> single bank
935 * else -> dual bank without gap
936 * note: the page size is invariant
937 */
938 page_size_kb = 2;
939 num_pages = flash_size_kb / page_size_kb;
940 stm32l4_info->bank1_sectors = num_pages;
941
942 /* check DUAL_BANK bit[21] if the flash is less than 1M */
943 if (flash_size_kb == 1024 || (options & BIT(21))) {
944 stm32l4_info->dual_bank_mode = true;
945 stm32l4_info->bank1_sectors = num_pages / 2;
946 }
947 break;
948 case 0x435: /* STM32L43/L44xx */
949 case 0x460: /* STM32G07/G08xx */
950 case 0x462: /* STM32L45/L46xx */
951 case 0x464: /* STM32L41/L42xx */
952 case 0x466: /* STM32G03/G04xx */
953 case 0x468: /* STM32G43/G44xx */
954 case 0x497: /* STM32WLEx */
955 /* single bank flash */
956 page_size_kb = 2;
957 num_pages = flash_size_kb / page_size_kb;
958 stm32l4_info->bank1_sectors = num_pages;
959 break;
960 case 0x469: /* STM32G47/G48xx */
961 /* STM32G47/8 can be single/dual bank:
962 * if DUAL_BANK = 0 -> single bank
963 * else -> dual bank WITH gap
964 */
965 page_size_kb = 4;
966 num_pages = flash_size_kb / page_size_kb;
967 stm32l4_info->bank1_sectors = num_pages;
968 if (options & BIT(22)) {
969 stm32l4_info->dual_bank_mode = true;
970 page_size_kb = 2;
971 num_pages = flash_size_kb / page_size_kb;
972 stm32l4_info->bank1_sectors = num_pages / 2;
973
974 /* for devices with trimmed flash, there is a gap between both banks */
975 stm32l4_info->hole_sectors =
976 (part_info->max_flash_size_kb - flash_size_kb) / (2 * page_size_kb);
977 }
978 break;
979 case 0x470: /* STM32L4R/L4Sxx */
980 case 0x471: /* STM32L4P5/L4Q5x */
981 /* STM32L4R/S can be single/dual bank:
982 * if size = 2M check DBANK bit(22)
983 * if size = 1M check DB1M bit(21)
984 * STM32L4P/Q can be single/dual bank
985 * if size = 1M check DBANK bit(22)
986 * if size = 512K check DB512K bit(21)
987 */
988 page_size_kb = 8;
989 num_pages = flash_size_kb / page_size_kb;
990 stm32l4_info->bank1_sectors = num_pages;
991 const bool use_dbank_bit = flash_size_kb == part_info->max_flash_size_kb;
992 if ((use_dbank_bit && (options & BIT(22))) ||
993 (!use_dbank_bit && (options & BIT(21)))) {
994 stm32l4_info->dual_bank_mode = true;
995 page_size_kb = 4;
996 num_pages = flash_size_kb / page_size_kb;
997 stm32l4_info->bank1_sectors = num_pages / 2;
998 }
999 break;
1000 case 0x495: /* STM32WB5x */
1001 case 0x496: /* STM32WB3x */
1002 /* single bank flash */
1003 page_size_kb = 4;
1004 num_pages = flash_size_kb / page_size_kb;
1005 stm32l4_info->bank1_sectors = num_pages;
1006 break;
1007 default:
1008 LOG_ERROR("unsupported device");
1009 return ERROR_FAIL;
1010 }
1011
1012 LOG_INFO("flash mode : %s-bank", stm32l4_info->dual_bank_mode ? "dual" : "single");
1013
1014 const int gap_size_kb = stm32l4_info->hole_sectors * page_size_kb;
1015
1016 if (gap_size_kb != 0) {
1017 LOG_INFO("gap detected from 0x%08" PRIx32 " to 0x%08" PRIx32,
1018 STM32_FLASH_BANK_BASE + stm32l4_info->bank1_sectors
1019 * page_size_kb * 1024,
1020 STM32_FLASH_BANK_BASE + (stm32l4_info->bank1_sectors
1021 * page_size_kb + gap_size_kb) * 1024 - 1);
1022 }
1023
1024 /* number of significant bits in WRPxxR differs per device,
1025 * always right adjusted, on some devices non-implemented
1026 * bits read as '0', on others as '1' ...
1027 * notably G4 Cat. 2 implement only 6 bits, contradicting the RM
1028 */
1029
1030 /* use *max_flash_size* instead of actual size as the trimmed versions
1031 * certainly use the same number of bits
1032 * max_flash_size is always power of two, so max_pages too
1033 */
1034 uint32_t max_pages = stm32l4_info->part_info->max_flash_size_kb / page_size_kb;
1035 assert((max_pages & (max_pages - 1)) == 0);
1036
1037 /* in dual bank mode number of pages is doubled, but extra bit is bank selection */
1038 stm32l4_info->wrpxxr_mask = ((max_pages >> (stm32l4_info->dual_bank_mode ? 1 : 0)) - 1);
1039 assert((stm32l4_info->wrpxxr_mask & 0xFFFF0000) == 0);
1040 LOG_DEBUG("WRPxxR mask 0x%04" PRIx16, (uint16_t)stm32l4_info->wrpxxr_mask);
1041
1042 if (bank->sectors) {
1043 free(bank->sectors);
1044 bank->sectors = NULL;
1045 }
1046
1047 bank->size = (flash_size_kb + gap_size_kb) * 1024;
1048 bank->base = STM32_FLASH_BANK_BASE;
1049 bank->num_sectors = num_pages;
1050 bank->sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
1051 if (bank->sectors == NULL) {
1052 LOG_ERROR("failed to allocate bank sectors");
1053 return ERROR_FAIL;
1054 }
1055
1056 for (int i = 0; i < bank->num_sectors; i++) {
1057 bank->sectors[i].offset = i * page_size_kb * 1024;
1058 /* in dual bank configuration, if there is a gap between banks
1059 * we fix up the sector offset to consider this gap */
1060 if (i >= stm32l4_info->bank1_sectors && stm32l4_info->hole_sectors)
1061 bank->sectors[i].offset += gap_size_kb * 1024;
1062 bank->sectors[i].size = page_size_kb * 1024;
1063 bank->sectors[i].is_erased = -1;
1064 bank->sectors[i].is_protected = 1;
1065 }
1066
1067 stm32l4_info->probed = true;
1068 return ERROR_OK;
1069 }
1070
1071 static int stm32l4_auto_probe(struct flash_bank *bank)
1072 {
1073 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1074 if (stm32l4_info->probed)
1075 return ERROR_OK;
1076
1077 return stm32l4_probe(bank);
1078 }
1079
1080 static int get_stm32l4_info(struct flash_bank *bank, char *buf, int buf_size)
1081 {
1082 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1083 const struct stm32l4_part_info *part_info = stm32l4_info->part_info;
1084
1085 if (part_info) {
1086 const char *rev_str = NULL;
1087 uint16_t rev_id = stm32l4_info->idcode >> 16;
1088 for (unsigned int i = 0; i < part_info->num_revs; i++) {
1089 if (rev_id == part_info->revs[i].rev) {
1090 rev_str = part_info->revs[i].str;
1091
1092 if (rev_str != NULL) {
1093 snprintf(buf, buf_size, "%s - Rev: %s%s",
1094 part_info->device_str, rev_str, stm32l4_info->probed ?
1095 (stm32l4_info->dual_bank_mode ? " dual-bank" : " single-bank") : "");
1096 return ERROR_OK;
1097 }
1098 }
1099 }
1100
1101 snprintf(buf, buf_size, "%s - Rev: unknown (0x%04x)%s",
1102 part_info->device_str, rev_id, stm32l4_info->probed ?
1103 (stm32l4_info->dual_bank_mode ? " dual-bank" : " single-bank") : "");
1104 return ERROR_OK;
1105 } else {
1106 snprintf(buf, buf_size, "Cannot identify target as an %s device", device_families);
1107 return ERROR_FAIL;
1108 }
1109
1110 return ERROR_OK;
1111 }
1112
1113 static int stm32l4_mass_erase(struct flash_bank *bank)
1114 {
1115 int retval, retval2;
1116 struct target *target = bank->target;
1117 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1118
1119 uint32_t action = FLASH_MER1;
1120
1121 if (stm32l4_info->part_info->has_dual_bank)
1122 action |= FLASH_MER2;
1123
1124 if (target->state != TARGET_HALTED) {
1125 LOG_ERROR("Target not halted");
1126 return ERROR_TARGET_NOT_HALTED;
1127 }
1128
1129 retval = stm32l4_unlock_reg(bank);
1130 if (retval != ERROR_OK)
1131 goto err_lock;
1132
1133 /* mass erase flash memory */
1134 retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT / 10);
1135 if (retval != ERROR_OK)
1136 goto err_lock;
1137
1138 retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, action);
1139 if (retval != ERROR_OK)
1140 goto err_lock;
1141
1142 retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, action | FLASH_STRT);
1143 if (retval != ERROR_OK)
1144 goto err_lock;
1145
1146 retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
1147
1148 err_lock:
1149 retval2 = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, FLASH_LOCK);
1150
1151 if (retval != ERROR_OK)
1152 return retval;
1153
1154 return retval2;
1155 }
1156
1157 COMMAND_HANDLER(stm32l4_handle_mass_erase_command)
1158 {
1159 if (CMD_ARGC < 1) {
1160 command_print(CMD, "stm32l4x mass_erase <STM32L4 bank>");
1161 return ERROR_COMMAND_SYNTAX_ERROR;
1162 }
1163
1164 struct flash_bank *bank;
1165 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1166 if (ERROR_OK != retval)
1167 return retval;
1168
1169 retval = stm32l4_mass_erase(bank);
1170 if (retval == ERROR_OK) {
1171 /* set all sectors as erased */
1172 for (int i = 0; i < bank->num_sectors; i++)
1173 bank->sectors[i].is_erased = 1;
1174
1175 command_print(CMD, "stm32l4x mass erase complete");
1176 } else {
1177 command_print(CMD, "stm32l4x mass erase failed");
1178 }
1179
1180 return retval;
1181 }
1182
1183 COMMAND_HANDLER(stm32l4_handle_option_read_command)
1184 {
1185 if (CMD_ARGC < 2) {
1186 command_print(CMD, "stm32l4x option_read <STM32L4 bank> <option_reg offset>");
1187 return ERROR_COMMAND_SYNTAX_ERROR;
1188 }
1189
1190 struct flash_bank *bank;
1191 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1192 if (ERROR_OK != retval)
1193 return retval;
1194
1195 uint32_t reg_offset, reg_addr;
1196 uint32_t value = 0;
1197
1198 reg_offset = strtoul(CMD_ARGV[1], NULL, 16);
1199 reg_addr = stm32l4_get_flash_reg(bank, reg_offset);
1200
1201 retval = stm32l4_read_flash_reg(bank, reg_offset, &value);
1202 if (ERROR_OK != retval)
1203 return retval;
1204
1205 command_print(CMD, "Option Register: <0x%" PRIx32 "> = 0x%" PRIx32 "", reg_addr, value);
1206
1207 return retval;
1208 }
1209
1210 COMMAND_HANDLER(stm32l4_handle_option_write_command)
1211 {
1212 if (CMD_ARGC < 3) {
1213 command_print(CMD, "stm32l4x option_write <STM32L4 bank> <option_reg offset> <value> [mask]");
1214 return ERROR_COMMAND_SYNTAX_ERROR;
1215 }
1216
1217 struct flash_bank *bank;
1218 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1219 if (ERROR_OK != retval)
1220 return retval;
1221
1222 uint32_t reg_offset;
1223 uint32_t value = 0;
1224 uint32_t mask = 0xFFFFFFFF;
1225
1226 reg_offset = strtoul(CMD_ARGV[1], NULL, 16);
1227 value = strtoul(CMD_ARGV[2], NULL, 16);
1228 if (CMD_ARGC > 3)
1229 mask = strtoul(CMD_ARGV[3], NULL, 16);
1230
1231 command_print(CMD, "%s Option written.\n"
1232 "INFO: a reset or power cycle is required "
1233 "for the new settings to take effect.", bank->driver->name);
1234
1235 retval = stm32l4_write_option(bank, reg_offset, value, mask);
1236 return retval;
1237 }
1238
1239 COMMAND_HANDLER(stm32l4_handle_option_load_command)
1240 {
1241 if (CMD_ARGC != 1)
1242 return ERROR_COMMAND_SYNTAX_ERROR;
1243
1244 struct flash_bank *bank;
1245 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1246 if (ERROR_OK != retval)
1247 return retval;
1248
1249 retval = stm32l4_unlock_reg(bank);
1250 if (ERROR_OK != retval)
1251 return retval;
1252
1253 retval = stm32l4_unlock_option_reg(bank);
1254 if (ERROR_OK != retval)
1255 return retval;
1256
1257 /* Set OBL_LAUNCH bit in CR -> system reset and option bytes reload,
1258 * but the RMs explicitly do *NOT* list this as power-on reset cause, and:
1259 * "Note: If the read protection is set while the debugger is still
1260 * connected through JTAG/SWD, apply a POR (power-on reset) instead of a system reset."
1261 */
1262 retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, FLASH_OBL_LAUNCH);
1263
1264 command_print(CMD, "stm32l4x option load completed. Power-on reset might be required");
1265
1266 /* Need to re-probe after change */
1267 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1268 stm32l4_info->probed = false;
1269
1270 return retval;
1271 }
1272
1273 COMMAND_HANDLER(stm32l4_handle_lock_command)
1274 {
1275 struct target *target = NULL;
1276
1277 if (CMD_ARGC < 1)
1278 return ERROR_COMMAND_SYNTAX_ERROR;
1279
1280 struct flash_bank *bank;
1281 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1282 if (ERROR_OK != retval)
1283 return retval;
1284
1285 target = bank->target;
1286
1287 if (target->state != TARGET_HALTED) {
1288 LOG_ERROR("Target not halted");
1289 return ERROR_TARGET_NOT_HALTED;
1290 }
1291
1292 /* set readout protection level 1 by erasing the RDP option byte */
1293 if (stm32l4_write_option(bank, STM32_FLASH_OPTR, 0, 0x000000FF) != ERROR_OK) {
1294 command_print(CMD, "%s failed to lock device", bank->driver->name);
1295 return ERROR_OK;
1296 }
1297
1298 return ERROR_OK;
1299 }
1300
1301 COMMAND_HANDLER(stm32l4_handle_unlock_command)
1302 {
1303 struct target *target = NULL;
1304
1305 if (CMD_ARGC < 1)
1306 return ERROR_COMMAND_SYNTAX_ERROR;
1307
1308 struct flash_bank *bank;
1309 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1310 if (ERROR_OK != retval)
1311 return retval;
1312
1313 target = bank->target;
1314
1315 if (target->state != TARGET_HALTED) {
1316 LOG_ERROR("Target not halted");
1317 return ERROR_TARGET_NOT_HALTED;
1318 }
1319
1320 if (stm32l4_write_option(bank, STM32_FLASH_OPTR, RDP_LEVEL_0, 0x000000FF) != ERROR_OK) {
1321 command_print(CMD, "%s failed to unlock device", bank->driver->name);
1322 return ERROR_OK;
1323 }
1324
1325 return ERROR_OK;
1326 }
1327
1328 static const struct command_registration stm32l4_exec_command_handlers[] = {
1329 {
1330 .name = "lock",
1331 .handler = stm32l4_handle_lock_command,
1332 .mode = COMMAND_EXEC,
1333 .usage = "bank_id",
1334 .help = "Lock entire flash device.",
1335 },
1336 {
1337 .name = "unlock",
1338 .handler = stm32l4_handle_unlock_command,
1339 .mode = COMMAND_EXEC,
1340 .usage = "bank_id",
1341 .help = "Unlock entire protected flash device.",
1342 },
1343 {
1344 .name = "mass_erase",
1345 .handler = stm32l4_handle_mass_erase_command,
1346 .mode = COMMAND_EXEC,
1347 .usage = "bank_id",
1348 .help = "Erase entire flash device.",
1349 },
1350 {
1351 .name = "option_read",
1352 .handler = stm32l4_handle_option_read_command,
1353 .mode = COMMAND_EXEC,
1354 .usage = "bank_id reg_offset",
1355 .help = "Read & Display device option bytes.",
1356 },
1357 {
1358 .name = "option_write",
1359 .handler = stm32l4_handle_option_write_command,
1360 .mode = COMMAND_EXEC,
1361 .usage = "bank_id reg_offset value mask",
1362 .help = "Write device option bit fields with provided value.",
1363 },
1364 {
1365 .name = "option_load",
1366 .handler = stm32l4_handle_option_load_command,
1367 .mode = COMMAND_EXEC,
1368 .usage = "bank_id",
1369 .help = "Force re-load of device options (will cause device reset).",
1370 },
1371 COMMAND_REGISTRATION_DONE
1372 };
1373
1374 static const struct command_registration stm32l4_command_handlers[] = {
1375 {
1376 .name = "stm32l4x",
1377 .mode = COMMAND_ANY,
1378 .help = "stm32l4x flash command group",
1379 .usage = "",
1380 .chain = stm32l4_exec_command_handlers,
1381 },
1382 COMMAND_REGISTRATION_DONE
1383 };
1384
1385 const struct flash_driver stm32l4x_flash = {
1386 .name = "stm32l4x",
1387 .commands = stm32l4_command_handlers,
1388 .flash_bank_command = stm32l4_flash_bank_command,
1389 .erase = stm32l4_erase,
1390 .protect = stm32l4_protect,
1391 .write = stm32l4_write,
1392 .read = default_flash_read,
1393 .probe = stm32l4_probe,
1394 .auto_probe = stm32l4_auto_probe,
1395 .erase_check = default_flash_blank_check,
1396 .protect_check = stm32l4_protect_check,
1397 .info = get_stm32l4_info,
1398 .free_driver_priv = default_flash_free_driver_priv,
1399 };
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