1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2011 by Clement Burin des Roziers *
9 * clement.burin-des-roziers@hikob.com *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
31 #include <helper/binarybuffer.h>
32 #include <target/algorithm.h>
33 #include <target/armv7m.h>
35 /* stm32lx flash register locations */
37 #define FLASH_BASE 0x40023C00
38 #define FLASH_ACR 0x40023C00
39 #define FLASH_PECR 0x40023C04
40 #define FLASH_PDKEYR 0x40023C08
41 #define FLASH_PEKEYR 0x40023C0C
42 #define FLASH_PRGKEYR 0x40023C10
43 #define FLASH_OPTKEYR 0x40023C14
44 #define FLASH_SR 0x40023C18
45 #define FLASH_OBR 0x40023C1C
46 #define FLASH_WRPR 0x40023C20
49 #define FLASH_ACR__LATENCY (1<<0)
50 #define FLASH_ACR__PRFTEN (1<<1)
51 #define FLASH_ACR__ACC64 (1<<2)
52 #define FLASH_ACR__SLEEP_PD (1<<3)
53 #define FLASH_ACR__RUN_PD (1<<4)
56 #define FLASH_PECR__PELOCK (1<<0)
57 #define FLASH_PECR__PRGLOCK (1<<1)
58 #define FLASH_PECR__OPTLOCK (1<<2)
59 #define FLASH_PECR__PROG (1<<3)
60 #define FLASH_PECR__DATA (1<<4)
61 #define FLASH_PECR__FTDW (1<<8)
62 #define FLASH_PECR__ERASE (1<<9)
63 #define FLASH_PECR__FPRG (1<<10)
64 #define FLASH_PECR__EOPIE (1<<16)
65 #define FLASH_PECR__ERRIE (1<<17)
66 #define FLASH_PECR__OBL_LAUNCH (1<<18)
69 #define FLASH_SR__BSY (1<<0)
70 #define FLASH_SR__EOP (1<<1)
71 #define FLASH_SR__ENDHV (1<<2)
72 #define FLASH_SR__READY (1<<3)
73 #define FLASH_SR__WRPERR (1<<8)
74 #define FLASH_SR__PGAERR (1<<9)
75 #define FLASH_SR__SIZERR (1<<10)
76 #define FLASH_SR__OPTVERR (1<<11)
79 #define PEKEY1 0x89ABCDEF
80 #define PEKEY2 0x02030405
81 #define PRGKEY1 0x8C9DAEBF
82 #define PRGKEY2 0x13141516
83 #define OPTKEY1 0xFBEAD9C8
84 #define OPTKEY2 0x24252627
87 #define DBGMCU_IDCODE 0xE0042000
88 #define F_SIZE 0x1FF8004C
91 #define FLASH_PAGE_SIZE 256
92 #define FLASH_SECTOR_SIZE 4096
93 #define FLASH_PAGES_PER_SECTOR 16
94 #define FLASH_BANK0_ADDRESS 0x08000000
96 /* stm32lx option byte register location */
97 #define OB_RDP 0x1FF80000
98 #define OB_USER 0x1FF80004
99 #define OB_WRP0_1 0x1FF80008
100 #define OB_WRP2_3 0x1FF8000C
103 #define OB_RDP__LEVEL0 0xFF5500AA
104 #define OB_RDP__LEVEL1 0xFFFF0000
106 /* stm32lx RCC register locations */
107 #define RCC_CR 0x40023800
108 #define RCC_ICSCR 0x40023804
109 #define RCC_CFGR 0x40023808
112 #define RCC_ICSCR__MSIRANGE_MASK (7<<13)
114 static int stm32lx_unlock_program_memory(struct flash_bank
*bank
);
115 static int stm32lx_lock_program_memory(struct flash_bank
*bank
);
116 static int stm32lx_enable_write_half_page(struct flash_bank
*bank
);
117 static int stm32lx_erase_sector(struct flash_bank
*bank
, int sector
);
118 static int stm32lx_wait_until_bsy_clear(struct flash_bank
*bank
);
120 struct stm32lx_flash_bank
122 struct working_area
*write_algorithm
;
126 /* flash bank stm32lx <base> <size> 0 0 <target#>
128 FLASH_BANK_COMMAND_HANDLER(stm32lx_flash_bank_command
)
130 struct stm32lx_flash_bank
*stm32lx_info
;
133 return ERROR_COMMAND_SYNTAX_ERROR
;
136 // Create the bank structure
137 stm32lx_info
= malloc(sizeof(struct stm32lx_flash_bank
));
140 if (stm32lx_info
== NULL
)
142 LOG_ERROR("failed to allocate bank structure");
146 bank
->driver_priv
= stm32lx_info
;
148 stm32lx_info
->write_algorithm
= NULL
;
149 stm32lx_info
->probed
= 0;
154 static int stm32lx_protect_check(struct flash_bank
*bank
)
157 struct target
*target
= bank
->target
;
161 if (target
->state
!= TARGET_HALTED
)
163 LOG_ERROR("Target not halted");
164 return ERROR_TARGET_NOT_HALTED
;
168 * Read the WRPR word, and check each bit (corresponding to each
171 retval
= target_read_u32(target
, FLASH_WRPR
, &wrpr
);
172 if (retval
!= ERROR_OK
)
175 for (int i
= 0; i
< 32; i
++)
179 bank
->sectors
[i
].is_protected
= 1;
183 bank
->sectors
[i
].is_protected
= 0;
189 static int stm32lx_erase(struct flash_bank
*bank
, int first
, int last
)
194 * It could be possible to do a mass erase if all sectors must be
195 * erased, but it is not implemented yet.
198 if (bank
->target
->state
!= TARGET_HALTED
)
200 LOG_ERROR("Target not halted");
201 return ERROR_TARGET_NOT_HALTED
;
205 * Loop over the selected sectors and erase them
207 for (int i
= first
; i
<= last
; i
++)
209 retval
= stm32lx_erase_sector(bank
, i
);
210 if (retval
!= ERROR_OK
)
212 bank
->sectors
[i
].is_erased
= 1;
217 static int stm32lx_protect(struct flash_bank
*bank
, int set
, int first
,
220 LOG_WARNING("protection of the STM32L flash is not implemented");
224 static int stm32lx_write_half_pages(struct flash_bank
*bank
, uint8_t *buffer
,
225 uint32_t offset
, uint32_t count
)
227 struct stm32lx_flash_bank
*stm32lx_info
= bank
->driver_priv
;
228 struct target
*target
= bank
->target
;
229 uint32_t buffer_size
= 4096 * 4;
230 struct working_area
*source
;
231 uint32_t address
= bank
->base
+ offset
;
233 struct reg_param reg_params
[5];
234 struct armv7m_algorithm armv7m_info
;
236 int retval
= ERROR_OK
;
239 /* see contib/loaders/flash/stm32lx.s for src */
241 static const uint16_t stm32lx_flash_write_code_16
[] =
243 // 00000000 <write_word-0x4>:
244 0x2300, // 0: 2300 movs r3, #0
245 0xe004, // 2: e004 b.n e <test_done>
247 // 00000004 <write_word>:
248 0xf851, 0xcb04, // 4: f851 cb04 ldr.w ip, [r1], #4
249 0xf840, 0xcb04, // 8: f840 cb04 str.w ip, [r0], #4
250 0x3301, // c: 3301 adds r3, #1
252 // 0000000e <test_done>:
253 0x4293, // e: 4293 cmp r3, r2
254 0xd3f8, // 10: d3f8 bcc.n 4 <write_word>
255 0xbe00, // 12: be00 bkpt 0x0000
260 uint8_t stm32lx_flash_write_code
[sizeof(stm32lx_flash_write_code_16
)];
261 for (unsigned int i
= 0; i
< sizeof(stm32lx_flash_write_code_16
) / 2; i
++)
263 stm32lx_flash_write_code
[i
* 2 + 0] = stm32lx_flash_write_code_16
[i
]
265 stm32lx_flash_write_code
[i
* 2 + 1] = (stm32lx_flash_write_code_16
[i
]
268 // Check if there is an even number of half pages (128bytes)
271 LOG_ERROR("there should be an even number "
272 "of half pages = 128 bytes (count = %" PRIi32
" bytes)", count
);
276 // Allocate working area
277 reg32
= sizeof(stm32lx_flash_write_code
);
278 // Add bytes to make 4byte aligned
279 reg32
+= (4 - (reg32
% 4)) % 4;
280 retval
= target_alloc_working_area(target
, reg32
,
281 &stm32lx_info
->write_algorithm
);
282 if (retval
!= ERROR_OK
)
285 // Write the flashing code
286 retval
= target_write_buffer(target
,
287 stm32lx_info
->write_algorithm
->address
,
288 sizeof(stm32lx_flash_write_code
),
289 (uint8_t*) stm32lx_flash_write_code
);
290 if (retval
!= ERROR_OK
)
292 target_free_working_area(target
, stm32lx_info
->write_algorithm
);
296 // Allocate half pages memory
297 while (target_alloc_working_area_try(target
, buffer_size
, &source
)
300 if (buffer_size
> 1024)
305 if (buffer_size
<= 256)
307 /* if we already allocated the writing code, but failed to get a
308 * buffer, free the algorithm */
309 if (stm32lx_info
->write_algorithm
)
310 target_free_working_area(target
, stm32lx_info
->write_algorithm
);
312 LOG_WARNING("no large enough working area available, can't do block memory writes");
313 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
316 LOG_DEBUG("allocated working area for data (%" PRIx32
" bytes)", buffer_size
);
318 armv7m_info
.common_magic
= ARMV7M_COMMON_MAGIC
;
319 armv7m_info
.core_mode
= ARMV7M_MODE_ANY
;
320 init_reg_param(®_params
[0], "r0", 32, PARAM_OUT
);
321 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
322 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
);
323 init_reg_param(®_params
[3], "r3", 32, PARAM_IN_OUT
);
324 init_reg_param(®_params
[4], "r4", 32, PARAM_OUT
);
326 // Enable half-page write
327 retval
= stm32lx_enable_write_half_page(bank
);
328 if (retval
!= ERROR_OK
)
331 target_free_working_area(target
, source
);
332 target_free_working_area(target
, stm32lx_info
->write_algorithm
);
334 destroy_reg_param(®_params
[0]);
335 destroy_reg_param(®_params
[1]);
336 destroy_reg_param(®_params
[2]);
337 destroy_reg_param(®_params
[3]);
342 // Loop while there are bytes to write
346 this_count
= (count
> buffer_size
) ? buffer_size
: count
;
348 // Write the next half pages
349 retval
= target_write_buffer(target
, source
->address
, this_count
,
351 if (retval
!= ERROR_OK
)
354 // 4: Store useful information in the registers
355 // the destination address of the copy (R0)
356 buf_set_u32(reg_params
[0].value
, 0, 32, address
);
357 // The source address of the copy (R1)
358 buf_set_u32(reg_params
[1].value
, 0, 32, source
->address
);
359 // The length of the copy (R2)
360 buf_set_u32(reg_params
[2].value
, 0, 32, this_count
/ 4);
362 // 5: Execute the bunch of code
363 retval
= target_run_algorithm(target
, 0, NULL
, sizeof(reg_params
)
364 / sizeof(*reg_params
), reg_params
,
365 stm32lx_info
->write_algorithm
->address
, 0, 20000, &armv7m_info
);
366 if (retval
!= ERROR_OK
)
369 // 6: Wait while busy
370 retval
= stm32lx_wait_until_bsy_clear(bank
);
371 if (retval
!= ERROR_OK
)
374 buffer
+= this_count
;
375 address
+= this_count
;
379 if (retval
== ERROR_OK
)
380 retval
= stm32lx_lock_program_memory(bank
);
382 target_free_working_area(target
, source
);
383 target_free_working_area(target
, stm32lx_info
->write_algorithm
);
385 destroy_reg_param(®_params
[0]);
386 destroy_reg_param(®_params
[1]);
387 destroy_reg_param(®_params
[2]);
388 destroy_reg_param(®_params
[3]);
392 static int stm32lx_write(struct flash_bank
*bank
, uint8_t *buffer
,
393 uint32_t offset
, uint32_t count
)
395 struct target
*target
= bank
->target
;
397 uint32_t halfpages_number
;
398 uint32_t words_remaining
;
399 uint32_t bytes_remaining
;
400 uint32_t address
= bank
->base
+ offset
;
401 uint32_t bytes_written
= 0;
404 if (bank
->target
->state
!= TARGET_HALTED
)
406 LOG_ERROR("Target not halted");
407 return ERROR_TARGET_NOT_HALTED
;
412 LOG_ERROR("offset 0x%" PRIx32
" breaks required 2-byte alignment", offset
);
413 return ERROR_FLASH_DST_BREAKS_ALIGNMENT
;
416 // Check if there are some full half pages
417 if (((offset
% 128) == 0) && (count
>= 128))
419 halfpages_number
= count
/ 128;
420 words_remaining
= (count
- 128 * halfpages_number
) / 4;
421 bytes_remaining
= (count
& 0x3);
425 halfpages_number
= 0;
426 words_remaining
= (count
/ 4);
427 bytes_remaining
= (count
& 0x3);
430 if (halfpages_number
)
432 retval
= stm32lx_write_half_pages(bank
, buffer
, offset
, 128
434 if (retval
!= ERROR_OK
)
438 bytes_written
= 128 * halfpages_number
;
440 retval
= stm32lx_unlock_program_memory(bank
);
441 if (retval
!= ERROR_OK
)
444 while (words_remaining
> 0)
447 uint8_t* p
= buffer
+ bytes_written
;
449 // Prepare the word, Little endian conversion
450 value
= p
[0] + (p
[1] << 8) + (p
[2] << 16) + (p
[3] << 24);
452 retval
= target_write_u32(target
, address
, value
);
453 if (retval
!= ERROR_OK
)
460 retval
= stm32lx_wait_until_bsy_clear(bank
);
461 if (retval
!= ERROR_OK
)
467 uint8_t last_word
[4] = {0xff, 0xff, 0xff, 0xff};
469 /* copy the last remaining bytes into the write buffer */
470 memcpy(last_word
, buffer
+bytes_written
, bytes_remaining
);
472 retval
= target_write_buffer(target
, address
, 4, last_word
);
473 if (retval
!= ERROR_OK
)
476 retval
= stm32lx_wait_until_bsy_clear(bank
);
477 if (retval
!= ERROR_OK
)
481 retval
= stm32lx_lock_program_memory(bank
);
482 if (retval
!= ERROR_OK
)
488 static int stm32lx_probe(struct flash_bank
*bank
)
490 struct target
*target
= bank
->target
;
491 struct stm32lx_flash_bank
*stm32lx_info
= bank
->driver_priv
;
497 stm32lx_info
->probed
= 0;
499 /* read stm32 device id register */
500 int retval
= target_read_u32(target
, DBGMCU_IDCODE
, &device_id
);
501 if (retval
!= ERROR_OK
)
504 LOG_DEBUG("device id = 0x%08" PRIx32
"", device_id
);
506 if ((device_id
& 0x7ff) != 0x416)
508 LOG_WARNING("Cannot identify target as a STM32L family.");
512 // Read the RDP byte and check if it is 0xAA
514 retval
= target_read_u32(target
, FLASH_OBR
, ®32
);
515 if (retval
!= ERROR_OK
)
521 * Unlocking the option byte is done by unlocking the PECR, then
522 * by writing the 2 option byte keys to OPTKEYR
525 /* To unlock the PECR write the 2 PEKEY to the PEKEYR register */
526 retval
= target_write_u32(target
, FLASH_PEKEYR
, PEKEY1
);
527 if (retval
!= ERROR_OK
)
530 retval
= target_write_u32(target
, FLASH_PEKEYR
, PEKEY2
);
531 if (retval
!= ERROR_OK
)
534 /* Make sure it worked */
535 retval
= target_read_u32(target
, FLASH_PECR
, ®32
);
536 if (retval
!= ERROR_OK
)
539 if (reg32
& FLASH_PECR__PELOCK
)
540 return ERROR_FLASH_OPERATION_FAILED
;
542 retval
= target_write_u32(target
, FLASH_OPTKEYR
, OPTKEY1
);
543 if (retval
!= ERROR_OK
)
545 retval
= target_write_u32(target
, FLASH_OPTKEYR
, OPTKEY2
);
546 if (retval
!= ERROR_OK
)
549 retval
= target_read_u32(target
, FLASH_PECR
, ®32
);
550 if (retval
!= ERROR_OK
)
553 if (reg32
& FLASH_PECR__OPTLOCK
)
555 LOG_ERROR("OPTLOCK is not cleared");
556 return ERROR_FLASH_OPERATION_FAILED
;
559 // Then, write RDP to 0x00 to set level 1
560 reg32
= ((~0xAA) << 16) | (0xAA);
561 retval
= target_write_u32(target
, OB_RDP
, reg32
);
562 if (retval
!= ERROR_OK
)
565 // Set Automatic update of the option byte, by setting OBL_LAUNCH in FLASH_PECR
566 reg32
= FLASH_PECR__OBL_LAUNCH
;
567 retval
= target_write_u32(target
, FLASH_PECR
, reg32
);
568 if (retval
!= ERROR_OK
)
572 /* get flash size from target. */
573 retval
= target_read_u16(target
, F_SIZE
, &flash_size
);
574 if (retval
!= ERROR_OK
)
577 /* check for valid flash size */
578 if (flash_size
== 0xffff)
580 /* number of sectors incorrect on revA */
581 LOG_ERROR("STM32 flash size failed, probe inaccurate");
585 /* STM32L - we have 32 sectors, 16 pages per sector -> 512 pages
586 * 16 pages for a protection area */
588 /* calculate numbers of sectors (4kB per sector) */
589 int num_sectors
= (flash_size
* 1024) / FLASH_SECTOR_SIZE
;
590 LOG_INFO("flash size = %dkbytes", flash_size
);
595 bank
->sectors
= NULL
;
598 bank
->base
= FLASH_BANK0_ADDRESS
;
599 bank
->size
= flash_size
* 1024;
600 bank
->num_sectors
= num_sectors
;
601 bank
->sectors
= malloc(sizeof(struct flash_sector
) * num_sectors
);
602 if (bank
->sectors
== NULL
)
604 LOG_ERROR("failed to allocate bank sectors");
608 for (i
= 0; i
< num_sectors
; i
++)
610 bank
->sectors
[i
].offset
= i
* FLASH_SECTOR_SIZE
;
611 bank
->sectors
[i
].size
= FLASH_SECTOR_SIZE
;
612 bank
->sectors
[i
].is_erased
= -1;
613 bank
->sectors
[i
].is_protected
= 1;
616 stm32lx_info
->probed
= 1;
621 static int stm32lx_auto_probe(struct flash_bank
*bank
)
623 struct stm32lx_flash_bank
*stm32lx_info
= bank
->driver_priv
;
625 if (stm32lx_info
->probed
)
630 return stm32lx_probe(bank
);
633 static int stm32lx_erase_check(struct flash_bank
*bank
)
635 struct target
*target
= bank
->target
;
636 const int buffer_size
= 4096;
639 int retval
= ERROR_OK
;
641 if (bank
->target
->state
!= TARGET_HALTED
)
643 LOG_ERROR("Target not halted");
644 return ERROR_TARGET_NOT_HALTED
;
647 uint8_t *buffer
= malloc(buffer_size
);
650 LOG_ERROR("failed to allocate read buffer");
654 for (i
= 0; i
< bank
->num_sectors
; i
++)
657 bank
->sectors
[i
].is_erased
= 1;
659 // Loop chunk by chunk over the sector
660 for (j
= 0; j
< bank
->sectors
[i
].size
; j
+= buffer_size
)
664 if (chunk
> (j
- bank
->sectors
[i
].size
))
666 chunk
= (j
- bank
->sectors
[i
].size
);
669 retval
= target_read_memory(target
, bank
->base
670 + bank
->sectors
[i
].offset
+ j
, 4, chunk
/ 4, buffer
);
671 if (retval
!= ERROR_OK
)
674 for (nBytes
= 0; nBytes
< chunk
; nBytes
++)
676 if (buffer
[nBytes
] != 0x00)
678 bank
->sectors
[i
].is_erased
= 0;
683 if (retval
!= ERROR_OK
)
692 static int stm32lx_get_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
694 // This method must return a string displaying information about the bank
696 struct target
*target
= bank
->target
;
700 /* read stm32 device id register */
701 int retval
= target_read_u32(target
, DBGMCU_IDCODE
, &device_id
);
702 if (retval
!= ERROR_OK
)
705 if ((device_id
& 0x7ff) == 0x416)
707 printed
= snprintf(buf
, buf_size
, "stm32lx - Rev: ");
711 switch (device_id
>> 16)
714 snprintf(buf
, buf_size
, "A");
718 snprintf(buf
, buf_size
, "Y");
721 snprintf(buf
, buf_size
, "unknown");
727 snprintf(buf
, buf_size
, "Cannot identify target as a stm32lx");
734 static const struct command_registration stm32lx_exec_command_handlers
[] =
736 COMMAND_REGISTRATION_DONE
739 static const struct command_registration stm32lx_command_handlers
[] =
744 .help
= "stm32lx flash command group",
745 .chain
= stm32lx_exec_command_handlers
,
747 COMMAND_REGISTRATION_DONE
750 struct flash_driver stm32lx_flash
=
753 .commands
= stm32lx_command_handlers
,
754 .flash_bank_command
= stm32lx_flash_bank_command
,
755 .erase
= stm32lx_erase
,
756 .protect
= stm32lx_protect
,
757 .write
= stm32lx_write
,
758 .read
= default_flash_read
,
759 .probe
= stm32lx_probe
,
760 .auto_probe
= stm32lx_auto_probe
,
761 .erase_check
= stm32lx_erase_check
,
762 .protect_check
= stm32lx_protect_check
,
763 .info
= stm32lx_get_info
,
766 // Static methods implementation
768 static int stm32lx_unlock_program_memory(struct flash_bank
*bank
)
770 struct target
*target
= bank
->target
;
775 * Unlocking the program memory is done by unlocking the PECR,
776 * then by writing the 2 PRGKEY to the PRGKEYR register
779 /* To unlock the PECR write the 2 PEKEY to the PEKEYR register */
780 retval
= target_write_u32(target
, FLASH_PEKEYR
, PEKEY1
);
781 if (retval
!= ERROR_OK
)
784 retval
= target_write_u32(target
, FLASH_PEKEYR
, PEKEY2
);
785 if (retval
!= ERROR_OK
)
788 /* Make sure it worked */
789 retval
= target_read_u32(target
, FLASH_PECR
, ®32
);
790 if (retval
!= ERROR_OK
)
793 if (reg32
& FLASH_PECR__PELOCK
)
795 LOG_ERROR("PELOCK is not cleared :(");
796 return ERROR_FLASH_OPERATION_FAILED
;
799 retval
= target_write_u32(target
, FLASH_PRGKEYR
, PRGKEY1
);
800 if (retval
!= ERROR_OK
)
802 retval
= target_write_u32(target
, FLASH_PRGKEYR
, PRGKEY2
);
803 if (retval
!= ERROR_OK
)
806 /* Make sure it worked */
807 retval
= target_read_u32(target
, FLASH_PECR
, ®32
);
808 if (retval
!= ERROR_OK
)
811 if (reg32
& FLASH_PECR__PRGLOCK
)
813 LOG_ERROR("PRGLOCK is not cleared :(");
814 return ERROR_FLASH_OPERATION_FAILED
;
819 static int stm32lx_enable_write_half_page(struct flash_bank
*bank
)
821 struct target
*target
= bank
->target
;
826 * Unlock the program memory, then set the FPRG bit in the PECR register.
828 retval
= stm32lx_unlock_program_memory(bank
);
829 if (retval
!= ERROR_OK
)
832 retval
= target_read_u32(target
, FLASH_PECR
, ®32
);
833 if (retval
!= ERROR_OK
)
836 reg32
|= FLASH_PECR__FPRG
;
837 retval
= target_write_u32(target
, FLASH_PECR
, reg32
);
838 if (retval
!= ERROR_OK
)
841 retval
= target_read_u32(target
, FLASH_PECR
, ®32
);
842 if (retval
!= ERROR_OK
)
845 reg32
|= FLASH_PECR__PROG
;
846 retval
= target_write_u32(target
, FLASH_PECR
, reg32
);
851 static int stm32lx_lock_program_memory(struct flash_bank
*bank
)
853 struct target
*target
= bank
->target
;
857 /* To lock the program memory, simply set the lock bit and lock PECR */
859 retval
= target_read_u32(target
, FLASH_PECR
, ®32
);
860 if (retval
!= ERROR_OK
)
863 reg32
|= FLASH_PECR__PRGLOCK
;
864 retval
= target_write_u32(target
, FLASH_PECR
, reg32
);
865 if (retval
!= ERROR_OK
)
868 retval
= target_read_u32(target
, FLASH_PECR
, ®32
);
869 if (retval
!= ERROR_OK
)
872 reg32
|= FLASH_PECR__PELOCK
;
873 retval
= target_write_u32(target
, FLASH_PECR
, reg32
);
874 if (retval
!= ERROR_OK
)
880 static int stm32lx_erase_sector(struct flash_bank
*bank
, int sector
)
882 struct target
*target
= bank
->target
;
887 * To erase a sector (i.e. FLASH_PAGES_PER_SECTOR pages),
888 * first unlock the memory, loop over the pages of this sector
889 * and write 0x0 to its first word.
892 retval
= stm32lx_unlock_program_memory(bank
);
893 if (retval
!= ERROR_OK
)
896 for (int page
= 0; page
< FLASH_PAGES_PER_SECTOR
; page
++)
898 reg32
= FLASH_PECR__PROG
| FLASH_PECR__ERASE
;
899 retval
= target_write_u32(target
, FLASH_PECR
, reg32
);
900 if (retval
!= ERROR_OK
)
903 retval
= stm32lx_wait_until_bsy_clear(bank
);
904 if (retval
!= ERROR_OK
)
907 uint32_t addr
= bank
->base
+ bank
->sectors
[sector
].offset
+ (page
909 retval
= target_write_u32(target
, addr
, 0x0);
910 if (retval
!= ERROR_OK
)
913 retval
= stm32lx_wait_until_bsy_clear(bank
);
914 if (retval
!= ERROR_OK
)
918 retval
= stm32lx_lock_program_memory(bank
);
919 if (retval
!= ERROR_OK
)
925 static int stm32lx_wait_until_bsy_clear(struct flash_bank
*bank
)
927 struct target
*target
= bank
->target
;
929 int retval
= ERROR_OK
;
932 /* wait for busy to clear */
935 retval
= target_read_u32(target
, FLASH_SR
, &status
);
936 if (retval
!= ERROR_OK
)
939 if ((status
& FLASH_SR__BSY
) == 0)
945 LOG_ERROR("timed out waiting for flash");
951 if (status
& FLASH_SR__WRPERR
)
953 LOG_ERROR("access denied / write protected");
957 if (status
& FLASH_SR__PGAERR
)
959 LOG_ERROR("invalid program address");
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)